From 3f3566ce38398eb8c54dffd6a1f5c0b31d45ae83 Mon Sep 17 00:00:00 2001 From: Jinsong Ji Date: Sat, 24 Oct 2026 10:49:57 -0400 Subject: [PATCH 01/31] [Test][clang-repl]Keep value names in clang-repl pragma-optimize.cpp (#235305) The test added by aa6e40c073e6 checks for named values (entry:, %x.addr, %x), which only appear when clang keeps value names. That is the default in assertion builds, but non-assertion CI builds discard them, so the CHECK-NEXT: entry: line fails. Pass -fno-discard-value-names explicitly. Assisted-By: Claude Opus 5.5 --- clang/test/Interpreter/pragma-optimize.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/clang/test/Interpreter/pragma-optimize.cpp b/clang/test/Interpreter/pragma-optimize.cpp index 1d43c54e8edb42..580901117da51a 100644 --- a/clang/test/Interpreter/pragma-optimize.cpp +++ b/clang/test/Interpreter/pragma-optimize.cpp @@ -3,7 +3,8 @@ // '#pragma clang repl optimize()' sets the optimization level and size for // input parsed after it; is an -O flag spelled without the leading dash. // -// RUN: cat %s | clang-repl -Xcc -Xclang -Xcc -emit-llvm | FileCheck %s +// RUN: cat %s | clang-repl -Xcc -fno-discard-value-names -Xcc -Xclang -Xcc -emit-llvm \ +// RUN: | FileCheck %s extern "C" int f_o0(int x) { return x; } // CHECK: ; Function Attrs: {{.*}}noinline {{.*}}optnone From 5916210dbe10049c264ecf0a0ad685d101c392d9 Mon Sep 17 00:00:00 2001 From: Ivan Butygin Date: Sat, 24 Oct 2026 17:13:59 +0200 Subject: [PATCH 02/31] [mlir] Find the pattern dump root only when IR debugging is enabled (#233771) Extracted from https://github.com/llvm/llvm-project/pull/231423 `PatternApplicator` debug printing was unconditionally calling `getDumpRootOp` which walks nested ops chains. This was taking a noticeable time in synthetic 1000-nested test. Call `getDumpRootOp` only if printing is actually enabled. --- mlir/lib/Rewrite/PatternApplicator.cpp | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/mlir/lib/Rewrite/PatternApplicator.cpp b/mlir/lib/Rewrite/PatternApplicator.cpp index e1b56fd6efda00..fc415e7dbb3847 100644 --- a/mlir/lib/Rewrite/PatternApplicator.cpp +++ b/mlir/lib/Rewrite/PatternApplicator.cpp @@ -200,7 +200,10 @@ LogicalResult PatternApplicator::matchAndRewrite( #ifndef NDEBUG // Operation `op` may be invalidated after applying the rewrite // pattern. - Operation *dumpRootOp = getDumpRootOp(op); + Operation *dumpRootOp = nullptr; + // Only find the dump root when level-2 IR debugging is enabled. + if (llvm::DebugFlag && llvm::isCurrentDebugType(DEBUG_TYPE, 2)) + dumpRootOp = getDumpRootOp(op); #endif if (pdlMatch) { result = From 127d4f032302e315e03b78f40a535fcad13f7a55 Mon Sep 17 00:00:00 2001 From: Daniel Petrovic Date: Sat, 24 Oct 2026 17:31:48 +0200 Subject: [PATCH 03/31] =?UTF-8?q?[clang-tidy]=20Don't=20suggest=20const=20?= =?UTF-8?q?on=20`std::moved`=20locals=20in=20templates=20=E2=80=A6=20(#226?= =?UTF-8?q?577)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit [clang-tidy] Don't suggest const on std::moved locals in templates Skip diagnostics in template instantiations for locals that are used as arguments of std::move. Reason: for some instantiations the move may be converted to copy so the variable may look unmutated and flagged, whereas for other template instantiations the real move semantics may apply. Fixes: #225395 Assisted by Gemini for constructing the matcher. --------- Co-authored-by: Zeyi Xu --- .../clang-tidy/misc/ConstCorrectnessCheck.cpp | 30 +++++++++++++++++-- clang-tools-extra/docs/ReleaseNotes.md | 8 +++-- .../misc/const-correctness-templates.cpp | 20 +++++++++++++ 3 files changed, 53 insertions(+), 5 deletions(-) diff --git a/clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp b/clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp index 90919555d447e8..4532a27962af29 100644 --- a/clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp +++ b/clang-tools-extra/clang-tidy/misc/ConstCorrectnessCheck.cpp @@ -199,6 +199,25 @@ void ConstCorrectnessCheck::registerMatchers(MatchFinder *Finder) { } } +static bool isStdMoveOperandInTemplate(const VarDecl *Variable, + const FunctionDecl *Func, + ASTContext &Context) { + if (Func->isTemplateInstantiation()) + if (const Stmt *Body = Func->getBody()) { + // Match on the instantiated body where `std::move` is resolved to a + // concrete function and the argument references the instantiated + // variable. + const auto Moves = + match(stmt(forEachDescendant( + callExpr(callee(functionDecl(hasName("std::move"))), + hasArgument(0, ignoringParenImpCasts(declRefExpr( + to(equalsNode(Variable)))))))), + *Body, Context); + return !Moves.empty(); + } + return false; +} + static void addConstFixits(const DiagnosticBuilder &Diag, const VarDecl *Variable, const FunctionDecl *Function, @@ -255,9 +274,6 @@ void ConstCorrectnessCheck::check(const MatchFinder::MatchResult &Result) { /// dependent. Variables like 'int x = 42;' in a template that can become /// const emit multiple warnings otherwise. bool IsNormalVariableInTemplate = Function->isTemplateInstantiation(); - if (IsNormalVariableInTemplate && - TemplateDiagnosticsCache.contains(Variable->getBeginLoc())) - return; VariableCategory VC = VariableCategory::Value; const QualType VT = Variable->getType(); @@ -269,6 +285,14 @@ void ConstCorrectnessCheck::check(const MatchFinder::MatchResult &Result) { ArrayT && ArrayT->getElementType()->isPointerType()) VC = VariableCategory::Pointer; + if (IsNormalVariableInTemplate && VC != VariableCategory::Pointer && + isStdMoveOperandInTemplate(Variable, Function, *Result.Context)) + return; + + if (IsNormalVariableInTemplate && + TemplateDiagnosticsCache.contains(Variable->getBeginLoc())) + return; + const auto CheckValue = [&]() { // Offload const-analysis to utility function. if (isMutated(Variable, LocalScope, Function, Result.Context)) diff --git a/clang-tools-extra/docs/ReleaseNotes.md b/clang-tools-extra/docs/ReleaseNotes.md index 57ed93042aff2c..037df4cd0937c4 100644 --- a/clang-tools-extra/docs/ReleaseNotes.md +++ b/clang-tools-extra/docs/ReleaseNotes.md @@ -261,10 +261,14 @@ infrastructure are described first, followed by tool-specific sections. - No longer diagnoses variables declared with `decltype(auto)`, where the suggested `const` does not compile. - + - No longer diagnoses parameters of `main`, whose signature is fixed by the standard. + - No longer diagnoses variables used as operands of `std::move` in template + instantiations, where the suggested `const` would break the move for + instantiations with real move semantics. + - Fixed an infinite loop in {doc}`misc-multiple-inheritance ` when checking a class that inherits from itself or has a circular inheritance graph. @@ -429,7 +433,7 @@ infrastructure are described first, followed by tool-specific sections. - Ignored preprocessor directives such as `#endif` that appear immediately before an enum's closing brace, which previously produced a false positive and a fix-it that inserted a comma after the directive. - + - Fixed a false positive on empty brace initializers of types with default member initializers. diff --git a/clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-templates.cpp b/clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-templates.cpp index 98bf27033c3b5f..624159210698c5 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-templates.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/misc/const-correctness-templates.cpp @@ -6,6 +6,9 @@ // RUN: misc-const-correctness.TransformPointersAsValues: false} \ // RUN: }" -- -fno-delayed-template-parsing +#include +#include + template void type_dependent_variables() { T value = 42; @@ -27,6 +30,23 @@ void instantiate_template_cases() { type_dependent_variables(); } +namespace gh225395 { + +template void my_swap(T &t1, T &t2) { + auto tmp = std::move(t1); + t1 = std::move(t2); + t2 = std::move(tmp); +} +void instantiate() { + std::string a; + std::string b; + my_swap(a, b); + int x = 0; + int y = 0; + my_swap(x, y); +} +} // namespace gh225395 + namespace gh57297{ // The expression to check may not be the dependent operand in a dependent // operator. From bfe094117ba828cd338ac415bf0f7e98f8b8d4c8 Mon Sep 17 00:00:00 2001 From: Federico Bruzzone Date: Sat, 24 Oct 2026 17:40:41 +0200 Subject: [PATCH 04/31] [mlir][linalg] Handle `DropPadUnitDims` when padding value is defined inside the pad body (#223712) `DropPadUnitDims` reused the pad's padding value as-is when building the replacement `tensor.pad`. If that value was defined inside the original pad's own body, the new op ended up referencing it from outside its region, and erasing the original pad then hit an assertion. This PR clone the defining op when the padding value lives inside the pad body. Fixes #203813 --------- Signed-off-by: Federico Bruzzone --- .../Linalg/Transforms/DropUnitDims.cpp | 4 ++ .../Dialect/Linalg/drop-unit-extent-dims.mlir | 43 +++++++++++++++++++ 2 files changed, 47 insertions(+) diff --git a/mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp b/mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp index 75e6fc9491129e..40dc35ce6babbf 100644 --- a/mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp +++ b/mlir/lib/Dialect/Linalg/Transforms/DropUnitDims.cpp @@ -702,6 +702,10 @@ struct DropPadUnitDims : public OpRewritePattern { return rewriter.notifyMatchFailure(padOp, "Failed to collapse source"); } + // Clone the padding value if it is defined in the region of the pad op. + if (paddingVal.getParentBlock() == &padOp.getRegion().front()) + paddingVal = rewriter.clone(*paddingVal.getDefiningOp())->getResult(0); + auto newResultType = RankedTensorType::get( newResultShape, padOp.getResultType().getElementType()); auto newPadOp = tensor::PadOp::create( diff --git a/mlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir b/mlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir index 841d0e5f565125..0c289823557fd5 100644 --- a/mlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir +++ b/mlir/test/Dialect/Linalg/drop-unit-extent-dims.mlir @@ -1032,6 +1032,49 @@ func.func @drop_unit_pad_dynamic_dims(%arg0: tensor<1x?xf32>) -> tensor<1x?xf32> // ----- +func.func @drop_unit_pad_dims_constant_inside_body(%arg0: tensor<1x28x28x1xf32>) -> tensor<1x32x32x1xf32> +{ + %0 = tensor.pad %arg0 low[0, 2, 2, 0] high[0, 2, 2, 0] { + ^bb0(%arg1: index, %arg2: index, %arg3: index, %arg4: index): + %cst = arith.constant 0.0 : f32 + tensor.yield %cst : f32 + } : tensor<1x28x28x1xf32> to tensor<1x32x32x1xf32> + return %0 : tensor<1x32x32x1xf32> +} + +// CHECK-LABEL: func @drop_unit_pad_dims_constant_inside_body +// CHECK: %[[CST:.+]] = arith.constant 0.000000e+00 : f32 +// CHECK: %[[COLLAPSE:.+]] = tensor.collapse_shape +// CHECK-SAME: {{\[}}[0, 1], [2, 3]{{\]}} : tensor<1x28x28x1xf32> into tensor<28x28xf32> +// CHECK: %[[PADDED:.+]] = tensor.pad %[[COLLAPSE]] low[2, 2] high[2, 2] +// CHECK: tensor.yield %[[CST]] +// CHECK: } : tensor<28x28xf32> to tensor<32x32xf32> +// CHECK: tensor.expand_shape %[[PADDED]] +// CHECK-SAME: {{\[}}[0, 1], [2, 3]{{\]}} output_shape [1, 32, 32, 1] : tensor<32x32xf32> into tensor<1x32x32x1xf32> + +// ----- + +// The pattern must not modify the IR when there are no unit dims to drop. + +func.func @negative_drop_pad_without_unit_dims_constant_inside_body(%arg0: tensor<2xf32>) -> tensor<3xf32> +{ + %0 = tensor.pad %arg0 low[0] high[1] { + ^bb0(%arg1: index): + %cst = arith.constant 0.0 : f32 + tensor.yield %cst : f32 + } : tensor<2xf32> to tensor<3xf32> + return %0 : tensor<3xf32> +} + +// CHECK-LABEL: func @negative_drop_pad_without_unit_dims_constant_inside_body +// CHECK-NOT: tensor.collapse_shape +// CHECK: %[[CST:.+]] = arith.constant 0.000000e+00 : f32 +// CHECK: tensor.pad %{{.*}} low[0] high[1] +// CHECK: tensor.yield %[[CST]] +// CHECK-NOT: tensor.expand_shape + +// ----- + func.func @do_not_drop_non_constant_padding(%arg0: tensor<1x1x3x1x1xf32>, %pad: f32) -> tensor<1x2x3x1x3xf32> { %c0 = arith.constant 0 : index From a98c5c2b79b6afe17e831f4962f7f1fa27e9ad86 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 24 Oct 2026 09:09:18 -0700 Subject: [PATCH 05/31] [SelectionDAG] Implement SDTCisSameAs in verifyNode. (#235157) Assisted-by: Claude --- llvm/lib/CodeGen/SelectionDAG/SDNodeInfo.cpp | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/SDNodeInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/SDNodeInfo.cpp index f5042aef054838..029dd583c2736f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SDNodeInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SDNodeInfo.cpp @@ -277,8 +277,17 @@ void SDNodeInfo::verifyNode(const SelectionDAG &DAG, const SDNode *N) const { reportNodeError(DAG, N, SS.str()); } break; - case SDTCisSameAs: + case SDTCisSameAs: { + SDNodeValue OtherVal = GetConstraintValue(C.ConstrainingValIdx); + EVT OtherVT = OtherVal.getValueType(); + + if (VT != OtherVT) { + SS << Val << " must have the same type as " << OtherVal << " (" + << OtherVT << "), but has type " << VT; + reportNodeError(DAG, N, SS.str()); + } break; + } case SDTCisVTSmallerThanOp: { const auto *VTNode = dyn_cast(Val.getValue().getNode()); if (!VTNode) { From 45e57b7dc4019258349b2bc1e28e9075ad1014ec Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 24 Oct 2026 09:09:37 -0700 Subject: [PATCH 06/31] [TargetLowering] Don't call SignBitIsZero for ABDS in expandABD. (#235134) --- llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index 0458f1109f54fb..6f63f9ff908d4e 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -11698,8 +11698,8 @@ SDValue TargetLowering::expandABD(SDNode *N, SelectionDAG &DAG) const { // abds, or abdu with non-negative operands: if the sub is nsw, abs(sub). // Otherwise abdu: if the sub is nuw then lhs >= rhs, so just sub. - bool IsNonNegative = DAG.SignBitIsZero(LHS) && DAG.SignBitIsZero(RHS); - bool UseSigned = IsSigned || IsNonNegative; + bool UseSigned = + IsSigned || (DAG.SignBitIsZero(LHS) && DAG.SignBitIsZero(RHS)); if (DAG.willNotOverflowSub(UseSigned, LHS, RHS)) { SDValue Sub = DAG.getNode(ISD::SUB, dl, VT, LHS, RHS); From e339ea8d26be09465cc6cff196ad7a4ddac30194 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 24 Oct 2026 09:09:59 -0700 Subject: [PATCH 07/31] [DAGCombiner] Delay calls to willNotOverflow and SignBitIsZero in foldABSToABD. (#235129) Do the cheaper hasOperation checks first --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 956f0d62a17192..43213a82ca1fe0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -12410,21 +12410,16 @@ SDValue DAGCombiner::foldABSToABD(SDNode *N, const SDLoc &DL) { // fold (abs (sub nsw x, y)) -> abds(x, y) // fold (abs (add nsw x, -y)) -> abds(x, y) - bool AbsOpWillNSW = - AbsOp0->getFlags().hasNoSignedWrap() || - (IsAdd ? DAG.willNotOverflowAdd(/*IsSigned=*/true, Op0, Op1) - : DAG.willNotOverflowSub(/*IsSigned=*/true, Op0, Op1)); - // Don't fold this for unsupported types as we lose the NSW handling. if (hasOperation(ISD::ABDS, VT) && TLI.preferABDSToABSWithNSW(VT) && - AbsOpWillNSW) + (AbsOp0->getFlags().hasNoSignedWrap() || + (IsAdd ? DAG.willNotOverflowAdd(/*IsSigned=*/true, Op0, Op1) + : DAG.willNotOverflowSub(/*IsSigned=*/true, Op0, Op1)))) return CreateZextedAbd(ISD::ABDS); // fold (abs (sub x, y)) -> abdu(x, y) - bool AbsOpWillNUW = - !IsAdd && DAG.SignBitIsZero(Op0) && DAG.SignBitIsZero(Op1); - - if (hasOperation(ISD::ABDU, VT) && AbsOpWillNUW) + if (!IsAdd && hasOperation(ISD::ABDU, VT) && DAG.SignBitIsZero(Op0) && + DAG.SignBitIsZero(Op1)) return CreateZextedAbd(ISD::ABDU); return SDValue(); From cfe60cf9d134a336d08aa74d2f72ca5c7b8d4e4b Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 24 Oct 2026 09:10:19 -0700 Subject: [PATCH 08/31] [RISCV] Use vector getConstant. NFC (#235152) It will eventually be legalized to a splat_vector and constant, but we usually use a vector getConstant so let's be consistent. --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index ebbcf93cce642b..a86115f9b36a95 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -13721,8 +13721,7 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, Rs2 = DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v4i16, Rs2, DAG.getUNDEF(MVT::v2i16)); if (IntNo == Intrinsic::riscv_pwmaccsu_i32x2) { - SDValue Zero = DAG.getNode(ISD::SPLAT_VECTOR, DL, MVT::v4i16, - DAG.getConstant(0, DL, XLenVT)); + SDValue Zero = DAG.getConstant(0, DL, MVT::v4i16); Rs1 = DAG.getNode(RISCVISD::PZIP, DL, MVT::v4i16, Rs1, Zero); Rs2 = DAG.getNode(RISCVISD::PZIP, DL, MVT::v4i16, Rs2, Zero); return DAG.getNode(RISCVISD::PMACCSU_HALVES_00, DL, VT, Acc, Rs1, Rs2); From 3736dfed9eaa38651d8f8b8ac67693a7fa5d5402 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 24 Oct 2026 09:11:21 -0700 Subject: [PATCH 09/31] [SelectionDAG][RISCV][X86] Keep jump table range checks with cf-protection-branch (#234733) When the default of a switch is unreachable, SelectionDAGBuilder elides the jump table range check, except when ARM branch-target-enforcement is enabled, since an unchecked table branch can be a JOP gadget. Extend this to the cf-protection-branch module flag used by RISC-V Zicfilp and X86 IBT. The module flag is merged with Module::Min behavior, so a value of 0 is treated as not enabled. Assisted-by: Claude --- .../SelectionDAG/SelectionDAGBuilder.cpp | 22 ++- .../CodeGen/RISCV/jumptable-cf-protection.ll | 117 +++++++++++++++ .../CodeGen/X86/jumptable-cf-protection.ll | 142 ++++++++++++++++++ 3 files changed, 273 insertions(+), 8 deletions(-) create mode 100644 llvm/test/CodeGen/RISCV/jumptable-cf-protection.ll create mode 100644 llvm/test/CodeGen/X86/jumptable-cf-protection.ll diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 58be54855abdea..48c9eedf7b9946 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -12795,16 +12795,22 @@ void SelectionDAGBuilder::lowerWorkItem(SwitchWorkListItem W, Value *Cond, // JTH->FallthroughUnreachable which will use it to suppress the range // check. // - // However, don't do this if we're doing branch target enforcement, - // because a table branch _without_ a range check can be a tempting JOP - // gadget - out-of-bounds inputs that are impossible in correct - // execution become possible again if an attacker can influence the - // control flow. So if an attacker doesn't already have a BTI bypass - // available, we don't want them to be able to get one out of this - // table branch. + // However, don't do this if we're doing branch target enforcement + // (e.g. Arm BTI, or the cf-protection-branch module flag used by + // RISC-V Zicfilp and X86 IBT), because a table branch _without_ a + // range check can be a tempting JOP gadget - out-of-bounds inputs + // that are impossible in correct execution become possible again if + // an attacker can influence the control flow. So if an attacker + // doesn't already have a branch target enforcement bypass available, + // we don't want them to be able to get one out of this table branch. if (FallthroughUnreachable) { Function &CurFunc = CurMF->getFunction(); - if (!CurFunc.hasFnAttribute("branch-target-enforcement")) + bool HasCFBranch = false; + if (auto *CFBranch = mdconst::extract_or_null( + CurFunc.getParent()->getModuleFlag("cf-protection-branch"))) + HasCFBranch = !CFBranch->isZero(); + if (!HasCFBranch && + !CurFunc.hasFnAttribute("branch-target-enforcement")) JTH->FallthroughUnreachable = true; } diff --git a/llvm/test/CodeGen/RISCV/jumptable-cf-protection.ll b/llvm/test/CodeGen/RISCV/jumptable-cf-protection.ll new file mode 100644 index 00000000000000..ae54ee134b5b0b --- /dev/null +++ b/llvm/test/CodeGen/RISCV/jumptable-cf-protection.ll @@ -0,0 +1,117 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefix=NOCF +; RUN: sed 's/^;ZEROFLAG //' %s | llc -mtriple=riscv64 | FileCheck %s --check-prefix=NOCF +; RUN: sed 's/^;BRANCHFLAG //' %s | llc -mtriple=riscv64 | FileCheck %s --check-prefix=CF + +; With an unreachable default, the jump table range check can be elided unless +; cf-protection-branch is enabled. Without the range check, the table branch +; could be a JOP gadget. A value of 0 means the flag is not enabled, which +; can happen when linking merges the Min flag. + +define i32 @switch_unreachable_default(i32 signext %x) { +; NOCF-LABEL: switch_unreachable_default: +; NOCF: # %bb.0: # %entry +; NOCF-NEXT: lui a1, %hi(.LJTI0_0) +; NOCF-NEXT: addi a1, a1, %lo(.LJTI0_0) +; NOCF-NEXT: slli a0, a0, 2 +; NOCF-NEXT: add a0, a1, a0 +; NOCF-NEXT: lw a0, 0(a0) +; NOCF-NEXT: jr a0 +; NOCF-NEXT: .LBB0_1: # %b0 +; NOCF-NEXT: li a0, 10 +; NOCF-NEXT: ret +; NOCF-NEXT: .LBB0_2: # %b4 +; NOCF-NEXT: li a0, 54 +; NOCF-NEXT: ret +; NOCF-NEXT: .LBB0_3: # %b2 +; NOCF-NEXT: li a0, 32 +; NOCF-NEXT: ret +; NOCF-NEXT: .LBB0_4: # %b3 +; NOCF-NEXT: li a0, 43 +; NOCF-NEXT: ret +; NOCF-NEXT: .LBB0_5: # %b7 +; NOCF-NEXT: li a0, 87 +; NOCF-NEXT: ret +; NOCF-NEXT: .LBB0_6: # %b1 +; NOCF-NEXT: li a0, 21 +; NOCF-NEXT: ret +; NOCF-NEXT: .LBB0_7: # %b5 +; NOCF-NEXT: li a0, 65 +; NOCF-NEXT: ret +; NOCF-NEXT: .LBB0_8: # %b6 +; NOCF-NEXT: li a0, 76 +; NOCF-NEXT: ret +; +; CF-LABEL: switch_unreachable_default: +; CF: # %bb.0: # %entry +; CF-NEXT: lpad 0 +; CF-NEXT: li a1, 7 +; CF-NEXT: bltu a1, a0, .LBB0_10 +; CF-NEXT: # %bb.1: # %entry +; CF-NEXT: slli a0, a0, 2 +; CF-NEXT: lui a1, %hi(.LJTI0_0) +; CF-NEXT: addi a1, a1, %lo(.LJTI0_0) +; CF-NEXT: add a0, a1, a0 +; CF-NEXT: lw t2, 0(a0) +; CF-NEXT: jr t2 +; CF-NEXT: .LBB0_2: # %b0 +; CF-NEXT: li a0, 10 +; CF-NEXT: ret +; CF-NEXT: .LBB0_3: # %b4 +; CF-NEXT: li a0, 54 +; CF-NEXT: ret +; CF-NEXT: .LBB0_4: # %b2 +; CF-NEXT: li a0, 32 +; CF-NEXT: ret +; CF-NEXT: .LBB0_5: # %b3 +; CF-NEXT: li a0, 43 +; CF-NEXT: ret +; CF-NEXT: .LBB0_6: # %b7 +; CF-NEXT: li a0, 87 +; CF-NEXT: ret +; CF-NEXT: .LBB0_7: # %b1 +; CF-NEXT: li a0, 21 +; CF-NEXT: ret +; CF-NEXT: .LBB0_8: # %b5 +; CF-NEXT: li a0, 65 +; CF-NEXT: ret +; CF-NEXT: .LBB0_9: # %b6 +; CF-NEXT: li a0, 76 +; CF-NEXT: ret +; CF-NEXT: .LBB0_10: # %def +entry: + switch i32 %x, label %def [ + i32 0, label %b0 + i32 1, label %b1 + i32 2, label %b2 + i32 3, label %b3 + i32 4, label %b4 + i32 5, label %b5 + i32 6, label %b6 + i32 7, label %b7 + ] +def: + unreachable +b0: + ret i32 10 +b1: + ret i32 21 +b2: + ret i32 32 +b3: + ret i32 43 +b4: + ret i32 54 +b5: + ret i32 65 +b6: + ret i32 76 +b7: + ret i32 87 +} + +;ZEROFLAG !llvm.module.flags = !{!0} +;ZEROFLAG !0 = !{i32 8, !"cf-protection-branch", i32 0} +;BRANCHFLAG !llvm.module.flags = !{!0, !1} +;BRANCHFLAG !0 = !{i32 8, !"cf-protection-branch", i32 1} +;BRANCHFLAG !1 = !{i32 1, !"cf-branch-label-scheme", !"unlabeled"} diff --git a/llvm/test/CodeGen/X86/jumptable-cf-protection.ll b/llvm/test/CodeGen/X86/jumptable-cf-protection.ll new file mode 100644 index 00000000000000..aaf466587f38c5 --- /dev/null +++ b/llvm/test/CodeGen/X86/jumptable-cf-protection.ll @@ -0,0 +1,142 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc -mtriple=x86_64 < %s | FileCheck %s --check-prefix=NOCF +; RUN: sed 's/^;ZEROFLAG //' %s | llc -mtriple=x86_64 | FileCheck %s --check-prefix=ZERO +; RUN: sed 's/^;BRANCHFLAG //' %s | llc -mtriple=x86_64 | FileCheck %s --check-prefix=CF + +; With an unreachable default, the jump table range check can be elided unless +; cf-protection-branch is enabled. Without the range check, the table branch +; could be a JOP gadget. A value of 0 means the flag is not enabled, which +; can happen when linking merges the Min flag. +; +; X86 currently only checks for the presence of the flag when emitting endbr64 +; and notrack, so the ZERO prefix still sees those, but the range check is +; elided for a value of 0. + +define i32 @switch_unreachable_default(i32 signext %x) { +; NOCF-LABEL: switch_unreachable_default: +; NOCF: # %bb.0: # %entry +; NOCF-NEXT: movl %edi, %eax +; NOCF-NEXT: jmpq *.LJTI0_0(,%rax,8) +; NOCF-NEXT: .LBB0_1: # %b0 +; NOCF-NEXT: movl $10, %eax +; NOCF-NEXT: retq +; NOCF-NEXT: .LBB0_5: # %b4 +; NOCF-NEXT: movl $54, %eax +; NOCF-NEXT: retq +; NOCF-NEXT: .LBB0_3: # %b2 +; NOCF-NEXT: movl $32, %eax +; NOCF-NEXT: retq +; NOCF-NEXT: .LBB0_4: # %b3 +; NOCF-NEXT: movl $43, %eax +; NOCF-NEXT: retq +; NOCF-NEXT: .LBB0_8: # %b7 +; NOCF-NEXT: movl $87, %eax +; NOCF-NEXT: retq +; NOCF-NEXT: .LBB0_2: # %b1 +; NOCF-NEXT: movl $21, %eax +; NOCF-NEXT: retq +; NOCF-NEXT: .LBB0_6: # %b5 +; NOCF-NEXT: movl $65, %eax +; NOCF-NEXT: retq +; NOCF-NEXT: .LBB0_7: # %b6 +; NOCF-NEXT: movl $76, %eax +; NOCF-NEXT: retq +; +; ZERO-LABEL: switch_unreachable_default: +; ZERO: # %bb.0: # %entry +; ZERO-NEXT: endbr64 +; ZERO-NEXT: movl %edi, %eax +; ZERO-NEXT: notrack jmpq *.LJTI0_0(,%rax,8) +; ZERO-NEXT: .LBB0_1: # %b0 +; ZERO-NEXT: movl $10, %eax +; ZERO-NEXT: retq +; ZERO-NEXT: .LBB0_5: # %b4 +; ZERO-NEXT: movl $54, %eax +; ZERO-NEXT: retq +; ZERO-NEXT: .LBB0_3: # %b2 +; ZERO-NEXT: movl $32, %eax +; ZERO-NEXT: retq +; ZERO-NEXT: .LBB0_4: # %b3 +; ZERO-NEXT: movl $43, %eax +; ZERO-NEXT: retq +; ZERO-NEXT: .LBB0_8: # %b7 +; ZERO-NEXT: movl $87, %eax +; ZERO-NEXT: retq +; ZERO-NEXT: .LBB0_2: # %b1 +; ZERO-NEXT: movl $21, %eax +; ZERO-NEXT: retq +; ZERO-NEXT: .LBB0_6: # %b5 +; ZERO-NEXT: movl $65, %eax +; ZERO-NEXT: retq +; ZERO-NEXT: .LBB0_7: # %b6 +; ZERO-NEXT: movl $76, %eax +; ZERO-NEXT: retq +; +; CF-LABEL: switch_unreachable_default: +; CF: # %bb.0: # %entry +; CF-NEXT: endbr64 +; CF-NEXT: cmpl $7, %edi +; CF-NEXT: ja .LBB0_2 +; CF-NEXT: # %bb.1: # %entry +; CF-NEXT: movl %edi, %eax +; CF-NEXT: notrack jmpq *.LJTI0_0(,%rax,8) +; CF-NEXT: .LBB0_3: # %b0 +; CF-NEXT: movl $10, %eax +; CF-NEXT: retq +; CF-NEXT: .LBB0_7: # %b4 +; CF-NEXT: movl $54, %eax +; CF-NEXT: retq +; CF-NEXT: .LBB0_5: # %b2 +; CF-NEXT: movl $32, %eax +; CF-NEXT: retq +; CF-NEXT: .LBB0_6: # %b3 +; CF-NEXT: movl $43, %eax +; CF-NEXT: retq +; CF-NEXT: .LBB0_10: # %b7 +; CF-NEXT: movl $87, %eax +; CF-NEXT: retq +; CF-NEXT: .LBB0_4: # %b1 +; CF-NEXT: movl $21, %eax +; CF-NEXT: retq +; CF-NEXT: .LBB0_8: # %b5 +; CF-NEXT: movl $65, %eax +; CF-NEXT: retq +; CF-NEXT: .LBB0_9: # %b6 +; CF-NEXT: movl $76, %eax +; CF-NEXT: retq +; CF-NEXT: .LBB0_2: # %def +entry: + switch i32 %x, label %def [ + i32 0, label %b0 + i32 1, label %b1 + i32 2, label %b2 + i32 3, label %b3 + i32 4, label %b4 + i32 5, label %b5 + i32 6, label %b6 + i32 7, label %b7 + ] +def: + unreachable +b0: + ret i32 10 +b1: + ret i32 21 +b2: + ret i32 32 +b3: + ret i32 43 +b4: + ret i32 54 +b5: + ret i32 65 +b6: + ret i32 76 +b7: + ret i32 87 +} + +;ZEROFLAG !llvm.module.flags = !{!0} +;ZEROFLAG !0 = !{i32 8, !"cf-protection-branch", i32 0} +;BRANCHFLAG !llvm.module.flags = !{!0} +;BRANCHFLAG !0 = !{i32 8, !"cf-protection-branch", i32 1} From 7bcef9facae727c9d2be1e4536bf3de21458968d Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 24 Oct 2026 09:11:25 -0700 Subject: [PATCH 10/31] RegAlloc: Only def the subregister regunits of a failed subregister def (#235307) After an allocation failure, cleanupFailedDefs added each failed def to the live ranges of all regunits of the assigned register. A subregister def only writes the subregister, so the remaining units got a def from an instruction that does not modify them, which the verifier rejects. Fixes ran-out-of-registers-errors.ll with EXPENSIVE_CHECKS after #233796. Co-authored-by: Claude Opus 5.5 --- llvm/lib/CodeGen/RegAllocBase.cpp | 6 ++++- .../regalloc-failure-subreg-def-regunits.mir | 26 +++++++++++++++++++ 2 files changed, 31 insertions(+), 1 deletion(-) create mode 100644 llvm/test/CodeGen/AMDGPU/regalloc-failure-subreg-def-regunits.mir diff --git a/llvm/lib/CodeGen/RegAllocBase.cpp b/llvm/lib/CodeGen/RegAllocBase.cpp index 0741e954bcc150..c6f078a63722fc 100644 --- a/llvm/lib/CodeGen/RegAllocBase.cpp +++ b/llvm/lib/CodeGen/RegAllocBase.cpp @@ -216,8 +216,12 @@ void RegAllocBase::cleanupFailedDefs(MachineInstr &MI, Register FailedReg, // Add the def to the PhysReg regunit ranges so it interferes with later // assignments. Ranges computed later will include the rewritten def. + MCRegister DefReg = PhysReg; + if (MO.getSubReg()) + DefReg = TRI->getSubReg(PhysReg, MO.getSubReg()); + SlotIndex DefIdx = Idx.getRegSlot(MO.isEarlyClobber()); - for (MCRegUnit Unit : TRI->regunits(PhysReg)) { + for (MCRegUnit Unit : TRI->regunits(DefReg)) { LiveRange *LR = LIS->getCachedRegUnit(Unit); if (LR && !LR->liveAt(DefIdx)) LR->createDeadDef(DefIdx, LIS->getVNInfoAllocator()); diff --git a/llvm/test/CodeGen/AMDGPU/regalloc-failure-subreg-def-regunits.mir b/llvm/test/CodeGen/AMDGPU/regalloc-failure-subreg-def-regunits.mir new file mode 100644 index 00000000000000..6195d7b6eddc4e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/regalloc-failure-subreg-def-regunits.mir @@ -0,0 +1,26 @@ +# RUN: not llc -mtriple=amdgpu9.08-amd-amdhsa -stress-regalloc=1 -run-pass=regallocbasic -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error %s +# RUN: not llc -mtriple=amdgpu9.08-amd-amdhsa -stress-regalloc=1 -run-pass=greedy -filetype=null %s 2>&1 | FileCheck -implicit-check-not=error %s + +# The failed subregister def should only def the subregister's regunits. + +# CHECK: error: :0:0: ran out of registers during register allocation in function 'subreg_def' + +--- +name: subreg_def +tracksRegLiveness: true +machineFunctionInfo: + scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3' + stackPtrOffsetReg: '$sgpr32' +body: | + bb.0: + liveins: $vgpr0, $vgpr1 + + undef %0.sub1:vreg_64 = COPY $vgpr1 + %0.sub0:vreg_64 = COPY $vgpr0 + %1:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (volatile load (s32), addrspace 1) + %2:vgpr_32 = GLOBAL_LOAD_DWORD %0, 0, 0, implicit $exec :: (volatile load (s32), addrspace 1) + KILL %0.sub0, %0.sub1 + %3:vgpr_32 = V_ADD_U32_e32 %1, %2, implicit $exec + $vgpr0 = COPY %3 + SI_RETURN implicit $vgpr0 +... From e8eba6e3e7b9baf06931bd3cd9f1e45ccaf1f21b Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 24 Oct 2026 09:52:45 -0700 Subject: [PATCH 11/31] AMDGPU: Don't reserve the implicit buffer pointer with architected flat scratch (#235258) Mesa shaders always had s[0:1] reserved for the implicit buffer pointer, which is only needed to set up the scratch buffer resource. With architected flat scratch, scratch is initialized by the hardware and the pointer is unused. The driver stopped passing this pointer so all user SGPRs were off by 2. Don't reserve it on targets with architected flat scratch, so the user SGPRs of Mesa shaders start at s0. Diagnose the use in the unsupported contexts. This fixes many test failures on my system when running piglit. Co-authored-by: Claude Opus 5.5 --- llvm/docs/AMDGPUUsage.md | 7 + .../lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp | 18 +- llvm/lib/Target/AMDGPU/GCNSubtarget.cpp | 4 +- llvm/lib/Target/AMDGPU/SIISelLowering.cpp | 14 +- .../test/CodeGen/AMDGPU/GlobalISel/add_shl.ll | 46 +- llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll | 266 +- .../GlobalISel/clamp-minmax-const-combine.ll | 20 +- .../GlobalISel/constant-bus-restriction.ll | 198 +- .../AMDGPU/GlobalISel/extractelement.i128.ll | 20 +- .../AMDGPU/GlobalISel/extractelement.i16.ll | 48 +- .../AMDGPU/GlobalISel/extractelement.i8.ll | 66 +- .../AMDGPU/GlobalISel/extractelement.ll | 1247 ++++---- .../AMDGPU/GlobalISel/insertelement.i16.ll | 288 +- .../AMDGPU/GlobalISel/insertelement.i8.ll | 219 +- .../AMDGPU/GlobalISel/insertelement.ll | 1594 +++++----- ...galize-llvm.amdgcn.image.atomic.dim.a16.ll | 1034 +++++-- .../legalize-llvm.amdgcn.image.dim.a16.ll | 2564 ++++++++++++++--- ...lize-llvm.amdgcn.image.load.2darraymsaa.ll | 62 +- .../legalize-llvm.amdgcn.image.load.3d.ll | 49 +- .../legalize-llvm.amdgcn.image.sample.a16.ll | 2444 ++++++++-------- .../legalize-llvm.amdgcn.image.sample.d.ll | 208 +- ...galize-llvm.amdgcn.image.sample.g16.a16.ll | 156 +- .../legalize-llvm.amdgcn.image.sample.g16.ll | 988 +++---- ...legalize-llvm.amdgcn.image.store.2d.d16.ll | 176 +- .../llvm.amdgcn.image.atomic.dim.a16.ll | 1428 +-------- .../llvm.amdgcn.image.atomic.dim.ll | 616 ++-- .../llvm.amdgcn.image.gather4.a16.dim.ll | 864 +----- .../llvm.amdgcn.image.gather4.dim.ll | 431 ++- .../llvm.amdgcn.image.getresinfo.a16.ll | 278 +- .../llvm.amdgcn.image.getresinfo.ll | 160 +- .../llvm.amdgcn.image.load.1d.d16.ll | 236 +- .../GlobalISel/llvm.amdgcn.image.load.1d.ll | 255 +- .../GlobalISel/llvm.amdgcn.image.load.2d.ll | 94 +- .../llvm.amdgcn.image.load.2darraymsaa.a16.ll | 118 +- .../llvm.amdgcn.image.load.2darraymsaa.ll | 94 +- .../llvm.amdgcn.image.load.3d.a16.ll | 150 +- .../GlobalISel/llvm.amdgcn.image.load.3d.ll | 94 +- .../GlobalISel/llvm.amdgcn.image.store.2d.ll | 180 +- .../llvm.amdgcn.ptr.s.buffer.load.ll | 522 ++-- .../llvm.amdgcn.raw.buffer.atomic.add.ll | 132 +- .../llvm.amdgcn.raw.buffer.atomic.cmpswap.ll | 224 +- .../llvm.amdgcn.raw.buffer.atomic.sub.ll | 132 +- .../llvm.amdgcn.raw.buffer.atomic.swap.ll | 132 +- .../llvm.amdgcn.raw.buffer.load.format.f16.ll | 94 +- .../llvm.amdgcn.raw.buffer.load.format.ll | 88 +- .../GlobalISel/llvm.amdgcn.raw.buffer.load.ll | 470 +-- ...llvm.amdgcn.raw.buffer.store.format.f16.ll | 112 +- ...llvm.amdgcn.raw.buffer.store.format.f32.ll | 124 +- .../llvm.amdgcn.raw.buffer.store.ll | 534 ++-- .../llvm.amdgcn.raw.ptr.buffer.load.ll | 390 +-- ...llvm.amdgcn.raw.ptr.buffer.offset-split.ll | 14 +- .../llvm.amdgcn.raw.ptr.tbuffer.load.ll | 188 +- .../llvm.amdgcn.raw.ptr.tbuffer.store.ll | 567 +++- .../llvm.amdgcn.raw.tbuffer.load.f16.ll | 130 +- .../llvm.amdgcn.raw.tbuffer.load.ll | 288 +- .../llvm.amdgcn.raw.tbuffer.store.f16.ll | 104 +- .../llvm.amdgcn.raw.tbuffer.store.i8.ll | 20 +- .../llvm.amdgcn.raw.tbuffer.store.ll | 821 +++++- .../GlobalISel/llvm.amdgcn.s.buffer.load.ll | 726 ++--- .../llvm.amdgcn.struct.buffer.atomic.add.ll | 152 +- ...lvm.amdgcn.struct.buffer.atomic.cmpswap.ll | 240 +- .../llvm.amdgcn.struct.buffer.atomic.sub.ll | 152 +- .../llvm.amdgcn.struct.buffer.atomic.swap.ll | 152 +- ...vm.amdgcn.struct.buffer.load.format.f16.ll | 66 +- .../llvm.amdgcn.struct.buffer.load.format.ll | 108 +- .../llvm.amdgcn.struct.buffer.load.ll | 416 +-- ...m.amdgcn.struct.buffer.store.format.f16.ll | 68 +- ...m.amdgcn.struct.buffer.store.format.f32.ll | 68 +- .../llvm.amdgcn.struct.buffer.store.ll | 244 +- ...llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll | 148 +- .../llvm.amdgcn.struct.ptr.tbuffer.load.ll | 181 +- .../llvm.amdgcn.struct.tbuffer.load.f16.ll | 214 +- .../llvm.amdgcn.struct.tbuffer.load.ll | 259 +- .../GlobalISel/llvm.amdgcn.writelane.ll | 77 +- .../CodeGen/AMDGPU/GlobalISel/mubuf-global.ll | 98 +- llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll | 266 +- .../regbankselect-amdgcn.ptr.s.buffer.load.ll | 260 +- .../regbankselect-amdgcn.s.buffer.load.ll | 538 ++-- .../GlobalISel/true16-merge-values-s16.ll | 12 +- llvm/test/CodeGen/AMDGPU/add3.ll | 77 +- llvm/test/CodeGen/AMDGPU/add_shl.ll | 46 +- llvm/test/CodeGen/AMDGPU/and_or.ll | 131 +- .../test/CodeGen/AMDGPU/flat-saddr-atomics.ll | 1532 +++++----- llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll | 600 ++-- llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll | 236 +- ...gfx12_scalar_subword_ptr_s_buffer_loads.ll | 507 +--- .../global-saddr-atomics-min-max-system.ll | 416 ++- .../CodeGen/AMDGPU/global-saddr-atomics.ll | 424 +-- llvm/test/CodeGen/AMDGPU/global-saddr-load.ll | 834 +++--- .../test/CodeGen/AMDGPU/global-saddr-store.ll | 236 +- .../test/CodeGen/AMDGPU/image-load-d16-tfe.ll | 77 +- .../CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll | 8 +- .../llvm.amdgcn.implicit.ptr.buffer.hsa.ll | 22 - ....amdgcn.implicit.ptr.buffer.unsupported.ll | 61 + .../CodeGen/AMDGPU/load-saddr-offset-imm.ll | 16 +- ...esa-architected-flat-scratch-user-sgprs.ll | 132 + llvm/test/CodeGen/AMDGPU/or3.ll | 124 +- .../AMDGPU/ptr-s-buffer-load-mmo-offsets.ll | 20 +- llvm/test/CodeGen/AMDGPU/ptrmask.ll | 114 +- .../AMDGPU/s-buffer-load-mmo-offsets.ll | 20 +- llvm/test/CodeGen/AMDGPU/shl_add.ll | 78 +- llvm/test/CodeGen/AMDGPU/shl_or.ll | 56 +- llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll | 14 +- llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll | 25 +- llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll | 4 +- llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll | 26 +- llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll | 15 +- llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll | 9 +- llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll | 43 +- llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll | 18 +- llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll | 4 +- llvm/test/CodeGen/AMDGPU/xor3.ll | 67 +- llvm/test/CodeGen/AMDGPU/xor_add.ll | 38 +- 113 files changed, 17248 insertions(+), 15047 deletions(-) delete mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll create mode 100644 llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.unsupported.ll create mode 100644 llvm/test/CodeGen/AMDGPU/mesa-architected-flat-scratch-user-sgprs.ll diff --git a/llvm/docs/AMDGPUUsage.md b/llvm/docs/AMDGPUUsage.md index ee17518233d323..a6ac9e4b78cc62 100644 --- a/llvm/docs/AMDGPUUsage.md +++ b/llvm/docs/AMDGPUUsage.md @@ -2614,6 +2614,13 @@ The AMDGPU backend implements the following LLVM IR intrinsics. The iglp_opt strategy implementations are subject to change. * - llvm.amdgcn.s.getpc - Provides access to the s_getpc_b64 instruction, but with the return value sign-extended from the width of the underlying PC hardware register even on processors where the s_getpc_b64 instruction returns a zero-extended value. +* - llvm.amdgcn.implicit.buffer.ptr + - Returns the implicit buffer pointer. This is pointer is passed in + the first two user SGPRs of graphics and compute shaders for the + `mesa3d` OS on targets without architected flat scratch. The + backend uses it to set up the scratch buffer resource. It is an + error to use for other ABIs, for kernels and non-entry functions, + and on targets with architected flat scratch. * - llvm.amdgcn.ballot - Returns a bitfield(i32 or i64) containing the result of its i1 argument in all active lanes, and zero in all inactive lanes. Provides a way to convert i1 in LLVM IR to i32 or i64 lane mask - bitfield used by hardware to control active lanes when used in EXEC register. diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 067e9e5f6ca916..9d6eba3492dbb0 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -8613,9 +8613,25 @@ bool AMDGPULegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper, case Intrinsic::amdgcn_queue_ptr: return legalizePreloadedArgIntrin(MI, MRI, B, AMDGPUFunctionArgInfo::QUEUE_PTR); - case Intrinsic::amdgcn_implicit_buffer_ptr: + case Intrinsic::amdgcn_implicit_buffer_ptr: { + const Function &Fn = B.getMF().getFunction(); + const SIMachineFunctionInfo *MFI = + B.getMF().getInfo(); + if (!MFI->getUserSGPRInfo().hasImplicitBufferPtr()) { + const char *Error = + ST.hasArchitectedFlatScratch() + ? "intrinsic not supported on subtarget" + : !ST.isMesa3DOS() ? "intrinsic not supported for OS" + : "intrinsic not supported for calling convention"; + Fn.getContext().diagnose( + DiagnosticInfoUnsupported(Fn, Error, MI.getDebugLoc())); + B.buildUndef(MI.getOperand(0).getReg()); + MI.eraseFromParent(); + return true; + } return legalizePreloadedArgIntrin( MI, MRI, B, AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR); + } case Intrinsic::amdgcn_dispatch_id: return legalizePreloadedArgIntrin(MI, MRI, B, AMDGPUFunctionArgInfo::DISPATCH_ID); diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp index 199c594c4083bd..6526c938494187 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.cpp @@ -919,8 +919,8 @@ GCNUserSGPRUsageInfo::GCNUserSGPRUsageInfo(const Function &F, bool IsAmdHsaOrMesa = ST.isAmdHsaOrMesa(F); if (IsAmdHsaOrMesa && !ST.hasFlatScratchEnabled()) PrivateSegmentBuffer = true; - else if (ST.isMesaGfxShader(F)) - ImplicitBufferPtr = true; + else if (!ST.hasArchitectedFlatScratch() && ST.isMesaGfxShader(F)) + ImplicitBufferPtr = true; // Only needed to set up scratch. if (!AMDGPU::isGraphics(CC)) { if (!F.hasFnAttribute("amdgpu-no-dispatch-ptr")) diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 8c5ba37dac43a1..74bcc05cb891b5 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -11316,8 +11316,18 @@ SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, return SDValue(); } case Intrinsic::amdgcn_implicit_buffer_ptr: { - if (getSubtarget()->isAmdHsaOrMesa(MF.getFunction())) - return emitNonHSAIntrinsicError(DAG, DL, VT); + if (!MFI->getUserSGPRInfo().hasImplicitBufferPtr()) { + const char *Error = + Subtarget->hasArchitectedFlatScratch() + ? "intrinsic not supported on subtarget" + : !Subtarget->isMesa3DOS() + ? "intrinsic not supported for OS" + : "intrinsic not supported for calling convention"; + DAG.getContext()->diagnose( + DiagnosticInfoUnsupported(MF.getFunction(), Error, DL.getDebugLoc())); + return DAG.getPOISON(VT); + } + return getPreloadedValue(DAG, *MFI, VT, AMDGPUFunctionArgInfo::IMPLICIT_BUFFER_PTR); } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll index 04c55a72af7cdb..de3ae9c19597f2 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/add_shl.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu8.03-amd-mesa3d < %s | FileCheck -check-prefix=VI %s ; RUN: llc -global-isel -mtriple=amdgpu9.00-amd-mesa3d < %s | FileCheck -check-prefix=GFX9 %s -; RUN: llc -global-isel -mtriple=amdgpu10.10-amd-mesa3d < %s | FileCheck -check-prefix=GFX10 %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s +; RUN: llc -global-isel -mtriple=amdgpu10.10-amd-mesa3d < %s | FileCheck -check-prefixes=GFX10P,GFX10 %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GFX10P,GFX11 %s ; =================================================================================== ; V_ADD_LSHL_U32 @@ -20,10 +20,10 @@ define amdgpu_ps float @add_shl(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: add_shl: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, v2 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: add_shl: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_add_lshl_u32 v0, v0, v1, v2 +; GFX10P-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = shl i32 %x, %c %bc = bitcast i32 %result to float @@ -47,6 +47,11 @@ define amdgpu_ps float @add_shl_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_add_lshl_u32 v0, s2, s3, v0 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: add_shl_vgpr_c: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_add_lshl_u32 v0, s0, s1, v0 +; GFX11-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = shl i32 %x, %c %bc = bitcast i32 %result to float @@ -69,6 +74,11 @@ define amdgpu_ps float @add_shl_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_add_lshl_u32 v0, v0, s2, v1 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: add_shl_vgpr_ac: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_add_lshl_u32 v0, v0, s0, v1 +; GFX11-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = shl i32 %x, %c %bc = bitcast i32 %result to float @@ -87,10 +97,10 @@ define amdgpu_ps float @add_shl_vgpr_const(i32 %a, i32 %b) { ; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, 9 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: add_shl_vgpr_const: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, 9 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: add_shl_vgpr_const: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_add_lshl_u32 v0, v0, v1, 9 +; GFX10P-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = shl i32 %x, 9 %bc = bitcast i32 %result to float @@ -110,10 +120,10 @@ define amdgpu_ps float @add_shl_vgpr_const_inline_const(i32 %a) { ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: add_shl_vgpr_const_inline_const: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x7e800 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: add_shl_vgpr_const_inline_const: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_lshl_add_u32 v0, v0, 9, 0x7e800 +; GFX10P-NEXT: ; return to shader part epilog %x = add i32 %a, 1012 %result = shl i32 %x, 9 %bc = bitcast i32 %result to float @@ -133,10 +143,10 @@ define amdgpu_ps float @add_shl_vgpr_inline_const_x2(i32 %a) { ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: add_shl_vgpr_inline_const_x2: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x600 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: add_shl_vgpr_inline_const_x2: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_lshl_add_u32 v0, v0, 9, 0x600 +; GFX10P-NEXT: ; return to shader part epilog %x = add i32 %a, 3 %result = shl i32 %x, 9 %bc = bitcast i32 %result to float diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll index d553f16d49013d..29556381293419 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll @@ -22,7 +22,7 @@ define amdgpu_ps i32 @s_andn2_i32(i32 inreg %src0, i32 inreg %src1) { ; ; GFX11-LABEL: s_andn2_i32: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b32 s0, s2, s3 +; GFX11-NEXT: s_and_not1_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i32 %src1, -1 %and = and i32 %src0, %not.src1 @@ -42,7 +42,7 @@ define amdgpu_ps i32 @s_andn2_i32_commute(i32 inreg %src0, i32 inreg %src1) { ; ; GFX11-LABEL: s_andn2_i32_commute: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b32 s0, s2, s3 +; GFX11-NEXT: s_and_not1_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i32 %src1, -1 %and = and i32 %not.src1, %src0 @@ -64,8 +64,8 @@ define amdgpu_ps { i32, i32 } @s_andn2_i32_multi_use(i32 inreg %src0, i32 inreg ; ; GFX11-LABEL: s_andn2_i32_multi_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b32 s0, s2, s3 -; GFX11-NEXT: s_not_b32 s1, s3 +; GFX11-NEXT: s_and_not1_b32 s0, s0, s1 +; GFX11-NEXT: s_not_b32 s1, s1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i32 %src1, -1 %and = and i32 %src0, %not.src1 @@ -89,8 +89,8 @@ define amdgpu_ps { i32, i32 } @s_andn2_i32_multi_foldable_use(i32 inreg %src0, i ; ; GFX11-LABEL: s_andn2_i32_multi_foldable_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b32 s0, s2, s4 -; GFX11-NEXT: s_and_not1_b32 s1, s3, s4 +; GFX11-NEXT: s_and_not1_b32 s0, s0, s2 +; GFX11-NEXT: s_and_not1_b32 s1, s1, s2 ; GFX11-NEXT: ; return to shader part epilog %not.src2 = xor i32 %src2, -1 %and0 = and i32 %src0, %not.src2 @@ -123,10 +123,15 @@ define amdgpu_ps float @v_andn2_i32_sv(i32 inreg %src0, i32 %src1) { ; GCN-NEXT: v_bfi_b32 v0, v0, 0, s2 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: v_andn2_i32_sv: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_bfi_b32 v0, v0, 0, s2 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: v_andn2_i32_sv: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_bfi_b32 v0, v0, 0, s2 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: v_andn2_i32_sv: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_bfi_b32 v0, v0, 0, s0 +; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i32 %src1, -1 %and = and i32 %src0, %not.src1 %cast = bitcast i32 %and to float @@ -139,10 +144,15 @@ define amdgpu_ps float @v_andn2_i32_vs(i32 %src0, i32 inreg %src1) { ; GCN-NEXT: v_bfi_b32 v0, s2, 0, v0 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: v_andn2_i32_vs: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_bfi_b32 v0, s2, 0, v0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: v_andn2_i32_vs: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_bfi_b32 v0, s2, 0, v0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: v_andn2_i32_vs: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_bfi_b32 v0, s0, 0, v0 +; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i32 %src1, -1 %and = and i32 %src0, %not.src1 %cast = bitcast i32 %and to float @@ -162,7 +172,7 @@ define amdgpu_ps i64 @s_andn2_i64(i64 inreg %src0, i64 inreg %src1) { ; ; GFX11-LABEL: s_andn2_i64: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b64 s[0:1], s[2:3], s[4:5] +; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3] ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i64 %src1, -1 %and = and i64 %src0, %not.src1 @@ -182,7 +192,7 @@ define amdgpu_ps i64 @s_andn2_i64_commute(i64 inreg %src0, i64 inreg %src1) { ; ; GFX11-LABEL: s_andn2_i64_commute: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b64 s[0:1], s[2:3], s[4:5] +; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3] ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i64 %src1, -1 %and = and i64 %not.src1, %src0 @@ -204,8 +214,8 @@ define amdgpu_ps { i64, i64 } @s_andn2_i64_multi_foldable_use(i64 inreg %src0, i ; ; GFX11-LABEL: s_andn2_i64_multi_foldable_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b64 s[0:1], s[2:3], s[6:7] -; GFX11-NEXT: s_and_not1_b64 s[2:3], s[4:5], s[6:7] +; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[4:5] +; GFX11-NEXT: s_and_not1_b64 s[2:3], s[2:3], s[4:5] ; GFX11-NEXT: ; return to shader part epilog %not.src2 = xor i64 %src2, -1 %and0 = and i64 %src0, %not.src2 @@ -232,8 +242,8 @@ define amdgpu_ps { i64, i64 } @s_andn2_i64_multi_use(i64 inreg %src0, i64 inreg ; ; GFX11-LABEL: s_andn2_i64_multi_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b64 s[0:1], s[2:3], s[4:5] -; GFX11-NEXT: s_not_b64 s[2:3], s[4:5] +; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3] +; GFX11-NEXT: s_not_b64 s[2:3], s[2:3] ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i64 %src1, -1 %and = and i64 %src0, %not.src1 @@ -274,13 +284,21 @@ define amdgpu_ps <2 x float> @v_andn2_i64_sv(i64 inreg %src0, i64 %src1) { ; GCN-NEXT: v_and_b32_e32 v1, s3, v1 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: v_andn2_i64_sv: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_xor_b32_e32 v0, -1, v0 -; GFX10PLUS-NEXT: v_xor_b32_e32 v1, -1, v1 -; GFX10PLUS-NEXT: v_and_b32_e32 v0, s2, v0 -; GFX10PLUS-NEXT: v_and_b32_e32 v1, s3, v1 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: v_andn2_i64_sv: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_xor_b32_e32 v0, -1, v0 +; GFX10-NEXT: v_xor_b32_e32 v1, -1, v1 +; GFX10-NEXT: v_and_b32_e32 v0, s2, v0 +; GFX10-NEXT: v_and_b32_e32 v1, s3, v1 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: v_andn2_i64_sv: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_xor_b32_e32 v0, -1, v0 +; GFX11-NEXT: v_xor_b32_e32 v1, -1, v1 +; GFX11-NEXT: v_and_b32_e32 v0, s0, v0 +; GFX11-NEXT: v_and_b32_e32 v1, s1, v1 +; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i64 %src1, -1 %and = and i64 %src0, %not.src1 %cast = bitcast i64 %and to <2 x float> @@ -308,7 +326,7 @@ define amdgpu_ps <2 x float> @v_andn2_i64_vs(i64 %src0, i64 inreg %src1) { ; ; GFX11-LABEL: v_andn2_i64_vs: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_not_b64 s[0:1], s[2:3] +; GFX11-NEXT: s_not_b64 s[0:1], s[0:1] ; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX11-NEXT: v_and_b32_e32 v1, v1, v3 ; GFX11-NEXT: v_and_b32_e32 v0, v0, v2 @@ -332,7 +350,7 @@ define amdgpu_ps <2 x i32> @s_andn2_v2i32(<2 x i32> inreg %src0, <2 x i32> inreg ; ; GFX11-LABEL: s_andn2_v2i32: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b64 s[0:1], s[2:3], s[4:5] +; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3] ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <2 x i32> %src1, %and = and <2 x i32> %src0, %not.src1 @@ -352,7 +370,7 @@ define amdgpu_ps <2 x i32> @s_andn2_v2i32_commute(<2 x i32> inreg %src0, <2 x i3 ; ; GFX11-LABEL: s_andn2_v2i32_commute: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b64 s[0:1], s[2:3], s[4:5] +; GFX11-NEXT: s_and_not1_b64 s[0:1], s[0:1], s[2:3] ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <2 x i32> %src1, %and = and <2 x i32> %not.src1, %src0 @@ -372,7 +390,7 @@ define amdgpu_ps i16 @s_andn2_i16(i16 inreg %src0, i16 inreg %src1) { ; ; GFX11-LABEL: s_andn2_i16: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b32 s0, s2, s3 +; GFX11-NEXT: s_and_not1_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i16 %src1, -1 %and = and i16 %src0, %not.src1 @@ -392,7 +410,7 @@ define amdgpu_ps i16 @s_andn2_i16_commute(i16 inreg %src0, i16 inreg %src1) { ; ; GFX11-LABEL: s_andn2_i16_commute: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b32 s0, s2, s3 +; GFX11-NEXT: s_and_not1_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i16 %src1, -1 %and = and i16 %not.src1, %src0 @@ -414,8 +432,8 @@ define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_use(i16 inreg %src0, i16 inreg ; ; GFX11-LABEL: s_andn2_i16_multi_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b32 s0, s2, s3 -; GFX11-NEXT: s_xor_b32 s1, s3, -1 +; GFX11-NEXT: s_and_not1_b32 s0, s0, s1 +; GFX11-NEXT: s_xor_b32 s1, s1, -1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i16 %src1, -1 %and = and i16 %src0, %not.src1 @@ -439,8 +457,8 @@ define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_foldable_use(i16 inreg %src0, i ; ; GFX11-LABEL: s_andn2_i16_multi_foldable_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b32 s0, s2, s4 -; GFX11-NEXT: s_and_not1_b32 s1, s3, s4 +; GFX11-NEXT: s_and_not1_b32 s0, s0, s2 +; GFX11-NEXT: s_and_not1_b32 s1, s1, s2 ; GFX11-NEXT: ; return to shader part epilog %not.src2 = xor i16 %src2, -1 %and0 = and i16 %src0, %not.src2 @@ -501,14 +519,14 @@ define amdgpu_ps float @v_andn2_i16_sv(i16 inreg %src0, i16 %src1) { ; GFX11-TRUE16-LABEL: v_andn2_i16_sv: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: v_xor_b16 v0.l, v0.l, -1 -; GFX11-TRUE16-NEXT: v_and_b16 v0.l, s2, v0.l +; GFX11-TRUE16-NEXT: v_and_b16 v0.l, s0, v0.l ; GFX11-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: v_andn2_i16_sv: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, -1, v0 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, s2, v0 +; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, s0, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: ; return to shader part epilog %not.src1 = xor i16 %src1, -1 @@ -535,14 +553,14 @@ define amdgpu_ps float @v_andn2_i16_vs(i16 %src0, i16 inreg %src1) { ; ; GFX11-TRUE16-LABEL: v_andn2_i16_vs: ; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_xor_b32 s0, s2, -1 +; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, -1 ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v0.l, s0 ; GFX11-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: v_andn2_i16_vs: ; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_xor_b32 s0, s2, -1 +; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, -1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, s0, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -572,7 +590,7 @@ define amdgpu_ps i32 @s_andn2_v2i16(<2 x i16> inreg %src0, <2 x i16> inreg %src1 ; ; GFX11-LABEL: s_andn2_v2i16: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b32 s0, s2, s3 +; GFX11-NEXT: s_and_not1_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <2 x i16> %src1, %and = and <2 x i16> %src0, %not.src1 @@ -599,7 +617,7 @@ define amdgpu_ps i32 @s_andn2_v2i16_commute(<2 x i16> inreg %src0, <2 x i16> inr ; ; GFX11-LABEL: s_andn2_v2i16_commute: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b32 s0, s2, s3 +; GFX11-NEXT: s_and_not1_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <2 x i16> %src1, %and = and <2 x i16> %not.src1, %src0 @@ -628,8 +646,8 @@ define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_use(<2 x i16> inreg %src0, <2 ; ; GFX11-LABEL: s_andn2_v2i16_multi_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b32 s0, s2, s3 -; GFX11-NEXT: s_xor_b32 s1, s3, -1 +; GFX11-NEXT: s_and_not1_b32 s0, s0, s1 +; GFX11-NEXT: s_xor_b32 s1, s1, -1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <2 x i16> %src1, %and = and <2 x i16> %src0, %not.src1 @@ -663,8 +681,8 @@ define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_foldable_use(<2 x i16> inreg ; ; GFX11-LABEL: s_andn2_v2i16_multi_foldable_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_not1_b32 s0, s2, s4 -; GFX11-NEXT: s_and_not1_b32 s1, s3, s4 +; GFX11-NEXT: s_and_not1_b32 s0, s0, s2 +; GFX11-NEXT: s_and_not1_b32 s1, s1, s2 ; GFX11-NEXT: ; return to shader part epilog %not.src2 = xor <2 x i16> %src2, %and0 = and <2 x i16> %src0, %not.src2 @@ -747,18 +765,18 @@ define amdgpu_ps i48 @s_andn2_v3i16(<3 x i16> inreg %src0, <3 x i16> inreg %src1 ; ; GFX11-TRUE16-LABEL: s_andn2_v3i16: ; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1 -; GFX11-TRUE16-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] -; GFX11-TRUE16-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1] +; GFX11-TRUE16-NEXT: s_mov_b64 s[4:5], -1 +; GFX11-TRUE16-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-TRUE16-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] ; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16 ; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2 ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: s_andn2_v3i16: ; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_mov_b64 s[0:1], -1 -; GFX11-FAKE16-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] -; GFX11-FAKE16-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1] +; GFX11-FAKE16-NEXT: s_mov_b64 s[4:5], -1 +; GFX11-FAKE16-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-FAKE16-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] ; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s0, 16 ; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff ; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16 @@ -821,18 +839,18 @@ define amdgpu_ps i48 @s_andn2_v3i16_commute(<3 x i16> inreg %src0, <3 x i16> inr ; ; GFX11-TRUE16-LABEL: s_andn2_v3i16_commute: ; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1 -; GFX11-TRUE16-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] -; GFX11-TRUE16-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] +; GFX11-TRUE16-NEXT: s_mov_b64 s[4:5], -1 +; GFX11-TRUE16-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-TRUE16-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1] ; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16 ; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2 ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: s_andn2_v3i16_commute: ; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_mov_b64 s[0:1], -1 -; GFX11-FAKE16-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] -; GFX11-FAKE16-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] +; GFX11-FAKE16-NEXT: s_mov_b64 s[4:5], -1 +; GFX11-FAKE16-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-FAKE16-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1] ; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s0, 16 ; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff ; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16 @@ -910,31 +928,30 @@ define amdgpu_ps { i48, i48 } @s_andn2_v3i16_multi_use(<3 x i16> inreg %src0, <3 ; ; GFX11-TRUE16-LABEL: s_andn2_v3i16_multi_use: ; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1 -; GFX11-TRUE16-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1] -; GFX11-TRUE16-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5] -; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s4, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s4, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 +; GFX11-TRUE16-NEXT: s_mov_b64 s[4:5], -1 +; GFX11-TRUE16-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-TRUE16-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s0, 16 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s4 ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: s_andn2_v3i16_multi_use: ; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_mov_b64 s[0:1], -1 -; GFX11-FAKE16-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1] -; GFX11-FAKE16-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5] -; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s4, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s0, 16 +; GFX11-FAKE16-NEXT: s_mov_b64 s[4:5], -1 +; GFX11-FAKE16-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-FAKE16-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] +; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s2, 16 +; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s0, 16 ; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s2 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s4, 0xffff +; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s4, 16 +; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s4 +; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s5, 16 ; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xffff -; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-FAKE16-NEXT: s_and_b32 s3, s5, 0xffff +; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s4 +; GFX11-FAKE16-NEXT: s_and_b32 s3, s3, 0xffff ; GFX11-FAKE16-NEXT: ; return to shader part epilog %not.src1 = xor <3 x i16> %src1, %and = and <3 x i16> %src0, %not.src1 @@ -1023,13 +1040,21 @@ define amdgpu_ps i64 @s_andn2_v4i16(<4 x i16> inreg %src0, <4 x i16> inreg %src1 ; GFX9-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1] ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_andn2_v4i16: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_mov_b32 s0, -1 -; GFX10PLUS-NEXT: s_mov_b32 s1, s0 -; GFX10PLUS-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] -; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1] -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_andn2_v4i16: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, -1 +; GFX10-NEXT: s_mov_b32 s1, s0 +; GFX10-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] +; GFX10-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1] +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_andn2_v4i16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s4, -1 +; GFX11-NEXT: s_mov_b32 s5, s4 +; GFX11-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] +; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <4 x i16> %src1, %and = and <4 x i16> %src0, %not.src1 %cast = bitcast <4 x i16> %and to i64 @@ -1067,13 +1092,21 @@ define amdgpu_ps i64 @s_andn2_v4i16_commute(<4 x i16> inreg %src0, <4 x i16> inr ; GFX9-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_andn2_v4i16_commute: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_mov_b32 s0, -1 -; GFX10PLUS-NEXT: s_mov_b32 s1, s0 -; GFX10PLUS-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] -; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_andn2_v4i16_commute: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, -1 +; GFX10-NEXT: s_mov_b32 s1, s0 +; GFX10-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] +; GFX10-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_andn2_v4i16_commute: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s4, -1 +; GFX11-NEXT: s_mov_b32 s5, s4 +; GFX11-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1] +; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <4 x i16> %src1, %and = and <4 x i16> %not.src1, %src0 %cast = bitcast <4 x i16> %and to i64 @@ -1113,15 +1146,23 @@ define amdgpu_ps { i64, i64 } @s_andn2_v4i16_multi_use(<4 x i16> inreg %src0, <4 ; GFX9-NEXT: s_mov_b32 s3, s5 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_andn2_v4i16_multi_use: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_mov_b32 s0, -1 -; GFX10PLUS-NEXT: s_mov_b32 s1, s0 -; GFX10PLUS-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1] -; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5] -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_andn2_v4i16_multi_use: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, -1 +; GFX10-NEXT: s_mov_b32 s1, s0 +; GFX10-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1] +; GFX10-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5] +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_andn2_v4i16_multi_use: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s4, -1 +; GFX11-NEXT: s_mov_b32 s5, s4 +; GFX11-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] +; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <4 x i16> %src1, %and = and <4 x i16> %src0, %not.src1 @@ -1173,14 +1214,23 @@ define amdgpu_ps { i64, i64 } @s_andn2_v4i16_multi_foldable_use(<4 x i16> inreg ; GFX9-NEXT: s_and_b64 s[2:3], s[4:5], s[6:7] ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_andn2_v4i16_multi_foldable_use: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_mov_b32 s0, -1 -; GFX10PLUS-NEXT: s_mov_b32 s1, s0 -; GFX10PLUS-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1] -; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[2:3], s[6:7] -; GFX10PLUS-NEXT: s_and_b64 s[2:3], s[4:5], s[6:7] -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_andn2_v4i16_multi_foldable_use: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, -1 +; GFX10-NEXT: s_mov_b32 s1, s0 +; GFX10-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1] +; GFX10-NEXT: s_and_b64 s[0:1], s[2:3], s[6:7] +; GFX10-NEXT: s_and_b64 s[2:3], s[4:5], s[6:7] +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_andn2_v4i16_multi_foldable_use: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s6, -1 +; GFX11-NEXT: s_mov_b32 s7, s6 +; GFX11-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7] +; GFX11-NEXT: s_and_b64 s[0:1], s[0:1], s[4:5] +; GFX11-NEXT: s_and_b64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: ; return to shader part epilog %not.src2 = xor <4 x i16> %src2, %and0 = and <4 x i16> %src0, %not.src2 %and1 = and <4 x i16> %src1, %not.src2 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll index 03f0d127223102..87d9002389cbd2 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/clamp-minmax-const-combine.ll @@ -524,7 +524,7 @@ define amdgpu_ps float @test_min_max_f32_sgpr(float inreg %a) { ; ; GFX1170-LABEL: test_min_max_f32_sgpr: ; GFX1170: ; %bb.0: -; GFX1170-NEXT: s_max_f32 s0, s2, 0 +; GFX1170-NEXT: s_max_f32 s0, s0, 0 ; GFX1170-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3) ; GFX1170-NEXT: s_min_f32 s0, s0, 1.0 ; GFX1170-NEXT: v_mov_b32_e32 v0, s0 @@ -532,7 +532,7 @@ define amdgpu_ps float @test_min_max_f32_sgpr(float inreg %a) { ; ; GFX12-LABEL: test_min_max_f32_sgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_max_num_f32 s0, s2, 0 +; GFX12-NEXT: s_max_num_f32 s0, s0, 0 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3) ; GFX12-NEXT: s_min_num_f32 s0, s0, 1.0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 @@ -551,7 +551,7 @@ define amdgpu_ps float @test_min_max_f32_sgpr_1(float inreg %a) { ; ; GFX1170-LABEL: test_min_max_f32_sgpr_1: ; GFX1170: ; %bb.0: ; %.entry -; GFX1170-NEXT: s_max_f32 s0, s2, 0 +; GFX1170-NEXT: s_max_f32 s0, s0, 0 ; GFX1170-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3) ; GFX1170-NEXT: s_min_f32 s0, s0, 1.0 ; GFX1170-NEXT: s_fmaak_f32 s0, s0, 0, 0x0 @@ -561,7 +561,7 @@ define amdgpu_ps float @test_min_max_f32_sgpr_1(float inreg %a) { ; ; GFX12-LABEL: test_min_max_f32_sgpr_1: ; GFX12: ; %bb.0: ; %.entry -; GFX12-NEXT: s_max_num_f32 s0, s2, 0 +; GFX12-NEXT: s_max_num_f32 s0, s0, 0 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3) ; GFX12-NEXT: s_min_num_f32 s0, s0, 1.0 ; GFX12-NEXT: s_fmaak_f32 s0, s0, 0, 0x0 @@ -585,22 +585,22 @@ define amdgpu_ps float @test_min_max_f32_sgpr_fma_user(float inreg %a, float inr ; ; GFX1170-LABEL: test_min_max_f32_sgpr_fma_user: ; GFX1170: ; %bb.0: -; GFX1170-NEXT: s_max_f32 s0, s2, 0 +; GFX1170-NEXT: s_max_f32 s0, s0, 0 ; GFX1170-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3) ; GFX1170-NEXT: s_min_f32 s0, s0, 1.0 -; GFX1170-NEXT: s_fmac_f32 s4, s0, s3 +; GFX1170-NEXT: s_fmac_f32 s2, s0, s1 ; GFX1170-NEXT: s_delay_alu instid0(SALU_CYCLE_3) -; GFX1170-NEXT: v_mov_b32_e32 v0, s4 +; GFX1170-NEXT: v_mov_b32_e32 v0, s2 ; GFX1170-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: test_min_max_f32_sgpr_fma_user: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_max_num_f32 s0, s2, 0 +; GFX12-NEXT: s_max_num_f32 s0, s0, 0 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_3) ; GFX12-NEXT: s_min_num_f32 s0, s0, 1.0 -; GFX12-NEXT: s_fmac_f32 s4, s0, s3 +; GFX12-NEXT: s_fmac_f32 s2, s0, s1 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) -; GFX12-NEXT: v_mov_b32_e32 v0, s4 +; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: ; return to shader part epilog %mx = call float @llvm.maxnum.f32(float %a, float 0.000000e+00) %mn = call float @llvm.minnum.f32(float %mx, float 1.000000e+00) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll index 1ba09ddd21ddac..e80aaa2d1de922 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/constant-bus-restriction.ll @@ -12,10 +12,15 @@ define amdgpu_ps float @fmul_s_s(float inreg %src0, float inreg %src1) { ; GFX9-NEXT: v_mul_f32_e32 v0, s2, v0 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: fmul_s_s: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_mul_f32_e64 v0, s2, s3 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: fmul_s_s: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_mul_f32_e64 v0, s2, s3 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: fmul_s_s: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_mul_f32_e64 v0, s0, s1 +; GFX11-NEXT: ; return to shader part epilog %result = fmul float %src0, %src1 ret float %result } @@ -26,10 +31,15 @@ define amdgpu_ps float @fmul_ss(float inreg %src) { ; GFX9-NEXT: v_mul_f32_e64 v0, s2, s2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: fmul_ss: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_mul_f32_e64 v0, s2, s2 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: fmul_ss: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_mul_f32_e64 v0, s2, s2 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: fmul_ss: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_mul_f32_e64 v0, s0, s0 +; GFX11-NEXT: ; return to shader part epilog %result = fmul float %src, %src ret float %result } @@ -43,11 +53,17 @@ define amdgpu_ps float @fma_s_s_s(float inreg %src0, float inreg %src1, float in ; GFX9-NEXT: v_fma_f32 v0, s2, v0, v1 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: fma_s_s_s: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s4 -; GFX10PLUS-NEXT: v_fma_f32 v0, s3, s2, v0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: fma_s_s_s: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_mov_b32_e32 v0, s4 +; GFX10-NEXT: v_fma_f32 v0, s3, s2, v0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: fma_s_s_s: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_fma_f32 v0, s1, s0, v0 +; GFX11-NEXT: ; return to shader part epilog %result = call float @llvm.fma.f32(float %src0, float %src1, float %src2) ret float %result } @@ -59,10 +75,15 @@ define amdgpu_ps float @fma_sss(float inreg %src) { ; GFX9-NEXT: v_fma_f32 v0, s2, s2, s2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: fma_sss: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_fma_f32 v0, s2, s2, s2 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: fma_sss: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_fma_f32 v0, s2, s2, s2 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: fma_sss: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_fma_f32 v0, s0, s0, s0 +; GFX11-NEXT: ; return to shader part epilog %result = call float @llvm.fma.f32(float %src, float %src, float %src) ret float %result } @@ -75,10 +96,15 @@ define amdgpu_ps float @fma_ss_s(float inreg %src01, float inreg %src2) { ; GFX9-NEXT: v_fma_f32 v0, s2, s2, v0 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: fma_ss_s: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_fma_f32 v0, s2, s2, s3 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: fma_ss_s: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_fma_f32 v0, s2, s2, s3 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: fma_ss_s: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_fma_f32 v0, s0, s0, s1 +; GFX11-NEXT: ; return to shader part epilog %result = call float @llvm.fma.f32(float %src01, float %src01, float %src2) ret float %result } @@ -91,10 +117,15 @@ define amdgpu_ps float @fma_s_ss(float inreg %src0, float inreg %src12) { ; GFX9-NEXT: v_fma_f32 v0, s2, v0, v0 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: fma_s_ss: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_fma_f32 v0, s2, s3, s3 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: fma_s_ss: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_fma_f32 v0, s2, s3, s3 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: fma_s_ss: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_fma_f32 v0, s0, s1, s1 +; GFX11-NEXT: ; return to shader part epilog %result = call float @llvm.fma.f32(float %src0, float %src12, float %src12) ret float %result } @@ -107,10 +138,15 @@ define amdgpu_ps float @fma_ss_s_same_outer(float inreg %src02, float inreg %src ; GFX9-NEXT: v_fma_f32 v0, s2, v0, s2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: fma_ss_s_same_outer: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_fma_f32 v0, s2, s3, s2 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: fma_ss_s_same_outer: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_fma_f32 v0, s2, s3, s2 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: fma_ss_s_same_outer: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_fma_f32 v0, s0, s1, s0 +; GFX11-NEXT: ; return to shader part epilog %result = call float @llvm.fma.f32(float %src02, float %src1, float %src02) ret float %result } @@ -125,13 +161,21 @@ define amdgpu_ps float @fcmp_s_s(float inreg %src0, float inreg %src1) { ; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: fcmp_s_s: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_cmp_eq_f32_e64 s0, s2, s3 -; GFX10PLUS-NEXT: s_cmp_lg_u32 s0, 0 -; GFX10PLUS-NEXT: s_cselect_b32 s0, 1.0, 0 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: fcmp_s_s: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_cmp_eq_f32_e64 s0, s2, s3 +; GFX10-NEXT: s_cmp_lg_u32 s0, 0 +; GFX10-NEXT: s_cselect_b32 s0, 1.0, 0 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: fcmp_s_s: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_cmp_eq_f32_e64 s0, s0, s1 +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_cselect_b32 s0, 1.0, 0 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog %cmp = fcmp oeq float %src0, %src1 %result = select i1 %cmp, float 1.0, float 0.0 ret float %result @@ -146,12 +190,19 @@ define amdgpu_ps float @select_vcc_s_s(float %cmp0, float %cmp1, float inreg %sr ; GFX9-NEXT: v_cndmask_b32_e32 v0, v3, v2, vcc ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: select_vcc_s_s: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_mov_b32_e32 v2, s3 -; GFX10PLUS-NEXT: v_cmp_eq_f32_e32 vcc_lo, v0, v1 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v2, s2, vcc_lo -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: select_vcc_s_s: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_mov_b32_e32 v2, s3 +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v0, v1 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, s2, vcc_lo +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: select_vcc_s_s: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_mov_b32_e32 v2, s1 +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v0, v1 +; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, s0, vcc_lo +; GFX11-NEXT: ; return to shader part epilog %cmp = fcmp oeq float %cmp0, %cmp1 %result = select i1 %cmp, float %src0, float %src1 ret float %result @@ -166,12 +217,19 @@ define amdgpu_ps float @select_vcc_fneg_s_s(float %cmp0, float %cmp1, float inre ; GFX9-NEXT: v_cndmask_b32_e64 v0, v3, -v2, vcc ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: select_vcc_fneg_s_s: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_mov_b32_e32 v2, s3 -; GFX10PLUS-NEXT: v_cmp_eq_f32_e32 vcc_lo, v0, v1 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v2, -s2, vcc_lo -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: select_vcc_fneg_s_s: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_mov_b32_e32 v2, s3 +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, v0, v1 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v2, -s2, vcc_lo +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: select_vcc_fneg_s_s: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_mov_b32_e32 v2, s1 +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, v0, v1 +; GFX11-NEXT: v_cndmask_b32_e64 v0, v2, -s0, vcc_lo +; GFX11-NEXT: ; return to shader part epilog %cmp = fcmp oeq float %cmp0, %cmp1 %neg.src0 = fneg float %src0 %result = select i1 %cmp, float %neg.src0, float %src1 @@ -188,11 +246,17 @@ define amdgpu_ps float @amdgcn_div_fmas_sss(float inreg %src, float %cmp.src) { ; GFX9-NEXT: v_div_fmas_f32 v0, v0, v0, v0 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: amdgcn_div_fmas_sss: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0 -; GFX10PLUS-NEXT: v_div_fmas_f32 v0, s2, s2, s2 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: amdgcn_div_fmas_sss: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0 +; GFX10-NEXT: v_div_fmas_f32 v0, s2, s2, s2 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: amdgcn_div_fmas_sss: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_cmp_eq_f32_e32 vcc_lo, 0, v0 +; GFX11-NEXT: v_div_fmas_f32 v0, s0, s0, s0 +; GFX11-NEXT: ; return to shader part epilog %vcc = fcmp oeq float %cmp.src, 0.0 %result = call float @llvm.amdgcn.div.fmas.f32(float %src, float %src, float %src, i1 %vcc) ret float %result @@ -208,13 +272,21 @@ define amdgpu_ps float @class_s_s(float inreg %src0, i32 inreg %src1) { ; GFX9-NEXT: v_mov_b32_e32 v0, s0 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: class_s_s: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_cmp_class_f32_e64 s0, s2, s3 -; GFX10PLUS-NEXT: s_cmp_lg_u32 s0, 0 -; GFX10PLUS-NEXT: s_cselect_b32 s0, 1.0, 0 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: class_s_s: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_cmp_class_f32_e64 s0, s2, s3 +; GFX10-NEXT: s_cmp_lg_u32 s0, 0 +; GFX10-NEXT: s_cselect_b32 s0, 1.0, 0 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: class_s_s: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_cmp_class_f32_e64 s0, s0, s1 +; GFX11-NEXT: s_cmp_lg_u32 s0, 0 +; GFX11-NEXT: s_cselect_b32 s0, 1.0, 0 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog %class = call i1 @llvm.amdgcn.class.f32(float %src0, i32 %src1) %result = select i1 %class, float 1.0, float 0.0 ret float %result @@ -234,7 +306,7 @@ define amdgpu_ps float @div_scale_s_s_true(float inreg %src0, float inreg %src1) ; ; GFX11-LABEL: div_scale_s_s_true: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_div_scale_f32 v0, null, s2, s3, s2 +; GFX11-NEXT: v_div_scale_f32 v0, null, s0, s1, s0 ; GFX11-NEXT: ; return to shader part epilog %div.scale = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %src0, float %src1, i1 true) %result = extractvalue { float, i1 } %div.scale, 0 @@ -255,7 +327,7 @@ define amdgpu_ps float @div_scale_s_s_false(float inreg %src0, float inreg %src1 ; ; GFX11-LABEL: div_scale_s_s_false: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_div_scale_f32 v0, null, s3, s3, s2 +; GFX11-NEXT: v_div_scale_f32 v0, null, s1, s1, s0 ; GFX11-NEXT: ; return to shader part epilog %div.scale = call { float, i1 } @llvm.amdgcn.div.scale.f32(float %src0, float %src1, i1 false) %result = extractvalue { float, i1 } %div.scale, 0 @@ -269,3 +341,5 @@ declare i1 @llvm.amdgcn.class.f32(float, i32) #1 attributes #0 = { nounwind readnone speculatable willreturn } attributes #1 = { nounwind readnone speculatable } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX10PLUS: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll index 56fb1c61a3ea7e..63ac9279389bd5 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i128.ll @@ -69,11 +69,11 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_sgpr_idx(ptr addrspace(4) inre ; ; GFX11-LABEL: extractelement_sgpr_v4i128_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_b32 s0, s4, 3 +; GFX11-NEXT: s_and_b32 s2, s2, 3 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_lshl_b32 s0, s0, 4 -; GFX11-NEXT: v_mov_b32_e32 v0, s0 -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX11-NEXT: s_lshl_b32 s2, s2, 4 +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1 @@ -154,7 +154,7 @@ define amdgpu_ps i128 @extractelement_vgpr_v4i128_sgpr_idx(ptr addrspace(1) %ptr ; ; GFX11-LABEL: extractelement_vgpr_v4i128_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_b32 s0, s2, 3 +; GFX11-NEXT: s_and_b32 s0, s0, 3 ; GFX11-NEXT: s_mov_b32 s1, 0 ; GFX11-NEXT: s_lshl_b32 s0, s0, 4 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -302,7 +302,7 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_vgpr_idx(ptr addrspace(4) inre ; GFX11-NEXT: v_and_b32_e32 v0, 3, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0 -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1 @@ -366,7 +366,7 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_idx0(ptr addrspace(4) inreg %p ; GFX11-LABEL: extractelement_sgpr_v4i128_idx0: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1 @@ -432,7 +432,7 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_idx1(ptr addrspace(4) inreg %p ; GFX11-LABEL: extractelement_sgpr_v4i128_idx1: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:16 +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1 @@ -498,7 +498,7 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_idx2(ptr addrspace(4) inreg %p ; GFX11-LABEL: extractelement_sgpr_v4i128_idx2: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:32 +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:32 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1 @@ -564,7 +564,7 @@ define amdgpu_ps i128 @extractelement_sgpr_v4i128_idx3(ptr addrspace(4) inreg %p ; GFX11-LABEL: extractelement_sgpr_v4i128_idx3: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:48 +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:48 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: v_readfirstlane_b32 s1, v1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll index 33823dcbe927eb..80fa9b53638575 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i16.ll @@ -57,11 +57,11 @@ define amdgpu_ps i16 @extractelement_sgpr_v4i16_sgpr_idx(ptr addrspace(4) inreg ; ; GFX11-LABEL: extractelement_sgpr_v4i16_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_b32 s0, s4, 3 +; GFX11-NEXT: s_and_b32 s2, s2, 3 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_lshl_b32 s0, s0, 1 -; GFX11-NEXT: v_mov_b32_e32 v0, s0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX11-NEXT: s_lshl_b32 s2, s2, 1 +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -127,7 +127,7 @@ define amdgpu_ps i16 @extractelement_vgpr_v4i16_sgpr_idx(ptr addrspace(1) %ptr, ; ; GFX11-LABEL: extractelement_vgpr_v4i16_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_b32 s0, s2, 3 +; GFX11-NEXT: s_and_b32 s0, s0, 3 ; GFX11-NEXT: s_mov_b32 s1, 0 ; GFX11-NEXT: s_lshl_b32 s0, s0, 1 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -260,7 +260,7 @@ define amdgpu_ps i16 @extractelement_sgpr_v4i16_vgpr_idx(ptr addrspace(4) inreg ; GFX11-NEXT: v_and_b32_e32 v0, 3, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -309,7 +309,7 @@ define amdgpu_ps i16 @extractelement_sgpr_v4i16_idx0(ptr addrspace(4) inreg %ptr ; GFX11-LABEL: extractelement_sgpr_v4i16_idx0: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -360,7 +360,7 @@ define amdgpu_ps i16 @extractelement_sgpr_v4i16_idx1(ptr addrspace(4) inreg %ptr ; GFX11-LABEL: extractelement_sgpr_v4i16_idx1: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:2 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] offset:2 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -411,7 +411,7 @@ define amdgpu_ps i16 @extractelement_sgpr_v4i16_idx2(ptr addrspace(4) inreg %ptr ; GFX11-LABEL: extractelement_sgpr_v4i16_idx2: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:4 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] offset:4 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -462,7 +462,7 @@ define amdgpu_ps i16 @extractelement_sgpr_v4i16_idx3(ptr addrspace(4) inreg %ptr ; GFX11-LABEL: extractelement_sgpr_v4i16_idx3: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:6 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] offset:6 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -701,11 +701,11 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_sgpr_idx(ptr addrspace(4) inreg ; ; GFX11-LABEL: extractelement_sgpr_v8i16_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_b32 s0, s4, 7 +; GFX11-NEXT: s_and_b32 s2, s2, 7 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_lshl_b32 s0, s0, 1 -; GFX11-NEXT: v_mov_b32_e32 v0, s0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX11-NEXT: s_lshl_b32 s2, s2, 1 +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -771,7 +771,7 @@ define amdgpu_ps i16 @extractelement_vgpr_v8i16_sgpr_idx(ptr addrspace(1) %ptr, ; ; GFX11-LABEL: extractelement_vgpr_v8i16_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_b32 s0, s2, 7 +; GFX11-NEXT: s_and_b32 s0, s0, 7 ; GFX11-NEXT: s_mov_b32 s1, 0 ; GFX11-NEXT: s_lshl_b32 s0, s0, 1 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -904,7 +904,7 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_vgpr_idx(ptr addrspace(4) inreg ; GFX11-NEXT: v_and_b32_e32 v0, 7, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -953,7 +953,7 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx0(ptr addrspace(4) inreg %ptr ; GFX11-LABEL: extractelement_sgpr_v8i16_idx0: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1004,7 +1004,7 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx1(ptr addrspace(4) inreg %ptr ; GFX11-LABEL: extractelement_sgpr_v8i16_idx1: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:2 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] offset:2 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1055,7 +1055,7 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx2(ptr addrspace(4) inreg %ptr ; GFX11-LABEL: extractelement_sgpr_v8i16_idx2: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:4 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] offset:4 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1106,7 +1106,7 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx3(ptr addrspace(4) inreg %ptr ; GFX11-LABEL: extractelement_sgpr_v8i16_idx3: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:6 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] offset:6 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1157,7 +1157,7 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx4(ptr addrspace(4) inreg %ptr ; GFX11-LABEL: extractelement_sgpr_v8i16_idx4: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:8 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] offset:8 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1208,7 +1208,7 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx5(ptr addrspace(4) inreg %ptr ; GFX11-LABEL: extractelement_sgpr_v8i16_idx5: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:10 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] offset:10 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1259,7 +1259,7 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx6(ptr addrspace(4) inreg %ptr ; GFX11-LABEL: extractelement_sgpr_v8i16_idx6: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:12 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] offset:12 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1310,7 +1310,7 @@ define amdgpu_ps i16 @extractelement_sgpr_v8i16_idx7(ptr addrspace(4) inreg %ptr ; GFX11-LABEL: extractelement_sgpr_v8i16_idx7: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:14 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] offset:14 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll index faf2898562d573..f2989cc4f6c5f4 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.i8.ll @@ -60,11 +60,11 @@ define amdgpu_ps i8 @extractelement_sgpr_v4i8_sgpr_idx(ptr addrspace(4) inreg %p ; ; GFX11-LABEL: extractelement_sgpr_v4i8_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_b32 s0, s4, 3 +; GFX11-NEXT: s_and_b32 s2, s2, 3 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: s_ashr_i32 s1, s0, 31 -; GFX11-NEXT: s_add_u32 s0, s2, s0 -; GFX11-NEXT: s_addc_u32 s1, s3, s1 +; GFX11-NEXT: s_ashr_i32 s3, s2, 31 +; GFX11-NEXT: s_add_u32 s0, s0, s2 +; GFX11-NEXT: s_addc_u32 s1, s1, s3 ; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 @@ -127,7 +127,7 @@ define amdgpu_ps i8 @extractelement_vgpr_v4i8_sgpr_idx(ptr addrspace(1) %ptr, i3 ; ; GFX11-LABEL: extractelement_vgpr_v4i8_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_b32 s0, s2, 3 +; GFX11-NEXT: s_and_b32 s0, s0, 3 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_ashr_i32 s1, s0, 31 ; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 @@ -262,8 +262,8 @@ define amdgpu_ps i8 @extractelement_sgpr_v4i8_vgpr_idx(ptr addrspace(4) inreg %p ; ; GFX11-LABEL: extractelement_sgpr_v4i8_vgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_and_b32 v2, 3, v0 -; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_and_b32 v2, 3, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 @@ -318,7 +318,7 @@ define amdgpu_ps i8 @extractelement_sgpr_v4i8_idx0(ptr addrspace(4) inreg %ptr) ; GFX11-LABEL: extractelement_sgpr_v4i8_idx0: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -369,7 +369,7 @@ define amdgpu_ps i8 @extractelement_sgpr_v4i8_idx1(ptr addrspace(4) inreg %ptr) ; GFX11-LABEL: extractelement_sgpr_v4i8_idx1: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:1 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -420,7 +420,7 @@ define amdgpu_ps i8 @extractelement_sgpr_v4i8_idx2(ptr addrspace(4) inreg %ptr) ; GFX11-LABEL: extractelement_sgpr_v4i8_idx2: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:2 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:2 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -471,7 +471,7 @@ define amdgpu_ps i8 @extractelement_sgpr_v4i8_idx3(ptr addrspace(4) inreg %ptr) ; GFX11-LABEL: extractelement_sgpr_v4i8_idx3: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:3 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:3 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -713,11 +713,11 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_sgpr_idx(ptr addrspace(4) inreg %p ; ; GFX11-LABEL: extractelement_sgpr_v8i8_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_b32 s0, s4, 7 +; GFX11-NEXT: s_and_b32 s2, s2, 7 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: s_ashr_i32 s1, s0, 31 -; GFX11-NEXT: s_add_u32 s0, s2, s0 -; GFX11-NEXT: s_addc_u32 s1, s3, s1 +; GFX11-NEXT: s_ashr_i32 s3, s2, 31 +; GFX11-NEXT: s_add_u32 s0, s0, s2 +; GFX11-NEXT: s_addc_u32 s1, s1, s3 ; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 @@ -780,7 +780,7 @@ define amdgpu_ps i8 @extractelement_vgpr_v8i8_sgpr_idx(ptr addrspace(1) %ptr, i3 ; ; GFX11-LABEL: extractelement_vgpr_v8i8_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_b32 s0, s2, 7 +; GFX11-NEXT: s_and_b32 s0, s0, 7 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_ashr_i32 s1, s0, 31 ; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 @@ -915,8 +915,8 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_vgpr_idx(ptr addrspace(4) inreg %p ; ; GFX11-LABEL: extractelement_sgpr_v8i8_vgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_and_b32 v2, 7, v0 -; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_and_b32 v2, 7, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 @@ -971,7 +971,7 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx0(ptr addrspace(4) inreg %ptr) ; GFX11-LABEL: extractelement_sgpr_v8i8_idx0: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1022,7 +1022,7 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx1(ptr addrspace(4) inreg %ptr) ; GFX11-LABEL: extractelement_sgpr_v8i8_idx1: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:1 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1073,7 +1073,7 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx2(ptr addrspace(4) inreg %ptr) ; GFX11-LABEL: extractelement_sgpr_v8i8_idx2: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:2 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:2 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1124,7 +1124,7 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx3(ptr addrspace(4) inreg %ptr) ; GFX11-LABEL: extractelement_sgpr_v8i8_idx3: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:3 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:3 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1175,7 +1175,7 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx4(ptr addrspace(4) inreg %ptr) ; GFX11-LABEL: extractelement_sgpr_v8i8_idx4: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:4 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:4 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1226,7 +1226,7 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx5(ptr addrspace(4) inreg %ptr) ; GFX11-LABEL: extractelement_sgpr_v8i8_idx5: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:5 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:5 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1277,7 +1277,7 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx6(ptr addrspace(4) inreg %ptr) ; GFX11-LABEL: extractelement_sgpr_v8i8_idx6: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:6 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:6 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1328,7 +1328,7 @@ define amdgpu_ps i8 @extractelement_sgpr_v8i8_idx7(ptr addrspace(4) inreg %ptr) ; GFX11-LABEL: extractelement_sgpr_v8i8_idx7: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:7 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:7 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-NEXT: ; return to shader part epilog @@ -1750,11 +1750,11 @@ define amdgpu_ps i8 @extractelement_sgpr_v16i8_sgpr_idx(ptr addrspace(4) inreg % ; ; GFX11-LABEL: extractelement_sgpr_v16i8_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_b32 s0, s4, 15 +; GFX11-NEXT: s_and_b32 s2, s2, 15 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: s_ashr_i32 s1, s0, 31 -; GFX11-NEXT: s_add_u32 s0, s2, s0 -; GFX11-NEXT: s_addc_u32 s1, s3, s1 +; GFX11-NEXT: s_ashr_i32 s3, s2, 31 +; GFX11-NEXT: s_add_u32 s0, s0, s2 +; GFX11-NEXT: s_addc_u32 s1, s1, s3 ; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 @@ -1817,7 +1817,7 @@ define amdgpu_ps i8 @extractelement_vgpr_v16i8_sgpr_idx(ptr addrspace(1) %ptr, i ; ; GFX11-LABEL: extractelement_vgpr_v16i8_sgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_and_b32 s0, s2, 15 +; GFX11-NEXT: s_and_b32 s0, s0, 15 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_ashr_i32 s1, s0, 31 ; GFX11-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v3, s1 @@ -1952,8 +1952,8 @@ define amdgpu_ps i8 @extractelement_sgpr_v16i8_vgpr_idx(ptr addrspace(4) inreg % ; ; GFX11-LABEL: extractelement_sgpr_v16i8_vgpr_idx: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_dual_mov_b32 v1, s3 :: v_dual_and_b32 v2, 15, v0 -; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_and_b32 v2, 15, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; GFX11-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll index d0e9c78f29fe6d..0a9baf12958784 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/extractelement.ll @@ -68,20 +68,35 @@ define amdgpu_ps float @dyn_extract_v8f32_const_s_s(i32 inreg %sel) { ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v8f32_const_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s4, 1.0 -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: s_mov_b32 s11, 0x41000000 -; GFX10PLUS-NEXT: s_mov_b32 s10, 0x40e00000 -; GFX10PLUS-NEXT: s_mov_b32 s9, 0x40c00000 -; GFX10PLUS-NEXT: s_mov_b32 s8, 0x40a00000 -; GFX10PLUS-NEXT: s_mov_b32 s7, 4.0 -; GFX10PLUS-NEXT: s_mov_b32 s6, 0x40400000 -; GFX10PLUS-NEXT: s_mov_b32 s5, 2.0 -; GFX10PLUS-NEXT: s_movrels_b32 s0, s4 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v8f32_const_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s4, 1.0 +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: s_mov_b32 s11, 0x41000000 +; GFX10-NEXT: s_mov_b32 s10, 0x40e00000 +; GFX10-NEXT: s_mov_b32 s9, 0x40c00000 +; GFX10-NEXT: s_mov_b32 s8, 0x40a00000 +; GFX10-NEXT: s_mov_b32 s7, 4.0 +; GFX10-NEXT: s_mov_b32 s6, 0x40400000 +; GFX10-NEXT: s_mov_b32 s5, 2.0 +; GFX10-NEXT: s_movrels_b32 s0, s4 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v8f32_const_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 s4, 1.0 +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: s_mov_b32 s11, 0x41000000 +; GFX11-NEXT: s_mov_b32 s10, 0x40e00000 +; GFX11-NEXT: s_mov_b32 s9, 0x40c00000 +; GFX11-NEXT: s_mov_b32 s8, 0x40a00000 +; GFX11-NEXT: s_mov_b32 s7, 4.0 +; GFX11-NEXT: s_mov_b32 s6, 0x40400000 +; GFX11-NEXT: s_mov_b32 s5, 2.0 +; GFX11-NEXT: s_movrels_b32 s0, s4 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <8 x float> , i32 %sel ret float %ext @@ -114,24 +129,43 @@ define amdgpu_ps float @dyn_extract_v8f32_s_v(<8 x float> inreg %vec, i32 %sel) ; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v8, vcc ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v8f32_s_v: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: v_mov_b32_e32 v1, s3 -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, s2, v1, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s7, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v1, s9, vcc_lo -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v8f32_s_v: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: v_mov_b32_e32 v1, s3 +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v1, s2, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s7, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s9, vcc_lo +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v8f32_s_v: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX11-NEXT: v_cndmask_b32_e32 v1, s0, v1, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s7, vcc_lo +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <8 x float> %vec, i32 %sel ret float %ext @@ -194,11 +228,17 @@ define amdgpu_ps float @dyn_extract_v8f32_v_s(<8 x float> %vec, i32 inreg %sel) ; MOVREL-NEXT: v_movrels_b32_e32 v0, v0 ; MOVREL-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v8f32_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movrels_b32_e32 v0, v0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v8f32_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movrels_b32_e32 v0, v0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v8f32_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movrels_b32_e32 v0, v0 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <8 x float> %vec, i32 %sel ret float %ext @@ -220,20 +260,27 @@ define amdgpu_ps float @dyn_extract_v8f32_s_s(<8 x float> inreg %vec, i32 inreg ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v8f32_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 m0, s10 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_mov_b32 s6, s8 -; GFX10PLUS-NEXT: s_mov_b32 s7, s9 -; GFX10PLUS-NEXT: s_movrels_b32 s0, s0 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v8f32_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 m0, s10 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: s_movrels_b32 s0, s0 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v8f32_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s8 +; GFX11-NEXT: s_movrels_b32 s0, s0 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <8 x float> %vec, i32 %sel ret float %ext @@ -339,7 +386,7 @@ define amdgpu_ps void @dyn_extract_v8i64_const_s_s(i32 inreg %sel) { ; GFX11-LABEL: dyn_extract_v8i64_const_s_s: ; GFX11: ; %bb.0: ; %entry ; GFX11-NEXT: s_mov_b64 s[4:5], 1 -; GFX11-NEXT: s_mov_b32 m0, s2 +; GFX11-NEXT: s_mov_b32 m0, s0 ; GFX11-NEXT: s_mov_b64 s[18:19], 8 ; GFX11-NEXT: s_mov_b64 s[16:17], 7 ; GFX11-NEXT: s_mov_b64 s[14:15], 6 @@ -472,28 +519,28 @@ define amdgpu_ps void @dyn_extract_v8i64_s_v(<8 x i64> inreg %vec, i32 %sel) { ; ; GFX11-LABEL: dyn_extract_v8i64_s_v: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s5 +; GFX11-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX11-NEXT: v_cndmask_b32_e32 v1, s2, v1, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e32 v2, s3, v2, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v1, s0, v1, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v2, s1, v2, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s5, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s7, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s9, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s10, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s11, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s12, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s13, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s14, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s15, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s16, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s17, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s14, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s15, vcc_lo ; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off ; GFX11-NEXT: s_endpgm entry: @@ -607,7 +654,7 @@ define amdgpu_ps void @dyn_extract_v8i64_v_s(<8 x i64> %vec, i32 inreg %sel) { ; ; GFX11-LABEL: dyn_extract_v8i64_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_lshl_b32 m0, s2, 1 +; GFX11-NEXT: s_lshl_b32 m0, s0, 1 ; GFX11-NEXT: v_movrels_b32_e32 v16, v0 ; GFX11-NEXT: v_movrels_b32_e32 v17, v1 ; GFX11-NEXT: global_store_b64 v[0:1], v[16:17], off @@ -696,23 +743,7 @@ define amdgpu_ps void @dyn_extract_v8i64_s_s(<8 x i64> inreg %vec, i32 inreg %se ; ; GFX11-LABEL: dyn_extract_v8i64_s_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 m0, s18 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 +; GFX11-NEXT: s_mov_b32 m0, s16 ; GFX11-NEXT: s_movrels_b64 s[0:1], s[0:1] ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off @@ -739,20 +770,27 @@ define amdgpu_ps float @dyn_extract_v8f32_s_s_offset3(<8 x float> inreg %vec, i3 ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v8f32_s_s_offset3: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 m0, s10 -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_mov_b32 s6, s8 -; GFX10PLUS-NEXT: s_mov_b32 s7, s9 -; GFX10PLUS-NEXT: s_movrels_b32 s0, s3 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v8f32_s_s_offset3: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 m0, s10 +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: s_movrels_b32 s0, s3 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v8f32_s_s_offset3: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s8 +; GFX11-NEXT: s_movrels_b32 s0, s3 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog entry: %add = add i32 %sel, 3 %ext = extractelement <8 x float> %vec, i32 %add @@ -876,23 +914,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset1(<8 x double> inreg %vec, ; ; GFX11-LABEL: dyn_extract_v8f64_s_s_offset1: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 m0, s18 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 +; GFX11-NEXT: s_mov_b32 m0, s16 ; GFX11-NEXT: s_movrels_b64 s[0:1], s[2:3] ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: ; return to shader part epilog @@ -953,23 +975,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset2(<8 x double> inreg %vec, ; ; GFX11-LABEL: dyn_extract_v8f64_s_s_offset2: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 m0, s18 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 +; GFX11-NEXT: s_mov_b32 m0, s16 ; GFX11-NEXT: s_movrels_b64 s[0:1], s[4:5] ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: ; return to shader part epilog @@ -1030,23 +1036,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset3(<8 x double> inreg %vec, ; ; GFX11-LABEL: dyn_extract_v8f64_s_s_offset3: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 m0, s18 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 +; GFX11-NEXT: s_mov_b32 m0, s16 ; GFX11-NEXT: s_movrels_b64 s[0:1], s[6:7] ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: ; return to shader part epilog @@ -1107,23 +1097,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset4(<8 x double> inreg %vec, ; ; GFX11-LABEL: dyn_extract_v8f64_s_s_offset4: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 m0, s18 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 +; GFX11-NEXT: s_mov_b32 m0, s16 ; GFX11-NEXT: s_movrels_b64 s[0:1], s[8:9] ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: ; return to shader part epilog @@ -1184,23 +1158,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset5(<8 x double> inreg %vec, ; ; GFX11-LABEL: dyn_extract_v8f64_s_s_offset5: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 m0, s18 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 +; GFX11-NEXT: s_mov_b32 m0, s16 ; GFX11-NEXT: s_movrels_b64 s[0:1], s[10:11] ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: ; return to shader part epilog @@ -1261,23 +1219,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset6(<8 x double> inreg %vec, ; ; GFX11-LABEL: dyn_extract_v8f64_s_s_offset6: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 m0, s18 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 +; GFX11-NEXT: s_mov_b32 m0, s16 ; GFX11-NEXT: s_movrels_b64 s[0:1], s[12:13] ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: ; return to shader part epilog @@ -1363,23 +1305,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offset7(<8 x double> inreg %vec, ; ; GFX11-LABEL: dyn_extract_v8f64_s_s_offset7: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 -; GFX11-NEXT: s_mov_b32 m0, s18 +; GFX11-NEXT: s_mov_b32 m0, s16 ; GFX11-NEXT: s_movrels_b64 s[0:1], s[14:15] ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: ; return to shader part epilog @@ -1440,23 +1366,7 @@ define amdgpu_ps double @dyn_extract_v8f64_s_s_offsetm1(<8 x double> inreg %vec, ; ; GFX11-LABEL: dyn_extract_v8f64_s_s_offsetm1: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_add_i32 m0, s18, -1 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 +; GFX11-NEXT: s_add_i32 m0, s16, -1 ; GFX11-NEXT: s_movrels_b64 s[0:1], s[0:1] ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: ; return to shader part epilog @@ -1668,15 +1578,7 @@ define amdgpu_ps void @dyn_extract_v8p3_s_s(<8 x ptr addrspace(3)> inreg %vec, i ; ; GFX11-LABEL: dyn_extract_v8p3_s_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 m0, s10 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 +; GFX11-NEXT: s_mov_b32 m0, s8 ; GFX11-NEXT: s_movrels_b32 s0, s0 ; GFX11-NEXT: v_mov_b32_e32 v0, s0 ; GFX11-NEXT: ds_store_b32 v0, v0 @@ -1841,23 +1743,7 @@ define amdgpu_ps void @dyn_extract_v8p1_s_s(<8 x ptr addrspace(1)> inreg %vec, i ; ; GFX11-LABEL: dyn_extract_v8p1_s_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 m0, s18 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 +; GFX11-NEXT: s_mov_b32 m0, s16 ; GFX11-NEXT: s_movrels_b64 s[0:1], s[0:1] ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off @@ -1882,11 +1768,17 @@ define amdgpu_ps float @dyn_extract_v16f32_v_s(<16 x float> %vec, i32 inreg %sel ; MOVREL-NEXT: v_movrels_b32_e32 v0, v0 ; MOVREL-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v16f32_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movrels_b32_e32 v0, v0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v16f32_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movrels_b32_e32 v0, v0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v16f32_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movrels_b32_e32 v0, v0 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <16 x float> %vec, i32 %sel ret float %ext @@ -1906,11 +1798,17 @@ define amdgpu_ps float @dyn_extract_v32f32_v_s(<32 x float> %vec, i32 inreg %sel ; MOVREL-NEXT: v_movrels_b32_e32 v0, v0 ; MOVREL-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v32f32_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movrels_b32_e32 v0, v0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v32f32_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movrels_b32_e32 v0, v0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v32f32_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movrels_b32_e32 v0, v0 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <32 x float> %vec, i32 %sel ret float %ext @@ -1935,13 +1833,21 @@ define amdgpu_ps double @dyn_extract_v16f64_v_s(<16 x double> %vec, i32 inreg %s ; MOVREL-NEXT: v_mov_b32_e32 v0, v32 ; MOVREL-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v16f64_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_lshl_b32 m0, s2, 1 -; GFX10PLUS-NEXT: v_movrels_b32_e32 v32, v0 -; GFX10PLUS-NEXT: v_movrels_b32_e32 v1, v1 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v32 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v16f64_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_lshl_b32 m0, s2, 1 +; GFX10-NEXT: v_movrels_b32_e32 v32, v0 +; GFX10-NEXT: v_movrels_b32_e32 v1, v1 +; GFX10-NEXT: v_mov_b32_e32 v0, v32 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v16f64_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_lshl_b32 m0, s0, 1 +; GFX11-NEXT: v_movrels_b32_e32 v32, v0 +; GFX11-NEXT: v_movrels_b32_e32 v1, v1 +; GFX11-NEXT: v_mov_b32_e32 v0, v32 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <16 x double> %vec, i32 %sel ret double %ext @@ -1971,28 +1877,51 @@ define amdgpu_ps float @dyn_extract_v16f32_s_s(i32 inreg %sel) { ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v16f32_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s4, 1.0 -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: s_mov_b32 s19, 0x41800000 -; GFX10PLUS-NEXT: s_mov_b32 s18, 0x41700000 -; GFX10PLUS-NEXT: s_mov_b32 s17, 0x41600000 -; GFX10PLUS-NEXT: s_mov_b32 s16, 0x41500000 -; GFX10PLUS-NEXT: s_mov_b32 s15, 0x41400000 -; GFX10PLUS-NEXT: s_mov_b32 s14, 0x41300000 -; GFX10PLUS-NEXT: s_mov_b32 s13, 0x41200000 -; GFX10PLUS-NEXT: s_mov_b32 s12, 0x41100000 -; GFX10PLUS-NEXT: s_mov_b32 s11, 0x41000000 -; GFX10PLUS-NEXT: s_mov_b32 s10, 0x40e00000 -; GFX10PLUS-NEXT: s_mov_b32 s9, 0x40c00000 -; GFX10PLUS-NEXT: s_mov_b32 s8, 0x40a00000 -; GFX10PLUS-NEXT: s_mov_b32 s7, 4.0 -; GFX10PLUS-NEXT: s_mov_b32 s6, 0x40400000 -; GFX10PLUS-NEXT: s_mov_b32 s5, 2.0 -; GFX10PLUS-NEXT: s_movrels_b32 s0, s4 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v16f32_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s4, 1.0 +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: s_mov_b32 s19, 0x41800000 +; GFX10-NEXT: s_mov_b32 s18, 0x41700000 +; GFX10-NEXT: s_mov_b32 s17, 0x41600000 +; GFX10-NEXT: s_mov_b32 s16, 0x41500000 +; GFX10-NEXT: s_mov_b32 s15, 0x41400000 +; GFX10-NEXT: s_mov_b32 s14, 0x41300000 +; GFX10-NEXT: s_mov_b32 s13, 0x41200000 +; GFX10-NEXT: s_mov_b32 s12, 0x41100000 +; GFX10-NEXT: s_mov_b32 s11, 0x41000000 +; GFX10-NEXT: s_mov_b32 s10, 0x40e00000 +; GFX10-NEXT: s_mov_b32 s9, 0x40c00000 +; GFX10-NEXT: s_mov_b32 s8, 0x40a00000 +; GFX10-NEXT: s_mov_b32 s7, 4.0 +; GFX10-NEXT: s_mov_b32 s6, 0x40400000 +; GFX10-NEXT: s_mov_b32 s5, 2.0 +; GFX10-NEXT: s_movrels_b32 s0, s4 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v16f32_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 s4, 1.0 +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: s_mov_b32 s19, 0x41800000 +; GFX11-NEXT: s_mov_b32 s18, 0x41700000 +; GFX11-NEXT: s_mov_b32 s17, 0x41600000 +; GFX11-NEXT: s_mov_b32 s16, 0x41500000 +; GFX11-NEXT: s_mov_b32 s15, 0x41400000 +; GFX11-NEXT: s_mov_b32 s14, 0x41300000 +; GFX11-NEXT: s_mov_b32 s13, 0x41200000 +; GFX11-NEXT: s_mov_b32 s12, 0x41100000 +; GFX11-NEXT: s_mov_b32 s11, 0x41000000 +; GFX11-NEXT: s_mov_b32 s10, 0x40e00000 +; GFX11-NEXT: s_mov_b32 s9, 0x40c00000 +; GFX11-NEXT: s_mov_b32 s8, 0x40a00000 +; GFX11-NEXT: s_mov_b32 s7, 4.0 +; GFX11-NEXT: s_mov_b32 s6, 0x40400000 +; GFX11-NEXT: s_mov_b32 s5, 2.0 +; GFX11-NEXT: s_movrels_b32 s0, s4 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <16 x float> , i32 %sel ret float %ext @@ -2038,44 +1967,83 @@ define amdgpu_ps float @dyn_extract_v32f32_s_s(i32 inreg %sel) { ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v32f32_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s36, 1.0 -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: s_mov_b32 s67, 0x42000000 -; GFX10PLUS-NEXT: s_mov_b32 s66, 0x41f80000 -; GFX10PLUS-NEXT: s_mov_b32 s65, 0x41f00000 -; GFX10PLUS-NEXT: s_mov_b32 s64, 0x41e80000 -; GFX10PLUS-NEXT: s_mov_b32 s63, 0x41e00000 -; GFX10PLUS-NEXT: s_mov_b32 s62, 0x41d80000 -; GFX10PLUS-NEXT: s_mov_b32 s61, 0x41d00000 -; GFX10PLUS-NEXT: s_mov_b32 s60, 0x41c80000 -; GFX10PLUS-NEXT: s_mov_b32 s59, 0x41c00000 -; GFX10PLUS-NEXT: s_mov_b32 s58, 0x41b80000 -; GFX10PLUS-NEXT: s_mov_b32 s57, 0x41b00000 -; GFX10PLUS-NEXT: s_mov_b32 s56, 0x41a80000 -; GFX10PLUS-NEXT: s_mov_b32 s55, 0x41a00000 -; GFX10PLUS-NEXT: s_mov_b32 s54, 0x41980000 -; GFX10PLUS-NEXT: s_mov_b32 s53, 0x41900000 -; GFX10PLUS-NEXT: s_mov_b32 s52, 0x41880000 -; GFX10PLUS-NEXT: s_mov_b32 s51, 0x41800000 -; GFX10PLUS-NEXT: s_mov_b32 s50, 0x41700000 -; GFX10PLUS-NEXT: s_mov_b32 s49, 0x41600000 -; GFX10PLUS-NEXT: s_mov_b32 s48, 0x41500000 -; GFX10PLUS-NEXT: s_mov_b32 s47, 0x41400000 -; GFX10PLUS-NEXT: s_mov_b32 s46, 0x41300000 -; GFX10PLUS-NEXT: s_mov_b32 s45, 0x41200000 -; GFX10PLUS-NEXT: s_mov_b32 s44, 0x41100000 -; GFX10PLUS-NEXT: s_mov_b32 s43, 0x41000000 -; GFX10PLUS-NEXT: s_mov_b32 s42, 0x40e00000 -; GFX10PLUS-NEXT: s_mov_b32 s41, 0x40c00000 -; GFX10PLUS-NEXT: s_mov_b32 s40, 0x40a00000 -; GFX10PLUS-NEXT: s_mov_b32 s39, 4.0 -; GFX10PLUS-NEXT: s_mov_b32 s38, 0x40400000 -; GFX10PLUS-NEXT: s_mov_b32 s37, 2.0 -; GFX10PLUS-NEXT: s_movrels_b32 s0, s36 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v32f32_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s36, 1.0 +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: s_mov_b32 s67, 0x42000000 +; GFX10-NEXT: s_mov_b32 s66, 0x41f80000 +; GFX10-NEXT: s_mov_b32 s65, 0x41f00000 +; GFX10-NEXT: s_mov_b32 s64, 0x41e80000 +; GFX10-NEXT: s_mov_b32 s63, 0x41e00000 +; GFX10-NEXT: s_mov_b32 s62, 0x41d80000 +; GFX10-NEXT: s_mov_b32 s61, 0x41d00000 +; GFX10-NEXT: s_mov_b32 s60, 0x41c80000 +; GFX10-NEXT: s_mov_b32 s59, 0x41c00000 +; GFX10-NEXT: s_mov_b32 s58, 0x41b80000 +; GFX10-NEXT: s_mov_b32 s57, 0x41b00000 +; GFX10-NEXT: s_mov_b32 s56, 0x41a80000 +; GFX10-NEXT: s_mov_b32 s55, 0x41a00000 +; GFX10-NEXT: s_mov_b32 s54, 0x41980000 +; GFX10-NEXT: s_mov_b32 s53, 0x41900000 +; GFX10-NEXT: s_mov_b32 s52, 0x41880000 +; GFX10-NEXT: s_mov_b32 s51, 0x41800000 +; GFX10-NEXT: s_mov_b32 s50, 0x41700000 +; GFX10-NEXT: s_mov_b32 s49, 0x41600000 +; GFX10-NEXT: s_mov_b32 s48, 0x41500000 +; GFX10-NEXT: s_mov_b32 s47, 0x41400000 +; GFX10-NEXT: s_mov_b32 s46, 0x41300000 +; GFX10-NEXT: s_mov_b32 s45, 0x41200000 +; GFX10-NEXT: s_mov_b32 s44, 0x41100000 +; GFX10-NEXT: s_mov_b32 s43, 0x41000000 +; GFX10-NEXT: s_mov_b32 s42, 0x40e00000 +; GFX10-NEXT: s_mov_b32 s41, 0x40c00000 +; GFX10-NEXT: s_mov_b32 s40, 0x40a00000 +; GFX10-NEXT: s_mov_b32 s39, 4.0 +; GFX10-NEXT: s_mov_b32 s38, 0x40400000 +; GFX10-NEXT: s_mov_b32 s37, 2.0 +; GFX10-NEXT: s_movrels_b32 s0, s36 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v32f32_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 s36, 1.0 +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: s_mov_b32 s67, 0x42000000 +; GFX11-NEXT: s_mov_b32 s66, 0x41f80000 +; GFX11-NEXT: s_mov_b32 s65, 0x41f00000 +; GFX11-NEXT: s_mov_b32 s64, 0x41e80000 +; GFX11-NEXT: s_mov_b32 s63, 0x41e00000 +; GFX11-NEXT: s_mov_b32 s62, 0x41d80000 +; GFX11-NEXT: s_mov_b32 s61, 0x41d00000 +; GFX11-NEXT: s_mov_b32 s60, 0x41c80000 +; GFX11-NEXT: s_mov_b32 s59, 0x41c00000 +; GFX11-NEXT: s_mov_b32 s58, 0x41b80000 +; GFX11-NEXT: s_mov_b32 s57, 0x41b00000 +; GFX11-NEXT: s_mov_b32 s56, 0x41a80000 +; GFX11-NEXT: s_mov_b32 s55, 0x41a00000 +; GFX11-NEXT: s_mov_b32 s54, 0x41980000 +; GFX11-NEXT: s_mov_b32 s53, 0x41900000 +; GFX11-NEXT: s_mov_b32 s52, 0x41880000 +; GFX11-NEXT: s_mov_b32 s51, 0x41800000 +; GFX11-NEXT: s_mov_b32 s50, 0x41700000 +; GFX11-NEXT: s_mov_b32 s49, 0x41600000 +; GFX11-NEXT: s_mov_b32 s48, 0x41500000 +; GFX11-NEXT: s_mov_b32 s47, 0x41400000 +; GFX11-NEXT: s_mov_b32 s46, 0x41300000 +; GFX11-NEXT: s_mov_b32 s45, 0x41200000 +; GFX11-NEXT: s_mov_b32 s44, 0x41100000 +; GFX11-NEXT: s_mov_b32 s43, 0x41000000 +; GFX11-NEXT: s_mov_b32 s42, 0x40e00000 +; GFX11-NEXT: s_mov_b32 s41, 0x40c00000 +; GFX11-NEXT: s_mov_b32 s40, 0x40a00000 +; GFX11-NEXT: s_mov_b32 s39, 4.0 +; GFX11-NEXT: s_mov_b32 s38, 0x40400000 +; GFX11-NEXT: s_mov_b32 s37, 2.0 +; GFX11-NEXT: s_movrels_b32 s0, s36 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <32 x float> , i32 %sel ret float %ext @@ -2159,7 +2127,7 @@ define amdgpu_ps double @dyn_extract_v16f64_s_s(i32 inreg %sel) { ; GFX11-LABEL: dyn_extract_v16f64_s_s: ; GFX11: ; %bb.0: ; %entry ; GFX11-NEXT: s_mov_b64 s[36:37], 1.0 -; GFX11-NEXT: s_mov_b32 m0, s2 +; GFX11-NEXT: s_mov_b32 m0, s0 ; GFX11-NEXT: s_mov_b32 s66, 0 ; GFX11-NEXT: s_mov_b32 s67, 0x40300000 ; GFX11-NEXT: s_mov_b32 s64, 0 @@ -2217,20 +2185,35 @@ define amdgpu_ps float @dyn_extract_v6f32_s_v(<6 x float> inreg %vec, i32 %sel) ; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v6, vcc ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v6f32_s_v: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: v_mov_b32_e32 v1, s3 -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, s2, v1, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v1, s7, vcc_lo -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v6f32_s_v: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: v_mov_b32_e32 v1, s3 +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v1, s2, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s7, vcc_lo +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v6f32_s_v: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX11-NEXT: v_cndmask_b32_e32 v1, s0, v1, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s5, vcc_lo +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <6 x float> %vec, i32 %sel ret float %ext @@ -2285,11 +2268,17 @@ define amdgpu_ps float @dyn_extract_v6f32_v_s(<6 x float> %vec, i32 inreg %sel) ; MOVREL-NEXT: v_movrels_b32_e32 v0, v0 ; MOVREL-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v6f32_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movrels_b32_e32 v0, v0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v6f32_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movrels_b32_e32 v0, v0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v6f32_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movrels_b32_e32 v0, v0 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <6 x float> %vec, i32 %sel ret float %ext @@ -2309,18 +2298,25 @@ define amdgpu_ps float @dyn_extract_v6f32_s_s(<6 x float> inreg %vec, i32 inreg ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v6f32_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 m0, s8 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_movrels_b32 s0, s0 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v6f32_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 m0, s8 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_movrels_b32 s0, s0 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v6f32_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s6 +; GFX11-NEXT: s_movrels_b32 s0, s0 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <6 x float> %vec, i32 %sel ret float %ext @@ -2350,22 +2346,39 @@ define amdgpu_ps float @dyn_extract_v7f32_s_v(<7 x float> inreg %vec, i32 %sel) ; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v7, vcc ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v7f32_s_v: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: v_mov_b32_e32 v1, s3 -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, s2, v1, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s7, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v1, s8, vcc_lo -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v7f32_s_v: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: v_mov_b32_e32 v1, s3 +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v1, s2, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s7, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s8, vcc_lo +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v7f32_s_v: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX11-NEXT: v_cndmask_b32_e32 v1, s0, v1, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s6, vcc_lo +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <7 x float> %vec, i32 %sel ret float %ext @@ -2424,11 +2437,17 @@ define amdgpu_ps float @dyn_extract_v7f32_v_s(<7 x float> %vec, i32 inreg %sel) ; MOVREL-NEXT: v_movrels_b32_e32 v0, v0 ; MOVREL-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v7f32_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movrels_b32_e32 v0, v0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v7f32_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movrels_b32_e32 v0, v0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v7f32_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movrels_b32_e32 v0, v0 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <7 x float> %vec, i32 %sel ret float %ext @@ -2449,19 +2468,26 @@ define amdgpu_ps float @dyn_extract_v7f32_s_s(<7 x float> inreg %vec, i32 inreg ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v7f32_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 m0, s9 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_mov_b32 s6, s8 -; GFX10PLUS-NEXT: s_movrels_b32 s0, s0 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v7f32_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 m0, s9 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_movrels_b32 s0, s0 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v7f32_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s7 +; GFX11-NEXT: s_movrels_b32 s0, s0 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <7 x float> %vec, i32 %sel ret float %ext @@ -2522,22 +2548,22 @@ define amdgpu_ps double @dyn_extract_v6f64_s_v(<6 x double> inreg %vec, i32 %sel ; ; GFX11-LABEL: dyn_extract_v6f64_s_v: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s5 +; GFX11-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX11-NEXT: v_cndmask_b32_e32 v1, s2, v1, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e32 v2, s3, v2, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v1, s0, v1, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v2, s1, v2, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s5, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s7, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s9, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s10, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s11, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s12, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s13, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s10, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s11, vcc_lo ; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <6 x double> %vec, i32 %sel @@ -2623,13 +2649,21 @@ define amdgpu_ps double @dyn_extract_v6f64_v_s(<6 x double> %vec, i32 inreg %sel ; MOVREL-NEXT: v_mov_b32_e32 v0, v12 ; MOVREL-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v6f64_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_lshl_b32 m0, s2, 1 -; GFX10PLUS-NEXT: v_movrels_b32_e32 v12, v0 -; GFX10PLUS-NEXT: v_movrels_b32_e32 v1, v1 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v12 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v6f64_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_lshl_b32 m0, s2, 1 +; GFX10-NEXT: v_movrels_b32_e32 v12, v0 +; GFX10-NEXT: v_movrels_b32_e32 v1, v1 +; GFX10-NEXT: v_mov_b32_e32 v0, v12 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v6f64_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_lshl_b32 m0, s0, 1 +; GFX11-NEXT: v_movrels_b32_e32 v12, v0 +; GFX11-NEXT: v_movrels_b32_e32 v1, v1 +; GFX11-NEXT: v_mov_b32_e32 v0, v12 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <6 x double> %vec, i32 %sel ret double %ext @@ -2678,19 +2712,7 @@ define amdgpu_ps double @dyn_extract_v6f64_s_s(<6 x double> inreg %vec, i32 inre ; ; GFX11-LABEL: dyn_extract_v6f64_s_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 m0, s14 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 +; GFX11-NEXT: s_mov_b32 m0, s12 ; GFX11-NEXT: s_movrels_b64 s[0:1], s[0:1] ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: ; return to shader part epilog @@ -2780,22 +2802,22 @@ define amdgpu_ps double @dyn_extract_v7f64_s_v_bitcast(<14 x float> inreg %userD ; ; GFX11-LABEL: dyn_extract_v7f64_s_v_bitcast: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3 -; GFX11-NEXT: v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5 +; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX11-NEXT: v_dual_mov_b32 v5, s6 :: v_dual_mov_b32 v6, s7 +; GFX11-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4 ; GFX11-NEXT: v_dual_cndmask_b32 v3, v1, v3 :: v_dual_cndmask_b32 v4, v2, v4 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 -; GFX11-NEXT: v_dual_mov_b32 v1, s8 :: v_dual_mov_b32 v2, s9 +; GFX11-NEXT: v_dual_mov_b32 v1, s6 :: v_dual_mov_b32 v2, s7 ; GFX11-NEXT: v_dual_cndmask_b32 v5, v3, v5 :: v_dual_cndmask_b32 v6, v4, v6 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 -; GFX11-NEXT: v_dual_mov_b32 v3, s10 :: v_dual_mov_b32 v4, s11 +; GFX11-NEXT: v_dual_mov_b32 v3, s8 :: v_dual_mov_b32 v4, s9 ; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v1 :: v_dual_cndmask_b32 v6, v6, v2 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 -; GFX11-NEXT: v_dual_mov_b32 v1, s12 :: v_dual_mov_b32 v2, s13 +; GFX11-NEXT: v_dual_mov_b32 v1, s10 :: v_dual_mov_b32 v2, s11 ; GFX11-NEXT: v_dual_cndmask_b32 v5, v5, v3 :: v_dual_cndmask_b32 v6, v6, v4 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 -; GFX11-NEXT: v_dual_mov_b32 v3, s14 :: v_dual_mov_b32 v4, s15 +; GFX11-NEXT: v_dual_mov_b32 v3, s12 :: v_dual_mov_b32 v4, s13 ; GFX11-NEXT: v_dual_cndmask_b32 v1, v5, v1 :: v_dual_cndmask_b32 v2, v6, v2 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 ; GFX11-NEXT: v_dual_cndmask_b32 v1, v1, v3 :: v_dual_cndmask_b32 v2, v2, v4 @@ -2815,11 +2837,17 @@ define amdgpu_ps i64 @dyn_extract_v7i64_s_v_bitcast(<14 x i32> inreg %userData, ; GCN-NEXT: s_mov_b32 s1, s11 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v7i64_s_v_bitcast: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s0, s10 -; GFX10PLUS-NEXT: s_mov_b32 s1, s11 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v7i64_s_v_bitcast: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, s10 +; GFX10-NEXT: s_mov_b32 s1, s11 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v7i64_s_v_bitcast: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 s0, s8 +; GFX11-NEXT: s_mov_b32 s1, s9 +; GFX11-NEXT: ; return to shader part epilog entry: %.bc = bitcast <14 x i32> %userData to <7 x i64> %ext = extractelement <7 x i64> %.bc, i32 4 @@ -2895,25 +2923,25 @@ define amdgpu_ps double @dyn_extract_v7f64_s_v(<7 x double> inreg %vec, i32 %sel ; ; GFX11-LABEL: dyn_extract_v7f64_s_v: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s5 +; GFX11-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX11-NEXT: v_cndmask_b32_e32 v1, s2, v1, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e32 v2, s3, v2, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v1, s0, v1, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v2, s1, v2, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s5, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s7, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s9, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s10, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s11, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s12, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s13, vcc_lo -; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s14, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s15, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 ; GFX11-NEXT: v_dual_cndmask_b32 v0, v1, v0 :: v_dual_cndmask_b32 v1, v2, v1 ; GFX11-NEXT: ; return to shader part epilog @@ -3017,13 +3045,21 @@ define amdgpu_ps double @dyn_extract_v7f64_v_s(<7 x double> %vec, i32 inreg %sel ; MOVREL-NEXT: v_mov_b32_e32 v0, v14 ; MOVREL-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v7f64_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_lshl_b32 m0, s2, 1 -; GFX10PLUS-NEXT: v_movrels_b32_e32 v14, v0 -; GFX10PLUS-NEXT: v_movrels_b32_e32 v1, v1 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, v14 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v7f64_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_lshl_b32 m0, s2, 1 +; GFX10-NEXT: v_movrels_b32_e32 v14, v0 +; GFX10-NEXT: v_movrels_b32_e32 v1, v1 +; GFX10-NEXT: v_mov_b32_e32 v0, v14 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v7f64_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_lshl_b32 m0, s0, 1 +; GFX11-NEXT: v_movrels_b32_e32 v14, v0 +; GFX11-NEXT: v_movrels_b32_e32 v1, v1 +; GFX11-NEXT: v_mov_b32_e32 v0, v14 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <7 x double> %vec, i32 %sel ret double %ext @@ -3076,21 +3112,7 @@ define amdgpu_ps double @dyn_extract_v7f64_s_s(<7 x double> inreg %vec, i32 inre ; ; GFX11-LABEL: dyn_extract_v7f64_s_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 m0, s16 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 +; GFX11-NEXT: s_mov_b32 m0, s14 ; GFX11-NEXT: s_movrels_b64 s[0:1], s[0:1] ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: ; return to shader part epilog @@ -3607,27 +3629,49 @@ define amdgpu_ps float @dyn_extract_v15f32_const_s_s(i32 inreg %sel) { ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v15f32_const_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s4, 1.0 -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: s_mov_b32 s18, 0x41700000 -; GFX10PLUS-NEXT: s_mov_b32 s17, 0x41600000 -; GFX10PLUS-NEXT: s_mov_b32 s16, 0x41500000 -; GFX10PLUS-NEXT: s_mov_b32 s15, 0x41400000 -; GFX10PLUS-NEXT: s_mov_b32 s14, 0x41300000 -; GFX10PLUS-NEXT: s_mov_b32 s13, 0x41200000 -; GFX10PLUS-NEXT: s_mov_b32 s12, 0x41100000 -; GFX10PLUS-NEXT: s_mov_b32 s11, 0x41000000 -; GFX10PLUS-NEXT: s_mov_b32 s10, 0x40e00000 -; GFX10PLUS-NEXT: s_mov_b32 s9, 0x40c00000 -; GFX10PLUS-NEXT: s_mov_b32 s8, 0x40a00000 -; GFX10PLUS-NEXT: s_mov_b32 s7, 4.0 -; GFX10PLUS-NEXT: s_mov_b32 s6, 0x40400000 -; GFX10PLUS-NEXT: s_mov_b32 s5, 2.0 -; GFX10PLUS-NEXT: s_movrels_b32 s0, s4 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v15f32_const_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s4, 1.0 +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: s_mov_b32 s18, 0x41700000 +; GFX10-NEXT: s_mov_b32 s17, 0x41600000 +; GFX10-NEXT: s_mov_b32 s16, 0x41500000 +; GFX10-NEXT: s_mov_b32 s15, 0x41400000 +; GFX10-NEXT: s_mov_b32 s14, 0x41300000 +; GFX10-NEXT: s_mov_b32 s13, 0x41200000 +; GFX10-NEXT: s_mov_b32 s12, 0x41100000 +; GFX10-NEXT: s_mov_b32 s11, 0x41000000 +; GFX10-NEXT: s_mov_b32 s10, 0x40e00000 +; GFX10-NEXT: s_mov_b32 s9, 0x40c00000 +; GFX10-NEXT: s_mov_b32 s8, 0x40a00000 +; GFX10-NEXT: s_mov_b32 s7, 4.0 +; GFX10-NEXT: s_mov_b32 s6, 0x40400000 +; GFX10-NEXT: s_mov_b32 s5, 2.0 +; GFX10-NEXT: s_movrels_b32 s0, s4 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v15f32_const_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 s4, 1.0 +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: s_mov_b32 s18, 0x41700000 +; GFX11-NEXT: s_mov_b32 s17, 0x41600000 +; GFX11-NEXT: s_mov_b32 s16, 0x41500000 +; GFX11-NEXT: s_mov_b32 s15, 0x41400000 +; GFX11-NEXT: s_mov_b32 s14, 0x41300000 +; GFX11-NEXT: s_mov_b32 s13, 0x41200000 +; GFX11-NEXT: s_mov_b32 s12, 0x41100000 +; GFX11-NEXT: s_mov_b32 s11, 0x41000000 +; GFX11-NEXT: s_mov_b32 s10, 0x40e00000 +; GFX11-NEXT: s_mov_b32 s9, 0x40c00000 +; GFX11-NEXT: s_mov_b32 s8, 0x40a00000 +; GFX11-NEXT: s_mov_b32 s7, 4.0 +; GFX11-NEXT: s_mov_b32 s6, 0x40400000 +; GFX11-NEXT: s_mov_b32 s5, 2.0 +; GFX11-NEXT: s_movrels_b32 s0, s4 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <15 x float> , i32 %sel ret float %ext @@ -3683,40 +3727,75 @@ define amdgpu_ps float @dyn_extract_v15f32_s_v(<15 x float> inreg %vec, i32 %sel ; GCN-NEXT: v_cndmask_b32_e32 v0, v1, v0, vcc ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v15f32_s_v: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: v_mov_b32_e32 v1, s3 -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e32 v1, s2, v1, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s7, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s9, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s10, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s11, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 10, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s12, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 11, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s13, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 12, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s14, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 13, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s15, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 14, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s16, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 15, v0 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v1, s0, vcc_lo -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v15f32_s_v: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: v_mov_b32_e32 v1, s3 +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX10-NEXT: v_cndmask_b32_e32 v1, s2, v1, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s7, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s9, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s10, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s11, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 10, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s12, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 11, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s13, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 12, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s14, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 13, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s15, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 14, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s16, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 15, v0 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v1, s0, vcc_lo +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v15f32_s_v: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: v_mov_b32_e32 v1, s1 +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 +; GFX11-NEXT: v_cndmask_b32_e32 v1, s0, v1, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s5, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s6, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s7, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s8, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s9, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 10, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s10, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 11, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s11, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 12, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s12, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 13, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s13, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 14, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s14, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 15, v0 +; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, s0, vcc_lo +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <15 x float> %vec, i32 %sel ret float %ext @@ -3846,11 +3925,17 @@ define amdgpu_ps float @dyn_extract_v15f32_v_s(<15 x float> %vec, i32 inreg %sel ; MOVREL-NEXT: v_movrels_b32_e32 v0, v0 ; MOVREL-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v15f32_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movrels_b32_e32 v0, v0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v15f32_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movrels_b32_e32 v0, v0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v15f32_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movrels_b32_e32 v0, v0 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <15 x float> %vec, i32 %sel ret float %ext @@ -3879,27 +3964,34 @@ define amdgpu_ps float @dyn_extract_v15f32_s_s(<15 x float> inreg %vec, i32 inre ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v15f32_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 m0, s17 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_mov_b32 s6, s8 -; GFX10PLUS-NEXT: s_mov_b32 s7, s9 -; GFX10PLUS-NEXT: s_mov_b32 s8, s10 -; GFX10PLUS-NEXT: s_mov_b32 s9, s11 -; GFX10PLUS-NEXT: s_mov_b32 s10, s12 -; GFX10PLUS-NEXT: s_mov_b32 s11, s13 -; GFX10PLUS-NEXT: s_mov_b32 s12, s14 -; GFX10PLUS-NEXT: s_mov_b32 s13, s15 -; GFX10PLUS-NEXT: s_mov_b32 s14, s16 -; GFX10PLUS-NEXT: s_movrels_b32 s0, s0 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v15f32_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 m0, s17 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: s_mov_b32 s8, s10 +; GFX10-NEXT: s_mov_b32 s9, s11 +; GFX10-NEXT: s_mov_b32 s10, s12 +; GFX10-NEXT: s_mov_b32 s11, s13 +; GFX10-NEXT: s_mov_b32 s12, s14 +; GFX10-NEXT: s_mov_b32 s13, s15 +; GFX10-NEXT: s_mov_b32 s14, s16 +; GFX10-NEXT: s_movrels_b32 s0, s0 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v15f32_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s15 +; GFX11-NEXT: s_movrels_b32 s0, s0 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog entry: %ext = extractelement <15 x float> %vec, i32 %sel ret float %ext @@ -3928,27 +4020,34 @@ define amdgpu_ps float @dyn_extract_v15f32_s_s_offset3(<15 x float> inreg %vec, ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_extract_v15f32_s_s_offset3: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 m0, s17 -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_mov_b32 s6, s8 -; GFX10PLUS-NEXT: s_mov_b32 s7, s9 -; GFX10PLUS-NEXT: s_mov_b32 s8, s10 -; GFX10PLUS-NEXT: s_mov_b32 s9, s11 -; GFX10PLUS-NEXT: s_mov_b32 s10, s12 -; GFX10PLUS-NEXT: s_mov_b32 s11, s13 -; GFX10PLUS-NEXT: s_mov_b32 s12, s14 -; GFX10PLUS-NEXT: s_mov_b32 s13, s15 -; GFX10PLUS-NEXT: s_mov_b32 s14, s16 -; GFX10PLUS-NEXT: s_movrels_b32 s0, s3 -; GFX10PLUS-NEXT: v_mov_b32_e32 v0, s0 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_extract_v15f32_s_s_offset3: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 m0, s17 +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: s_mov_b32 s8, s10 +; GFX10-NEXT: s_mov_b32 s9, s11 +; GFX10-NEXT: s_mov_b32 s10, s12 +; GFX10-NEXT: s_mov_b32 s11, s13 +; GFX10-NEXT: s_mov_b32 s12, s14 +; GFX10-NEXT: s_mov_b32 s13, s15 +; GFX10-NEXT: s_mov_b32 s14, s16 +; GFX10-NEXT: s_movrels_b32 s0, s3 +; GFX10-NEXT: v_mov_b32_e32 v0, s0 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_extract_v15f32_s_s_offset3: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s15 +; GFX11-NEXT: s_movrels_b32 s0, s3 +; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog entry: %add = add i32 %sel, 3 %ext = extractelement <15 x float> %vec, i32 %add diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll index b74665f781b56c..67a3e5af19a008 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i16.ll @@ -77,9 +77,9 @@ define amdgpu_ps void @insertelement_s_v2i16_s_s(ptr addrspace(4) inreg %ptr, i1 ; ; GFX11-LABEL: insertelement_s_v2i16_s_s: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 -; GFX11-NEXT: s_and_b32 s1, s5, 1 -; GFX11-NEXT: s_and_b32 s2, s4, 0xffff +; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 +; GFX11-NEXT: s_and_b32 s1, s3, 1 +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff ; GFX11-NEXT: s_lshl_b32 s1, s1, 4 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0 ; GFX11-NEXT: s_lshl_b32 s3, 0xffff, s1 @@ -169,12 +169,12 @@ define amdgpu_ps void @insertelement_v_v2i16_s_s(ptr addrspace(1) %ptr, i16 inre ; GFX11-LABEL: insertelement_v_v2i16_s_s: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b32 v2, v[0:1], off -; GFX11-NEXT: s_and_b32 s0, s3, 1 -; GFX11-NEXT: s_and_b32 s1, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s0, s0, 4 +; GFX11-NEXT: s_and_b32 s1, s1, 1 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_lshl_b32 s1, s1, 4 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0 -; GFX11-NEXT: s_lshl_b32 s2, 0xffff, s0 -; GFX11-NEXT: s_lshl_b32 s0, s1, s0 +; GFX11-NEXT: s_lshl_b32 s2, 0xffff, s1 +; GFX11-NEXT: s_lshl_b32 s0, s0, s1 ; GFX11-NEXT: s_not_b32 s1, s2 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_and_or_b32 v2, v2, s1, s0 @@ -253,8 +253,8 @@ define amdgpu_ps void @insertelement_s_v2i16_v_s(ptr addrspace(4) inreg %ptr, i1 ; ; GFX11-LABEL: insertelement_s_v2i16_v_s: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 -; GFX11-NEXT: s_and_b32 s1, s4, 1 +; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 +; GFX11-NEXT: s_and_b32 s1, s2, 1 ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v2, 0xffff, v0 ; GFX11-NEXT: s_lshl_b32 s1, s1, 4 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 @@ -341,9 +341,9 @@ define amdgpu_ps void @insertelement_s_v2i16_s_v(ptr addrspace(4) inreg %ptr, i1 ; ; GFX11-LABEL: insertelement_s_v2i16_s_v: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 +; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX11-NEXT: s_and_b32 s1, s4, 0xffff +; GFX11-NEXT: s_and_b32 s1, s2, 0xffff ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GFX11-NEXT: v_lshlrev_b32_e64 v1, v0, 0xffff @@ -429,7 +429,7 @@ define amdgpu_ps void @insertelement_s_v2i16_v_v(ptr addrspace(4) inreg %ptr, i1 ; ; GFX11-LABEL: insertelement_s_v2i16_v_v: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 +; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: v_and_b32_e32 v1, 1, v1 ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -524,7 +524,7 @@ define amdgpu_ps void @insertelement_v_v2i16_s_v(ptr addrspace(1) %ptr, i16 inre ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b32 v3, v[0:1], off ; GFX11-NEXT: v_and_b32_e32 v0, 1, v2 -; GFX11-NEXT: s_and_b32 s0, s2, 0xffff +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0 ; GFX11-NEXT: v_lshlrev_b32_e64 v1, v0, 0xffff @@ -613,7 +613,7 @@ define amdgpu_ps void @insertelement_v_v2i16_v_s(ptr addrspace(1) %ptr, i16 %val ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b32 v3, v[0:1], off ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0xffff, v2 -; GFX11-NEXT: s_and_b32 s0, s2, 1 +; GFX11-NEXT: s_and_b32 s0, s0, 1 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_lshl_b32 s0, s0, 4 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -866,12 +866,12 @@ define amdgpu_ps void @insertelement_v_v4i16_s_s(ptr addrspace(1) %ptr, i16 inre ; GFX11-LABEL: insertelement_v_v4i16_s_s: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off -; GFX11-NEXT: s_and_b32 s0, s3, 1 -; GFX11-NEXT: s_lshr_b32 m0, s3, 1 -; GFX11-NEXT: s_lshl_b32 s0, s0, 4 -; GFX11-NEXT: s_and_b32 s1, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s2, 0xffff, s0 -; GFX11-NEXT: s_lshl_b32 s0, s1, s0 +; GFX11-NEXT: s_and_b32 s2, s1, 1 +; GFX11-NEXT: s_lshr_b32 m0, s1, 1 +; GFX11-NEXT: s_lshl_b32 s1, s2, 4 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_lshl_b32 s2, 0xffff, s1 +; GFX11-NEXT: s_lshl_b32 s0, s0, s1 ; GFX11-NEXT: s_not_b32 s1, s2 ; GFX11-NEXT: v_mov_b32_e32 v3, 0 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -978,10 +978,10 @@ define amdgpu_ps void @insertelement_s_v4i16_v_s(ptr addrspace(4) inreg %ptr, i1 ; ; GFX11-LABEL: insertelement_s_v4i16_v_s: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_and_b32 s2, s4, 1 -; GFX11-NEXT: s_lshr_b32 m0, s4, 1 -; GFX11-NEXT: s_lshl_b32 s2, s2, 4 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; GFX11-NEXT: s_and_b32 s3, s2, 1 +; GFX11-NEXT: s_lshr_b32 m0, s2, 1 +; GFX11-NEXT: s_lshl_b32 s2, s3, 4 ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-NEXT: s_lshl_b32 s3, 0xffff, s2 ; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0 @@ -1103,10 +1103,10 @@ define amdgpu_ps void @insertelement_s_v4i16_s_v(ptr addrspace(4) inreg %ptr, i1 ; ; GFX11-LABEL: insertelement_s_v4i16_s_v: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: v_and_b32_e32 v1, 1, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v4, 1, v0 -; GFX11-NEXT: s_and_b32 s2, s4, 0xffff +; GFX11-NEXT: s_and_b32 s2, s2, 0xffff ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) @@ -1230,7 +1230,7 @@ define amdgpu_ps void @insertelement_s_v4i16_v_v(ptr addrspace(4) inreg %ptr, i1 ; ; GFX11-LABEL: insertelement_s_v4i16_v_v: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: v_and_b32_e32 v2, 1, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 1, v1 ; GFX11-NEXT: v_and_b32_e32 v3, 0xffff, v0 @@ -1356,7 +1356,7 @@ define amdgpu_ps void @insertelement_v_v4i16_s_v(ptr addrspace(1) %ptr, i16 inre ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 1, v2 -; GFX11-NEXT: s_and_b32 s0, s2, 0xffff +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5 ; GFX11-NEXT: v_and_b32_e32 v3, 1, v2 @@ -1467,9 +1467,9 @@ define amdgpu_ps void @insertelement_v_v4i16_v_s(ptr addrspace(1) %ptr, i16 %val ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-NEXT: s_and_b32 s0, s2, 1 -; GFX11-NEXT: s_lshr_b32 m0, s2, 1 -; GFX11-NEXT: s_lshl_b32 s0, s0, 4 +; GFX11-NEXT: s_and_b32 s1, s0, 1 +; GFX11-NEXT: s_lshr_b32 m0, s0, 1 +; GFX11-NEXT: s_lshl_b32 s0, s1, 4 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_lshlrev_b32_e32 v2, s0, v2 ; GFX11-NEXT: s_lshl_b32 s0, 0xffff, s0 @@ -1705,23 +1705,23 @@ define amdgpu_ps void @insertelement_s_v8i16_s_s(ptr addrspace(4) inreg %ptr, i1 ; ; GFX11-LABEL: insertelement_s_v8i16_s_s: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: s_lshr_b32 m0, s5, 1 -; GFX11-NEXT: s_and_b32 s5, s5, 1 -; GFX11-NEXT: s_and_b32 s4, s4, 0xffff -; GFX11-NEXT: s_lshl_b32 s5, s5, 4 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0 +; GFX11-NEXT: s_and_b32 s0, s3, 1 +; GFX11-NEXT: s_lshr_b32 m0, s3, 1 +; GFX11-NEXT: s_lshl_b32 s0, s0, 4 +; GFX11-NEXT: s_and_b32 s1, s2, 0xffff +; GFX11-NEXT: s_lshl_b32 s3, 0xffff, s0 +; GFX11-NEXT: s_lshl_b32 s0, s1, s0 ; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0 -; GFX11-NEXT: s_lshl_b32 s7, 0xffff, s5 -; GFX11-NEXT: s_lshl_b32 s4, s4, s5 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_movrels_b32 s6, s0 +; GFX11-NEXT: s_movrels_b32 s2, s4 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_and_not1_b32 s5, s6, s7 -; GFX11-NEXT: s_or_b32 s4, s5, s4 +; GFX11-NEXT: s_and_not1_b32 s1, s2, s3 +; GFX11-NEXT: s_or_b32 s0, s1, s0 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_movreld_b32 s0, s4 -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-NEXT: s_movreld_b32 s4, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 +; GFX11-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off ; GFX11-NEXT: s_endpgm %vec = load <8 x i16>, ptr addrspace(4) %ptr @@ -1818,12 +1818,12 @@ define amdgpu_ps void @insertelement_v_v8i16_s_s(ptr addrspace(1) %ptr, i16 inre ; GFX11-LABEL: insertelement_v_v8i16_s_s: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off -; GFX11-NEXT: s_and_b32 s0, s3, 1 -; GFX11-NEXT: s_lshr_b32 m0, s3, 1 -; GFX11-NEXT: s_lshl_b32 s0, s0, 4 -; GFX11-NEXT: s_and_b32 s1, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s2, 0xffff, s0 -; GFX11-NEXT: s_lshl_b32 s0, s1, s0 +; GFX11-NEXT: s_and_b32 s2, s1, 1 +; GFX11-NEXT: s_lshr_b32 m0, s1, 1 +; GFX11-NEXT: s_lshl_b32 s1, s2, 4 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_lshl_b32 s2, 0xffff, s1 +; GFX11-NEXT: s_lshl_b32 s0, s0, s1 ; GFX11-NEXT: s_not_b32 s1, s2 ; GFX11-NEXT: v_mov_b32_e32 v5, 0 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1938,21 +1938,21 @@ define amdgpu_ps void @insertelement_s_v8i16_v_s(ptr addrspace(4) inreg %ptr, i1 ; ; GFX11-LABEL: insertelement_s_v8i16_v_s: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: s_and_b32 s5, s4, 1 -; GFX11-NEXT: s_lshr_b32 m0, s4, 1 -; GFX11-NEXT: s_lshl_b32 s4, s5, 4 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0 +; GFX11-NEXT: s_and_b32 s0, s2, 1 +; GFX11-NEXT: s_lshr_b32 m0, s2, 1 +; GFX11-NEXT: s_lshl_b32 s0, s0, 4 ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-NEXT: s_lshl_b32 s5, 0xffff, s4 +; GFX11-NEXT: s_lshl_b32 s1, 0xffff, s0 ; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v2, s2 -; GFX11-NEXT: s_movrels_b32 s6, s0 -; GFX11-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-NEXT: s_and_not1_b32 s5, s6, s5 -; GFX11-NEXT: v_mov_b32_e32 v3, s3 -; GFX11-NEXT: v_lshl_or_b32 v6, v0, s4, s5 -; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: v_mov_b32_e32 v2, s6 +; GFX11-NEXT: s_movrels_b32 s2, s4 +; GFX11-NEXT: v_mov_b32_e32 v1, s5 +; GFX11-NEXT: s_and_not1_b32 s1, s2, s1 +; GFX11-NEXT: v_mov_b32_e32 v3, s7 +; GFX11-NEXT: v_lshl_or_b32 v6, v0, s0, s1 +; GFX11-NEXT: v_mov_b32_e32 v0, s4 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_movreld_b32_e32 v0, v6 ; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off @@ -2097,29 +2097,30 @@ define amdgpu_ps void @insertelement_s_v8i16_s_v(ptr addrspace(4) inreg %ptr, i1 ; ; GFX11-LABEL: insertelement_s_v8i16_s_v: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 1, v0 ; GFX11-NEXT: v_and_b32_e32 v4, 1, v0 +; GFX11-NEXT: s_and_b32 s1, s2, 0xffff ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2 -; GFX11-NEXT: v_lshlrev_b32_e32 v4, 4, v4 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v6 -; GFX11-NEXT: s_and_b32 s1, s4, 0xffff -; GFX11-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v6 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7 +; GFX11-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_dual_cndmask_b32 v5, v0, v1 :: v_dual_lshlrev_b32 v4, 4, v4 ; GFX11-NEXT: v_lshlrev_b32_e64 v7, v4, 0xffff ; GFX11-NEXT: v_lshlrev_b32_e64 v4, v4, s1 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v6 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v2, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_not_b32_e32 v7, v7 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v3, s1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_and_or_b32 v7, v5, v7, v4 ; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v7, s2 ; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v7, s0 @@ -2263,7 +2264,7 @@ define amdgpu_ps void @insertelement_s_v8i16_v_v(ptr addrspace(4) inreg %ptr, i1 ; ; GFX11-LABEL: insertelement_s_v8i16_v_v: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0 ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 1, v1 ; GFX11-NEXT: v_and_b32_e32 v5, 1, v1 ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 @@ -2422,7 +2423,7 @@ define amdgpu_ps void @insertelement_v_v8i16_s_v(ptr addrspace(1) %ptr, i16 inre ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 1, v2 ; GFX11-NEXT: v_and_b32_e32 v0, 1, v2 -; GFX11-NEXT: s_and_b32 s1, s2, 0xffff +; GFX11-NEXT: s_and_b32 s1, s0, 0xffff ; GFX11-NEXT: v_mov_b32_e32 v8, 0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 @@ -2540,9 +2541,9 @@ define amdgpu_ps void @insertelement_v_v8i16_v_s(ptr addrspace(1) %ptr, i16 %val ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v2 -; GFX11-NEXT: s_and_b32 s0, s2, 1 -; GFX11-NEXT: s_lshr_b32 m0, s2, 1 -; GFX11-NEXT: s_lshl_b32 s0, s0, 4 +; GFX11-NEXT: s_and_b32 s1, s0, 1 +; GFX11-NEXT: s_lshr_b32 m0, s0, 1 +; GFX11-NEXT: s_lshl_b32 s0, s1, 4 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_lshlrev_b32_e32 v0, s0, v0 ; GFX11-NEXT: s_lshl_b32 s0, 0xffff, s0 @@ -2836,26 +2837,26 @@ define amdgpu_ps void @insertelement_s_v16i16_s_s(ptr addrspace(4) inreg %ptr, i ; ; GFX11-LABEL: insertelement_s_v16i16_s_s: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b256 s[8:15], s[2:3], 0x0 -; GFX11-NEXT: s_and_b32 s0, s5, 1 -; GFX11-NEXT: s_lshr_b32 m0, s5, 1 +; GFX11-NEXT: s_load_b256 s[4:11], s[0:1], 0x0 +; GFX11-NEXT: s_and_b32 s0, s3, 1 +; GFX11-NEXT: s_lshr_b32 m0, s3, 1 ; GFX11-NEXT: s_lshl_b32 s0, s0, 4 -; GFX11-NEXT: s_and_b32 s1, s4, 0xffff +; GFX11-NEXT: s_and_b32 s1, s2, 0xffff ; GFX11-NEXT: s_lshl_b32 s2, 0xffff, s0 ; GFX11-NEXT: s_lshl_b32 s0, s1, s0 ; GFX11-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v9, 0 ; GFX11-NEXT: v_dual_mov_b32 v10, 16 :: v_dual_mov_b32 v11, 0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_movrels_b32 s3, s8 +; GFX11-NEXT: s_movrels_b32 s3, s4 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_and_not1_b32 s1, s3, s2 ; GFX11-NEXT: s_or_b32 s0, s1, s0 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_movreld_b32 s8, s0 -; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9 -; GFX11-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11 -; GFX11-NEXT: v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v5, s13 -; GFX11-NEXT: v_dual_mov_b32 v6, s14 :: v_dual_mov_b32 v7, s15 +; GFX11-NEXT: s_movreld_b32 s4, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 +; GFX11-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 +; GFX11-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v5, s9 +; GFX11-NEXT: v_dual_mov_b32 v6, s10 :: v_dual_mov_b32 v7, s11 ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: global_store_b128 v[8:9], v[0:3], off ; GFX11-NEXT: global_store_b128 v[10:11], v[4:7], off @@ -2974,14 +2975,14 @@ define amdgpu_ps void @insertelement_v_v16i16_s_s(ptr addrspace(1) %ptr, i16 inr ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: global_load_b128 v[2:5], v[0:1], off ; GFX11-NEXT: global_load_b128 v[6:9], v[0:1], off offset:16 -; GFX11-NEXT: s_and_b32 s0, s3, 1 -; GFX11-NEXT: s_lshr_b32 m0, s3, 1 -; GFX11-NEXT: s_lshl_b32 s0, s0, 4 -; GFX11-NEXT: s_and_b32 s1, s2, 0xffff -; GFX11-NEXT: s_lshl_b32 s2, 0xffff, s0 -; GFX11-NEXT: s_lshl_b32 s0, s1, s0 -; GFX11-NEXT: s_not_b32 s1, s2 +; GFX11-NEXT: s_lshr_b32 m0, s1, 1 +; GFX11-NEXT: s_and_b32 s1, s1, 1 +; GFX11-NEXT: s_and_b32 s0, s0, 0xffff +; GFX11-NEXT: s_lshl_b32 s1, s1, 4 ; GFX11-NEXT: v_dual_mov_b32 v10, 16 :: v_dual_mov_b32 v11, 0 +; GFX11-NEXT: s_lshl_b32 s2, 0xffff, s1 +; GFX11-NEXT: s_lshl_b32 s0, s0, s1 +; GFX11-NEXT: s_not_b32 s1, s2 ; GFX11-NEXT: v_mov_b32_e32 v1, 0 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_movrels_b32_e32 v0, v2 @@ -3124,23 +3125,23 @@ define amdgpu_ps void @insertelement_s_v16i16_v_s(ptr addrspace(4) inreg %ptr, i ; ; GFX11-LABEL: insertelement_s_v16i16_v_s: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b256 s[8:15], s[2:3], 0x0 -; GFX11-NEXT: s_and_b32 s0, s4, 1 -; GFX11-NEXT: s_lshr_b32 m0, s4, 1 +; GFX11-NEXT: s_load_b256 s[4:11], s[0:1], 0x0 +; GFX11-NEXT: s_and_b32 s0, s2, 1 +; GFX11-NEXT: s_lshr_b32 m0, s2, 1 ; GFX11-NEXT: s_lshl_b32 s0, s0, 4 ; GFX11-NEXT: v_and_b32_e32 v8, 0xffff, v0 ; GFX11-NEXT: s_lshl_b32 s1, 0xffff, s0 ; GFX11-NEXT: v_dual_mov_b32 v10, 16 :: v_dual_mov_b32 v9, 0 ; GFX11-NEXT: v_mov_b32_e32 v11, 0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_movrels_b32 s2, s8 -; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s11 +; GFX11-NEXT: s_movrels_b32 s2, s4 +; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7 ; GFX11-NEXT: s_and_not1_b32 s1, s2, s1 -; GFX11-NEXT: v_mov_b32_e32 v1, s9 +; GFX11-NEXT: v_mov_b32_e32 v1, s5 ; GFX11-NEXT: v_lshl_or_b32 v12, v8, s0, s1 -; GFX11-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v5, s13 -; GFX11-NEXT: v_dual_mov_b32 v4, s12 :: v_dual_mov_b32 v7, s15 -; GFX11-NEXT: v_mov_b32_e32 v6, s14 +; GFX11-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v5, s9 +; GFX11-NEXT: v_dual_mov_b32 v4, s8 :: v_dual_mov_b32 v7, s11 +; GFX11-NEXT: v_mov_b32_e32 v6, s10 ; GFX11-NEXT: v_mov_b32_e32 v8, 0 ; GFX11-NEXT: v_movreld_b32_e32 v0, v12 ; GFX11-NEXT: s_clause 0x1 @@ -3362,52 +3363,49 @@ define amdgpu_ps void @insertelement_s_v16i16_s_v(ptr addrspace(4) inreg %ptr, i ; ; GFX11-LABEL: insertelement_s_v16i16_s_v: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b256 s[8:15], s[2:3], 0x0 +; GFX11-NEXT: s_load_b256 s[4:11], s[0:1], 0x0 ; GFX11-NEXT: v_lshrrev_b32_e32 v13, 1, v0 -; GFX11-NEXT: v_and_b32_e32 v0, 1, v0 -; GFX11-NEXT: s_and_b32 s5, s4, 0xffff -; GFX11-NEXT: v_mov_b32_e32 v11, 16 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: v_dual_mov_b32 v11, 16 :: v_dual_and_b32 v0, 1, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v13 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v13 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v13 -; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 4, v13 -; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 5, v13 +; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 4, v13 ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 4, v0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 6, v13 -; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v13 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-NEXT: v_lshlrev_b32_e64 v10, v0, 0xffff -; GFX11-NEXT: v_lshlrev_b32_e64 v0, v0, s5 -; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v13 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_not_b32_e32 v10, v10 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_dual_mov_b32 v1, s8 :: v_dual_mov_b32 v2, s9 -; GFX11-NEXT: v_dual_mov_b32 v3, s10 :: v_dual_mov_b32 v4, s11 -; GFX11-NEXT: v_dual_mov_b32 v5, s12 :: v_dual_mov_b32 v6, s13 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) +; GFX11-NEXT: v_dual_mov_b32 v1, s4 :: v_dual_mov_b32 v2, s5 +; GFX11-NEXT: v_dual_mov_b32 v3, s6 :: v_dual_mov_b32 v4, s7 +; GFX11-NEXT: v_dual_mov_b32 v5, s8 :: v_dual_mov_b32 v6, s9 ; GFX11-NEXT: v_cndmask_b32_e32 v9, v1, v2, vcc_lo -; GFX11-NEXT: v_dual_mov_b32 v7, s14 :: v_dual_mov_b32 v8, s15 -; GFX11-NEXT: v_not_b32_e32 v10, v10 +; GFX11-NEXT: v_dual_mov_b32 v7, s10 :: v_dual_mov_b32 v8, s11 +; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 5, v13 +; GFX11-NEXT: s_and_b32 s5, s2, 0xffff ; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v3, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 6, v13 +; GFX11-NEXT: v_lshlrev_b32_e64 v0, v0, s5 +; GFX11-NEXT: v_cmp_eq_u32_e64 s5, 7, v13 +; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v13 ; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v4, s1 -; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v5, s2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v6, s3 -; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v7, s4 +; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v5, s3 +; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v6, s4 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v7, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, v8, s5 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_and_or_b32 v14, v9, v10, v0 ; GFX11-NEXT: v_dual_mov_b32 v9, 0 :: v_dual_mov_b32 v10, 0 ; GFX11-NEXT: v_mov_b32_e32 v12, 0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-NEXT: v_cndmask_b32_e64 v0, v1, v14, s6 ; GFX11-NEXT: v_cndmask_b32_e32 v1, v2, v14, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, v3, v14, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v3, v4, v14, s1 -; GFX11-NEXT: v_cndmask_b32_e64 v4, v5, v14, s2 -; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, v14, s3 -; GFX11-NEXT: v_cndmask_b32_e64 v6, v7, v14, s4 +; GFX11-NEXT: v_cndmask_b32_e64 v4, v5, v14, s3 +; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, v14, s4 +; GFX11-NEXT: v_cndmask_b32_e64 v6, v7, v14, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v7, v8, v14, s5 ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: global_store_b128 v[9:10], v[0:3], off @@ -3625,7 +3623,7 @@ define amdgpu_ps void @insertelement_s_v16i16_v_v(ptr addrspace(4) inreg %ptr, i ; ; GFX11-LABEL: insertelement_s_v16i16_v_v: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b256 s[0:7], s[2:3], 0x0 +; GFX11-NEXT: s_load_b256 s[0:7], s[0:1], 0x0 ; GFX11-NEXT: v_lshrrev_b32_e32 v14, 1, v1 ; GFX11-NEXT: v_and_b32_e32 v1, 1, v1 ; GFX11-NEXT: v_dual_mov_b32 v13, 0 :: v_dual_and_b32 v0, 0xffff, v0 @@ -3877,16 +3875,16 @@ define amdgpu_ps void @insertelement_v_v16i16_s_v(ptr addrspace(1) %ptr, i16 inr ; GFX11-NEXT: global_load_b128 v[7:10], v[0:1], off offset:16 ; GFX11-NEXT: v_lshrrev_b32_e32 v0, 1, v2 ; GFX11-NEXT: v_and_b32_e32 v2, 1, v2 -; GFX11-NEXT: s_and_b32 s5, s2, 0xffff +; GFX11-NEXT: s_and_b32 s5, s0, 0xffff ; GFX11-NEXT: v_dual_mov_b32 v13, 16 :: v_dual_mov_b32 v12, 0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v0 +; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 2, v0 +; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 3, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 4, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s4, 5, v0 ; GFX11-NEXT: v_lshlrev_b32_e32 v2, 4, v2 -; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 6, v0 +; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 6, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s6, 0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_lshlrev_b32_e64 v11, v2, 0xffff @@ -3896,25 +3894,25 @@ define amdgpu_ps void @insertelement_v_v16i16_s_v(ptr addrspace(1) %ptr, i16 inr ; GFX11-NEXT: s_waitcnt vmcnt(1) ; GFX11-NEXT: v_cndmask_b32_e32 v1, v3, v4, vcc_lo ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v5, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v6, s1 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v5, s1 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v6, s2 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v7, s3 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v8, s4 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v9, s2 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v9, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, v10, s5 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_and_or_b32 v15, v1, v11, v2 ; GFX11-NEXT: v_dual_mov_b32 v11, 0 :: v_dual_mov_b32 v14, 0 ; GFX11-NEXT: v_cndmask_b32_e32 v1, v4, v15, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v0, v3, v15, s6 -; GFX11-NEXT: v_cndmask_b32_e64 v2, v5, v15, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v3, v6, v15, s1 +; GFX11-NEXT: v_cndmask_b32_e64 v2, v5, v15, s1 +; GFX11-NEXT: v_cndmask_b32_e64 v3, v6, v15, s2 ; GFX11-NEXT: v_cndmask_b32_e64 v4, v7, v15, s3 ; GFX11-NEXT: v_cndmask_b32_e64 v5, v8, v15, s4 -; GFX11-NEXT: v_cndmask_b32_e64 v6, v9, v15, s2 +; GFX11-NEXT: v_cndmask_b32_e64 v6, v9, v15, s0 ; GFX11-NEXT: v_cndmask_b32_e64 v7, v10, v15, s5 ; GFX11-NEXT: s_clause 0x1 ; GFX11-NEXT: global_store_b128 v[11:12], v[0:3], off @@ -4032,12 +4030,12 @@ define amdgpu_ps void @insertelement_v_v16i16_v_s(ptr addrspace(1) %ptr, i16 %va ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off ; GFX11-NEXT: global_load_b128 v[7:10], v[0:1], off offset:16 ; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v2 -; GFX11-NEXT: s_and_b32 s0, s2, 1 -; GFX11-NEXT: s_lshr_b32 m0, s2, 1 -; GFX11-NEXT: s_lshl_b32 s0, s0, 4 +; GFX11-NEXT: s_and_b32 s1, s0, 1 +; GFX11-NEXT: s_lshr_b32 m0, s0, 1 +; GFX11-NEXT: s_lshl_b32 s1, s1, 4 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: v_dual_mov_b32 v11, 16 :: v_dual_lshlrev_b32 v0, s0, v0 -; GFX11-NEXT: s_lshl_b32 s0, 0xffff, s0 +; GFX11-NEXT: v_dual_mov_b32 v11, 16 :: v_dual_lshlrev_b32 v0, s1, v0 +; GFX11-NEXT: s_lshl_b32 s0, 0xffff, s1 ; GFX11-NEXT: v_mov_b32_e32 v12, 0 ; GFX11-NEXT: s_not_b32 s0, s0 ; GFX11-NEXT: s_waitcnt vmcnt(0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll index 2473b71525a7af..b44d0bc66857e2 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.i8.ll @@ -89,15 +89,15 @@ define amdgpu_ps void @insertelement_s_v2i8_s_s(ptr addrspace(4) inreg %ptr, i8 ; GFX11-TRUE16-LABEL: insertelement_s_v2i8_s_s: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0 -; GFX11-TRUE16-NEXT: s_mov_b32 m0, s5 +; GFX11-TRUE16-NEXT: s_mov_b32 m0, s3 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0 -; GFX11-TRUE16-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX11-TRUE16-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-TRUE16-NEXT: s_and_b32 s1, 0xffff, s0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_4) | instid1(SALU_CYCLE_1) ; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 8 -; GFX11-TRUE16-NEXT: s_movreld_b32 s0, s4 +; GFX11-TRUE16-NEXT: s_movreld_b32 s0, s2 ; GFX11-TRUE16-NEXT: s_and_b32 s1, s1, 0xff ; GFX11-TRUE16-NEXT: s_and_b32 s0, s0, 0xff ; GFX11-TRUE16-NEXT: s_lshl_b32 s1, s1, 8 @@ -110,13 +110,13 @@ define amdgpu_ps void @insertelement_s_v2i8_s_s(ptr addrspace(4) inreg %ptr, i8 ; GFX11-FAKE16-LABEL: insertelement_s_v2i8_s_s: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0 -; GFX11-FAKE16-NEXT: s_mov_b32 m0, s5 -; GFX11-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX11-FAKE16-NEXT: s_mov_b32 m0, s3 +; GFX11-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0 ; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 8 -; GFX11-FAKE16-NEXT: s_movreld_b32 s0, s4 +; GFX11-FAKE16-NEXT: s_movreld_b32 s0, s2 ; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xff ; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xff ; GFX11-FAKE16-NEXT: s_lshl_b32 s1, s1, 8 @@ -203,10 +203,10 @@ define amdgpu_ps void @insertelement_v_v2i8_s_s(ptr addrspace(1) %ptr, i8 inreg ; GFX11-TRUE16-LABEL: insertelement_v_v2i8_s_s: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: global_load_u16 v1, v[0:1], off -; GFX11-TRUE16-NEXT: s_mov_b32 m0, s3 +; GFX11-TRUE16-NEXT: s_mov_b32 m0, s1 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_lshrrev_b16 v2.l, 8, v1.l -; GFX11-TRUE16-NEXT: v_movreld_b32_e32 v1, s2 +; GFX11-TRUE16-NEXT: v_movreld_b32_e32 v1, s0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v2.l, 0xff ; GFX11-TRUE16-NEXT: v_and_b16 v0.h, v1.l, 0xff @@ -220,10 +220,10 @@ define amdgpu_ps void @insertelement_v_v2i8_s_s(ptr addrspace(1) %ptr, i8 inreg ; GFX11-FAKE16-LABEL: insertelement_v_v2i8_s_s: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off -; GFX11-FAKE16-NEXT: s_mov_b32 m0, s3 +; GFX11-FAKE16-NEXT: s_mov_b32 m0, s1 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 -; GFX11-FAKE16-NEXT: v_movreld_b32_e32 v0, s2 +; GFX11-FAKE16-NEXT: v_movreld_b32_e32 v0, s0 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v0 @@ -325,8 +325,8 @@ define amdgpu_ps void @insertelement_s_v2i8_v_s(ptr addrspace(4) inreg %ptr, i8 ; GFX11-TRUE16-LABEL: insertelement_s_v2i8_v_s: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-TRUE16-NEXT: s_mov_b32 m0, s4 -; GFX11-TRUE16-NEXT: global_load_u16 v1, v1, s[2:3] +; GFX11-TRUE16-NEXT: s_mov_b32 m0, s2 +; GFX11-TRUE16-NEXT: global_load_u16 v1, v1, s[0:1] ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v1 ; GFX11-TRUE16-NEXT: s_and_b32 s1, 0xffff, s0 @@ -347,8 +347,8 @@ define amdgpu_ps void @insertelement_s_v2i8_v_s(ptr addrspace(4) inreg %ptr, i8 ; GFX11-FAKE16-LABEL: insertelement_s_v2i8_v_s: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-FAKE16-NEXT: s_mov_b32 m0, s4 -; GFX11-FAKE16-NEXT: global_load_u16 v1, v1, s[2:3] +; GFX11-FAKE16-NEXT: s_mov_b32 m0, s2 +; GFX11-FAKE16-NEXT: global_load_u16 v1, v1, s[0:1] ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v1 ; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 8 @@ -466,7 +466,7 @@ define amdgpu_ps void @insertelement_s_v2i8_s_v(ptr addrspace(4) inreg %ptr, i8 ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX11-TRUE16-NEXT: global_load_u16 v1, v1, s[2:3] +; GFX11-TRUE16-NEXT: global_load_u16 v1, v1, s[0:1] ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v1 ; GFX11-TRUE16-NEXT: s_and_b32 s1, 0xffff, s0 @@ -474,11 +474,11 @@ define amdgpu_ps void @insertelement_s_v2i8_s_v(ptr addrspace(4) inreg %ptr, i8 ; GFX11-TRUE16-NEXT: s_lshr_b32 s1, s1, 8 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v1.l, 0xff -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, s4, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, 8, v0.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) @@ -492,17 +492,17 @@ define amdgpu_ps void @insertelement_s_v2i8_s_v(ptr addrspace(4) inreg %ptr, i8 ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX11-FAKE16-NEXT: global_load_u16 v1, v1, s[2:3] +; GFX11-FAKE16-NEXT: global_load_u16 v1, v1, s[0:1] ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v1 ; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 8 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, s4, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v2, s4, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v2, s2, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshlrev_b16 v3, 8, v1 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v2, 0xff, v0 @@ -608,7 +608,7 @@ define amdgpu_ps void @insertelement_s_v2i8_v_v(ptr addrspace(4) inreg %ptr, i8 ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0 ; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-TRUE16-NEXT: global_load_u16 v2, v2, s[2:3] +; GFX11-TRUE16-NEXT: global_load_u16 v2, v2, s[0:1] ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s0, v2 ; GFX11-TRUE16-NEXT: s_and_b32 s1, 0xffff, s0 @@ -632,7 +632,7 @@ define amdgpu_ps void @insertelement_s_v2i8_v_v(ptr addrspace(4) inreg %ptr, i8 ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, 0 ; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-FAKE16-NEXT: global_load_u16 v2, v2, s[2:3] +; GFX11-FAKE16-NEXT: global_load_u16 v2, v2, s[0:1] ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_readfirstlane_b32 s0, v2 ; GFX11-FAKE16-NEXT: s_lshr_b32 s1, s0, 8 @@ -739,9 +739,9 @@ define amdgpu_ps void @insertelement_v_v2i8_s_v(ptr addrspace(1) %ptr, i8 inreg ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.l, 8, v0.l ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_3) -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo ; GFX11-TRUE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 -; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, s2, vcc_lo +; GFX11-TRUE16-NEXT: v_cndmask_b32_e64 v2, v0, s0, vcc_lo ; GFX11-TRUE16-NEXT: v_and_b16 v0.l, v1.l, 0xff ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) @@ -760,10 +760,10 @@ define amdgpu_ps void @insertelement_v_v2i8_s_v(ptr addrspace(1) %ptr, i8 inreg ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) -; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo ; GFX11-FAKE16-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xff, v1 -; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo +; GFX11-FAKE16-NEXT: v_cndmask_b32_e64 v0, v0, s0, vcc_lo ; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_4) ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xff, v0 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, 0 @@ -848,7 +848,7 @@ define amdgpu_ps void @insertelement_v_v2i8_v_s(ptr addrspace(1) %ptr, i8 %val, ; GFX11-TRUE16-LABEL: insertelement_v_v2i8_v_s: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: global_load_u16 v3, v[0:1], off -; GFX11-TRUE16-NEXT: s_mov_b32 m0, s2 +; GFX11-TRUE16-NEXT: s_mov_b32 m0, s0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_lshrrev_b16 v4.l, 8, v3.l @@ -866,7 +866,7 @@ define amdgpu_ps void @insertelement_v_v2i8_v_s(ptr addrspace(1) %ptr, i8 %val, ; GFX11-FAKE16-LABEL: insertelement_v_v2i8_v_s: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off -; GFX11-FAKE16-NEXT: s_mov_b32 m0, s2 +; GFX11-FAKE16-NEXT: s_mov_b32 m0, s0 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_lshrrev_b32_e32 v1, 8, v0 ; GFX11-FAKE16-NEXT: v_movreld_b32_e32 v0, v2 @@ -1133,12 +1133,12 @@ define amdgpu_ps void @insertelement_v_v4i8_s_s(ptr addrspace(1) %ptr, i8 inreg ; GFX11-LABEL: insertelement_v_v4i8_s_s: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b32 v2, v[0:1], off -; GFX11-NEXT: s_and_b32 s0, s3, 3 -; GFX11-NEXT: s_and_b32 s1, s2, 0xff -; GFX11-NEXT: s_lshl_b32 s0, s0, 3 +; GFX11-NEXT: s_and_b32 s1, s1, 3 +; GFX11-NEXT: s_and_b32 s0, s0, 0xff +; GFX11-NEXT: s_lshl_b32 s1, s1, 3 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0 -; GFX11-NEXT: s_lshl_b32 s2, 0xff, s0 -; GFX11-NEXT: s_lshl_b32 s0, s1, s0 +; GFX11-NEXT: s_lshl_b32 s2, 0xff, s1 +; GFX11-NEXT: s_lshl_b32 s0, s0, s1 ; GFX11-NEXT: s_not_b32 s1, s2 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_and_or_b32 v2, v2, s1, s0 @@ -1217,8 +1217,8 @@ define amdgpu_ps void @insertelement_s_v4i8_v_s(ptr addrspace(4) inreg %ptr, i8 ; ; GFX11-LABEL: insertelement_s_v4i8_v_s: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 -; GFX11-NEXT: s_and_b32 s1, s4, 3 +; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 +; GFX11-NEXT: s_and_b32 s1, s2, 3 ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v2, 0xff, v0 ; GFX11-NEXT: s_lshl_b32 s1, s1, 3 ; GFX11-NEXT: v_mov_b32_e32 v0, 0 @@ -1305,9 +1305,9 @@ define amdgpu_ps void @insertelement_s_v4i8_s_v(ptr addrspace(4) inreg %ptr, i8 ; ; GFX11-LABEL: insertelement_s_v4i8_s_v: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 +; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: v_and_b32_e32 v0, 3, v0 -; GFX11-NEXT: s_and_b32 s1, s4, 0xff +; GFX11-NEXT: s_and_b32 s1, s2, 0xff ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GFX11-NEXT: v_lshlrev_b32_e64 v1, v0, 0xff @@ -1393,7 +1393,7 @@ define amdgpu_ps void @insertelement_s_v4i8_v_v(ptr addrspace(4) inreg %ptr, i8 ; ; GFX11-LABEL: insertelement_s_v4i8_v_v: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b32 s0, s[2:3], 0x0 +; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0 ; GFX11-NEXT: v_and_b32_e32 v1, 3, v1 ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -1488,7 +1488,7 @@ define amdgpu_ps void @insertelement_v_v4i8_s_v(ptr addrspace(1) %ptr, i8 inreg ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b32 v3, v[0:1], off ; GFX11-NEXT: v_and_b32_e32 v0, 3, v2 -; GFX11-NEXT: s_and_b32 s0, s2, 0xff +; GFX11-NEXT: s_and_b32 s0, s0, 0xff ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GFX11-NEXT: v_lshlrev_b32_e64 v1, v0, 0xff @@ -1577,7 +1577,7 @@ define amdgpu_ps void @insertelement_v_v4i8_v_s(ptr addrspace(1) %ptr, i8 %val, ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b32 v3, v[0:1], off ; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_and_b32 v0, 0xff, v2 -; GFX11-NEXT: s_and_b32 s0, s2, 3 +; GFX11-NEXT: s_and_b32 s0, s0, 3 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX11-NEXT: s_lshl_b32 s0, s0, 3 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) @@ -1773,14 +1773,14 @@ define amdgpu_ps void @insertelement_s_v8i8_s_s(ptr addrspace(4) inreg %ptr, i8 ; ; GFX11-LABEL: insertelement_s_v8i8_s_s: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_and_b32 s2, s5, 3 -; GFX11-NEXT: s_lshr_b32 m0, s5, 2 -; GFX11-NEXT: s_lshl_b32 s2, s2, 3 -; GFX11-NEXT: s_and_b32 s3, s4, 0xff -; GFX11-NEXT: s_lshl_b32 s5, 0xff, s2 -; GFX11-NEXT: s_lshl_b32 s2, s3, s2 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; GFX11-NEXT: s_lshr_b32 m0, s3, 2 +; GFX11-NEXT: s_and_b32 s3, s3, 3 +; GFX11-NEXT: s_and_b32 s2, s2, 0xff +; GFX11-NEXT: s_lshl_b32 s3, s3, 3 ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 0 +; GFX11-NEXT: s_lshl_b32 s5, 0xff, s3 +; GFX11-NEXT: s_lshl_b32 s2, s2, s3 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) ; GFX11-NEXT: s_movrels_b32 s4, s0 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) @@ -1885,12 +1885,12 @@ define amdgpu_ps void @insertelement_v_v8i8_s_s(ptr addrspace(1) %ptr, i8 inreg ; GFX11-LABEL: insertelement_v_v8i8_s_s: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off -; GFX11-NEXT: s_and_b32 s0, s3, 3 -; GFX11-NEXT: s_lshr_b32 m0, s3, 2 -; GFX11-NEXT: s_lshl_b32 s0, s0, 3 -; GFX11-NEXT: s_and_b32 s1, s2, 0xff -; GFX11-NEXT: s_lshl_b32 s2, 0xff, s0 -; GFX11-NEXT: s_lshl_b32 s0, s1, s0 +; GFX11-NEXT: s_and_b32 s2, s1, 3 +; GFX11-NEXT: s_lshr_b32 m0, s1, 2 +; GFX11-NEXT: s_lshl_b32 s1, s2, 3 +; GFX11-NEXT: s_and_b32 s0, s0, 0xff +; GFX11-NEXT: s_lshl_b32 s2, 0xff, s1 +; GFX11-NEXT: s_lshl_b32 s0, s0, s1 ; GFX11-NEXT: s_not_b32 s1, s2 ; GFX11-NEXT: v_mov_b32_e32 v3, 0 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1997,10 +1997,10 @@ define amdgpu_ps void @insertelement_s_v8i8_v_s(ptr addrspace(4) inreg %ptr, i8 ; ; GFX11-LABEL: insertelement_s_v8i8_v_s: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 -; GFX11-NEXT: s_and_b32 s2, s4, 3 -; GFX11-NEXT: s_lshr_b32 m0, s4, 2 -; GFX11-NEXT: s_lshl_b32 s2, s2, 3 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; GFX11-NEXT: s_and_b32 s3, s2, 3 +; GFX11-NEXT: s_lshr_b32 m0, s2, 2 +; GFX11-NEXT: s_lshl_b32 s2, s3, 3 ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 ; GFX11-NEXT: s_lshl_b32 s3, 0xff, s2 ; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v3, 0 @@ -2122,10 +2122,10 @@ define amdgpu_ps void @insertelement_s_v8i8_s_v(ptr addrspace(4) inreg %ptr, i8 ; ; GFX11-LABEL: insertelement_s_v8i8_s_v: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: v_and_b32_e32 v1, 3, v0 ; GFX11-NEXT: v_lshrrev_b32_e32 v4, 2, v0 -; GFX11-NEXT: s_and_b32 s2, s4, 0xff +; GFX11-NEXT: s_and_b32 s2, s2, 0xff ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v4 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) @@ -2249,7 +2249,7 @@ define amdgpu_ps void @insertelement_s_v8i8_v_v(ptr addrspace(4) inreg %ptr, i8 ; ; GFX11-LABEL: insertelement_s_v8i8_v_v: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b64 s[0:1], s[2:3], 0x0 +; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 ; GFX11-NEXT: v_and_b32_e32 v2, 3, v1 ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 2, v1 ; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v0 @@ -2375,7 +2375,7 @@ define amdgpu_ps void @insertelement_v_v8i8_s_v(ptr addrspace(1) %ptr, i8 inreg ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: v_lshrrev_b32_e32 v5, 2, v2 -; GFX11-NEXT: s_and_b32 s0, s2, 0xff +; GFX11-NEXT: s_and_b32 s0, s0, 0xff ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v5 ; GFX11-NEXT: v_and_b32_e32 v3, 3, v2 @@ -2486,9 +2486,9 @@ define amdgpu_ps void @insertelement_v_v8i8_v_s(ptr addrspace(1) %ptr, i8 %val, ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2 -; GFX11-NEXT: s_and_b32 s0, s2, 3 -; GFX11-NEXT: s_lshr_b32 m0, s2, 2 -; GFX11-NEXT: s_lshl_b32 s0, s0, 3 +; GFX11-NEXT: s_and_b32 s1, s0, 3 +; GFX11-NEXT: s_lshr_b32 m0, s0, 2 +; GFX11-NEXT: s_lshl_b32 s0, s1, 3 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_lshlrev_b32_e32 v2, s0, v2 ; GFX11-NEXT: s_lshl_b32 s0, 0xff, s0 @@ -2724,23 +2724,23 @@ define amdgpu_ps void @insertelement_s_v16i8_s_s(ptr addrspace(4) inreg %ptr, i8 ; ; GFX11-LABEL: insertelement_s_v16i8_s_s: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: s_lshr_b32 m0, s5, 2 -; GFX11-NEXT: s_and_b32 s5, s5, 3 -; GFX11-NEXT: s_and_b32 s4, s4, 0xff -; GFX11-NEXT: s_lshl_b32 s5, s5, 3 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0 +; GFX11-NEXT: s_and_b32 s0, s3, 3 +; GFX11-NEXT: s_lshr_b32 m0, s3, 2 +; GFX11-NEXT: s_lshl_b32 s0, s0, 3 +; GFX11-NEXT: s_and_b32 s1, s2, 0xff +; GFX11-NEXT: s_lshl_b32 s3, 0xff, s0 +; GFX11-NEXT: s_lshl_b32 s0, s1, s0 ; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0 -; GFX11-NEXT: s_lshl_b32 s7, 0xff, s5 -; GFX11-NEXT: s_lshl_b32 s4, s4, s5 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: s_movrels_b32 s6, s0 +; GFX11-NEXT: s_movrels_b32 s2, s4 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_and_not1_b32 s5, s6, s7 -; GFX11-NEXT: s_or_b32 s4, s5, s4 +; GFX11-NEXT: s_and_not1_b32 s1, s2, s3 +; GFX11-NEXT: s_or_b32 s0, s1, s0 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX11-NEXT: s_movreld_b32 s0, s4 -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-NEXT: s_movreld_b32 s4, s0 +; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, s5 +; GFX11-NEXT: v_dual_mov_b32 v2, s6 :: v_dual_mov_b32 v3, s7 ; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off ; GFX11-NEXT: s_endpgm %vec = load <16 x i8>, ptr addrspace(4) %ptr @@ -2837,12 +2837,12 @@ define amdgpu_ps void @insertelement_v_v16i8_s_s(ptr addrspace(1) %ptr, i8 inreg ; GFX11-LABEL: insertelement_v_v16i8_s_s: ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b128 v[0:3], v[0:1], off -; GFX11-NEXT: s_and_b32 s0, s3, 3 -; GFX11-NEXT: s_lshr_b32 m0, s3, 2 -; GFX11-NEXT: s_lshl_b32 s0, s0, 3 -; GFX11-NEXT: s_and_b32 s1, s2, 0xff -; GFX11-NEXT: s_lshl_b32 s2, 0xff, s0 -; GFX11-NEXT: s_lshl_b32 s0, s1, s0 +; GFX11-NEXT: s_and_b32 s2, s1, 3 +; GFX11-NEXT: s_lshr_b32 m0, s1, 2 +; GFX11-NEXT: s_lshl_b32 s1, s2, 3 +; GFX11-NEXT: s_and_b32 s0, s0, 0xff +; GFX11-NEXT: s_lshl_b32 s2, 0xff, s1 +; GFX11-NEXT: s_lshl_b32 s0, s0, s1 ; GFX11-NEXT: s_not_b32 s1, s2 ; GFX11-NEXT: v_mov_b32_e32 v5, 0 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -2957,21 +2957,21 @@ define amdgpu_ps void @insertelement_s_v16i8_v_s(ptr addrspace(4) inreg %ptr, i8 ; ; GFX11-LABEL: insertelement_s_v16i8_v_s: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 -; GFX11-NEXT: s_and_b32 s5, s4, 3 -; GFX11-NEXT: s_lshr_b32 m0, s4, 2 -; GFX11-NEXT: s_lshl_b32 s4, s5, 3 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0 +; GFX11-NEXT: s_and_b32 s0, s2, 3 +; GFX11-NEXT: s_lshr_b32 m0, s2, 2 +; GFX11-NEXT: s_lshl_b32 s0, s0, 3 ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 -; GFX11-NEXT: s_lshl_b32 s5, 0xff, s4 +; GFX11-NEXT: s_lshl_b32 s1, 0xff, s0 ; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0 ; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_mov_b32_e32 v2, s2 -; GFX11-NEXT: s_movrels_b32 s6, s0 -; GFX11-NEXT: v_mov_b32_e32 v1, s1 -; GFX11-NEXT: s_and_not1_b32 s5, s6, s5 -; GFX11-NEXT: v_mov_b32_e32 v3, s3 -; GFX11-NEXT: v_lshl_or_b32 v6, v0, s4, s5 -; GFX11-NEXT: v_mov_b32_e32 v0, s0 +; GFX11-NEXT: v_mov_b32_e32 v2, s6 +; GFX11-NEXT: s_movrels_b32 s2, s4 +; GFX11-NEXT: v_mov_b32_e32 v1, s5 +; GFX11-NEXT: s_and_not1_b32 s1, s2, s1 +; GFX11-NEXT: v_mov_b32_e32 v3, s7 +; GFX11-NEXT: v_lshl_or_b32 v6, v0, s0, s1 +; GFX11-NEXT: v_mov_b32_e32 v0, s4 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_movreld_b32_e32 v0, v6 ; GFX11-NEXT: global_store_b128 v[4:5], v[0:3], off @@ -3116,29 +3116,30 @@ define amdgpu_ps void @insertelement_s_v16i8_s_v(ptr addrspace(4) inreg %ptr, i8 ; ; GFX11-LABEL: insertelement_s_v16i8_s_v: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 +; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x0 ; GFX11-NEXT: v_lshrrev_b32_e32 v6, 2, v0 ; GFX11-NEXT: v_and_b32_e32 v4, 3, v0 +; GFX11-NEXT: s_and_b32 s1, s2, 0xff ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v6 -; GFX11-NEXT: s_waitcnt lgkmcnt(0) -; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2 -; GFX11-NEXT: v_lshlrev_b32_e32 v4, 3, v4 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 2, v6 -; GFX11-NEXT: s_and_b32 s1, s4, 0xff -; GFX11-NEXT: v_cndmask_b32_e32 v5, v0, v1, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 0, v6 +; GFX11-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v3, s7 +; GFX11-NEXT: v_dual_mov_b32 v1, s5 :: v_dual_mov_b32 v2, s6 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) +; GFX11-NEXT: v_dual_cndmask_b32 v5, v0, v1 :: v_dual_lshlrev_b32 v4, 3, v4 ; GFX11-NEXT: v_lshlrev_b32_e64 v7, v4, 0xff ; GFX11-NEXT: v_lshlrev_b32_e64 v4, v4, s1 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 3, v6 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v2, s0 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_not_b32_e32 v7, v7 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, v3, s1 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX11-NEXT: v_and_or_b32 v7, v5, v7, v4 ; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v5, 0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) ; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, v7, s2 ; GFX11-NEXT: v_cndmask_b32_e32 v1, v1, v7, vcc_lo ; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, v7, s0 @@ -3282,7 +3283,7 @@ define amdgpu_ps void @insertelement_s_v16i8_v_v(ptr addrspace(4) inreg %ptr, i8 ; ; GFX11-LABEL: insertelement_s_v16i8_v_v: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_load_b128 s[0:3], s[2:3], 0x0 +; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x0 ; GFX11-NEXT: v_lshrrev_b32_e32 v7, 2, v1 ; GFX11-NEXT: v_and_b32_e32 v5, 3, v1 ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v0 @@ -3441,7 +3442,7 @@ define amdgpu_ps void @insertelement_v_v16i8_s_v(ptr addrspace(1) %ptr, i8 inreg ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 2, v2 ; GFX11-NEXT: v_and_b32_e32 v0, 3, v2 -; GFX11-NEXT: s_and_b32 s1, s2, 0xff +; GFX11-NEXT: s_and_b32 s1, s0, 0xff ; GFX11-NEXT: v_mov_b32_e32 v8, 0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 @@ -3559,9 +3560,9 @@ define amdgpu_ps void @insertelement_v_v16i8_v_s(ptr addrspace(1) %ptr, i8 %val, ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b128 v[3:6], v[0:1], off ; GFX11-NEXT: v_and_b32_e32 v0, 0xff, v2 -; GFX11-NEXT: s_and_b32 s0, s2, 3 -; GFX11-NEXT: s_lshr_b32 m0, s2, 2 -; GFX11-NEXT: s_lshl_b32 s0, s0, 3 +; GFX11-NEXT: s_and_b32 s1, s0, 3 +; GFX11-NEXT: s_lshr_b32 m0, s0, 2 +; GFX11-NEXT: s_lshl_b32 s0, s1, 3 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: v_lshlrev_b32_e32 v0, s0, v0 ; GFX11-NEXT: s_lshl_b32 s0, 0xff, s0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll index 04077b9b3e9aa0..131a43316076a0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/insertelement.ll @@ -20,19 +20,25 @@ define amdgpu_ps <8 x i32> @dyn_insertelement_v8i32_s_s_s(<8 x i32> inreg %vec, ; GPRIDX-NEXT: s_movreld_b32 s0, s10 ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v8i32_s_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 m0, s11 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_mov_b32 s6, s8 -; GFX10PLUS-NEXT: s_mov_b32 s7, s9 -; GFX10PLUS-NEXT: s_movreld_b32 s0, s10 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v8i32_s_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 m0, s11 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: s_movreld_b32 s0, s10 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v8i32_s_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s9 +; GFX11-NEXT: s_movreld_b32 s0, s8 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v8i32_s_s_s: ; GFX8: ; %bb.0: ; %entry @@ -68,19 +74,25 @@ define amdgpu_ps <8 x ptr addrspace(3)> @dyn_insertelement_v8p3i8_s_s_s(<8 x ptr ; GPRIDX-NEXT: s_movreld_b32 s0, s10 ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v8p3i8_s_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 m0, s11 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_mov_b32 s6, s8 -; GFX10PLUS-NEXT: s_mov_b32 s7, s9 -; GFX10PLUS-NEXT: s_movreld_b32 s0, s10 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v8p3i8_s_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 m0, s11 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: s_movreld_b32 s0, s10 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v8p3i8_s_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s9 +; GFX11-NEXT: s_movreld_b32 s0, s8 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v8p3i8_s_s_s: ; GFX8: ; %bb.0: ; %entry @@ -268,28 +280,28 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_v(<8 x float> inreg %v ; ; GFX11-LABEL: dyn_insertelement_v8f32_s_s_v: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: v_dual_mov_b32 v1, s2 :: v_dual_mov_b32 v2, s3 +; GFX11-NEXT: v_dual_mov_b32 v1, s0 :: v_dual_mov_b32 v2, s1 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 -; GFX11-NEXT: v_dual_mov_b32 v3, s4 :: v_dual_mov_b32 v4, s5 -; GFX11-NEXT: v_dual_mov_b32 v5, s6 :: v_dual_mov_b32 v6, s7 -; GFX11-NEXT: v_cndmask_b32_e64 v8, v1, s10, vcc_lo +; GFX11-NEXT: v_dual_mov_b32 v3, s2 :: v_dual_mov_b32 v4, s3 +; GFX11-NEXT: v_dual_mov_b32 v5, s4 :: v_dual_mov_b32 v6, s5 +; GFX11-NEXT: v_cndmask_b32_e64 v8, v1, s8, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v0 -; GFX11-NEXT: v_mov_b32_e32 v7, s8 -; GFX11-NEXT: v_mov_b32_e32 v9, s9 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s10, vcc_lo +; GFX11-NEXT: v_mov_b32_e32 v7, s6 +; GFX11-NEXT: v_mov_b32_e32 v9, s7 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v2, s8, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v2, v3, s10, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v2, v3, s8, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v3, v4, s10, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v3, v4, s8, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v4, v5, s10, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v4, v5, s8, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, s10, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v5, v6, s8, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v6, v7, s10, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v6, v7, s8, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v0 ; GFX11-NEXT: v_mov_b32_e32 v0, v8 -; GFX11-NEXT: v_cndmask_b32_e64 v7, v9, s10, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v7, v9, s8, vcc_lo ; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v8f32_s_s_v: @@ -376,17 +388,9 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_v_s(<8 x float> inreg %v ; ; GFX11-LABEL: dyn_insertelement_v8f32_s_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: v_dual_mov_b32 v8, v0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: s_mov_b32 m0, s10 +; GFX11-NEXT: s_mov_b32 m0, s8 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7 ; GFX11-NEXT: v_mov_b32_e32 v6, s6 @@ -429,11 +433,17 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_s_s(<8 x float> %vec, fl ; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s3 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, s2 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v8f32_v_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s3 +; GFX10-NEXT: v_movreld_b32_e32 v0, s2 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v8f32_v_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s1 +; GFX11-NEXT: v_movreld_b32_e32 v0, s0 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v8f32_v_s_s: ; GFX8: ; %bb.0: ; %entry @@ -502,22 +512,22 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_v_v(<8 x float> inreg %v ; GFX11-LABEL: dyn_insertelement_v8f32_s_v_v: ; GFX11: ; %bb.0: ; %entry ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v8, s2, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v8, s0, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v9, s3, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v9, s1, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v2, s2, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v3, s5, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v3, s3, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v4, s6, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v4, s4, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v5, s7, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v5, s5, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v6, s8, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v6, s6, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1 ; GFX11-NEXT: v_mov_b32_e32 v1, v9 -; GFX11-NEXT: v_dual_cndmask_b32 v7, s9, v0 :: v_dual_mov_b32 v0, v8 +; GFX11-NEXT: v_dual_cndmask_b32 v7, s7, v0 :: v_dual_mov_b32 v0, v8 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v8f32_s_v_v: @@ -576,25 +586,45 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_s_v(<8 x float> %vec, fl ; GPRIDX-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_s_v: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v8 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v8 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v3, v3, s2, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v8 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v8 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v5, v5, s2, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v8 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v6, v6, s2, vcc_lo -; GFX10PLUS-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v8 -; GFX10PLUS-NEXT: v_cndmask_b32_e64 v7, v7, s2, vcc_lo -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v8f32_v_s_v: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8 +; GFX10-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8 +; GFX10-NEXT: v_cndmask_b32_e64 v1, v1, s2, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v8 +; GFX10-NEXT: v_cndmask_b32_e64 v2, v2, s2, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v8 +; GFX10-NEXT: v_cndmask_b32_e64 v3, v3, s2, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v8 +; GFX10-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v8 +; GFX10-NEXT: v_cndmask_b32_e64 v5, v5, s2, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v8 +; GFX10-NEXT: v_cndmask_b32_e64 v6, v6, s2, vcc_lo +; GFX10-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v8 +; GFX10-NEXT: v_cndmask_b32_e64 v7, v7, s2, vcc_lo +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v8f32_v_s_v: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v8 +; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s0, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v8 +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s0, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v8 +; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s0, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v8 +; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s0, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v8 +; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s0, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v8 +; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s0, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v8 +; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s0, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v8 +; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s0, vcc_lo +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v8f32_v_s_v: ; GFX8: ; %bb.0: ; %entry @@ -629,11 +659,17 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_v_v_s(<8 x float> %vec, fl ; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v8f32_v_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v8 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v8f32_v_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movreld_b32_e32 v0, v8 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v8f32_v_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movreld_b32_e32 v0, v8 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v8f32_v_v_s: ; GFX8: ; %bb.0: ; %entry @@ -653,11 +689,17 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8p3i8_v_v_s(<8 x ptr addrspace( ; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v8p3i8_v_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v8 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v8p3i8_v_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movreld_b32_e32 v0, v8 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v8p3i8_v_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movreld_b32_e32 v0, v8 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v8p3i8_v_v_s: ; GFX8: ; %bb.0: ; %entry @@ -757,25 +799,45 @@ define amdgpu_ps <8 x i64> @dyn_insertelement_v8i64_s_s_s(<8 x i64> inreg %vec, ; GPRIDX-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17] ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v8i64_s_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 0 -; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 1 -; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 2 -; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 3 -; GFX10PLUS-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 4 -; GFX10PLUS-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 5 -; GFX10PLUS-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 6 -; GFX10PLUS-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 7 -; GFX10PLUS-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17] -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v8i64_s_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_cmp_eq_u32 s20, 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3] +; GFX10-NEXT: s_cmp_eq_u32 s20, 1 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5] +; GFX10-NEXT: s_cmp_eq_u32 s20, 2 +; GFX10-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7] +; GFX10-NEXT: s_cmp_eq_u32 s20, 3 +; GFX10-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9] +; GFX10-NEXT: s_cmp_eq_u32 s20, 4 +; GFX10-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11] +; GFX10-NEXT: s_cmp_eq_u32 s20, 5 +; GFX10-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13] +; GFX10-NEXT: s_cmp_eq_u32 s20, 6 +; GFX10-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15] +; GFX10-NEXT: s_cmp_eq_u32 s20, 7 +; GFX10-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17] +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v8i64_s_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_cmp_eq_u32 s18, 0 +; GFX11-NEXT: s_cselect_b64 s[0:1], s[16:17], s[0:1] +; GFX11-NEXT: s_cmp_eq_u32 s18, 1 +; GFX11-NEXT: s_cselect_b64 s[2:3], s[16:17], s[2:3] +; GFX11-NEXT: s_cmp_eq_u32 s18, 2 +; GFX11-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5] +; GFX11-NEXT: s_cmp_eq_u32 s18, 3 +; GFX11-NEXT: s_cselect_b64 s[6:7], s[16:17], s[6:7] +; GFX11-NEXT: s_cmp_eq_u32 s18, 4 +; GFX11-NEXT: s_cselect_b64 s[8:9], s[16:17], s[8:9] +; GFX11-NEXT: s_cmp_eq_u32 s18, 5 +; GFX11-NEXT: s_cselect_b64 s[10:11], s[16:17], s[10:11] +; GFX11-NEXT: s_cmp_eq_u32 s18, 6 +; GFX11-NEXT: s_cselect_b64 s[12:13], s[16:17], s[12:13] +; GFX11-NEXT: s_cmp_eq_u32 s18, 7 +; GFX11-NEXT: s_cselect_b64 s[14:15], s[16:17], s[14:15] +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v8i64_s_s_s: ; GFX8: ; %bb.0: ; %entry @@ -822,25 +884,45 @@ define amdgpu_ps <8 x ptr addrspace(1)> @dyn_insertelement_v8p1i8_s_s_s(<8 x ptr ; GPRIDX-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17] ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v8p1i8_s_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 0 -; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 1 -; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 2 -; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 3 -; GFX10PLUS-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 4 -; GFX10PLUS-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 5 -; GFX10PLUS-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 6 -; GFX10PLUS-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s20, 7 -; GFX10PLUS-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17] -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v8p1i8_s_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_cmp_eq_u32 s20, 0 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3] +; GFX10-NEXT: s_cmp_eq_u32 s20, 1 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5] +; GFX10-NEXT: s_cmp_eq_u32 s20, 2 +; GFX10-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7] +; GFX10-NEXT: s_cmp_eq_u32 s20, 3 +; GFX10-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9] +; GFX10-NEXT: s_cmp_eq_u32 s20, 4 +; GFX10-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11] +; GFX10-NEXT: s_cmp_eq_u32 s20, 5 +; GFX10-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13] +; GFX10-NEXT: s_cmp_eq_u32 s20, 6 +; GFX10-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15] +; GFX10-NEXT: s_cmp_eq_u32 s20, 7 +; GFX10-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17] +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v8p1i8_s_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_cmp_eq_u32 s18, 0 +; GFX11-NEXT: s_cselect_b64 s[0:1], s[16:17], s[0:1] +; GFX11-NEXT: s_cmp_eq_u32 s18, 1 +; GFX11-NEXT: s_cselect_b64 s[2:3], s[16:17], s[2:3] +; GFX11-NEXT: s_cmp_eq_u32 s18, 2 +; GFX11-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5] +; GFX11-NEXT: s_cmp_eq_u32 s18, 3 +; GFX11-NEXT: s_cselect_b64 s[6:7], s[16:17], s[6:7] +; GFX11-NEXT: s_cmp_eq_u32 s18, 4 +; GFX11-NEXT: s_cselect_b64 s[8:9], s[16:17], s[8:9] +; GFX11-NEXT: s_cmp_eq_u32 s18, 5 +; GFX11-NEXT: s_cselect_b64 s[10:11], s[16:17], s[10:11] +; GFX11-NEXT: s_cmp_eq_u32 s18, 6 +; GFX11-NEXT: s_cselect_b64 s[12:13], s[16:17], s[12:13] +; GFX11-NEXT: s_cmp_eq_u32 s18, 7 +; GFX11-NEXT: s_cselect_b64 s[14:15], s[16:17], s[14:15] +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v8p1i8_s_s_s: ; GFX8: ; %bb.0: ; %entry @@ -1272,22 +1354,6 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_v(<8 x double> inreg %vec, do ; ; GFX11-LABEL: dyn_insertelement_v8f64_s_s_v: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 ; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v0 ; GFX11-NEXT: v_dual_mov_b32 v16, s15 :: v_dual_mov_b32 v15, s14 @@ -1298,28 +1364,28 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_v(<8 x double> inreg %vec, do ; GFX11-NEXT: v_dual_mov_b32 v6, s5 :: v_dual_mov_b32 v5, s4 ; GFX11-NEXT: v_dual_mov_b32 v4, s3 :: v_dual_mov_b32 v3, s2 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s18, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s19, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s16, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s17, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 7, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s18, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s19, s0 +; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s16, s0 +; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s17, s0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s18, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s19, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s16, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s17, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, s18, s1 -; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s18, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s19, s0 +; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, s16, s1 +; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s16, s0 +; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s17, s0 ; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, s18, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, s19, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, s16, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, s17, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v0 -; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, s19, s1 -; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, s18, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, s19, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, s18, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, s19, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v16, v16, s17, s1 +; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, s16, s0 +; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, s17, s0 +; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, s16, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, s17, vcc_lo ; GFX11-NEXT: global_store_b128 v[0:1], v[1:4], off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: global_store_b128 v[0:1], v[5:8], off dlc @@ -1511,24 +1577,8 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_s(<8 x double> inreg %vec, do ; ; GFX11-LABEL: dyn_insertelement_v8f64_s_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 ; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 -; GFX11-NEXT: s_lshl_b32 m0, s18, 1 +; GFX11-NEXT: s_lshl_b32 m0, s16, 1 ; GFX11-NEXT: v_dual_mov_b32 v17, s15 :: v_dual_mov_b32 v16, s14 ; GFX11-NEXT: v_dual_mov_b32 v15, s13 :: v_dual_mov_b32 v14, s12 ; GFX11-NEXT: v_dual_mov_b32 v13, s11 :: v_dual_mov_b32 v12, s10 @@ -1646,9 +1696,9 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_s_s(<8 x double> %vec, double i ; ; GFX11-LABEL: dyn_insertelement_v8f64_v_s_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_lshl_b32 m0, s4, 1 -; GFX11-NEXT: v_movreld_b32_e32 v0, s2 -; GFX11-NEXT: v_movreld_b32_e32 v1, s3 +; GFX11-NEXT: s_lshl_b32 m0, s2, 1 +; GFX11-NEXT: v_movreld_b32_e32 v0, s0 +; GFX11-NEXT: v_movreld_b32_e32 v1, s1 ; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc @@ -1827,22 +1877,6 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_v_v(<8 x double> inreg %vec, do ; ; GFX11-LABEL: dyn_insertelement_v8f64_s_v_v: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 ; GFX11-NEXT: v_dual_mov_b32 v4, s1 :: v_dual_mov_b32 v3, s0 ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v2 ; GFX11-NEXT: v_dual_mov_b32 v18, s15 :: v_dual_mov_b32 v17, s14 @@ -2039,29 +2073,29 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_s_v(<8 x double> %vec, double i ; GFX11-LABEL: dyn_insertelement_v8f64_v_s_v: ; GFX11: ; %bb.0: ; %entry ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v16 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 1, v16 -; GFX11-NEXT: v_cmp_eq_u32_e64 s1, 7, v16 -; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s2, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s3, vcc_lo +; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 1, v16 +; GFX11-NEXT: v_cmp_eq_u32_e64 s3, 7, v16 +; GFX11-NEXT: v_cndmask_b32_e64 v0, v0, s0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v1, v1, s1, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v16 -; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s2, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s3, s0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 3, v16 -; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, s2, s1 -; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s2, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s3, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v2, v2, s0, s2 +; GFX11-NEXT: v_cndmask_b32_e64 v3, v3, s1, s2 +; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 3, v16 +; GFX11-NEXT: v_cndmask_b32_e64 v14, v14, s0, s3 +; GFX11-NEXT: v_cndmask_b32_e64 v4, v4, s0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v5, v5, s1, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v16 -; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s2, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s3, s0 -; GFX11-NEXT: v_cmp_eq_u32_e64 s0, 5, v16 -; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, s3, s1 -; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s2, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, s3, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v6, v6, s0, s2 +; GFX11-NEXT: v_cndmask_b32_e64 v7, v7, s1, s2 +; GFX11-NEXT: v_cmp_eq_u32_e64 s2, 5, v16 +; GFX11-NEXT: v_cndmask_b32_e64 v15, v15, s1, s3 +; GFX11-NEXT: v_cndmask_b32_e64 v8, v8, s0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v9, v9, s1, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v16 -; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, s2, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, s3, s0 -; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, s2, vcc_lo -; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, s3, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v10, v10, s0, s2 +; GFX11-NEXT: v_cndmask_b32_e64 v11, v11, s1, s2 +; GFX11-NEXT: v_cndmask_b32_e64 v12, v12, s0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e64 v13, v13, s1, vcc_lo ; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: global_store_b128 v[0:1], v[4:7], off dlc @@ -2157,7 +2191,7 @@ define amdgpu_ps void @dyn_insertelement_v8f64_v_v_s(<8 x double> %vec, double % ; ; GFX11-LABEL: dyn_insertelement_v8f64_v_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_lshl_b32 m0, s2, 1 +; GFX11-NEXT: s_lshl_b32 m0, s0, 1 ; GFX11-NEXT: v_movreld_b32_e32 v0, v16 ; GFX11-NEXT: v_movreld_b32_e32 v1, v17 ; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc @@ -2361,14 +2395,20 @@ define amdgpu_ps <3 x i32> @dyn_insertelement_v3i32_s_s_s(<3 x i32> inreg %vec, ; GPRIDX-NEXT: s_movreld_b32 s0, s5 ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v3i32_s_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 m0, s6 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_movreld_b32 s0, s5 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v3i32_s_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 m0, s6 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_movreld_b32 s0, s5 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v3i32_s_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s4 +; GFX11-NEXT: s_movreld_b32 s0, s3 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v3i32_s_s_s: ; GFX8: ; %bb.0: ; %entry @@ -2391,11 +2431,17 @@ define amdgpu_ps <3 x float> @dyn_insertelement_v3i32_v_v_s(<3 x float> %vec, fl ; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v3i32_v_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v3 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v3i32_v_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movreld_b32_e32 v0, v3 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v3i32_v_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movreld_b32_e32 v0, v3 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v3i32_v_v_s: ; GFX8: ; %bb.0: ; %entry @@ -2420,16 +2466,22 @@ define amdgpu_ps <5 x i32> @dyn_insertelement_v5i32_s_s_s(<5 x i32> inreg %vec, ; GPRIDX-NEXT: s_movreld_b32 s0, s7 ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v5i32_s_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 m0, s8 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_movreld_b32 s0, s7 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v5i32_s_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 m0, s8 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_movreld_b32 s0, s7 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v5i32_s_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s6 +; GFX11-NEXT: s_movreld_b32 s0, s5 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v5i32_s_s_s: ; GFX8: ; %bb.0: ; %entry @@ -2454,11 +2506,17 @@ define amdgpu_ps <5 x float> @dyn_insertelement_v5i32_v_v_s(<5 x float> %vec, fl ; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v5i32_v_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v5 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v5i32_v_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movreld_b32_e32 v0, v5 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v5i32_v_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movreld_b32_e32 v0, v5 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v5i32_v_v_s: ; GFX8: ; %bb.0: ; %entry @@ -2510,43 +2568,49 @@ define amdgpu_ps <32 x i32> @dyn_insertelement_v32i32_s_s_s(<32 x i32> inreg %ve ; GPRIDX-NEXT: s_movreld_b32 s0, s34 ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v32i32_s_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 m0, s35 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_mov_b32 s6, s8 -; GFX10PLUS-NEXT: s_mov_b32 s7, s9 -; GFX10PLUS-NEXT: s_mov_b32 s8, s10 -; GFX10PLUS-NEXT: s_mov_b32 s9, s11 -; GFX10PLUS-NEXT: s_mov_b32 s10, s12 -; GFX10PLUS-NEXT: s_mov_b32 s11, s13 -; GFX10PLUS-NEXT: s_mov_b32 s12, s14 -; GFX10PLUS-NEXT: s_mov_b32 s13, s15 -; GFX10PLUS-NEXT: s_mov_b32 s14, s16 -; GFX10PLUS-NEXT: s_mov_b32 s15, s17 -; GFX10PLUS-NEXT: s_mov_b32 s16, s18 -; GFX10PLUS-NEXT: s_mov_b32 s17, s19 -; GFX10PLUS-NEXT: s_mov_b32 s18, s20 -; GFX10PLUS-NEXT: s_mov_b32 s19, s21 -; GFX10PLUS-NEXT: s_mov_b32 s20, s22 -; GFX10PLUS-NEXT: s_mov_b32 s21, s23 -; GFX10PLUS-NEXT: s_mov_b32 s22, s24 -; GFX10PLUS-NEXT: s_mov_b32 s23, s25 -; GFX10PLUS-NEXT: s_mov_b32 s24, s26 -; GFX10PLUS-NEXT: s_mov_b32 s25, s27 -; GFX10PLUS-NEXT: s_mov_b32 s26, s28 -; GFX10PLUS-NEXT: s_mov_b32 s27, s29 -; GFX10PLUS-NEXT: s_mov_b32 s28, s30 -; GFX10PLUS-NEXT: s_mov_b32 s29, s31 -; GFX10PLUS-NEXT: s_mov_b32 s31, s33 -; GFX10PLUS-NEXT: s_mov_b32 s30, s32 -; GFX10PLUS-NEXT: s_movreld_b32 s0, s34 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v32i32_s_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 m0, s35 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: s_mov_b32 s8, s10 +; GFX10-NEXT: s_mov_b32 s9, s11 +; GFX10-NEXT: s_mov_b32 s10, s12 +; GFX10-NEXT: s_mov_b32 s11, s13 +; GFX10-NEXT: s_mov_b32 s12, s14 +; GFX10-NEXT: s_mov_b32 s13, s15 +; GFX10-NEXT: s_mov_b32 s14, s16 +; GFX10-NEXT: s_mov_b32 s15, s17 +; GFX10-NEXT: s_mov_b32 s16, s18 +; GFX10-NEXT: s_mov_b32 s17, s19 +; GFX10-NEXT: s_mov_b32 s18, s20 +; GFX10-NEXT: s_mov_b32 s19, s21 +; GFX10-NEXT: s_mov_b32 s20, s22 +; GFX10-NEXT: s_mov_b32 s21, s23 +; GFX10-NEXT: s_mov_b32 s22, s24 +; GFX10-NEXT: s_mov_b32 s23, s25 +; GFX10-NEXT: s_mov_b32 s24, s26 +; GFX10-NEXT: s_mov_b32 s25, s27 +; GFX10-NEXT: s_mov_b32 s26, s28 +; GFX10-NEXT: s_mov_b32 s27, s29 +; GFX10-NEXT: s_mov_b32 s28, s30 +; GFX10-NEXT: s_mov_b32 s29, s31 +; GFX10-NEXT: s_mov_b32 s31, s33 +; GFX10-NEXT: s_mov_b32 s30, s32 +; GFX10-NEXT: s_movreld_b32 s0, s34 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v32i32_s_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s33 +; GFX11-NEXT: s_movreld_b32 s0, s32 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v32i32_s_s_s: ; GFX8: ; %bb.0: ; %entry @@ -2598,11 +2662,17 @@ define amdgpu_ps <32 x float> @dyn_insertelement_v32i32_v_v_s(<32 x float> %vec, ; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v32i32_v_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v32 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v32i32_v_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movreld_b32_e32 v0, v32 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v32i32_v_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movreld_b32_e32 v0, v32 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v32i32_v_v_s: ; GFX8: ; %bb.0: ; %entry @@ -2662,16 +2732,8 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_s_add_1(<8 x float> in ; ; GFX11-LABEL: dyn_insertelement_v8f32_s_s_s_add_1: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 m0, s11 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_movreld_b32 s1, s10 +; GFX11-NEXT: s_mov_b32 m0, s9 +; GFX11-NEXT: s_movreld_b32 s1, s8 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 @@ -2753,16 +2815,8 @@ define amdgpu_ps <8 x float> @dyn_insertelement_v8f32_s_s_s_add_7(<8 x float> in ; ; GFX11-LABEL: dyn_insertelement_v8f32_s_s_s_add_7: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 m0, s11 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_movreld_b32 s7, s10 +; GFX11-NEXT: s_mov_b32 m0, s9 +; GFX11-NEXT: s_movreld_b32 s7, s8 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 @@ -3025,28 +3079,28 @@ define amdgpu_ps void @dyn_insertelement_v8f64_s_s_s_add_1(<8 x double> inreg %v ; ; GFX11-LABEL: dyn_insertelement_v8f64_s_s_s_add_1: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_add_u32 s20, s20, 1 -; GFX11-NEXT: s_cselect_b64 s[0:1], s[18:19], s[2:3] -; GFX11-NEXT: s_cmp_eq_u32 s20, 1 -; GFX11-NEXT: s_cselect_b64 s[2:3], s[18:19], s[4:5] -; GFX11-NEXT: s_cmp_eq_u32 s20, 2 +; GFX11-NEXT: s_add_u32 s18, s18, 1 +; GFX11-NEXT: s_cselect_b64 s[0:1], s[16:17], s[0:1] +; GFX11-NEXT: s_cmp_eq_u32 s18, 1 +; GFX11-NEXT: s_cselect_b64 s[2:3], s[16:17], s[2:3] +; GFX11-NEXT: s_cmp_eq_u32 s18, 2 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_cselect_b64 s[4:5], s[18:19], s[6:7] -; GFX11-NEXT: s_cmp_eq_u32 s20, 3 +; GFX11-NEXT: s_cselect_b64 s[4:5], s[16:17], s[4:5] +; GFX11-NEXT: s_cmp_eq_u32 s18, 3 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: s_cselect_b64 s[6:7], s[18:19], s[8:9] -; GFX11-NEXT: s_cmp_eq_u32 s20, 4 +; GFX11-NEXT: s_cselect_b64 s[6:7], s[16:17], s[6:7] +; GFX11-NEXT: s_cmp_eq_u32 s18, 4 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 -; GFX11-NEXT: s_cselect_b64 s[8:9], s[18:19], s[10:11] -; GFX11-NEXT: s_cmp_eq_u32 s20, 5 +; GFX11-NEXT: s_cselect_b64 s[8:9], s[16:17], s[8:9] +; GFX11-NEXT: s_cmp_eq_u32 s18, 5 ; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 -; GFX11-NEXT: s_cselect_b64 s[10:11], s[18:19], s[12:13] -; GFX11-NEXT: s_cmp_eq_u32 s20, 6 +; GFX11-NEXT: s_cselect_b64 s[10:11], s[16:17], s[10:11] +; GFX11-NEXT: s_cmp_eq_u32 s18, 6 ; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 -; GFX11-NEXT: s_cselect_b64 s[12:13], s[18:19], s[14:15] -; GFX11-NEXT: s_cmp_eq_u32 s20, 7 +; GFX11-NEXT: s_cselect_b64 s[12:13], s[16:17], s[12:13] +; GFX11-NEXT: s_cmp_eq_u32 s18, 7 ; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 -; GFX11-NEXT: s_cselect_b64 s[14:15], s[18:19], s[16:17] +; GFX11-NEXT: s_cselect_b64 s[14:15], s[16:17], s[14:15] ; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 ; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 ; GFX11-NEXT: global_store_b128 v[0:1], v[0:3], off dlc @@ -3329,17 +3383,8 @@ define amdgpu_ps <9 x float> @dyn_insertelement_v9f32_s_v_s(<9 x float> inreg %v ; ; GFX11-LABEL: dyn_insertelement_v9f32_s_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 ; GFX11-NEXT: v_dual_mov_b32 v9, v0 :: v_dual_mov_b32 v0, s0 -; GFX11-NEXT: s_mov_b32 m0, s11 +; GFX11-NEXT: s_mov_b32 m0, s9 ; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2 ; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v4, s4 ; GFX11-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, s6 @@ -3437,23 +3482,23 @@ define amdgpu_ps <9 x float> @dyn_insertelement_v9f32_s_v_v(<9 x float> inreg %v ; GFX11-LABEL: dyn_insertelement_v9f32_s_v_v: ; GFX11: ; %bb.0: ; %entry ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v10, s2, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v10, s0, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v9, s3, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v9, s1, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v2, s2, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v3, s5, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v3, s3, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v4, s6, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v4, s4, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v5, s7, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v5, s5, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v6, s8, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v6, s6, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v7, s9, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v7, s7, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v1 -; GFX11-NEXT: v_dual_mov_b32 v1, v9 :: v_dual_cndmask_b32 v8, s10, v0 +; GFX11-NEXT: v_dual_mov_b32 v1, v9 :: v_dual_cndmask_b32 v8, s8, v0 ; GFX11-NEXT: v_mov_b32_e32 v0, v10 ; GFX11-NEXT: ; return to shader part epilog ; @@ -3502,11 +3547,17 @@ define amdgpu_ps <9 x float> @dyn_insertelement_v9f32_v_v_s(<9 x float> %vec, fl ; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v9f32_v_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v9 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v9f32_v_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movreld_b32_e32 v0, v9 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v9f32_v_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movreld_b32_e32 v0, v9 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v9f32_v_v_s: ; GFX8: ; %bb.0: ; %entry @@ -3647,19 +3698,9 @@ define amdgpu_ps <10 x float> @dyn_insertelement_v10f32_s_v_s(<10 x float> inreg ; ; GFX11-LABEL: dyn_insertelement_v10f32_s_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 ; GFX11-NEXT: v_dual_mov_b32 v10, v0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: s_mov_b32 m0, s12 +; GFX11-NEXT: s_mov_b32 m0, s10 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7 ; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v9, s9 @@ -3764,26 +3805,26 @@ define amdgpu_ps <10 x float> @dyn_insertelement_v10f32_s_v_v(<10 x float> inreg ; GFX11-LABEL: dyn_insertelement_v10f32_s_v_v: ; GFX11: ; %bb.0: ; %entry ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v10, s2, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v10, s0, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v11, s3, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v11, s1, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v2, s2, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v3, s5, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v3, s3, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v4, s6, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v4, s4, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v5, s7, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v5, s5, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v6, s8, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v6, s6, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v7, s9, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v7, s7, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v8, s10, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v8, s8, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v1 ; GFX11-NEXT: v_mov_b32_e32 v1, v11 -; GFX11-NEXT: v_dual_cndmask_b32 v9, s11, v0 :: v_dual_mov_b32 v0, v10 +; GFX11-NEXT: v_dual_cndmask_b32 v9, s9, v0 :: v_dual_mov_b32 v0, v10 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v10f32_s_v_v: @@ -3834,11 +3875,17 @@ define amdgpu_ps <10 x float> @dyn_insertelement_v10f32_v_v_s(<10 x float> %vec, ; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v10f32_v_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v10 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v10f32_v_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movreld_b32_e32 v0, v10 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v10f32_v_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movreld_b32_e32 v0, v10 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v10f32_v_v_s: ; GFX8: ; %bb.0: ; %entry @@ -3989,19 +4036,8 @@ define amdgpu_ps <11 x float> @dyn_insertelement_v11f32_s_v_s(<11 x float> inreg ; ; GFX11-LABEL: dyn_insertelement_v11f32_s_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 ; GFX11-NEXT: v_dual_mov_b32 v11, v0 :: v_dual_mov_b32 v0, s0 -; GFX11-NEXT: s_mov_b32 m0, s13 +; GFX11-NEXT: s_mov_b32 m0, s11 ; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2 ; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v4, s4 ; GFX11-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, s6 @@ -4114,27 +4150,27 @@ define amdgpu_ps <11 x float> @dyn_insertelement_v11f32_s_v_v(<11 x float> inreg ; GFX11-LABEL: dyn_insertelement_v11f32_s_v_v: ; GFX11: ; %bb.0: ; %entry ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v12, s2, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v12, s0, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v11, s3, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v11, s1, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v2, s2, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v3, s5, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v3, s3, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v4, s6, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v4, s4, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v5, s7, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v5, s5, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v6, s8, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v6, s6, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v7, s9, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v7, s7, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v8, s10, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v8, s8, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v9, s11, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v9, s9, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 10, v1 -; GFX11-NEXT: v_dual_mov_b32 v1, v11 :: v_dual_cndmask_b32 v10, s12, v0 +; GFX11-NEXT: v_dual_mov_b32 v1, v11 :: v_dual_cndmask_b32 v10, s10, v0 ; GFX11-NEXT: v_mov_b32_e32 v0, v12 ; GFX11-NEXT: ; return to shader part epilog ; @@ -4189,11 +4225,17 @@ define amdgpu_ps <11 x float> @dyn_insertelement_v11f32_v_v_s(<11 x float> %vec, ; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v11f32_v_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v11 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v11f32_v_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movreld_b32_e32 v0, v11 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v11f32_v_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movreld_b32_e32 v0, v11 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v11f32_v_v_s: ; GFX8: ; %bb.0: ; %entry @@ -4354,21 +4396,9 @@ define amdgpu_ps <12 x float> @dyn_insertelement_v12f32_s_v_s(<12 x float> inreg ; ; GFX11-LABEL: dyn_insertelement_v12f32_s_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 ; GFX11-NEXT: v_dual_mov_b32 v12, v0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: s_mov_b32 m0, s14 +; GFX11-NEXT: s_mov_b32 m0, s12 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7 ; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v9, s9 @@ -4488,30 +4518,30 @@ define amdgpu_ps <12 x float> @dyn_insertelement_v12f32_s_v_v(<12 x float> inreg ; GFX11-LABEL: dyn_insertelement_v12f32_s_v_v: ; GFX11: ; %bb.0: ; %entry ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v12, s2, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v12, s0, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v13, s3, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v13, s1, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v2, s2, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v3, s5, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v3, s3, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v4, s6, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v4, s4, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v5, s7, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v5, s5, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v6, s8, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v6, s6, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 7, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v7, s9, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v7, s7, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 8, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v8, s10, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v8, s8, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 9, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v9, s11, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v9, s9, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 10, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v10, s12, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v10, s10, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 11, v1 ; GFX11-NEXT: v_mov_b32_e32 v1, v13 -; GFX11-NEXT: v_dual_cndmask_b32 v11, s13, v0 :: v_dual_mov_b32 v0, v12 +; GFX11-NEXT: v_dual_cndmask_b32 v11, s11, v0 :: v_dual_mov_b32 v0, v12 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v12f32_s_v_v: @@ -4568,11 +4598,17 @@ define amdgpu_ps <12 x float> @dyn_insertelement_v12f32_v_v_s(<12 x float> %vec, ; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v12f32_v_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v12 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v12f32_v_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movreld_b32_e32 v0, v12 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v12f32_v_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movreld_b32_e32 v0, v12 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v12f32_v_v_s: ; GFX8: ; %bb.0: ; %entry @@ -4697,27 +4733,33 @@ define amdgpu_ps <16 x i32> @dyn_insertelement_v16i32_s_s_s(<16 x i32> inreg %ve ; GPRIDX-NEXT: s_movreld_b32 s0, s18 ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v16i32_s_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 m0, s19 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_mov_b32 s6, s8 -; GFX10PLUS-NEXT: s_mov_b32 s7, s9 -; GFX10PLUS-NEXT: s_mov_b32 s8, s10 -; GFX10PLUS-NEXT: s_mov_b32 s9, s11 -; GFX10PLUS-NEXT: s_mov_b32 s10, s12 -; GFX10PLUS-NEXT: s_mov_b32 s11, s13 -; GFX10PLUS-NEXT: s_mov_b32 s12, s14 -; GFX10PLUS-NEXT: s_mov_b32 s13, s15 -; GFX10PLUS-NEXT: s_mov_b32 s14, s16 -; GFX10PLUS-NEXT: s_mov_b32 s15, s17 -; GFX10PLUS-NEXT: s_movreld_b32 s0, s18 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v16i32_s_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 m0, s19 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: s_mov_b32 s8, s10 +; GFX10-NEXT: s_mov_b32 s9, s11 +; GFX10-NEXT: s_mov_b32 s10, s12 +; GFX10-NEXT: s_mov_b32 s11, s13 +; GFX10-NEXT: s_mov_b32 s12, s14 +; GFX10-NEXT: s_mov_b32 s13, s15 +; GFX10-NEXT: s_mov_b32 s14, s16 +; GFX10-NEXT: s_mov_b32 s15, s17 +; GFX10-NEXT: s_movreld_b32 s0, s18 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v16i32_s_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s17 +; GFX11-NEXT: s_movreld_b32 s0, s16 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v16i32_s_s_s: ; GFX8: ; %bb.0: ; %entry @@ -4825,24 +4867,8 @@ define amdgpu_ps <16 x float> @dyn_insertelement_v16f32_s_s_s(<16 x float> inreg ; ; GFX11-LABEL: dyn_insertelement_v16f32_s_s_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 m0, s19 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 -; GFX11-NEXT: s_movreld_b32 s0, s18 +; GFX11-NEXT: s_mov_b32 m0, s17 +; GFX11-NEXT: s_movreld_b32 s0, s16 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 @@ -5039,40 +5065,8 @@ define amdgpu_ps <32 x float> @dyn_insertelement_v32f32_s_s_s(<32 x float> inreg ; ; GFX11-LABEL: dyn_insertelement_v32f32_s_s_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 m0, s35 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 -; GFX11-NEXT: s_mov_b32 s16, s18 -; GFX11-NEXT: s_mov_b32 s17, s19 -; GFX11-NEXT: s_mov_b32 s18, s20 -; GFX11-NEXT: s_mov_b32 s19, s21 -; GFX11-NEXT: s_mov_b32 s20, s22 -; GFX11-NEXT: s_mov_b32 s21, s23 -; GFX11-NEXT: s_mov_b32 s22, s24 -; GFX11-NEXT: s_mov_b32 s23, s25 -; GFX11-NEXT: s_mov_b32 s24, s26 -; GFX11-NEXT: s_mov_b32 s25, s27 -; GFX11-NEXT: s_mov_b32 s26, s28 -; GFX11-NEXT: s_mov_b32 s27, s29 -; GFX11-NEXT: s_mov_b32 s28, s30 -; GFX11-NEXT: s_mov_b32 s29, s31 -; GFX11-NEXT: s_mov_b32 s31, s33 -; GFX11-NEXT: s_mov_b32 s30, s32 -; GFX11-NEXT: s_movreld_b32 s0, s34 +; GFX11-NEXT: s_mov_b32 m0, s33 +; GFX11-NEXT: s_movreld_b32 s0, s32 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 @@ -5204,43 +5198,81 @@ define amdgpu_ps <16 x i64> @dyn_insertelement_v16i64_s_s_s(<16 x i64> inreg %ve ; GPRIDX-NEXT: s_cselect_b64 s[30:31], s[34:35], s[38:39] ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v16i64_s_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 0 -; GFX10PLUS-NEXT: s_mov_b32 s39, s33 -; GFX10PLUS-NEXT: s_cselect_b64 s[0:1], s[34:35], s[2:3] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 1 -; GFX10PLUS-NEXT: s_mov_b32 s38, s32 -; GFX10PLUS-NEXT: s_cselect_b64 s[2:3], s[34:35], s[4:5] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 2 -; GFX10PLUS-NEXT: s_cselect_b64 s[4:5], s[34:35], s[6:7] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 3 -; GFX10PLUS-NEXT: s_cselect_b64 s[6:7], s[34:35], s[8:9] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 4 -; GFX10PLUS-NEXT: s_cselect_b64 s[8:9], s[34:35], s[10:11] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 5 -; GFX10PLUS-NEXT: s_cselect_b64 s[10:11], s[34:35], s[12:13] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 6 -; GFX10PLUS-NEXT: s_cselect_b64 s[12:13], s[34:35], s[14:15] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 7 -; GFX10PLUS-NEXT: s_cselect_b64 s[14:15], s[34:35], s[16:17] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 8 -; GFX10PLUS-NEXT: s_cselect_b64 s[16:17], s[34:35], s[18:19] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 9 -; GFX10PLUS-NEXT: s_cselect_b64 s[18:19], s[34:35], s[20:21] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 10 -; GFX10PLUS-NEXT: s_cselect_b64 s[20:21], s[34:35], s[22:23] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 11 -; GFX10PLUS-NEXT: s_cselect_b64 s[22:23], s[34:35], s[24:25] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 12 -; GFX10PLUS-NEXT: s_cselect_b64 s[24:25], s[34:35], s[26:27] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 13 -; GFX10PLUS-NEXT: s_cselect_b64 s[26:27], s[34:35], s[28:29] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 14 -; GFX10PLUS-NEXT: s_cselect_b64 s[28:29], s[34:35], s[30:31] -; GFX10PLUS-NEXT: s_cmp_eq_u32 s36, 15 -; GFX10PLUS-NEXT: s_cselect_b64 s[30:31], s[34:35], s[38:39] -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v16i64_s_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_cmp_eq_u32 s36, 0 +; GFX10-NEXT: s_mov_b32 s39, s33 +; GFX10-NEXT: s_cselect_b64 s[0:1], s[34:35], s[2:3] +; GFX10-NEXT: s_cmp_eq_u32 s36, 1 +; GFX10-NEXT: s_mov_b32 s38, s32 +; GFX10-NEXT: s_cselect_b64 s[2:3], s[34:35], s[4:5] +; GFX10-NEXT: s_cmp_eq_u32 s36, 2 +; GFX10-NEXT: s_cselect_b64 s[4:5], s[34:35], s[6:7] +; GFX10-NEXT: s_cmp_eq_u32 s36, 3 +; GFX10-NEXT: s_cselect_b64 s[6:7], s[34:35], s[8:9] +; GFX10-NEXT: s_cmp_eq_u32 s36, 4 +; GFX10-NEXT: s_cselect_b64 s[8:9], s[34:35], s[10:11] +; GFX10-NEXT: s_cmp_eq_u32 s36, 5 +; GFX10-NEXT: s_cselect_b64 s[10:11], s[34:35], s[12:13] +; GFX10-NEXT: s_cmp_eq_u32 s36, 6 +; GFX10-NEXT: s_cselect_b64 s[12:13], s[34:35], s[14:15] +; GFX10-NEXT: s_cmp_eq_u32 s36, 7 +; GFX10-NEXT: s_cselect_b64 s[14:15], s[34:35], s[16:17] +; GFX10-NEXT: s_cmp_eq_u32 s36, 8 +; GFX10-NEXT: s_cselect_b64 s[16:17], s[34:35], s[18:19] +; GFX10-NEXT: s_cmp_eq_u32 s36, 9 +; GFX10-NEXT: s_cselect_b64 s[18:19], s[34:35], s[20:21] +; GFX10-NEXT: s_cmp_eq_u32 s36, 10 +; GFX10-NEXT: s_cselect_b64 s[20:21], s[34:35], s[22:23] +; GFX10-NEXT: s_cmp_eq_u32 s36, 11 +; GFX10-NEXT: s_cselect_b64 s[22:23], s[34:35], s[24:25] +; GFX10-NEXT: s_cmp_eq_u32 s36, 12 +; GFX10-NEXT: s_cselect_b64 s[24:25], s[34:35], s[26:27] +; GFX10-NEXT: s_cmp_eq_u32 s36, 13 +; GFX10-NEXT: s_cselect_b64 s[26:27], s[34:35], s[28:29] +; GFX10-NEXT: s_cmp_eq_u32 s36, 14 +; GFX10-NEXT: s_cselect_b64 s[28:29], s[34:35], s[30:31] +; GFX10-NEXT: s_cmp_eq_u32 s36, 15 +; GFX10-NEXT: s_cselect_b64 s[30:31], s[34:35], s[38:39] +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v16i64_s_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 s37, s33 +; GFX11-NEXT: s_mov_b32 s36, s32 +; GFX11-NEXT: s_cmp_eq_u32 s34, 0 +; GFX11-NEXT: s_cselect_b64 s[0:1], s[36:37], s[0:1] +; GFX11-NEXT: s_cmp_eq_u32 s34, 1 +; GFX11-NEXT: s_cselect_b64 s[2:3], s[36:37], s[2:3] +; GFX11-NEXT: s_cmp_eq_u32 s34, 2 +; GFX11-NEXT: s_cselect_b64 s[4:5], s[36:37], s[4:5] +; GFX11-NEXT: s_cmp_eq_u32 s34, 3 +; GFX11-NEXT: s_cselect_b64 s[6:7], s[36:37], s[6:7] +; GFX11-NEXT: s_cmp_eq_u32 s34, 4 +; GFX11-NEXT: s_cselect_b64 s[8:9], s[36:37], s[8:9] +; GFX11-NEXT: s_cmp_eq_u32 s34, 5 +; GFX11-NEXT: s_cselect_b64 s[10:11], s[36:37], s[10:11] +; GFX11-NEXT: s_cmp_eq_u32 s34, 6 +; GFX11-NEXT: s_cselect_b64 s[12:13], s[36:37], s[12:13] +; GFX11-NEXT: s_cmp_eq_u32 s34, 7 +; GFX11-NEXT: s_cselect_b64 s[14:15], s[36:37], s[14:15] +; GFX11-NEXT: s_cmp_eq_u32 s34, 8 +; GFX11-NEXT: s_cselect_b64 s[16:17], s[36:37], s[16:17] +; GFX11-NEXT: s_cmp_eq_u32 s34, 9 +; GFX11-NEXT: s_cselect_b64 s[18:19], s[36:37], s[18:19] +; GFX11-NEXT: s_cmp_eq_u32 s34, 10 +; GFX11-NEXT: s_cselect_b64 s[20:21], s[36:37], s[20:21] +; GFX11-NEXT: s_cmp_eq_u32 s34, 11 +; GFX11-NEXT: s_cselect_b64 s[22:23], s[36:37], s[22:23] +; GFX11-NEXT: s_cmp_eq_u32 s34, 12 +; GFX11-NEXT: s_cselect_b64 s[24:25], s[36:37], s[24:25] +; GFX11-NEXT: s_cmp_eq_u32 s34, 13 +; GFX11-NEXT: s_cselect_b64 s[26:27], s[36:37], s[26:27] +; GFX11-NEXT: s_cmp_eq_u32 s34, 14 +; GFX11-NEXT: s_cselect_b64 s[28:29], s[36:37], s[28:29] +; GFX11-NEXT: s_cmp_eq_u32 s34, 15 +; GFX11-NEXT: s_cselect_b64 s[30:31], s[36:37], s[30:31] +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v16i64_s_s_s: ; GFX8: ; %bb.0: ; %entry @@ -5427,56 +5459,56 @@ define amdgpu_ps <16 x double> @dyn_insertelement_v16f64_s_s_s(<16 x double> inr ; ; GFX11-LABEL: dyn_insertelement_v16f64_s_s_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_cmp_eq_u32 s36, 0 -; GFX11-NEXT: s_mov_b32 s1, s33 -; GFX11-NEXT: s_cselect_b64 s[2:3], s[34:35], s[2:3] -; GFX11-NEXT: s_cmp_eq_u32 s36, 1 -; GFX11-NEXT: s_mov_b32 s0, s32 -; GFX11-NEXT: s_cselect_b64 s[4:5], s[34:35], s[4:5] -; GFX11-NEXT: s_cmp_eq_u32 s36, 2 -; GFX11-NEXT: v_dual_mov_b32 v0, s2 :: v_dual_mov_b32 v1, s3 -; GFX11-NEXT: s_cselect_b64 s[6:7], s[34:35], s[6:7] -; GFX11-NEXT: s_cmp_eq_u32 s36, 3 -; GFX11-NEXT: v_dual_mov_b32 v2, s4 :: v_dual_mov_b32 v3, s5 -; GFX11-NEXT: s_cselect_b64 s[8:9], s[34:35], s[8:9] -; GFX11-NEXT: s_cmp_eq_u32 s36, 4 -; GFX11-NEXT: v_dual_mov_b32 v4, s6 :: v_dual_mov_b32 v5, s7 -; GFX11-NEXT: s_cselect_b64 s[10:11], s[34:35], s[10:11] -; GFX11-NEXT: s_cmp_eq_u32 s36, 5 -; GFX11-NEXT: v_dual_mov_b32 v6, s8 :: v_dual_mov_b32 v7, s9 -; GFX11-NEXT: s_cselect_b64 s[12:13], s[34:35], s[12:13] -; GFX11-NEXT: s_cmp_eq_u32 s36, 6 -; GFX11-NEXT: v_dual_mov_b32 v8, s10 :: v_dual_mov_b32 v9, s11 -; GFX11-NEXT: s_cselect_b64 s[14:15], s[34:35], s[14:15] -; GFX11-NEXT: s_cmp_eq_u32 s36, 7 -; GFX11-NEXT: v_dual_mov_b32 v10, s12 :: v_dual_mov_b32 v11, s13 -; GFX11-NEXT: s_cselect_b64 s[16:17], s[34:35], s[16:17] -; GFX11-NEXT: s_cmp_eq_u32 s36, 8 -; GFX11-NEXT: v_dual_mov_b32 v12, s14 :: v_dual_mov_b32 v13, s15 -; GFX11-NEXT: s_cselect_b64 s[18:19], s[34:35], s[18:19] -; GFX11-NEXT: s_cmp_eq_u32 s36, 9 -; GFX11-NEXT: v_dual_mov_b32 v14, s16 :: v_dual_mov_b32 v15, s17 -; GFX11-NEXT: s_cselect_b64 s[20:21], s[34:35], s[20:21] -; GFX11-NEXT: s_cmp_eq_u32 s36, 10 -; GFX11-NEXT: v_dual_mov_b32 v16, s18 :: v_dual_mov_b32 v17, s19 -; GFX11-NEXT: s_cselect_b64 s[22:23], s[34:35], s[22:23] -; GFX11-NEXT: s_cmp_eq_u32 s36, 11 -; GFX11-NEXT: v_dual_mov_b32 v18, s20 :: v_dual_mov_b32 v19, s21 -; GFX11-NEXT: s_cselect_b64 s[24:25], s[34:35], s[24:25] -; GFX11-NEXT: s_cmp_eq_u32 s36, 12 -; GFX11-NEXT: v_dual_mov_b32 v20, s22 :: v_dual_mov_b32 v21, s23 -; GFX11-NEXT: s_cselect_b64 s[26:27], s[34:35], s[26:27] -; GFX11-NEXT: s_cmp_eq_u32 s36, 13 -; GFX11-NEXT: v_dual_mov_b32 v22, s24 :: v_dual_mov_b32 v23, s25 -; GFX11-NEXT: s_cselect_b64 s[28:29], s[34:35], s[28:29] -; GFX11-NEXT: s_cmp_eq_u32 s36, 14 -; GFX11-NEXT: v_dual_mov_b32 v24, s26 :: v_dual_mov_b32 v25, s27 -; GFX11-NEXT: s_cselect_b64 s[30:31], s[34:35], s[30:31] -; GFX11-NEXT: s_cmp_eq_u32 s36, 15 -; GFX11-NEXT: v_dual_mov_b32 v26, s28 :: v_dual_mov_b32 v27, s29 -; GFX11-NEXT: s_cselect_b64 s[0:1], s[34:35], s[0:1] -; GFX11-NEXT: v_dual_mov_b32 v28, s30 :: v_dual_mov_b32 v29, s31 -; GFX11-NEXT: v_dual_mov_b32 v30, s0 :: v_dual_mov_b32 v31, s1 +; GFX11-NEXT: s_mov_b32 s37, s33 +; GFX11-NEXT: s_mov_b32 s36, s32 +; GFX11-NEXT: s_cmp_eq_u32 s34, 0 +; GFX11-NEXT: s_cselect_b64 s[0:1], s[36:37], s[0:1] +; GFX11-NEXT: s_cmp_eq_u32 s34, 1 +; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 +; GFX11-NEXT: s_cselect_b64 s[2:3], s[36:37], s[2:3] +; GFX11-NEXT: s_cmp_eq_u32 s34, 2 +; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX11-NEXT: s_cselect_b64 s[4:5], s[36:37], s[4:5] +; GFX11-NEXT: s_cmp_eq_u32 s34, 3 +; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 +; GFX11-NEXT: s_cselect_b64 s[6:7], s[36:37], s[6:7] +; GFX11-NEXT: s_cmp_eq_u32 s34, 4 +; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 +; GFX11-NEXT: s_cselect_b64 s[8:9], s[36:37], s[8:9] +; GFX11-NEXT: s_cmp_eq_u32 s34, 5 +; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 +; GFX11-NEXT: s_cselect_b64 s[10:11], s[36:37], s[10:11] +; GFX11-NEXT: s_cmp_eq_u32 s34, 6 +; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 +; GFX11-NEXT: s_cselect_b64 s[12:13], s[36:37], s[12:13] +; GFX11-NEXT: s_cmp_eq_u32 s34, 7 +; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 +; GFX11-NEXT: s_cselect_b64 s[14:15], s[36:37], s[14:15] +; GFX11-NEXT: s_cmp_eq_u32 s34, 8 +; GFX11-NEXT: v_dual_mov_b32 v14, s14 :: v_dual_mov_b32 v15, s15 +; GFX11-NEXT: s_cselect_b64 s[16:17], s[36:37], s[16:17] +; GFX11-NEXT: s_cmp_eq_u32 s34, 9 +; GFX11-NEXT: v_dual_mov_b32 v16, s16 :: v_dual_mov_b32 v17, s17 +; GFX11-NEXT: s_cselect_b64 s[18:19], s[36:37], s[18:19] +; GFX11-NEXT: s_cmp_eq_u32 s34, 10 +; GFX11-NEXT: v_dual_mov_b32 v18, s18 :: v_dual_mov_b32 v19, s19 +; GFX11-NEXT: s_cselect_b64 s[20:21], s[36:37], s[20:21] +; GFX11-NEXT: s_cmp_eq_u32 s34, 11 +; GFX11-NEXT: v_dual_mov_b32 v20, s20 :: v_dual_mov_b32 v21, s21 +; GFX11-NEXT: s_cselect_b64 s[22:23], s[36:37], s[22:23] +; GFX11-NEXT: s_cmp_eq_u32 s34, 12 +; GFX11-NEXT: v_dual_mov_b32 v22, s22 :: v_dual_mov_b32 v23, s23 +; GFX11-NEXT: s_cselect_b64 s[24:25], s[36:37], s[24:25] +; GFX11-NEXT: s_cmp_eq_u32 s34, 13 +; GFX11-NEXT: v_dual_mov_b32 v24, s24 :: v_dual_mov_b32 v25, s25 +; GFX11-NEXT: s_cselect_b64 s[26:27], s[36:37], s[26:27] +; GFX11-NEXT: s_cmp_eq_u32 s34, 14 +; GFX11-NEXT: v_dual_mov_b32 v26, s26 :: v_dual_mov_b32 v27, s27 +; GFX11-NEXT: s_cselect_b64 s[28:29], s[36:37], s[28:29] +; GFX11-NEXT: s_cmp_eq_u32 s34, 15 +; GFX11-NEXT: v_dual_mov_b32 v28, s28 :: v_dual_mov_b32 v29, s29 +; GFX11-NEXT: s_cselect_b64 s[30:31], s[36:37], s[30:31] +; GFX11-NEXT: v_dual_mov_b32 v30, s30 :: v_dual_mov_b32 v31, s31 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v16f64_s_s_s: @@ -5665,24 +5697,8 @@ define amdgpu_ps <16 x i32> @dyn_insertelement_v16i32_s_v_s(<16 x i32> inreg %ve ; ; GFX11-LABEL: dyn_insertelement_v16i32_s_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 ; GFX11-NEXT: v_dual_mov_b32 v2, s1 :: v_dual_mov_b32 v1, s0 -; GFX11-NEXT: s_mov_b32 m0, s18 +; GFX11-NEXT: s_mov_b32 m0, s16 ; GFX11-NEXT: v_dual_mov_b32 v16, s15 :: v_dual_mov_b32 v15, s14 ; GFX11-NEXT: v_dual_mov_b32 v14, s13 :: v_dual_mov_b32 v13, s12 ; GFX11-NEXT: v_dual_mov_b32 v12, s11 :: v_dual_mov_b32 v11, s10 @@ -5849,25 +5865,9 @@ define amdgpu_ps <16 x float> @dyn_insertelement_v16f32_s_v_s(<16 x float> inreg ; ; GFX11-LABEL: dyn_insertelement_v16f32_s_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 ; GFX11-NEXT: v_dual_mov_b32 v16, v0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: s_mov_b32 m0, s18 +; GFX11-NEXT: s_mov_b32 m0, s16 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7 ; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v9, s9 @@ -6067,41 +6067,9 @@ define amdgpu_ps <32 x float> @dyn_insertelement_v32f32_s_v_s(<32 x float> inreg ; ; GFX11-LABEL: dyn_insertelement_v32f32_s_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 -; GFX11-NEXT: s_mov_b32 s16, s18 -; GFX11-NEXT: s_mov_b32 s17, s19 -; GFX11-NEXT: s_mov_b32 s18, s20 -; GFX11-NEXT: s_mov_b32 s19, s21 -; GFX11-NEXT: s_mov_b32 s20, s22 -; GFX11-NEXT: s_mov_b32 s21, s23 -; GFX11-NEXT: s_mov_b32 s22, s24 -; GFX11-NEXT: s_mov_b32 s23, s25 -; GFX11-NEXT: s_mov_b32 s24, s26 -; GFX11-NEXT: s_mov_b32 s25, s27 -; GFX11-NEXT: s_mov_b32 s26, s28 -; GFX11-NEXT: s_mov_b32 s27, s29 -; GFX11-NEXT: s_mov_b32 s28, s30 -; GFX11-NEXT: s_mov_b32 s29, s31 -; GFX11-NEXT: s_mov_b32 s31, s33 -; GFX11-NEXT: s_mov_b32 s30, s32 ; GFX11-NEXT: v_dual_mov_b32 v32, v0 :: v_dual_mov_b32 v1, s1 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: s_mov_b32 m0, s34 +; GFX11-NEXT: s_mov_b32 m0, s32 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v5, s5 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v7, s7 ; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v9, s9 @@ -6406,40 +6374,8 @@ define amdgpu_ps <16 x i64> @dyn_insertelement_v16i64_s_v_s(<16 x i64> inreg %ve ; ; GFX11-LABEL: dyn_insertelement_v16i64_s_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 -; GFX11-NEXT: s_mov_b32 s16, s18 -; GFX11-NEXT: s_mov_b32 s17, s19 -; GFX11-NEXT: s_mov_b32 s18, s20 -; GFX11-NEXT: s_mov_b32 s19, s21 -; GFX11-NEXT: s_mov_b32 s20, s22 -; GFX11-NEXT: s_mov_b32 s21, s23 -; GFX11-NEXT: s_mov_b32 s22, s24 -; GFX11-NEXT: s_mov_b32 s23, s25 -; GFX11-NEXT: s_mov_b32 s24, s26 -; GFX11-NEXT: s_mov_b32 s25, s27 -; GFX11-NEXT: s_mov_b32 s26, s28 -; GFX11-NEXT: s_mov_b32 s27, s29 -; GFX11-NEXT: s_mov_b32 s28, s30 -; GFX11-NEXT: s_mov_b32 s29, s31 -; GFX11-NEXT: s_mov_b32 s31, s33 -; GFX11-NEXT: s_mov_b32 s30, s32 ; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 -; GFX11-NEXT: s_lshl_b32 m0, s34, 1 +; GFX11-NEXT: s_lshl_b32 m0, s32, 1 ; GFX11-NEXT: v_dual_mov_b32 v33, s31 :: v_dual_mov_b32 v32, s30 ; GFX11-NEXT: v_dual_mov_b32 v31, s29 :: v_dual_mov_b32 v30, s28 ; GFX11-NEXT: v_dual_mov_b32 v29, s27 :: v_dual_mov_b32 v28, s26 @@ -6749,41 +6685,9 @@ define amdgpu_ps <16 x double> @dyn_insertelement_v16f64_s_v_s(<16 x double> inr ; ; GFX11-LABEL: dyn_insertelement_v16f64_s_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 -; GFX11-NEXT: s_mov_b32 s14, s16 -; GFX11-NEXT: s_mov_b32 s15, s17 -; GFX11-NEXT: s_mov_b32 s16, s18 -; GFX11-NEXT: s_mov_b32 s17, s19 -; GFX11-NEXT: s_mov_b32 s18, s20 -; GFX11-NEXT: s_mov_b32 s19, s21 -; GFX11-NEXT: s_mov_b32 s20, s22 -; GFX11-NEXT: s_mov_b32 s21, s23 -; GFX11-NEXT: s_mov_b32 s22, s24 -; GFX11-NEXT: s_mov_b32 s23, s25 -; GFX11-NEXT: s_mov_b32 s24, s26 -; GFX11-NEXT: s_mov_b32 s25, s27 -; GFX11-NEXT: s_mov_b32 s26, s28 -; GFX11-NEXT: s_mov_b32 s27, s29 -; GFX11-NEXT: s_mov_b32 s28, s30 -; GFX11-NEXT: s_mov_b32 s29, s31 -; GFX11-NEXT: s_mov_b32 s31, s33 -; GFX11-NEXT: s_mov_b32 s30, s32 ; GFX11-NEXT: v_dual_mov_b32 v32, v0 :: v_dual_mov_b32 v33, v1 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_lshl_b32 m0, s34, 1 +; GFX11-NEXT: s_lshl_b32 m0, s32, 1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 ; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 @@ -6895,18 +6799,24 @@ define amdgpu_ps <7 x i32> @dyn_insertelement_v7i32_s_s_s(<7 x i32> inreg %vec, ; GPRIDX-NEXT: s_movreld_b32 s0, s9 ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v7i32_s_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 m0, s10 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_mov_b32 s6, s8 -; GFX10PLUS-NEXT: s_movreld_b32 s0, s9 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v7i32_s_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 m0, s10 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_movreld_b32 s0, s9 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v7i32_s_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s8 +; GFX11-NEXT: s_movreld_b32 s0, s7 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v7i32_s_s_s: ; GFX8: ; %bb.0: ; %entry @@ -6940,18 +6850,24 @@ define amdgpu_ps <7 x ptr addrspace(3)> @dyn_insertelement_v7p3i8_s_s_s(<7 x ptr ; GPRIDX-NEXT: s_movreld_b32 s0, s9 ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v7p3i8_s_s_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 m0, s10 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_mov_b32 s6, s8 -; GFX10PLUS-NEXT: s_movreld_b32 s0, s9 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v7p3i8_s_s_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 m0, s10 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_movreld_b32 s0, s9 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v7p3i8_s_s_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s8 +; GFX11-NEXT: s_movreld_b32 s0, s7 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v7p3i8_s_s_s: ; GFX8: ; %bb.0: ; %entry @@ -7016,15 +6932,8 @@ define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_s_v_s(<7 x float> inreg %v ; ; GFX11-LABEL: dyn_insertelement_v7f32_s_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 ; GFX11-NEXT: v_dual_mov_b32 v7, v0 :: v_dual_mov_b32 v0, s0 -; GFX11-NEXT: s_mov_b32 m0, s9 +; GFX11-NEXT: s_mov_b32 m0, s7 ; GFX11-NEXT: v_dual_mov_b32 v1, s1 :: v_dual_mov_b32 v2, s2 ; GFX11-NEXT: v_dual_mov_b32 v3, s3 :: v_dual_mov_b32 v4, s4 ; GFX11-NEXT: v_dual_mov_b32 v5, s5 :: v_dual_mov_b32 v6, s6 @@ -7107,19 +7016,19 @@ define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_s_v_v(<7 x float> inreg %v ; GFX11-LABEL: dyn_insertelement_v7f32_s_v_v: ; GFX11: ; %bb.0: ; %entry ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 0, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v8, s2, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v8, s0, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 1, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v7, s3, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v7, s1, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 2, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v2, s4, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v2, s2, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 3, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v3, s5, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v3, s3, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 4, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v4, s6, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v4, s4, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 5, v1 -; GFX11-NEXT: v_cndmask_b32_e32 v5, s7, v0, vcc_lo +; GFX11-NEXT: v_cndmask_b32_e32 v5, s5, v0, vcc_lo ; GFX11-NEXT: v_cmp_eq_u32_e32 vcc_lo, 6, v1 -; GFX11-NEXT: v_dual_mov_b32 v1, v7 :: v_dual_cndmask_b32 v6, s8, v0 +; GFX11-NEXT: v_dual_mov_b32 v1, v7 :: v_dual_cndmask_b32 v6, s6, v0 ; GFX11-NEXT: v_mov_b32_e32 v0, v8 ; GFX11-NEXT: ; return to shader part epilog ; @@ -7162,11 +7071,17 @@ define amdgpu_ps <7 x float> @dyn_insertelement_v7f32_v_v_s(<7 x float> %vec, fl ; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v7f32_v_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_mov_b32 m0, s2 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v7 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v7f32_v_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_mov_b32 m0, s2 +; GFX10-NEXT: v_movreld_b32_e32 v0, v7 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v7f32_v_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_mov_b32 m0, s0 +; GFX11-NEXT: v_movreld_b32_e32 v0, v7 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v7f32_v_v_s: ; GFX8: ; %bb.0: ; %entry @@ -7304,26 +7219,26 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_s_s(<7 x double> inreg ; ; GFX11-LABEL: dyn_insertelement_v7f64_s_s_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_cmp_eq_u32 s18, 0 -; GFX11-NEXT: s_cselect_b64 s[0:1], s[16:17], s[2:3] -; GFX11-NEXT: s_cmp_eq_u32 s18, 1 +; GFX11-NEXT: s_cmp_eq_u32 s16, 0 +; GFX11-NEXT: s_cselect_b64 s[0:1], s[14:15], s[0:1] +; GFX11-NEXT: s_cmp_eq_u32 s16, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_cselect_b64 s[2:3], s[16:17], s[4:5] -; GFX11-NEXT: s_cmp_eq_u32 s18, 2 +; GFX11-NEXT: s_cselect_b64 s[2:3], s[14:15], s[2:3] +; GFX11-NEXT: s_cmp_eq_u32 s16, 2 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: s_cselect_b64 s[4:5], s[16:17], s[6:7] -; GFX11-NEXT: s_cmp_eq_u32 s18, 3 +; GFX11-NEXT: s_cselect_b64 s[4:5], s[14:15], s[4:5] +; GFX11-NEXT: s_cmp_eq_u32 s16, 3 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 -; GFX11-NEXT: s_cselect_b64 s[6:7], s[16:17], s[8:9] -; GFX11-NEXT: s_cmp_eq_u32 s18, 4 +; GFX11-NEXT: s_cselect_b64 s[6:7], s[14:15], s[6:7] +; GFX11-NEXT: s_cmp_eq_u32 s16, 4 ; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 -; GFX11-NEXT: s_cselect_b64 s[8:9], s[16:17], s[10:11] -; GFX11-NEXT: s_cmp_eq_u32 s18, 5 +; GFX11-NEXT: s_cselect_b64 s[8:9], s[14:15], s[8:9] +; GFX11-NEXT: s_cmp_eq_u32 s16, 5 ; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 -; GFX11-NEXT: s_cselect_b64 s[10:11], s[16:17], s[12:13] -; GFX11-NEXT: s_cmp_eq_u32 s18, 6 +; GFX11-NEXT: s_cselect_b64 s[10:11], s[14:15], s[10:11] +; GFX11-NEXT: s_cmp_eq_u32 s16, 6 ; GFX11-NEXT: v_dual_mov_b32 v10, s10 :: v_dual_mov_b32 v11, s11 -; GFX11-NEXT: s_cselect_b64 s[12:13], s[16:17], s[14:15] +; GFX11-NEXT: s_cselect_b64 s[12:13], s[14:15], s[12:13] ; GFX11-NEXT: v_dual_mov_b32 v12, s12 :: v_dual_mov_b32 v13, s13 ; GFX11-NEXT: ; return to shader part epilog ; @@ -7446,23 +7361,9 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_s(<7 x double> inreg ; ; GFX11-LABEL: dyn_insertelement_v7f64_s_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 ; GFX11-NEXT: v_dual_mov_b32 v16, v0 :: v_dual_mov_b32 v17, v1 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_lshl_b32 m0, s16, 1 +; GFX11-NEXT: s_lshl_b32 m0, s14, 1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 ; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 @@ -7635,20 +7536,6 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_s_v_v(<7 x double> inreg ; ; GFX11-LABEL: dyn_insertelement_v7f64_s_v_v: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: s_mov_b32 s10, s12 -; GFX11-NEXT: s_mov_b32 s11, s13 -; GFX11-NEXT: s_mov_b32 s12, s14 -; GFX11-NEXT: s_mov_b32 s13, s15 ; GFX11-NEXT: v_dual_mov_b32 v30, s15 :: v_dual_mov_b32 v29, s14 ; GFX11-NEXT: v_dual_mov_b32 v28, s13 :: v_dual_mov_b32 v27, s12 ; GFX11-NEXT: v_dual_mov_b32 v26, s11 :: v_dual_mov_b32 v25, s10 @@ -7751,13 +7638,21 @@ define amdgpu_ps <7 x double> @dyn_insertelement_v7f64_v_v_s(<7 x double> %vec, ; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v7f64_v_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: v_mov_b32_e32 v16, v15 -; GFX10PLUS-NEXT: s_lshl_b32 m0, s2, 1 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v14 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v1, v16 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v7f64_v_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: v_mov_b32_e32 v16, v15 +; GFX10-NEXT: s_lshl_b32 m0, s2, 1 +; GFX10-NEXT: v_movreld_b32_e32 v0, v14 +; GFX10-NEXT: v_movreld_b32_e32 v1, v16 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v7f64_v_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: v_mov_b32_e32 v16, v15 +; GFX11-NEXT: s_lshl_b32 m0, s0, 1 +; GFX11-NEXT: v_movreld_b32_e32 v0, v14 +; GFX11-NEXT: v_movreld_b32_e32 v1, v16 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v7f64_v_v_s: ; GFX8: ; %bb.0: ; %entry @@ -7924,20 +7819,20 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_s_s(<5 x double> inreg ; ; GFX11-LABEL: dyn_insertelement_v5f64_s_s_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_cmp_eq_u32 s14, 0 -; GFX11-NEXT: s_cselect_b64 s[0:1], s[12:13], s[2:3] -; GFX11-NEXT: s_cmp_eq_u32 s14, 1 +; GFX11-NEXT: s_cmp_eq_u32 s12, 0 +; GFX11-NEXT: s_cselect_b64 s[0:1], s[10:11], s[0:1] +; GFX11-NEXT: s_cmp_eq_u32 s12, 1 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_cselect_b64 s[2:3], s[12:13], s[4:5] -; GFX11-NEXT: s_cmp_eq_u32 s14, 2 +; GFX11-NEXT: s_cselect_b64 s[2:3], s[10:11], s[2:3] +; GFX11-NEXT: s_cmp_eq_u32 s12, 2 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 -; GFX11-NEXT: s_cselect_b64 s[4:5], s[12:13], s[6:7] -; GFX11-NEXT: s_cmp_eq_u32 s14, 3 +; GFX11-NEXT: s_cselect_b64 s[4:5], s[10:11], s[4:5] +; GFX11-NEXT: s_cmp_eq_u32 s12, 3 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 -; GFX11-NEXT: s_cselect_b64 s[6:7], s[12:13], s[8:9] -; GFX11-NEXT: s_cmp_eq_u32 s14, 4 +; GFX11-NEXT: s_cselect_b64 s[6:7], s[10:11], s[6:7] +; GFX11-NEXT: s_cmp_eq_u32 s12, 4 ; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 -; GFX11-NEXT: s_cselect_b64 s[8:9], s[12:13], s[10:11] +; GFX11-NEXT: s_cselect_b64 s[8:9], s[10:11], s[8:9] ; GFX11-NEXT: v_dual_mov_b32 v8, s8 :: v_dual_mov_b32 v9, s9 ; GFX11-NEXT: ; return to shader part epilog ; @@ -8032,19 +7927,9 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_s(<5 x double> inreg ; ; GFX11-LABEL: dyn_insertelement_v5f64_s_v_s: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 ; GFX11-NEXT: v_dual_mov_b32 v10, v0 :: v_dual_mov_b32 v11, v1 ; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 -; GFX11-NEXT: s_lshl_b32 m0, s12, 1 +; GFX11-NEXT: s_lshl_b32 m0, s10, 1 ; GFX11-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX11-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5 ; GFX11-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7 @@ -8173,17 +8058,7 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_s_v_v(<5 x double> inreg ; ; GFX11-LABEL: dyn_insertelement_v5f64_s_v_v: ; GFX11: ; %bb.0: ; %entry -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 -; GFX11-NEXT: s_mov_b32 s8, s10 -; GFX11-NEXT: s_mov_b32 s9, s11 -; GFX11-NEXT: v_dual_mov_b32 v20, s8 :: v_dual_mov_b32 v21, s9 +; GFX11-NEXT: v_dual_mov_b32 v21, s9 :: v_dual_mov_b32 v20, s8 ; GFX11-NEXT: v_dual_mov_b32 v19, s7 :: v_dual_mov_b32 v18, s6 ; GFX11-NEXT: v_dual_mov_b32 v17, s5 :: v_dual_mov_b32 v16, s4 ; GFX11-NEXT: v_dual_mov_b32 v15, s3 :: v_dual_mov_b32 v14, s2 @@ -8262,12 +8137,19 @@ define amdgpu_ps <5 x double> @dyn_insertelement_v5f64_v_v_s(<5 x double> %vec, ; GPRIDX-NEXT: s_set_gpr_idx_off ; GPRIDX-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: dyn_insertelement_v5f64_v_v_s: -; GFX10PLUS: ; %bb.0: ; %entry -; GFX10PLUS-NEXT: s_lshl_b32 m0, s2, 1 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v0, v10 -; GFX10PLUS-NEXT: v_movreld_b32_e32 v1, v11 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: dyn_insertelement_v5f64_v_v_s: +; GFX10: ; %bb.0: ; %entry +; GFX10-NEXT: s_lshl_b32 m0, s2, 1 +; GFX10-NEXT: v_movreld_b32_e32 v0, v10 +; GFX10-NEXT: v_movreld_b32_e32 v1, v11 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: dyn_insertelement_v5f64_v_v_s: +; GFX11: ; %bb.0: ; %entry +; GFX11-NEXT: s_lshl_b32 m0, s0, 1 +; GFX11-NEXT: v_movreld_b32_e32 v0, v10 +; GFX11-NEXT: v_movreld_b32_e32 v1, v11 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX8-LABEL: dyn_insertelement_v5f64_v_v_s: ; GFX8: ; %bb.0: ; %entry diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll index 1e3cbb574470b8..a888ed8b21f823 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.atomic.dim.a16.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX11 %s ; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX12 %s define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) { @@ -51,18 +51,41 @@ define amdgpu_ps float @atomic_swap_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_swap_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.swap.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_swap_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -126,18 +149,41 @@ define amdgpu_ps float @atomic_add_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_add_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_add_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -201,18 +247,41 @@ define amdgpu_ps float @atomic_sub_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_sub_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.sub.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_sub_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -276,18 +345,41 @@ define amdgpu_ps float @atomic_smin_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_smin_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smin.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_smin_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -352,18 +444,41 @@ define amdgpu_ps float @atomic_umin_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_umin_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umin.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_umin_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -427,18 +542,41 @@ define amdgpu_ps float @atomic_smax_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_smax_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.smax.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_smax_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -502,18 +640,41 @@ define amdgpu_ps float @atomic_umax_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_umax_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.umax.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_umax_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -577,18 +738,41 @@ define amdgpu_ps float @atomic_and_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_and_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.and.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_and_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -652,18 +836,41 @@ define amdgpu_ps float @atomic_or_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) { ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_or_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.or.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_or_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -727,18 +934,41 @@ define amdgpu_ps float @atomic_xor_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_xor_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.xor.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_xor_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -802,18 +1032,41 @@ define amdgpu_ps float @atomic_inc_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_inc_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.inc.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_inc_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -877,18 +1130,41 @@ define amdgpu_ps float @atomic_dec_1d(<8 x i32> inreg %rsrc, i32 %data, i16 %s) ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_dec_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.dec.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_dec_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -956,18 +1232,43 @@ define amdgpu_ps float @atomic_cmpswap_1d(<8 x i32> inreg %rsrc, i32 %cmp, i32 % ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_cmpswap_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.1d), [[BUILD_VECTOR1]](<2 x i32>), $noreg, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_cmpswap_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1035,18 +1336,42 @@ define amdgpu_ps float @atomic_add_2d(<8 x i32> inreg %rsrc, i32 %data, i16 %s, ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_add_2d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_add_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1122,18 +1447,46 @@ define amdgpu_ps float @atomic_add_3d(<8 x i32> inreg %rsrc, i32 %data, i16 %s, ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_add_3d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32) + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3 + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.3d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_add_3d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1213,18 +1566,46 @@ define amdgpu_ps float @atomic_add_cube(<8 x i32> inreg %rsrc, i32 %data, i16 %s ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_add_cube + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32) + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3 + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.cube), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_add_cube ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1295,18 +1676,42 @@ define amdgpu_ps float @atomic_add_1darray(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_add_1darray + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1darray), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_add_1darray ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1382,18 +1787,46 @@ define amdgpu_ps float @atomic_add_2darray(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_add_2darray + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32) + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3 + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darray), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_add_2darray ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1473,18 +1906,46 @@ define amdgpu_ps float @atomic_add_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_add_2dmsaa + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32) + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3 + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2dmsaa), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_add_2dmsaa ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1566,18 +2027,47 @@ define amdgpu_ps float @atomic_add_2darraymsaa(<8 x i32> inreg %rsrc, i32 %data, ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_add_2darraymsaa + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32) + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3 + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr4 + ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.2darraymsaa), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_add_2darraymsaa ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1647,18 +2137,41 @@ define amdgpu_ps float @atomic_add_1d_slc(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_add_1d_slc + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY9]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.add.1d), [[COPY8]](i32), [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 2, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_add_1d_slc ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1728,18 +2241,44 @@ define amdgpu_ps float @atomic_cmpswap_2d(<8 x i32> inreg %rsrc, i32 %cmp, i32 % ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_cmpswap_2d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32) + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3 + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2d), [[BUILD_VECTOR1]](<2 x i32>), $noreg, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_cmpswap_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1821,18 +2360,48 @@ define amdgpu_ps float @atomic_cmpswap_3d(<8 x i32> inreg %rsrc, i32 %cmp, i32 % ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_cmpswap_3d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32) + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3 + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr4 + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.3d), [[BUILD_VECTOR1]](<2 x i32>), $noreg, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_cmpswap_3d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1920,18 +2489,49 @@ define amdgpu_ps float @atomic_cmpswap_2darraymsaa(<8 x i32> inreg %rsrc, i32 %c ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: atomic_cmpswap_2darraymsaa + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32) + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3 + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[COPY11]](i32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr4 + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr5 + ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[COPY13]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(i32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.atomic.cmpswap.2darraymsaa), [[BUILD_VECTOR1]](<2 x i32>), $noreg, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (volatile dereferenceable load store (i32), addrspace 8) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[AMDGPU_INTRIN_IMAGE_LOAD]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: atomic_cmpswap_2darraymsaa ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll index d761f2cd8a97ee..814996a63457c4 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.dim.a16.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX11 %s ; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX12 %s define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) { @@ -61,18 +61,46 @@ define amdgpu_ps <4 x float> @load_1d(<8 x i32> inreg %rsrc, <2 x i16> %coords) ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -157,18 +185,49 @@ define amdgpu_ps <4 x float> @load_2d(<8 x i32> inreg %rsrc, <2 x i16> %coords) ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_2d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -270,18 +329,55 @@ define amdgpu_ps <4 x float> @load_3d(<8 x i32> inreg %rsrc, <2 x i16> %coords_l ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_3d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_3d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 @@ -390,18 +486,55 @@ define amdgpu_ps <4 x float> @load_cube(<8 x i32> inreg %rsrc, <2 x i16> %coords ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_cube + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.cube), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_cube ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 @@ -497,18 +630,49 @@ define amdgpu_ps <4 x float> @load_1darray(<8 x i32> inreg %rsrc, <2 x i16> %coo ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_1darray + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1darray), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_1darray ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -610,18 +774,55 @@ define amdgpu_ps <4 x float> @load_2darray(<8 x i32> inreg %rsrc, <2 x i16> %coo ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_2darray + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darray), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_2darray ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 @@ -730,18 +931,55 @@ define amdgpu_ps <4 x float> @load_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_2dmsaa + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2dmsaa), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_2dmsaa ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 @@ -854,18 +1092,57 @@ define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, <2 x i16> ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_2darraymsaa + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_2darraymsaa ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 @@ -964,18 +1241,49 @@ define amdgpu_ps <4 x float> @load_mip_1d(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_mip_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1d), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_mip_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -1077,18 +1385,55 @@ define amdgpu_ps <4 x float> @load_mip_2d(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_mip_2d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2d), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_mip_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 @@ -1201,18 +1546,57 @@ define amdgpu_ps <4 x float> @load_mip_3d(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_mip_3d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.3d), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_mip_3d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 @@ -1328,18 +1712,57 @@ define amdgpu_ps <4 x float> @load_mip_cube(<8 x i32> inreg %rsrc, <2 x i16> %co ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_mip_cube + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.cube), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_mip_cube ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 @@ -1451,18 +1874,55 @@ define amdgpu_ps <4 x float> @load_mip_1darray(<8 x i32> inreg %rsrc, <2 x i16> ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_mip_1darray + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.1darray), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_mip_1darray ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 @@ -1575,18 +2035,57 @@ define amdgpu_ps <4 x float> @load_mip_2darray(<8 x i32> inreg %rsrc, <2 x i16> ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_mip_2darray + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.mip.2darray), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_mip_2darray ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 @@ -1679,18 +2178,46 @@ define amdgpu_ps void @store_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -1775,18 +2302,49 @@ define amdgpu_ps void @store_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_2d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -1888,18 +2446,55 @@ define amdgpu_ps void @store_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 x ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.3d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_3d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr5 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.3d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_3d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -2008,18 +2603,55 @@ define amdgpu_ps void @store_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, <2 ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.cube), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_cube + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr5 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.cube), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_cube ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -2115,18 +2747,49 @@ define amdgpu_ps void @store_1darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1darray), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_1darray + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1darray), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_1darray ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -2228,18 +2891,55 @@ define amdgpu_ps void @store_2darray(<8 x i32> inreg %rsrc, <4 x float> %vdata, ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2darray), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_2darray + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr5 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2darray), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_2darray ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -2348,18 +3048,55 @@ define amdgpu_ps void @store_2dmsaa(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2dmsaa), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_2dmsaa + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr5 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2dmsaa), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_2dmsaa ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -2472,18 +3209,57 @@ define amdgpu_ps void @store_2darraymsaa(<8 x i32> inreg %rsrc, <4 x float> %vda ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2darraymsaa), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_2darraymsaa + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr5 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX11-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.2darraymsaa), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_2darraymsaa ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -2582,18 +3358,49 @@ define amdgpu_ps void @store_mip_1d(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_mip_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_mip_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -2695,18 +3502,55 @@ define amdgpu_ps void @store_mip_2d(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_mip_2d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr5 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_mip_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -2819,18 +3663,57 @@ define amdgpu_ps void @store_mip_3d(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.3d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_mip_3d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr5 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX11-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.3d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_mip_3d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -2946,18 +3829,57 @@ define amdgpu_ps void @store_mip_cube(<8 x i32> inreg %rsrc, <4 x float> %vdata, ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.cube), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_mip_cube + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr5 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX11-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.cube), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_mip_cube ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -3069,18 +3991,55 @@ define amdgpu_ps void @store_mip_1darray(<8 x i32> inreg %rsrc, <4 x float> %vda ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1darray), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_mip_1darray + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr5 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.1darray), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_mip_1darray ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -3193,18 +4152,57 @@ define amdgpu_ps void @store_mip_2darray(<8 x i32> inreg %rsrc, <4 x float> %vda ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2darray), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_mip_2darray + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr5 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY13]](<2 x i16>) + ; GFX11-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.mip.2darray), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR3]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_mip_2darray ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -3297,18 +4295,46 @@ define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, <2 x i16> %co ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: getresinfo_1d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1d), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: getresinfo_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -3387,18 +4413,46 @@ define amdgpu_ps <4 x float> @getresinfo_2d(<8 x i32> inreg %rsrc, <2 x i16> %co ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: getresinfo_2d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2d), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: getresinfo_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -3477,18 +4531,46 @@ define amdgpu_ps <4 x float> @getresinfo_3d(<8 x i32> inreg %rsrc, <2 x i16> %co ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: getresinfo_3d + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.3d), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: getresinfo_3d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -3567,18 +4649,46 @@ define amdgpu_ps <4 x float> @getresinfo_cube(<8 x i32> inreg %rsrc, <2 x i16> % ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: getresinfo_cube + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.cube), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: getresinfo_cube ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -3657,18 +4767,46 @@ define amdgpu_ps <4 x float> @getresinfo_1darray(<8 x i32> inreg %rsrc, <2 x i16 ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: getresinfo_1darray + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.1darray), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: getresinfo_1darray ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -3747,18 +4885,46 @@ define amdgpu_ps <4 x float> @getresinfo_2darray(<8 x i32> inreg %rsrc, <2 x i16 ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: getresinfo_2darray + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2darray), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: getresinfo_2darray ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -3837,18 +5003,46 @@ define amdgpu_ps <4 x float> @getresinfo_2dmsaa(<8 x i32> inreg %rsrc, <2 x i16> ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: getresinfo_2dmsaa + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2dmsaa), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: getresinfo_2dmsaa ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -3927,18 +5121,46 @@ define amdgpu_ps <4 x float> @getresinfo_2darraymsaa(<8 x i32> inreg %rsrc, <2 x ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: getresinfo_2darraymsaa + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.getresinfo.2darraymsaa), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: getresinfo_2darraymsaa ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -4009,18 +5231,42 @@ define amdgpu_ps float @load_1d_V1(<8 x i32> inreg %rsrc, <2 x i16> %coords) { ; GFX10NSA-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: load_1d_V1 + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(f32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 8, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (f32), addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: load_1d_V1 ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -4091,18 +5337,44 @@ define amdgpu_ps <2 x float> @load_1d_V2(<8 x i32> inreg %rsrc, <2 x i16> %coord ; GFX10NSA-NEXT: $vgpr1 = COPY [[UV1]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 ; + ; GFX11-LABEL: name: load_1d_V2 + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 9, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable load (<2 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; ; GFX12-LABEL: name: load_1d_V2 ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -4171,18 +5443,42 @@ define amdgpu_ps void @store_1d_V1(<8 x i32> inreg %rsrc, float %vdata, <2 x i16 ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[COPY8]](f32), 2, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (f32), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_1d_V1 + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[COPY8]](f32), 2, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (f32), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_1d_V1 ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 @@ -4253,18 +5549,44 @@ define amdgpu_ps void @store_1d_V2(<8 x i32> inreg %rsrc, <2 x float> %vdata, <2 ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<2 x f32>), 12, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<2 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_1d_V2 + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32) + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr2 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY10]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<2 x f32>), 12, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 1 :: (dereferenceable store (<2 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_1d_V2 ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -4341,18 +5663,46 @@ define amdgpu_ps <4 x float> @load_1d_glc(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_1d_glc + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 1, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_1d_glc ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -4431,18 +5781,46 @@ define amdgpu_ps <4 x float> @load_1d_slc(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_1d_slc + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 2, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_1d_slc ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -4521,18 +5899,46 @@ define amdgpu_ps <4 x float> @load_1d_glc_slc(<8 x i32> inreg %rsrc, <2 x i16> % ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_1d_glc_slc + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 3, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_1d_glc_slc ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 @@ -4611,18 +6017,46 @@ define amdgpu_ps void @store_1d_glc(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 1, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_1d_glc + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 1, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_1d_glc ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -4701,18 +6135,46 @@ define amdgpu_ps void @store_1d_slc(<8 x i32> inreg %rsrc, <4 x float> %vdata, < ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 2, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_1d_slc + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 2, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_1d_slc ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -4791,18 +6253,46 @@ define amdgpu_ps void @store_1d_glc_slc(<8 x i32> inreg %rsrc, <4 x float> %vdat ; GFX10NSA-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 3, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) ; GFX10NSA-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: store_1d_glc_slc + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(f32) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(f32) = COPY $vgpr3 + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x f32>) = G_BUILD_VECTOR [[COPY8]](f32), [[COPY9]](f32), [[COPY10]](f32), [[COPY11]](f32) + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr4 + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY12]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE intrinsic(@llvm.amdgcn.image.store.1d), [[BUILD_VECTOR1]](<4 x f32>), 15, [[BUILD_VECTOR2]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 0, 3, 1 :: (dereferenceable store (<4 x f32>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: store_1d_glc_slc ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -4847,9 +6337,20 @@ define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x floa ; GFX10NSA-NEXT: $vgpr3 = COPY [[DEF]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: getresinfo_dmask0 + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(f32) = G_IMPLICIT_DEF + ; GFX11-NEXT: $vgpr0 = COPY [[DEF]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[DEF]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[DEF]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[DEF]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: getresinfo_dmask0 ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(f32) = G_IMPLICIT_DEF ; GFX12-NEXT: $vgpr0 = COPY [[DEF]](f32) @@ -4932,18 +6433,52 @@ define amdgpu_ps <4 x float> @load_1d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: $vgpr3 = COPY [[BITCAST4]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_1d_tfe + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[DEF1:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[DEF1]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.1d), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR]](<8 x i32>), 1, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x i32>) + ; GFX11-NEXT: G_STORE [[UV4]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) + ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) + ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST1]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[BITCAST2]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[BITCAST3]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[BITCAST4]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_1d_tfe ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF @@ -5049,18 +6584,55 @@ define amdgpu_ps <4 x float> @load_2d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: $vgpr3 = COPY [[BITCAST5]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_2d_tfe + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2d), 15, [[BUILD_VECTOR1]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 1, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x i32>) + ; GFX11-NEXT: G_STORE [[UV4]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) + ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) + ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST2]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[BITCAST3]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[BITCAST4]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[BITCAST5]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_2d_tfe ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF @@ -5183,18 +6755,61 @@ define amdgpu_ps <4 x float> @load_3d_tfe(<8 x i32> inreg %rsrc, <2 x i16> %coor ; GFX10NSA-NEXT: $vgpr3 = COPY [[BITCAST6]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_3d_tfe + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[DEF1:%[0-9]+]]:_(i16) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[DEF1]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 1, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x i32>) + ; GFX11-NEXT: G_STORE [[UV4]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) + ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) + ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) + ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST3]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[BITCAST4]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[BITCAST5]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[BITCAST6]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_3d_tfe ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 @@ -5328,18 +6943,63 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, <2 x i ; GFX10NSA-NEXT: $vgpr3 = COPY [[BITCAST7]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: load_2darraymsaa_tfe + ; GFX11: bb.1.main_body: + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 + ; GFX11-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF + ; GFX11-NEXT: [[C:%[0-9]+]]:_(i32) = G_CONSTANT i32 0 + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[LSHR:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR]](i32) + ; GFX11-NEXT: [[BITCAST1:%[0-9]+]]:_(i32) = G_BITCAST [[COPY8]](<2 x i16>) + ; GFX11-NEXT: [[C1:%[0-9]+]]:_(i32) = G_CONSTANT i32 16 + ; GFX11-NEXT: [[LSHR1:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST1]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC1:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR1]](i32) + ; GFX11-NEXT: [[BITCAST2:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR2:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST2]], [[C]](i32) + ; GFX11-NEXT: [[TRUNC2:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR2]](i32) + ; GFX11-NEXT: [[BITCAST3:%[0-9]+]]:_(i32) = G_BITCAST [[COPY9]](<2 x i16>) + ; GFX11-NEXT: [[LSHR3:%[0-9]+]]:_(i32) = G_LSHR [[BITCAST3]], [[C1]](i32) + ; GFX11-NEXT: [[TRUNC3:%[0-9]+]]:_(i16) = G_TRUNC [[LSHR3]](i32) + ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC]](i16), [[TRUNC1]](i16) + ; GFX11-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<2 x i16>) = G_BUILD_VECTOR [[TRUNC2]](i16), [[TRUNC3]](i16) + ; GFX11-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[BUILD_VECTOR1]](<2 x i16>), [[BUILD_VECTOR2]](<2 x i16>), $noreg, $noreg, [[BUILD_VECTOR]](<8 x i32>), 1, 0, 1 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x i32>) + ; GFX11-NEXT: G_STORE [[UV4]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) + ; GFX11-NEXT: [[BITCAST4:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX11-NEXT: [[BITCAST5:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) + ; GFX11-NEXT: [[BITCAST6:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) + ; GFX11-NEXT: [[BITCAST7:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) + ; GFX11-NEXT: $vgpr0 = COPY [[BITCAST4]](f32) + ; GFX11-NEXT: $vgpr1 = COPY [[BITCAST5]](f32) + ; GFX11-NEXT: $vgpr2 = COPY [[BITCAST6]](f32) + ; GFX11-NEXT: $vgpr3 = COPY [[BITCAST7]](f32) + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: load_2darraymsaa_tfe ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(<2 x i16>) = COPY $vgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll index 2d4b241a673c2c..2102edd231b75e 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.2darraymsaa.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s -; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX11PLUS %s +; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX11PLUS %s define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %slice, i32 %fragid) { ; GFX6-LABEL: name: load_2darraymsaa @@ -55,6 +55,31 @@ define amdgpu_ps <4 x float> @load_2darraymsaa(<8 x i32> inreg %rsrc, i32 %s, i3 ; GFX10NSA-NEXT: $vgpr2 = COPY [[UV2]](f32) ; GFX10NSA-NEXT: $vgpr3 = COPY [[UV3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; + ; GFX11PLUS-LABEL: name: load_2darraymsaa + ; GFX11PLUS: bb.1 (%ir-block.0): + ; GFX11PLUS-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11PLUS-NEXT: {{ $}} + ; GFX11PLUS-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11PLUS-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11PLUS-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11PLUS-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11PLUS-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11PLUS-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11PLUS-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11PLUS-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11PLUS-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11PLUS-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11PLUS-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11PLUS-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr3 + ; GFX11PLUS-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<4 x f32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11PLUS-NEXT: [[UV:%[0-9]+]]:_(f32), [[UV1:%[0-9]+]]:_(f32), [[UV2:%[0-9]+]]:_(f32), [[UV3:%[0-9]+]]:_(f32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<4 x f32>) + ; GFX11PLUS-NEXT: $vgpr0 = COPY [[UV]](f32) + ; GFX11PLUS-NEXT: $vgpr1 = COPY [[UV1]](f32) + ; GFX11PLUS-NEXT: $vgpr2 = COPY [[UV2]](f32) + ; GFX11PLUS-NEXT: $vgpr3 = COPY [[UV3]](f32) + ; GFX11PLUS-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 %v = call <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 0, i32 0) ret <4 x float> %v } @@ -126,6 +151,39 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_tfe(<8 x i32> inreg %rsrc, ptr ad ; GFX10NSA-NEXT: $vgpr2 = COPY [[BITCAST2]](f32) ; GFX10NSA-NEXT: $vgpr3 = COPY [[BITCAST3]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; + ; GFX11PLUS-LABEL: name: load_2darraymsaa_tfe + ; GFX11PLUS: bb.1 (%ir-block.0): + ; GFX11PLUS-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11PLUS-NEXT: {{ $}} + ; GFX11PLUS-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11PLUS-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11PLUS-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11PLUS-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11PLUS-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11PLUS-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11PLUS-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11PLUS-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11PLUS-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11PLUS-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11PLUS-NEXT: [[MV:%[0-9]+]]:_(p1) = G_MERGE_VALUES [[COPY8]](i32), [[COPY9]](i32) + ; GFX11PLUS-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11PLUS-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11PLUS-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11PLUS-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr3 + ; GFX11PLUS-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<5 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.2darraymsaa), 15, [[COPY10]](i32), [[COPY11]](i32), [[COPY12]](i32), [[COPY13]](i32), [[BUILD_VECTOR]](<8 x i32>), 1, 0, 0 :: (dereferenceable load (<4 x f32>), addrspace 8) + ; GFX11PLUS-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32), [[UV2:%[0-9]+]]:_(i32), [[UV3:%[0-9]+]]:_(i32), [[UV4:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<5 x i32>) + ; GFX11PLUS-NEXT: G_STORE [[UV4]](i32), [[MV]](p1) :: (store (i32) into %ir.out, addrspace 1) + ; GFX11PLUS-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX11PLUS-NEXT: [[BITCAST1:%[0-9]+]]:_(f32) = G_BITCAST [[UV1]](i32) + ; GFX11PLUS-NEXT: [[BITCAST2:%[0-9]+]]:_(f32) = G_BITCAST [[UV2]](i32) + ; GFX11PLUS-NEXT: [[BITCAST3:%[0-9]+]]:_(f32) = G_BITCAST [[UV3]](i32) + ; GFX11PLUS-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11PLUS-NEXT: $vgpr1 = COPY [[BITCAST1]](f32) + ; GFX11PLUS-NEXT: $vgpr2 = COPY [[BITCAST2]](f32) + ; GFX11PLUS-NEXT: $vgpr3 = COPY [[BITCAST3]](f32) + ; GFX11PLUS-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 1, i32 0) %v.vec = extractvalue { <4 x float>, i32 } %v, 0 %v.err = extractvalue { <4 x float>, i32 } %v, 1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll index 4c325e25c56af8..c662b674bfb824 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.load.3d.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX6 %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s -; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10NSA %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX11PLUS %s +; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX11PLUS %s define amdgpu_ps float @image_load_3d_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, i32 %r) { ; GFX6-LABEL: name: image_load_3d_f32 @@ -45,6 +45,26 @@ define amdgpu_ps float @image_load_3d_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ; GFX10NSA-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(f32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable load (f32), addrspace 8) ; GFX10NSA-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX11PLUS-LABEL: name: image_load_3d_f32 + ; GFX11PLUS: bb.1 (%ir-block.0): + ; GFX11PLUS-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 + ; GFX11PLUS-NEXT: {{ $}} + ; GFX11PLUS-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11PLUS-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11PLUS-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11PLUS-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11PLUS-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11PLUS-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11PLUS-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11PLUS-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11PLUS-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11PLUS-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11PLUS-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11PLUS-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(f32) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable load (f32), addrspace 8) + ; GFX11PLUS-NEXT: $vgpr0 = COPY [[AMDGPU_INTRIN_IMAGE_LOAD]](f32) + ; GFX11PLUS-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 %tex = call float @llvm.amdgcn.image.load.3d.f32.i32(i32 1, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 0, i32 0) ret float %tex } @@ -100,6 +120,31 @@ define amdgpu_ps float @image_load_3d_tfe_f32(<8 x i32> inreg %rsrc, i32 %s, i32 ; GFX10NSA-NEXT: G_STORE [[COPY11]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) ; GFX10NSA-NEXT: $vgpr0 = COPY [[BITCAST]](f32) ; GFX10NSA-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX11PLUS-LABEL: name: image_load_3d_tfe_f32 + ; GFX11PLUS: bb.1 (%ir-block.0): + ; GFX11PLUS-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 + ; GFX11PLUS-NEXT: {{ $}} + ; GFX11PLUS-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11PLUS-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11PLUS-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11PLUS-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11PLUS-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11PLUS-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11PLUS-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11PLUS-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11PLUS-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11PLUS-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11PLUS-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11PLUS-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11PLUS-NEXT: [[DEF:%[0-9]+]]:_(p1) = G_IMPLICIT_DEF + ; GFX11PLUS-NEXT: [[AMDGPU_INTRIN_IMAGE_LOAD:%[0-9]+]]:_(<2 x i32>) = G_AMDGPU_INTRIN_IMAGE_LOAD intrinsic(@llvm.amdgcn.image.load.3d), 1, [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[BUILD_VECTOR]](<8 x i32>), 1, 0, 0 :: (dereferenceable load (f32), addrspace 8) + ; GFX11PLUS-NEXT: [[UV:%[0-9]+]]:_(i32), [[UV1:%[0-9]+]]:_(i32) = G_UNMERGE_VALUES [[AMDGPU_INTRIN_IMAGE_LOAD]](<2 x i32>) + ; GFX11PLUS-NEXT: [[BITCAST:%[0-9]+]]:_(f32) = G_BITCAST [[UV]](i32) + ; GFX11PLUS-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY [[UV1]](i32) + ; GFX11PLUS-NEXT: G_STORE [[COPY11]](i32), [[DEF]](p1) :: (store (i32) into `ptr addrspace(1) poison`, addrspace 1) + ; GFX11PLUS-NEXT: $vgpr0 = COPY [[BITCAST]](f32) + ; GFX11PLUS-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 %val = call { float, i32 } @llvm.amdgcn.image.load.3d.sl_f32i32s.i32(i32 1, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 1, i32 0) %tex = extractvalue { float, i32 } %val, 0 %tfe = extractvalue { float, i32 } %val, 1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll index 61006f8c1eab62..59319d6ea58ba4 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.a16.ll @@ -67,21 +67,21 @@ define amdgpu_ps <4 x float> @sample_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg % ; ; GFX11-LABEL: name: sample_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -98,21 +98,21 @@ define amdgpu_ps <4 x float> @sample_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg % ; ; GFX12-LABEL: name: sample_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -196,21 +196,21 @@ define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg % ; ; GFX11-LABEL: name: sample_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -229,21 +229,21 @@ define amdgpu_ps <4 x float> @sample_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg % ; ; GFX12-LABEL: name: sample_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -338,21 +338,21 @@ define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg % ; ; GFX11-LABEL: name: sample_3d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -376,21 +376,21 @@ define amdgpu_ps <4 x float> @sample_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg % ; ; GFX12-LABEL: name: sample_3d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -490,21 +490,21 @@ define amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-LABEL: name: sample_cube ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -528,21 +528,21 @@ define amdgpu_ps <4 x float> @sample_cube(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX12-LABEL: name: sample_cube ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -633,21 +633,21 @@ define amdgpu_ps <4 x float> @sample_1darray(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_1darray ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -666,21 +666,21 @@ define amdgpu_ps <4 x float> @sample_1darray(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_1darray ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -775,21 +775,21 @@ define amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_2darray ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -813,21 +813,21 @@ define amdgpu_ps <4 x float> @sample_2darray(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_2darray ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -921,21 +921,21 @@ define amdgpu_ps <4 x float> @sample_c_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-LABEL: name: sample_c_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -954,21 +954,21 @@ define amdgpu_ps <4 x float> @sample_c_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX12-LABEL: name: sample_c_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1059,21 +1059,21 @@ define amdgpu_ps <4 x float> @sample_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-LABEL: name: sample_c_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1094,21 +1094,21 @@ define amdgpu_ps <4 x float> @sample_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX12-LABEL: name: sample_c_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1196,21 +1196,21 @@ define amdgpu_ps <4 x float> @sample_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX11-LABEL: name: sample_cl_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -1229,21 +1229,21 @@ define amdgpu_ps <4 x float> @sample_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX12-LABEL: name: sample_cl_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -1338,21 +1338,21 @@ define amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX11-LABEL: name: sample_cl_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -1376,21 +1376,21 @@ define amdgpu_ps <4 x float> @sample_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX12-LABEL: name: sample_cl_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -1486,21 +1486,21 @@ define amdgpu_ps <4 x float> @sample_c_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_c_cl_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1521,21 +1521,21 @@ define amdgpu_ps <4 x float> @sample_c_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_c_cl_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1636,21 +1636,21 @@ define amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_c_cl_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1676,21 +1676,21 @@ define amdgpu_ps <4 x float> @sample_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_c_cl_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1788,21 +1788,21 @@ define amdgpu_ps <4 x float> @sample_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-LABEL: name: sample_b_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -1823,21 +1823,21 @@ define amdgpu_ps <4 x float> @sample_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX12-LABEL: name: sample_b_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -1934,21 +1934,21 @@ define amdgpu_ps <4 x float> @sample_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-LABEL: name: sample_b_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -1972,21 +1972,21 @@ define amdgpu_ps <4 x float> @sample_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX12-LABEL: name: sample_b_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -2086,21 +2086,21 @@ define amdgpu_ps <4 x float> @sample_c_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX11-LABEL: name: sample_c_b_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -2123,21 +2123,21 @@ define amdgpu_ps <4 x float> @sample_c_b_1d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX12-LABEL: name: sample_c_b_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -2240,21 +2240,21 @@ define amdgpu_ps <4 x float> @sample_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX11-LABEL: name: sample_c_b_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -2280,21 +2280,21 @@ define amdgpu_ps <4 x float> @sample_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX12-LABEL: name: sample_c_b_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -2396,21 +2396,21 @@ define amdgpu_ps <4 x float> @sample_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_b_cl_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -2434,21 +2434,21 @@ define amdgpu_ps <4 x float> @sample_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_b_cl_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -2554,21 +2554,21 @@ define amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_b_cl_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -2596,21 +2596,21 @@ define amdgpu_ps <4 x float> @sample_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_b_cl_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -2718,21 +2718,21 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX11-LABEL: name: sample_c_b_cl_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -2758,21 +2758,21 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX12-LABEL: name: sample_c_b_cl_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -2884,21 +2884,21 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX11-LABEL: name: sample_c_b_cl_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -2928,21 +2928,21 @@ define amdgpu_ps <4 x float> @sample_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX12-LABEL: name: sample_c_b_cl_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -3050,21 +3050,21 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-LABEL: name: sample_d_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -3089,21 +3089,21 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX12-LABEL: name: sample_d_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -3216,21 +3216,21 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-LABEL: name: sample_d_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -3263,21 +3263,21 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX12-LABEL: name: sample_d_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -3419,21 +3419,21 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-LABEL: name: sample_d_3d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -3480,21 +3480,21 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX12-LABEL: name: sample_d_3d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -3623,21 +3623,21 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX11-LABEL: name: sample_c_d_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -3664,21 +3664,21 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX12-LABEL: name: sample_c_d_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -3797,21 +3797,21 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX11-LABEL: name: sample_c_d_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -3846,21 +3846,21 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX12-LABEL: name: sample_c_d_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -3977,21 +3977,21 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_d_cl_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -4019,21 +4019,21 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_d_cl_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -4157,21 +4157,21 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_d_cl_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -4209,21 +4209,21 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_d_cl_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -4347,21 +4347,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX11-LABEL: name: sample_c_d_cl_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -4391,21 +4391,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX12-LABEL: name: sample_c_d_cl_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -4535,21 +4535,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX11-LABEL: name: sample_c_d_cl_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -4589,21 +4589,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX12-LABEL: name: sample_c_d_cl_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -4722,21 +4722,21 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX11-LABEL: name: sample_cd_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -4761,21 +4761,21 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX12-LABEL: name: sample_cd_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -4888,21 +4888,21 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX11-LABEL: name: sample_cd_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -4935,21 +4935,21 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX12-LABEL: name: sample_cd_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -5064,21 +5064,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_c_cd_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -5105,21 +5105,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_c_cd_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -5238,21 +5238,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_c_cd_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -5287,21 +5287,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_c_cd_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -5418,21 +5418,21 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i ; ; GFX11-LABEL: name: sample_cd_cl_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -5460,21 +5460,21 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i ; ; GFX12-LABEL: name: sample_cd_cl_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -5598,21 +5598,21 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i ; ; GFX11-LABEL: name: sample_cd_cl_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -5650,21 +5650,21 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i ; ; GFX12-LABEL: name: sample_cd_cl_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -5788,21 +5788,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX11-LABEL: name: sample_c_cd_cl_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -5832,21 +5832,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX12-LABEL: name: sample_c_cd_cl_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -5976,21 +5976,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX11-LABEL: name: sample_c_cd_cl_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -6030,21 +6030,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX12-LABEL: name: sample_c_cd_cl_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -6152,21 +6152,21 @@ define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-LABEL: name: sample_l_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -6185,21 +6185,21 @@ define amdgpu_ps <4 x float> @sample_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX12-LABEL: name: sample_l_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -6294,21 +6294,21 @@ define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-LABEL: name: sample_l_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -6332,21 +6332,21 @@ define amdgpu_ps <4 x float> @sample_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX12-LABEL: name: sample_l_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -6442,21 +6442,21 @@ define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX11-LABEL: name: sample_c_l_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -6477,21 +6477,21 @@ define amdgpu_ps <4 x float> @sample_c_l_1d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX12-LABEL: name: sample_c_l_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -6592,21 +6592,21 @@ define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX11-LABEL: name: sample_c_l_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -6632,21 +6632,21 @@ define amdgpu_ps <4 x float> @sample_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX12-LABEL: name: sample_c_l_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -6737,21 +6737,21 @@ define amdgpu_ps <4 x float> @sample_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX11-LABEL: name: sample_lz_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -6768,21 +6768,21 @@ define amdgpu_ps <4 x float> @sample_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX12-LABEL: name: sample_lz_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -6866,21 +6866,21 @@ define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX11-LABEL: name: sample_lz_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -6899,21 +6899,21 @@ define amdgpu_ps <4 x float> @sample_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX12-LABEL: name: sample_lz_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -7002,21 +7002,21 @@ define amdgpu_ps <4 x float> @sample_c_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_c_lz_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -7035,21 +7035,21 @@ define amdgpu_ps <4 x float> @sample_c_lz_1d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_c_lz_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -7140,21 +7140,21 @@ define amdgpu_ps <4 x float> @sample_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_c_lz_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -7175,21 +7175,21 @@ define amdgpu_ps <4 x float> @sample_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_c_lz_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -7307,21 +7307,21 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX11-LABEL: name: sample_c_d_o_2darray_V1 ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -7360,21 +7360,21 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX12-LABEL: name: sample_c_d_o_2darray_V1 ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -7514,21 +7514,21 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 ; ; GFX11-LABEL: name: sample_c_d_o_2darray_V2 ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -7569,21 +7569,21 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 ; ; GFX12-LABEL: name: sample_c_d_o_2darray_V2 ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.d.ll index 97d1fd8baee557..c6a1e79dc6be62 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.d.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.d.ll @@ -51,21 +51,21 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-LABEL: name: sample_d_3d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -92,21 +92,21 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX12-LABEL: name: sample_d_3d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -186,21 +186,21 @@ define amdgpu_ps <4 x float> @sample_c_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX11-LABEL: name: sample_c_d_3d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -229,21 +229,21 @@ define amdgpu_ps <4 x float> @sample_c_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX12-LABEL: name: sample_c_d_3d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -327,21 +327,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_3d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX11-LABEL: name: sample_c_d_cl_3d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -372,21 +372,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_3d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX12-LABEL: name: sample_c_d_cl_3d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -473,21 +473,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_o_3d(<8 x i32> inreg %rsrc, <4 x i32 ; ; GFX11-LABEL: name: sample_c_d_cl_o_3d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -520,21 +520,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_o_3d(<8 x i32> inreg %rsrc, <4 x i32 ; ; GFX12-LABEL: name: sample_c_d_cl_o_3d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll index 4934f93ac18df6..d0fff80390fd27 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.a16.ll @@ -42,21 +42,21 @@ define amdgpu_ps <4 x float> @sample_d_1d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3 ; ; GFX11-LABEL: name: sample_d_1d_g16_a16 ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -81,21 +81,21 @@ define amdgpu_ps <4 x float> @sample_d_1d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3 ; ; GFX12-LABEL: name: sample_d_1d_g16_a16 ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -166,21 +166,21 @@ define amdgpu_ps <4 x float> @sample_d_2d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3 ; ; GFX11-LABEL: name: sample_d_2d_g16_a16 ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -213,21 +213,21 @@ define amdgpu_ps <4 x float> @sample_d_2d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3 ; ; GFX12-LABEL: name: sample_d_2d_g16_a16 ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -317,21 +317,21 @@ define amdgpu_ps <4 x float> @sample_d_3d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3 ; ; GFX11-LABEL: name: sample_d_3d_g16_a16 ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -378,21 +378,21 @@ define amdgpu_ps <4 x float> @sample_d_3d_g16_a16(<8 x i32> inreg %rsrc, <4 x i3 ; ; GFX12-LABEL: name: sample_d_3d_g16_a16 ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll index 2ab7e0d348f416..0f2009f7236776 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.sample.g16.ll @@ -41,21 +41,21 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-LABEL: name: sample_d_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -78,21 +78,21 @@ define amdgpu_ps <4 x float> @sample_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX12-LABEL: name: sample_d_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -160,21 +160,21 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-LABEL: name: sample_d_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -204,21 +204,21 @@ define amdgpu_ps <4 x float> @sample_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX12-LABEL: name: sample_d_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -303,21 +303,21 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-LABEL: name: sample_d_3d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -359,21 +359,21 @@ define amdgpu_ps <4 x float> @sample_d_3d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX12-LABEL: name: sample_d_3d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -457,21 +457,21 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX11-LABEL: name: sample_c_d_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -496,21 +496,21 @@ define amdgpu_ps <4 x float> @sample_c_d_1d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX12-LABEL: name: sample_c_d_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -582,21 +582,21 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX11-LABEL: name: sample_c_d_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -628,21 +628,21 @@ define amdgpu_ps <4 x float> @sample_c_d_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX12-LABEL: name: sample_c_d_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -717,21 +717,21 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_d_cl_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -756,21 +756,21 @@ define amdgpu_ps <4 x float> @sample_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_d_cl_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -842,21 +842,21 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_d_cl_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -888,21 +888,21 @@ define amdgpu_ps <4 x float> @sample_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_d_cl_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -979,21 +979,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX11-LABEL: name: sample_c_d_cl_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1020,21 +1020,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX12-LABEL: name: sample_c_d_cl_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1112,21 +1112,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX11-LABEL: name: sample_c_d_cl_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1161,21 +1161,21 @@ define amdgpu_ps <4 x float> @sample_c_d_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX12-LABEL: name: sample_c_d_cl_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1250,21 +1250,21 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX11-LABEL: name: sample_cd_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -1287,21 +1287,21 @@ define amdgpu_ps <4 x float> @sample_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX12-LABEL: name: sample_cd_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -1369,21 +1369,21 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX11-LABEL: name: sample_cd_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -1413,21 +1413,21 @@ define amdgpu_ps <4 x float> @sample_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX12-LABEL: name: sample_cd_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -1499,21 +1499,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_c_cd_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1538,21 +1538,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_1d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_c_cd_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1624,21 +1624,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-LABEL: name: sample_c_cd_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1670,21 +1670,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX12-LABEL: name: sample_c_cd_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -1759,21 +1759,21 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i ; ; GFX11-LABEL: name: sample_cd_cl_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -1798,21 +1798,21 @@ define amdgpu_ps <4 x float> @sample_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> i ; ; GFX12-LABEL: name: sample_cd_cl_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -1884,21 +1884,21 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i ; ; GFX11-LABEL: name: sample_cd_cl_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -1930,21 +1930,21 @@ define amdgpu_ps <4 x float> @sample_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i ; ; GFX12-LABEL: name: sample_cd_cl_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY12]](i32) @@ -2021,21 +2021,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX11-LABEL: name: sample_c_cd_cl_1d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -2062,21 +2062,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_1d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX12-LABEL: name: sample_c_cd_cl_1d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -2154,21 +2154,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX11-LABEL: name: sample_c_cd_cl_2d ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -2203,21 +2203,21 @@ define amdgpu_ps <4 x float> @sample_c_cd_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX12-LABEL: name: sample_c_cd_cl_2d ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(f32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -2300,21 +2300,21 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX11-LABEL: name: sample_c_d_o_2darray_V1 ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -2347,21 +2347,21 @@ define amdgpu_ps float @sample_c_d_o_2darray_V1(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX12-LABEL: name: sample_c_d_o_2darray_V1 ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -2444,21 +2444,21 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 ; ; GFX11-LABEL: name: sample_c_d_o_2darray_V2 ; GFX11: bb.1.main_body: - ; GFX11-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX11-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX11-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX11-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 @@ -2493,21 +2493,21 @@ define amdgpu_ps <2 x float> @sample_c_d_o_2darray_V2(<8 x i32> inreg %rsrc, <4 ; ; GFX12-LABEL: name: sample_c_d_o_2darray_V2 ; GFX12: bb.1.main_body: - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $sgpr12, $sgpr13, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $sgpr10, $sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr10 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr11 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr12 - ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr13 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $sgpr10 + ; GFX12-NEXT: [[COPY11:%[0-9]+]]:_(i32) = COPY $sgpr11 ; GFX12-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x i32>) = G_BUILD_VECTOR [[COPY8]](i32), [[COPY9]](i32), [[COPY10]](i32), [[COPY11]](i32) ; GFX12-NEXT: [[COPY12:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY13:%[0-9]+]]:_(f32) = COPY $vgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll index 9657f2ec27268d..c1605da60673ca 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-llvm.amdgcn.image.store.2d.d16.ll @@ -3,7 +3,7 @@ ; RUN: llc -global-isel -mtriple=amdgpu8.10-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX81 %s ; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX10 %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX11 %s ; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -stop-after=legalizer -o - %s | FileCheck -check-prefix=GFX12 %s define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, half %data) { @@ -70,18 +70,59 @@ define amdgpu_ps void @image_store_f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ha ; GFX9-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](f16), 1, [[BUILD_VECTOR1]](<2 x i32>), $noreg, [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (f16), addrspace 8) ; GFX9-NEXT: S_ENDPGM 0 ; + ; GFX10-LABEL: name: image_store_f16 + ; GFX10: bb.1 (%ir-block.0): + ; GFX10-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2 + ; GFX10-NEXT: {{ $}} + ; GFX10-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX10-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX10-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX10-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX10-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX10-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX10-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 + ; GFX10-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX10-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX10-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX10-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX10-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX10-NEXT: [[TRUNC:%[0-9]+]]:_(f16) = G_TRUNC [[COPY10]](i32) + ; GFX10-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[TRUNC]](f16), 1, [[COPY8]](i32), [[COPY9]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (f16), addrspace 8) + ; GFX10-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: image_store_f16 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(i32) = COPY $vgpr2 + ; GFX11-NEXT: [[TRUNC:%[0-9]+]]:_(i16) = G_TRUNC [[COPY10]](i32) + ; GFX11-NEXT: [[BITCAST:%[0-9]+]]:_(f16) = G_BITCAST [[TRUNC]](i16) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[BITCAST]](f16), 1, [[COPY8]](i32), [[COPY9]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (f16), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: image_store_f16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -183,18 +224,37 @@ define amdgpu_ps void @image_store_v2f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ; GFX10-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[COPY10]](<2 x f16>), 3, [[COPY8]](i32), [[COPY9]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (<2 x f16>), addrspace 8) ; GFX10-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: image_store_v2f16 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr2 + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[COPY10]](<2 x f16>), 3, [[COPY8]](i32), [[COPY9]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (<2 x f16>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: image_store_v2f16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -314,18 +374,39 @@ define amdgpu_ps void @image_store_v3f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ; GFX10-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[CONCAT_VECTORS]](<4 x f16>), 7, [[COPY8]](i32), [[COPY9]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (<3 x f16>), align 8, addrspace 8) ; GFX10-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: image_store_v3f16 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr3 + ; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[COPY10]](<2 x f16>), [[COPY11]](<2 x f16>) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[CONCAT_VECTORS]](<4 x f16>), 7, [[COPY8]](i32), [[COPY9]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (<3 x f16>), align 8, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: image_store_v3f16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 @@ -439,18 +520,39 @@ define amdgpu_ps void @image_store_v4f16(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ; GFX10-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[CONCAT_VECTORS]](<4 x f16>), 15, [[COPY8]](i32), [[COPY9]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (<4 x f16>), addrspace 8) ; GFX10-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: image_store_v4f16 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 + ; GFX11-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr2 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:_(<2 x f16>) = COPY $vgpr3 + ; GFX11-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<4 x f16>) = G_CONCAT_VECTORS [[COPY10]](<2 x f16>), [[COPY11]](<2 x f16>) + ; GFX11-NEXT: G_AMDGPU_INTRIN_IMAGE_STORE_D16 intrinsic(@llvm.amdgcn.image.store.2d), [[CONCAT_VECTORS]](<4 x f16>), 15, [[COPY8]](i32), [[COPY9]](i32), [[BUILD_VECTOR]](<8 x i32>), 0, 0, 0 :: (dereferenceable store (<4 x f16>), addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: image_store_v4f16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8, $sgpr9, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr5 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr8 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr9 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:_(i32) = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:_(i32) = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:_(i32) = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:_(i32) = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:_(i32) = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:_(i32) = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:_(i32) = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:_(i32) = COPY $sgpr7 ; GFX12-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32), [[COPY4]](i32), [[COPY5]](i32), [[COPY6]](i32), [[COPY7]](i32) ; GFX12-NEXT: [[COPY8:%[0-9]+]]:_(i32) = COPY $vgpr0 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:_(i32) = COPY $vgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll index dd5bcfdf47bba7..a906a3104cb420 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.a16.ll @@ -41,14 +41,6 @@ define amdgpu_ps float @atomic_swap_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; ; GFX11-TRUE16-LABEL: atomic_swap_i32_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -56,29 +48,14 @@ define amdgpu_ps float @atomic_swap_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX11-FAKE16-LABEL: atomic_swap_i32_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_swap_i32_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -86,15 +63,8 @@ define amdgpu_ps float @atomic_swap_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX12-FAKE16-LABEL: atomic_swap_i32_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -139,14 +109,6 @@ define amdgpu_ps float @atomic_add_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; ; GFX11-TRUE16-LABEL: atomic_add_i32_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -154,29 +116,14 @@ define amdgpu_ps float @atomic_add_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX11-FAKE16-LABEL: atomic_add_i32_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_add_i32_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -184,15 +131,8 @@ define amdgpu_ps float @atomic_add_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX12-FAKE16-LABEL: atomic_add_i32_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -237,14 +177,6 @@ define amdgpu_ps float @atomic_sub_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; ; GFX11-TRUE16-LABEL: atomic_sub_i32_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_sub v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -252,29 +184,14 @@ define amdgpu_ps float @atomic_sub_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX11-FAKE16-LABEL: atomic_sub_i32_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_sub v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_sub_i32_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -282,15 +199,8 @@ define amdgpu_ps float @atomic_sub_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX12-FAKE16-LABEL: atomic_sub_i32_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -335,14 +245,6 @@ define amdgpu_ps float @atomic_smin_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; ; GFX11-TRUE16-LABEL: atomic_smin_i32_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_smin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -350,29 +252,14 @@ define amdgpu_ps float @atomic_smin_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX11-FAKE16-LABEL: atomic_smin_i32_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_smin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_smin_i32_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -380,15 +267,8 @@ define amdgpu_ps float @atomic_smin_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX12-FAKE16-LABEL: atomic_smin_i32_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -433,14 +313,6 @@ define amdgpu_ps float @atomic_umin_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; ; GFX11-TRUE16-LABEL: atomic_umin_i32_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_umin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -448,29 +320,14 @@ define amdgpu_ps float @atomic_umin_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX11-FAKE16-LABEL: atomic_umin_i32_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_umin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_umin_i32_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_min_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -478,15 +335,8 @@ define amdgpu_ps float @atomic_umin_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX12-FAKE16-LABEL: atomic_umin_i32_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_min_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -531,14 +381,6 @@ define amdgpu_ps float @atomic_smax_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; ; GFX11-TRUE16-LABEL: atomic_smax_i32_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_smax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -546,29 +388,14 @@ define amdgpu_ps float @atomic_smax_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX11-FAKE16-LABEL: atomic_smax_i32_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_smax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_smax_i32_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_max_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -576,15 +403,8 @@ define amdgpu_ps float @atomic_smax_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX12-FAKE16-LABEL: atomic_smax_i32_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_max_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -629,14 +449,6 @@ define amdgpu_ps float @atomic_umax_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; ; GFX11-TRUE16-LABEL: atomic_umax_i32_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_umax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -644,29 +456,14 @@ define amdgpu_ps float @atomic_umax_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX11-FAKE16-LABEL: atomic_umax_i32_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_umax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_umax_i32_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_max_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -674,15 +471,8 @@ define amdgpu_ps float @atomic_umax_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX12-FAKE16-LABEL: atomic_umax_i32_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_max_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -727,14 +517,6 @@ define amdgpu_ps float @atomic_and_i321d(<8 x i32> inreg %rsrc, i32 %data, i16 % ; ; GFX11-TRUE16-LABEL: atomic_and_i321d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -742,29 +524,14 @@ define amdgpu_ps float @atomic_and_i321d(<8 x i32> inreg %rsrc, i32 %data, i16 % ; GFX11-FAKE16-LABEL: atomic_and_i321d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_and_i321d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -772,15 +539,8 @@ define amdgpu_ps float @atomic_and_i321d(<8 x i32> inreg %rsrc, i32 %data, i16 % ; GFX12-FAKE16-LABEL: atomic_and_i321d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -825,14 +585,6 @@ define amdgpu_ps float @atomic_or_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 % ; ; GFX11-TRUE16-LABEL: atomic_or_i32_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -840,29 +592,14 @@ define amdgpu_ps float @atomic_or_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 % ; GFX11-FAKE16-LABEL: atomic_or_i32_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_or_i32_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -870,15 +607,8 @@ define amdgpu_ps float @atomic_or_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 % ; GFX12-FAKE16-LABEL: atomic_or_i32_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -923,14 +653,6 @@ define amdgpu_ps float @atomic_xor_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; ; GFX11-TRUE16-LABEL: atomic_xor_i32_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -938,29 +660,14 @@ define amdgpu_ps float @atomic_xor_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX11-FAKE16-LABEL: atomic_xor_i32_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_xor_i32_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -968,15 +675,8 @@ define amdgpu_ps float @atomic_xor_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX12-FAKE16-LABEL: atomic_xor_i32_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1021,14 +721,6 @@ define amdgpu_ps float @atomic_inc_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; ; GFX11-TRUE16-LABEL: atomic_inc_i32_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_inc v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -1036,29 +728,14 @@ define amdgpu_ps float @atomic_inc_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX11-FAKE16-LABEL: atomic_inc_i32_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_inc v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_inc_i32_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_inc_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -1066,15 +743,8 @@ define amdgpu_ps float @atomic_inc_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX12-FAKE16-LABEL: atomic_inc_i32_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_inc_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1119,14 +789,6 @@ define amdgpu_ps float @atomic_dec_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; ; GFX11-TRUE16-LABEL: atomic_dec_i32_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_dec v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -1134,29 +796,14 @@ define amdgpu_ps float @atomic_dec_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX11-FAKE16-LABEL: atomic_dec_i32_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_dec v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_dec_i32_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_dec_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -1164,15 +811,8 @@ define amdgpu_ps float @atomic_dec_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX12-FAKE16-LABEL: atomic_dec_i32_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_dec_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1217,14 +857,6 @@ define amdgpu_ps float @atomic_cmpswap_i32_1d(<8 x i32> inreg %rsrc, i32 %cmp, i ; ; GFX11-TRUE16-LABEL: atomic_cmpswap_i32_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -1232,29 +864,14 @@ define amdgpu_ps float @atomic_cmpswap_i32_1d(<8 x i32> inreg %rsrc, i32 %cmp, i ; GFX11-FAKE16-LABEL: atomic_cmpswap_i32_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_cmpswap_i32_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -1262,15 +879,8 @@ define amdgpu_ps float @atomic_cmpswap_i32_1d(<8 x i32> inreg %rsrc, i32 %cmp, i ; GFX12-FAKE16-LABEL: atomic_cmpswap_i32_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1316,14 +926,6 @@ define amdgpu_ps float @atomic_add_i32_2d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX11-TRUE16-LABEL: atomic_add_i32_2d: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -1331,15 +933,8 @@ define amdgpu_ps float @atomic_add_i32_2d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX11-FAKE16-LABEL: atomic_add_i32_2d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -1347,14 +942,6 @@ define amdgpu_ps float @atomic_add_i32_2d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX12-TRUE16-LABEL: atomic_add_i32_2d: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -1362,15 +949,8 @@ define amdgpu_ps float @atomic_add_i32_2d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX12-FAKE16-LABEL: atomic_add_i32_2d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1420,14 +1000,6 @@ define amdgpu_ps float @atomic_add_i32_3d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX11-TRUE16-LABEL: atomic_add_i32_3d: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -1436,16 +1008,9 @@ define amdgpu_ps float @atomic_add_i32_3d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v3 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -1453,14 +1018,6 @@ define amdgpu_ps float @atomic_add_i32_3d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX12-TRUE16-LABEL: atomic_add_i32_3d: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -1469,16 +1026,9 @@ define amdgpu_ps float @atomic_add_i32_3d(<8 x i32> inreg %rsrc, i32 %data, i16 ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v3 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1528,14 +1078,6 @@ define amdgpu_ps float @atomic_add_i32_cube(<8 x i32> inreg %rsrc, i32 %data, i1 ; GFX11-TRUE16-LABEL: atomic_add_i32_cube: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -1544,16 +1086,9 @@ define amdgpu_ps float @atomic_add_i32_cube(<8 x i32> inreg %rsrc, i32 %data, i1 ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v3 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -1561,14 +1096,6 @@ define amdgpu_ps float @atomic_add_i32_cube(<8 x i32> inreg %rsrc, i32 %data, i1 ; GFX12-TRUE16-LABEL: atomic_add_i32_cube: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -1577,16 +1104,9 @@ define amdgpu_ps float @atomic_add_i32_cube(<8 x i32> inreg %rsrc, i32 %data, i1 ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v3 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1632,14 +1152,6 @@ define amdgpu_ps float @atomic_add_i32_1darray(<8 x i32> inreg %rsrc, i32 %data, ; GFX11-TRUE16-LABEL: atomic_add_i32_1darray: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -1647,15 +1159,8 @@ define amdgpu_ps float @atomic_add_i32_1darray(<8 x i32> inreg %rsrc, i32 %data, ; GFX11-FAKE16-LABEL: atomic_add_i32_1darray: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -1663,14 +1168,6 @@ define amdgpu_ps float @atomic_add_i32_1darray(<8 x i32> inreg %rsrc, i32 %data, ; GFX12-TRUE16-LABEL: atomic_add_i32_1darray: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -1678,15 +1175,8 @@ define amdgpu_ps float @atomic_add_i32_1darray(<8 x i32> inreg %rsrc, i32 %data, ; GFX12-FAKE16-LABEL: atomic_add_i32_1darray: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1736,14 +1226,6 @@ define amdgpu_ps float @atomic_add_i32_2darray(<8 x i32> inreg %rsrc, i32 %data, ; GFX11-TRUE16-LABEL: atomic_add_i32_2darray: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -1752,16 +1234,9 @@ define amdgpu_ps float @atomic_add_i32_2darray(<8 x i32> inreg %rsrc, i32 %data, ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v3 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -1769,14 +1244,6 @@ define amdgpu_ps float @atomic_add_i32_2darray(<8 x i32> inreg %rsrc, i32 %data, ; GFX12-TRUE16-LABEL: atomic_add_i32_2darray: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -1785,16 +1252,9 @@ define amdgpu_ps float @atomic_add_i32_2darray(<8 x i32> inreg %rsrc, i32 %data, ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v3 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1844,14 +1304,6 @@ define amdgpu_ps float @atomic_add_i32_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, ; GFX11-TRUE16-LABEL: atomic_add_i32_2dmsaa: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -1860,16 +1312,9 @@ define amdgpu_ps float @atomic_add_i32_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v3 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -1877,14 +1322,6 @@ define amdgpu_ps float @atomic_add_i32_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, ; GFX12-TRUE16-LABEL: atomic_add_i32_2dmsaa: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -1893,16 +1330,9 @@ define amdgpu_ps float @atomic_add_i32_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v3 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1955,14 +1385,6 @@ define amdgpu_ps float @atomic_add_i32_2darraymsaa(<8 x i32> inreg %rsrc, i32 %d ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v3 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v2.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v4.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v0, v[5:6], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -1971,16 +1393,9 @@ define amdgpu_ps float @atomic_add_i32_2darraymsaa(<8 x i32> inreg %rsrc, i32 %d ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 16, v3 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -1989,14 +1404,6 @@ define amdgpu_ps float @atomic_add_i32_2darraymsaa(<8 x i32> inreg %rsrc, i32 %d ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v3.h, v4.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v0, [v1, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -2005,16 +1412,9 @@ define amdgpu_ps float @atomic_add_i32_2darraymsaa(<8 x i32> inreg %rsrc, i32 %d ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v4, 16, v3 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -2059,14 +1459,6 @@ define amdgpu_ps float @atomic_add_i32_1d_slc(<8 x i32> inreg %rsrc, i32 %data, ; ; GFX11-TRUE16-LABEL: atomic_add_i32_1d_slc: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc slc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -2074,29 +1466,14 @@ define amdgpu_ps float @atomic_add_i32_1d_slc(<8 x i32> inreg %rsrc, i32 %data, ; GFX11-FAKE16-LABEL: atomic_add_i32_1d_slc: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc slc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_add_i32_1d_slc: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -2104,15 +1481,8 @@ define amdgpu_ps float @atomic_add_i32_1d_slc(<8 x i32> inreg %rsrc, i32 %data, ; GFX12-FAKE16-LABEL: atomic_add_i32_1d_slc: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -2157,14 +1527,6 @@ define amdgpu_ps <2 x float> @atomic_swap_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; ; GFX11-TRUE16-LABEL: atomic_swap_i64_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -2172,29 +1534,14 @@ define amdgpu_ps <2 x float> @atomic_swap_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX11-FAKE16-LABEL: atomic_swap_i64_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_swap_i64_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -2202,15 +1549,8 @@ define amdgpu_ps <2 x float> @atomic_swap_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX12-FAKE16-LABEL: atomic_swap_i64_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -2255,14 +1595,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; ; GFX11-TRUE16-LABEL: atomic_add_i64_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -2270,29 +1602,14 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX11-FAKE16-LABEL: atomic_add_i64_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_add_i64_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -2300,15 +1617,8 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX12-FAKE16-LABEL: atomic_add_i64_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -2353,14 +1663,6 @@ define amdgpu_ps <2 x float> @atomic_sub_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; ; GFX11-TRUE16-LABEL: atomic_sub_i64_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_sub v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -2368,29 +1670,14 @@ define amdgpu_ps <2 x float> @atomic_sub_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX11-FAKE16-LABEL: atomic_sub_i64_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_sub v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_sub_i64_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_sub_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -2398,15 +1685,8 @@ define amdgpu_ps <2 x float> @atomic_sub_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX12-FAKE16-LABEL: atomic_sub_i64_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_sub_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -2451,14 +1731,6 @@ define amdgpu_ps <2 x float> @atomic_smin_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; ; GFX11-TRUE16-LABEL: atomic_smin_i64_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_smin v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -2466,29 +1738,14 @@ define amdgpu_ps <2 x float> @atomic_smin_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX11-FAKE16-LABEL: atomic_smin_i64_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_smin v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_smin_i64_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_min_int v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -2496,15 +1753,8 @@ define amdgpu_ps <2 x float> @atomic_smin_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX12-FAKE16-LABEL: atomic_smin_i64_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_min_int v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -2549,14 +1799,6 @@ define amdgpu_ps <2 x float> @atomic_umin_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; ; GFX11-TRUE16-LABEL: atomic_umin_i64_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_umin v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -2564,29 +1806,14 @@ define amdgpu_ps <2 x float> @atomic_umin_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX11-FAKE16-LABEL: atomic_umin_i64_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_umin v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_umin_i64_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_min_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -2594,15 +1821,8 @@ define amdgpu_ps <2 x float> @atomic_umin_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX12-FAKE16-LABEL: atomic_umin_i64_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_min_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -2647,14 +1867,6 @@ define amdgpu_ps <2 x float> @atomic_smax_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; ; GFX11-TRUE16-LABEL: atomic_smax_i64_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_smax v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -2662,29 +1874,14 @@ define amdgpu_ps <2 x float> @atomic_smax_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX11-FAKE16-LABEL: atomic_smax_i64_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_smax v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_smax_i64_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_max_int v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -2692,15 +1889,8 @@ define amdgpu_ps <2 x float> @atomic_smax_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX12-FAKE16-LABEL: atomic_smax_i64_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_max_int v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -2745,14 +1935,6 @@ define amdgpu_ps <2 x float> @atomic_umax_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; ; GFX11-TRUE16-LABEL: atomic_umax_i64_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_umax v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -2760,29 +1942,14 @@ define amdgpu_ps <2 x float> @atomic_umax_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX11-FAKE16-LABEL: atomic_umax_i64_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_umax v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_umax_i64_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_max_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -2790,15 +1957,8 @@ define amdgpu_ps <2 x float> @atomic_umax_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX12-FAKE16-LABEL: atomic_umax_i64_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_max_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -2843,14 +2003,6 @@ define amdgpu_ps <2 x float> @atomic_and_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; ; GFX11-TRUE16-LABEL: atomic_and_i64_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_and v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -2858,29 +2010,14 @@ define amdgpu_ps <2 x float> @atomic_and_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX11-FAKE16-LABEL: atomic_and_i64_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_and v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_and_i64_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_and v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -2888,15 +2025,8 @@ define amdgpu_ps <2 x float> @atomic_and_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX12-FAKE16-LABEL: atomic_and_i64_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_and v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -2941,14 +2071,6 @@ define amdgpu_ps <2 x float> @atomic_or_i64_1d(<8 x i32> inreg %rsrc, i64 %data, ; ; GFX11-TRUE16-LABEL: atomic_or_i64_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_or v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -2956,29 +2078,14 @@ define amdgpu_ps <2 x float> @atomic_or_i64_1d(<8 x i32> inreg %rsrc, i64 %data, ; GFX11-FAKE16-LABEL: atomic_or_i64_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_or v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_or_i64_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_or v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -2986,15 +2093,8 @@ define amdgpu_ps <2 x float> @atomic_or_i64_1d(<8 x i32> inreg %rsrc, i64 %data, ; GFX12-FAKE16-LABEL: atomic_or_i64_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_or v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -3039,14 +2139,6 @@ define amdgpu_ps <2 x float> @atomic_xor_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; ; GFX11-TRUE16-LABEL: atomic_xor_i64_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_xor v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -3054,29 +2146,14 @@ define amdgpu_ps <2 x float> @atomic_xor_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX11-FAKE16-LABEL: atomic_xor_i64_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_xor v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_xor_i64_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_xor v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -3084,15 +2161,8 @@ define amdgpu_ps <2 x float> @atomic_xor_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX12-FAKE16-LABEL: atomic_xor_i64_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_xor v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -3137,14 +2207,6 @@ define amdgpu_ps <2 x float> @atomic_inc_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; ; GFX11-TRUE16-LABEL: atomic_inc_i64_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_inc v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -3152,29 +2214,14 @@ define amdgpu_ps <2 x float> @atomic_inc_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX11-FAKE16-LABEL: atomic_inc_i64_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_inc v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_inc_i64_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_inc_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -3182,15 +2229,8 @@ define amdgpu_ps <2 x float> @atomic_inc_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX12-FAKE16-LABEL: atomic_inc_i64_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_inc_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -3235,14 +2275,6 @@ define amdgpu_ps <2 x float> @atomic_dec_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; ; GFX11-TRUE16-LABEL: atomic_dec_i64_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_dec v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -3250,29 +2282,14 @@ define amdgpu_ps <2 x float> @atomic_dec_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX11-FAKE16-LABEL: atomic_dec_i64_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_dec v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_dec_i64_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_dec_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -3280,15 +2297,8 @@ define amdgpu_ps <2 x float> @atomic_dec_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX12-FAKE16-LABEL: atomic_dec_i64_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_dec_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -3333,14 +2343,6 @@ define amdgpu_ps <2 x float> @atomic_cmpswap_i64_1d(<8 x i32> inreg %rsrc, i64 % ; ; GFX11-TRUE16-LABEL: atomic_cmpswap_i64_1d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -3348,29 +2350,14 @@ define amdgpu_ps <2 x float> @atomic_cmpswap_i64_1d(<8 x i32> inreg %rsrc, i64 % ; GFX11-FAKE16-LABEL: atomic_cmpswap_i64_1d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v4, s0, 16, v4 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_cmpswap_i64_1d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -3378,15 +2365,8 @@ define amdgpu_ps <2 x float> @atomic_cmpswap_i64_1d(<8 x i32> inreg %rsrc, i64 % ; GFX12-FAKE16-LABEL: atomic_cmpswap_i64_1d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v4, s0, 16, v4 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -3432,14 +2412,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2d(<8 x i32> inreg %rsrc, i64 %data ; GFX11-TRUE16-LABEL: atomic_add_i64_2d: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -3447,15 +2419,8 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2d(<8 x i32> inreg %rsrc, i64 %data ; GFX11-FAKE16-LABEL: atomic_add_i64_2d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -3463,14 +2428,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2d(<8 x i32> inreg %rsrc, i64 %data ; GFX12-TRUE16-LABEL: atomic_add_i64_2d: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -3478,15 +2435,8 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2d(<8 x i32> inreg %rsrc, i64 %data ; GFX12-FAKE16-LABEL: atomic_add_i64_2d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -3536,14 +2486,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_3d(<8 x i32> inreg %rsrc, i64 %data ; GFX11-TRUE16-LABEL: atomic_add_i64_3d: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -3552,16 +2494,9 @@ define amdgpu_ps <2 x float> @atomic_add_i64_3d(<8 x i32> inreg %rsrc, i64 %data ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, s0, 16, v4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -3569,14 +2504,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_3d(<8 x i32> inreg %rsrc, i64 %data ; GFX12-TRUE16-LABEL: atomic_add_i64_3d: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -3585,16 +2512,9 @@ define amdgpu_ps <2 x float> @atomic_add_i64_3d(<8 x i32> inreg %rsrc, i64 %data ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v3, s0, 16, v4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -3644,14 +2564,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_cube(<8 x i32> inreg %rsrc, i64 %da ; GFX11-TRUE16-LABEL: atomic_add_i64_cube: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -3660,16 +2572,9 @@ define amdgpu_ps <2 x float> @atomic_add_i64_cube(<8 x i32> inreg %rsrc, i64 %da ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, s0, 16, v4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -3677,14 +2582,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_cube(<8 x i32> inreg %rsrc, i64 %da ; GFX12-TRUE16-LABEL: atomic_add_i64_cube: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -3693,16 +2590,9 @@ define amdgpu_ps <2 x float> @atomic_add_i64_cube(<8 x i32> inreg %rsrc, i64 %da ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v3, s0, 16, v4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -3748,14 +2638,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1darray(<8 x i32> inreg %rsrc, i64 ; GFX11-TRUE16-LABEL: atomic_add_i64_1darray: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -3763,15 +2645,8 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1darray(<8 x i32> inreg %rsrc, i64 ; GFX11-FAKE16-LABEL: atomic_add_i64_1darray: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -3779,14 +2654,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1darray(<8 x i32> inreg %rsrc, i64 ; GFX12-TRUE16-LABEL: atomic_add_i64_1darray: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -3794,15 +2661,8 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1darray(<8 x i32> inreg %rsrc, i64 ; GFX12-FAKE16-LABEL: atomic_add_i64_1darray: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -3852,14 +2712,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darray(<8 x i32> inreg %rsrc, i64 ; GFX11-TRUE16-LABEL: atomic_add_i64_2darray: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -3868,16 +2720,9 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darray(<8 x i32> inreg %rsrc, i64 ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, s0, 16, v4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -3885,14 +2730,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darray(<8 x i32> inreg %rsrc, i64 ; GFX12-TRUE16-LABEL: atomic_add_i64_2darray: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -3901,16 +2738,9 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darray(<8 x i32> inreg %rsrc, i64 ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v3, s0, 16, v4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -3960,14 +2790,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2dmsaa(<8 x i32> inreg %rsrc, i64 % ; GFX11-TRUE16-LABEL: atomic_add_i64_2dmsaa: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -3976,16 +2798,9 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2dmsaa(<8 x i32> inreg %rsrc, i64 % ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, s0, 16, v4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -3993,14 +2808,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2dmsaa(<8 x i32> inreg %rsrc, i64 % ; GFX12-TRUE16-LABEL: atomic_add_i64_2dmsaa: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -4009,16 +2816,9 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2dmsaa(<8 x i32> inreg %rsrc, i64 % ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v3, s0, 16, v4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -4071,14 +2871,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darraymsaa(<8 x i32> inreg %rsrc, ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v4 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.h, v3.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v7.h, v5.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v[0:1], v[6:7], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -4087,16 +2879,9 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darraymsaa(<8 x i32> inreg %rsrc, ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -4105,14 +2890,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darraymsaa(<8 x i32> inreg %rsrc, ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v4.h, v5.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v[0:1], [v2, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY th:TH_ATOMIC_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -4121,16 +2898,9 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darraymsaa(<8 x i32> inreg %rsrc, ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v3, v5, 16, v4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY th:TH_ATOMIC_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -4175,14 +2945,6 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1d_slc(<8 x i32> inreg %rsrc, i64 % ; ; GFX11-TRUE16-LABEL: atomic_add_i64_1d_slc: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc slc a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -4190,29 +2952,14 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1d_slc(<8 x i32> inreg %rsrc, i64 % ; GFX11-FAKE16-LABEL: atomic_add_i64_1d_slc: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc slc a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: atomic_add_i64_1d_slc: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -4220,15 +2967,8 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1d_slc(<8 x i32> inreg %rsrc, i64 % ; GFX12-FAKE16-LABEL: atomic_add_i64_1d_slc: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll index ce9d9a1b96aad6..99019120f5c89f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.atomic.dim.ll @@ -4,7 +4,7 @@ ; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d -o - %s | FileCheck -check-prefix=GFX900 %s ; RUN: llc -global-isel -mtriple=amdgpu9.0a-mesa-mesa3d -o - %s | FileCheck -check-prefix=GFX90A %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -o - %s | FileCheck -check-prefix=GFX10PLUS %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -o - %s | FileCheck -check-prefix=GFX10PLUS %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -o - %s | FileCheck -check-prefix=GFX11 %s ; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -o - %s | FileCheck -check-prefixes=GFX12 %s define amdgpu_ps float @atomic_swap_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32 %s) { @@ -79,16 +79,14 @@ define amdgpu_ps float @atomic_swap_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_swap_i32_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_swap_i32_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_swap v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -170,16 +168,14 @@ define amdgpu_ps float @atomic_add_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i32_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i32_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -261,16 +257,14 @@ define amdgpu_ps float @atomic_sub_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_sub_i32_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_sub v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_sub_i32_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_sub_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -352,16 +346,14 @@ define amdgpu_ps float @atomic_smin_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_smin_i32_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_smin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_smin_i32_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_min_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -443,16 +435,14 @@ define amdgpu_ps float @atomic_umin_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_umin_i32_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_umin v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_umin_i32_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_min_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -534,16 +524,14 @@ define amdgpu_ps float @atomic_smax_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_smax_i32_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_smax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_smax_i32_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_max_int v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -625,16 +613,14 @@ define amdgpu_ps float @atomic_umax_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_umax_i32_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_umax v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_umax_i32_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_max_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -716,16 +702,14 @@ define amdgpu_ps float @atomic_and_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_and_i32_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_and_i32_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_and v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -807,16 +791,14 @@ define amdgpu_ps float @atomic_or_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32 % ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_or_i32_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_or_i32_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_or v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -898,16 +880,14 @@ define amdgpu_ps float @atomic_xor_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_xor_i32_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_xor_i32_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_xor v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -989,16 +969,14 @@ define amdgpu_ps float @atomic_inc_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_inc_i32_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_inc v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_inc_i32_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_inc_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -1080,16 +1058,14 @@ define amdgpu_ps float @atomic_dec_i32_1d(<8 x i32> inreg %rsrc, i32 %data, i32 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_dec_i32_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_dec v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_dec_i32_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_dec_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -1170,16 +1146,14 @@ define amdgpu_ps float @atomic_cmpswap_i32_1d(<8 x i32> inreg %rsrc, i32 %cmp, i ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_cmpswap_i32_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_cmpswap_i32_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -1255,16 +1229,13 @@ define amdgpu_ps void @atomic_cmpswap_i32_1d_no_return(<8 x i32> inreg %rsrc, i3 ; GFX10PLUS-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm ; GFX10PLUS-NEXT: s_endpgm ; +; GFX11-LABEL: atomic_cmpswap_i32_1d_no_return: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm +; GFX11-NEXT: s_endpgm +; ; GFX12-LABEL: atomic_cmpswap_i32_1d_no_return: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_cmpswap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_endpgm main_body: @@ -1345,16 +1316,14 @@ define amdgpu_ps float @atomic_add_i32_2d(<8 x i32> inreg %rsrc, i32 %data, i32 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i32_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i32_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -1438,16 +1407,14 @@ define amdgpu_ps float @atomic_add_i32_3d(<8 x i32> inreg %rsrc, i32 %data, i32 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i32_3d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i32_3d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_3D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -1531,16 +1498,14 @@ define amdgpu_ps float @atomic_add_i32_cube(<8 x i32> inreg %rsrc, i32 %data, i3 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i32_cube: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i32_cube: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_CUBE th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -1623,16 +1588,14 @@ define amdgpu_ps float @atomic_add_i32_1darray(<8 x i32> inreg %rsrc, i32 %data, ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i32_1darray: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v0, v[1:2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i32_1darray: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v0, [v1, v2], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D_ARRAY th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -1716,16 +1679,14 @@ define amdgpu_ps float @atomic_add_i32_2darray(<8 x i32> inreg %rsrc, i32 %data, ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i32_2darray: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i32_2darray: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -1809,16 +1770,14 @@ define amdgpu_ps float @atomic_add_i32_2dmsaa(<8 x i32> inreg %rsrc, i32 %data, ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i32_2dmsaa: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v0, v[1:3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i32_2dmsaa: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v0, [v1, v2, v3], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -1903,16 +1862,14 @@ define amdgpu_ps float @atomic_add_i32_2darraymsaa(<8 x i32> inreg %rsrc, i32 %d ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i32_2darraymsaa: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v0, v[1:4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i32_2darraymsaa: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v0, [v1, v2, v3, v4], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -1994,16 +1951,14 @@ define amdgpu_ps float @atomic_add_i32_1d_slc(<8 x i32> inreg %rsrc, i32 %data, ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i32_1d_slc: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm glc slc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i32_1d_slc: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v0, v1, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -2084,16 +2039,14 @@ define amdgpu_ps <2 x float> @atomic_swap_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_swap_i64_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_swap_i64_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_swap v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -2174,16 +2127,14 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i64_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i64_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -2264,16 +2215,14 @@ define amdgpu_ps <2 x float> @atomic_sub_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_sub_i64_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_sub v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_sub_i64_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_sub_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -2354,16 +2303,14 @@ define amdgpu_ps <2 x float> @atomic_smin_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_smin_i64_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_smin v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_smin_i64_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_min_int v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -2444,16 +2391,14 @@ define amdgpu_ps <2 x float> @atomic_umin_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_umin_i64_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_umin v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_umin_i64_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_min_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -2534,16 +2479,14 @@ define amdgpu_ps <2 x float> @atomic_smax_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_smax_i64_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_smax v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_smax_i64_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_max_int v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -2624,16 +2567,14 @@ define amdgpu_ps <2 x float> @atomic_umax_i64_1d(<8 x i32> inreg %rsrc, i64 %dat ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_umax_i64_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_umax v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_umax_i64_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_max_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -2714,16 +2655,14 @@ define amdgpu_ps <2 x float> @atomic_and_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_and_i64_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_and v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_and_i64_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_and v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -2804,16 +2743,14 @@ define amdgpu_ps <2 x float> @atomic_or_i64_1d(<8 x i32> inreg %rsrc, i64 %data, ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_or_i64_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_or v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_or_i64_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_or v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -2894,16 +2831,14 @@ define amdgpu_ps <2 x float> @atomic_xor_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_xor_i64_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_xor v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_xor_i64_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_xor v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -2984,16 +2919,14 @@ define amdgpu_ps <2 x float> @atomic_inc_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_inc_i64_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_inc v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_inc_i64_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_inc_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -3074,16 +3007,14 @@ define amdgpu_ps <2 x float> @atomic_dec_i64_1d(<8 x i32> inreg %rsrc, i64 %data ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_dec_i64_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_dec v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_dec_i64_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_dec_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -3164,16 +3095,14 @@ define amdgpu_ps <2 x float> @atomic_cmpswap_i64_1d(<8 x i32> inreg %rsrc, i64 % ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_cmpswap_i64_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_cmpswap_i64_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -3249,16 +3178,13 @@ define amdgpu_ps void @atomic_cmpswap_i64_1d_no_return(<8 x i32> inreg %rsrc, i6 ; GFX10PLUS-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; GFX10PLUS-NEXT: s_endpgm ; +; GFX11-LABEL: atomic_cmpswap_i64_1d_no_return: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm +; GFX11-NEXT: s_endpgm +; ; GFX12-LABEL: atomic_cmpswap_i64_1d_no_return: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_cmpswap v[0:3], v4, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_endpgm main_body: @@ -3337,16 +3263,14 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2d(<8 x i32> inreg %rsrc, i64 %data ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i64_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i64_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -3427,16 +3351,14 @@ define amdgpu_ps <2 x float> @atomic_add_i64_3d(<8 x i32> inreg %rsrc, i64 %data ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i64_3d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v[0:1], v[2:4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i64_3d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v[0:1], [v2, v3, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_3D th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -3517,16 +3439,14 @@ define amdgpu_ps <2 x float> @atomic_add_i64_cube(<8 x i32> inreg %rsrc, i64 %da ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i64_cube: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v[0:1], v[2:4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i64_cube: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v[0:1], [v2, v3, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_CUBE th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -3607,16 +3527,14 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1darray(<8 x i32> inreg %rsrc, i64 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i64_1darray: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v[0:1], v[2:3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i64_1darray: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v[0:1], [v2, v3], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D_ARRAY th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -3697,16 +3615,14 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darray(<8 x i32> inreg %rsrc, i64 ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i64_2darray: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v[0:1], v[2:4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i64_2darray: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v[0:1], [v2, v3, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_ARRAY th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -3787,16 +3703,14 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2dmsaa(<8 x i32> inreg %rsrc, i64 % ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i64_2dmsaa: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v[0:1], v[2:4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i64_2dmsaa: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v[0:1], [v2, v3, v4], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -3877,16 +3791,14 @@ define amdgpu_ps <2 x float> @atomic_add_i64_2darraymsaa(<8 x i32> inreg %rsrc, ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i64_2darraymsaa: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v[0:1], v[2:5], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm glc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i64_2darraymsaa: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v[0:1], [v2, v3, v4, v5], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D_MSAA_ARRAY th:TH_ATOMIC_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -3967,16 +3879,14 @@ define amdgpu_ps <2 x float> @atomic_add_i64_1d_slc(<8 x i32> inreg %rsrc, i64 % ; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) ; GFX10PLUS-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: atomic_add_i64_1d_slc: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_atomic_add v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm glc slc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: atomic_add_i64_1d_slc: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_atomic_add_uint v[0:1], v2, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D th:TH_ATOMIC_NT_RETURN ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll index 0cd3a5d235ea60..e4cf8a89129312 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.a16.dim.ll @@ -55,90 +55,44 @@ define amdgpu_ps <4 x float> @gather4_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; ; GFX11-TRUE16-LABEL: gather4_2d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX11-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX11-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX11-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l -; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-TRUE16-NEXT: image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: gather4_2d: ; GFX11-FAKE16: ; %bb.0: ; %main_body -; GFX11-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX11-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX11-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-FAKE16-NEXT: image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: gather4_2d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX12-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX12-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX12-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX12-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l -; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-TRUE16-NEXT: image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-FAKE16-LABEL: gather4_2d: ; GFX12-FAKE16: ; %bb.0: ; %main_body -; GFX12-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX12-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX12-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX12-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX12-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-FAKE16-NEXT: image_gather4 v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -200,94 +154,48 @@ define amdgpu_ps <4 x float> @gather4_cube(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX11-TRUE16-LABEL: gather4_cube: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX11-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX11-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX11-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l -; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-TRUE16-NEXT: image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: gather4_cube: ; GFX11-FAKE16: ; %bb.0: ; %main_body -; GFX11-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX11-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX11-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-FAKE16-NEXT: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: gather4_cube: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX12-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX12-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX12-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX12-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l -; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-TRUE16-NEXT: image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16 ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-FAKE16-LABEL: gather4_cube: ; GFX12-FAKE16: ; %bb.0: ; %main_body -; GFX12-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX12-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX12-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX12-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX12-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-FAKE16-NEXT: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE a16 ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -349,94 +257,48 @@ define amdgpu_ps <4 x float> @gather4_2darray(<8 x i32> inreg %rsrc, <4 x i32> i ; ; GFX11-TRUE16-LABEL: gather4_2darray: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX11-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX11-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX11-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l -; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-TRUE16-NEXT: image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: gather4_2darray: ; GFX11-FAKE16: ; %bb.0: ; %main_body -; GFX11-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX11-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX11-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-FAKE16-NEXT: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: gather4_2darray: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX12-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX12-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX12-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX12-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l -; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-TRUE16-NEXT: image_gather4 v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-FAKE16-LABEL: gather4_2darray: ; GFX12-FAKE16: ; %bb.0: ; %main_body -; GFX12-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX12-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX12-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX12-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX12-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-FAKE16-NEXT: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY a16 ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -494,90 +356,44 @@ define amdgpu_ps <4 x float> @gather4_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX11-TRUE16-LABEL: gather4_c_2d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX11-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX11-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX11-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-TRUE16-NEXT: image_gather4_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: gather4_c_2d: ; GFX11-FAKE16: ; %bb.0: ; %main_body -; GFX11-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX11-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX11-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 -; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-FAKE16-NEXT: image_gather4_c v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: gather4_c_2d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX12-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX12-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX12-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX12-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-TRUE16-NEXT: image_gather4_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-FAKE16-LABEL: gather4_c_2d: ; GFX12-FAKE16: ; %bb.0: ; %main_body -; GFX12-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX12-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX12-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX12-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX12-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 -; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-FAKE16-NEXT: image_gather4_c v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -639,94 +455,48 @@ define amdgpu_ps <4 x float> @gather4_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; ; GFX11-TRUE16-LABEL: gather4_cl_2d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX11-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX11-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX11-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l -; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-TRUE16-NEXT: image_gather4_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: gather4_cl_2d: ; GFX11-FAKE16: ; %bb.0: ; %main_body -; GFX11-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX11-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX11-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-FAKE16-NEXT: image_gather4_cl v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: gather4_cl_2d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX12-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX12-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX12-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX12-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l -; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-TRUE16-NEXT: image_gather4_cl v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-FAKE16-LABEL: gather4_cl_2d: ; GFX12-FAKE16: ; %bb.0: ; %main_body -; GFX12-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX12-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX12-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX12-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX12-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-FAKE16-NEXT: image_gather4_cl v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -788,94 +558,48 @@ define amdgpu_ps <4 x float> @gather4_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i ; ; GFX11-TRUE16-LABEL: gather4_c_cl_2d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX11-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX11-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX11-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-TRUE16-NEXT: image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: gather4_c_cl_2d: ; GFX11-FAKE16: ; %bb.0: ; %main_body -; GFX11-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX11-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX11-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v3 -; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-FAKE16-NEXT: image_gather4_c_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: gather4_c_cl_2d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX12-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX12-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX12-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX12-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-TRUE16-NEXT: image_gather4_c_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-FAKE16-LABEL: gather4_c_cl_2d: ; GFX12-FAKE16: ; %bb.0: ; %main_body -; GFX12-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX12-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX12-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX12-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX12-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v3 -; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-FAKE16-NEXT: image_gather4_c_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -937,94 +661,48 @@ define amdgpu_ps <4 x float> @gather4_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; ; GFX11-TRUE16-LABEL: gather4_b_2d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX11-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX11-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX11-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-TRUE16-NEXT: image_gather4_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: gather4_b_2d: ; GFX11-FAKE16: ; %bb.0: ; %main_body -; GFX11-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX11-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX11-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 -; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-FAKE16-NEXT: image_gather4_b v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: gather4_b_2d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX12-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX12-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX12-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX12-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-TRUE16-NEXT: image_gather4_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-FAKE16-LABEL: gather4_b_2d: ; GFX12-FAKE16: ; %bb.0: ; %main_body -; GFX12-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX12-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX12-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX12-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX12-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 -; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-FAKE16-NEXT: image_gather4_b v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1086,94 +764,48 @@ define amdgpu_ps <4 x float> @gather4_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; ; GFX11-TRUE16-LABEL: gather4_c_b_2d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX11-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX11-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX11-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-TRUE16-NEXT: image_gather4_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: gather4_c_b_2d: ; GFX11-FAKE16: ; %bb.0: ; %main_body -; GFX11-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX11-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX11-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 -; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-FAKE16-NEXT: image_gather4_c_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: gather4_c_b_2d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX12-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX12-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX12-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX12-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-TRUE16-NEXT: image_gather4_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-FAKE16-LABEL: gather4_c_b_2d: ; GFX12-FAKE16: ; %bb.0: ; %main_body -; GFX12-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX12-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX12-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX12-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX12-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 -; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-FAKE16-NEXT: image_gather4_c_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1237,98 +869,54 @@ define amdgpu_ps <4 x float> @gather4_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i ; ; GFX11-TRUE16-LABEL: gather4_b_cl_2d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX11-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX11-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX11-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-TRUE16-NEXT: image_gather4_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: gather4_b_cl_2d: ; GFX11-FAKE16: ; %bb.0: ; %main_body -; GFX11-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX11-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX11-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v3 -; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-FAKE16-NEXT: image_gather4_b_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: gather4_b_cl_2d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX12-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX12-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX12-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX12-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-TRUE16-NEXT: image_gather4_b_cl v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-FAKE16-LABEL: gather4_b_cl_2d: ; GFX12-FAKE16: ; %bb.0: ; %main_body -; GFX12-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX12-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX12-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX12-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX12-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v3 -; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-FAKE16-NEXT: image_gather4_b_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1392,98 +980,54 @@ define amdgpu_ps <4 x float> @gather4_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> ; ; GFX11-TRUE16-LABEL: gather4_c_b_cl_2d: ; GFX11-TRUE16: ; %bb.0: ; %main_body -; GFX11-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX11-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX11-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX11-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-TRUE16-NEXT: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: gather4_c_b_cl_2d: ; GFX11-FAKE16: ; %bb.0: ; %main_body -; GFX11-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX11-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX11-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX11-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v3, s0, 16, v4 -; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX11-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX11-FAKE16-NEXT: image_gather4_c_b_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: gather4_c_b_cl_2d: ; GFX12-TRUE16: ; %bb.0: ; %main_body -; GFX12-TRUE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 +; GFX12-TRUE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-TRUE16-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX12-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX12-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX12-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX12-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-TRUE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-TRUE16-NEXT: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-FAKE16-LABEL: gather4_c_b_cl_2d: ; GFX12-FAKE16: ; %bb.0: ; %main_body -; GFX12-FAKE16-NEXT: s_mov_b32 s14, exec_lo -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 +; GFX12-FAKE16-NEXT: s_mov_b32 s12, exec_lo ; GFX12-FAKE16-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v4, 0xffff, v4 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX12-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX12-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX12-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX12-FAKE16-NEXT: s_mov_b32 s11, s13 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, s0, 16, v0 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, v3, 16, v2 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v3, s0, 16, v4 -; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-FAKE16-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-FAKE16-NEXT: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1540,18 +1084,6 @@ define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX11-TRUE16-LABEL: gather4_l_2d: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX11-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX11-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX11-TRUE16-NEXT: image_gather4_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -1560,20 +1092,9 @@ define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX11-FAKE16-NEXT: s_mov_b32 s11, s13 ; GFX11-FAKE16-NEXT: image_gather4_l v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -1581,18 +1102,6 @@ define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX12-TRUE16-LABEL: gather4_l_2d: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX12-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX12-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX12-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX12-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX12-TRUE16-NEXT: image_gather4_l v[0:3], [v0, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -1601,20 +1110,9 @@ define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX12-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX12-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX12-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX12-FAKE16-NEXT: s_mov_b32 s11, s13 ; GFX12-FAKE16-NEXT: image_gather4_l v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1671,18 +1169,6 @@ define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; GFX11-TRUE16-LABEL: gather4_c_l_2d: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX11-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX11-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX11-TRUE16-NEXT: image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -1691,20 +1177,9 @@ define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v3 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX11-FAKE16-NEXT: s_mov_b32 s11, s13 ; GFX11-FAKE16-NEXT: image_gather4_c_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -1712,18 +1187,6 @@ define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; GFX12-TRUE16-LABEL: gather4_c_l_2d: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX12-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX12-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX12-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX12-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX12-TRUE16-NEXT: image_gather4_c_l v[0:3], [v0, v1, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -1732,20 +1195,9 @@ define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v3, 0xffff, v3 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v2, s0, 16, v3 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX12-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX12-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX12-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX12-FAKE16-NEXT: s_mov_b32 s11, s13 ; GFX12-FAKE16-NEXT: image_gather4_c_l v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1798,18 +1250,6 @@ define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; GFX11-TRUE16-LABEL: gather4_lz_2d: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX11-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX11-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX11-TRUE16-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -1817,19 +1257,8 @@ define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; GFX11-FAKE16-LABEL: gather4_lz_2d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX11-FAKE16-NEXT: s_mov_b32 s11, s13 ; GFX11-FAKE16-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -1837,18 +1266,6 @@ define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; GFX12-TRUE16-LABEL: gather4_lz_2d: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX12-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX12-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX12-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX12-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX12-TRUE16-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -1856,19 +1273,8 @@ define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; GFX12-FAKE16-LABEL: gather4_lz_2d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX12-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX12-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX12-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX12-FAKE16-NEXT: s_mov_b32 s11, s13 ; GFX12-FAKE16-NEXT: image_gather4_lz v[0:3], v0, s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -1921,18 +1327,6 @@ define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> i ; GFX11-TRUE16-LABEL: gather4_c_lz_2d: ; GFX11-TRUE16: ; %bb.0: ; %main_body ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX11-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX11-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX11-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX11-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX11-TRUE16-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -1940,19 +1334,8 @@ define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> i ; GFX11-FAKE16-LABEL: gather4_c_lz_2d: ; GFX11-FAKE16: ; %bb.0: ; %main_body ; GFX11-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX11-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX11-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX11-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX11-FAKE16-NEXT: s_mov_b32 s11, s13 ; GFX11-FAKE16-NEXT: image_gather4_c_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -1960,18 +1343,6 @@ define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> i ; GFX12-TRUE16-LABEL: gather4_c_lz_2d: ; GFX12-TRUE16: ; %bb.0: ; %main_body ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v1.h, v2.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 -; GFX12-TRUE16-NEXT: s_mov_b32 s8, s10 -; GFX12-TRUE16-NEXT: s_mov_b32 s9, s11 -; GFX12-TRUE16-NEXT: s_mov_b32 s10, s12 -; GFX12-TRUE16-NEXT: s_mov_b32 s11, s13 ; GFX12-TRUE16-NEXT: image_gather4_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-TRUE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -1979,19 +1350,8 @@ define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> i ; GFX12-FAKE16-LABEL: gather4_c_lz_2d: ; GFX12-FAKE16: ; %bb.0: ; %main_body ; GFX12-FAKE16-NEXT: v_and_b32_e32 v1, 0xffff, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v2, 16, v1 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 -; GFX12-FAKE16-NEXT: s_mov_b32 s8, s10 -; GFX12-FAKE16-NEXT: s_mov_b32 s9, s11 -; GFX12-FAKE16-NEXT: s_mov_b32 s10, s12 -; GFX12-FAKE16-NEXT: s_mov_b32 s11, s13 ; GFX12-FAKE16-NEXT: image_gather4_c_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D a16 ; GFX12-FAKE16-NEXT: s_wait_samplecnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll index e57682d6837d73..eac96c2e4514dc 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.gather4.dim.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -o - %s | FileCheck -check-prefix=GFX6 %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -o - %s | FileCheck -check-prefix=GFX10NSA %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -o - %s | FileCheck -check-prefix=GFX10NSA %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -o - %s | FileCheck -check-prefix=GFX11 %s ; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -amdgpu-enable-delay-alu=0 -amdgpu-enable-vopd=0 -o - %s | FileCheck -check-prefix=GFX12 %s define amdgpu_ps <4 x float> @gather4_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %s, float %t) { @@ -47,23 +47,20 @@ define amdgpu_ps <4 x float> @gather4_2d(<8 x i32> inreg %rsrc, <4 x i32> inreg ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_mov_b32 s12, exec_lo +; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo +; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12 +; GFX11-NEXT: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s1, exec_lo -; GFX12-NEXT: s_mov_b32 s0, s2 +; GFX12-NEXT: s_mov_b32 s12, exec_lo ; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s1 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 +; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-NEXT: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -129,30 +126,34 @@ define amdgpu_ps <4 x float> @gather4_2d_tfe(<8 x i32> inreg %rsrc, <4 x i32> in ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_2d_tfe: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_mov_b32 s12, exec_lo +; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo +; GFX11-NEXT: v_mov_b32_e32 v5, v0 +; GFX11-NEXT: v_mov_b32_e32 v0, 0 +; GFX11-NEXT: v_mov_b32_e32 v6, v1 +; GFX11-NEXT: v_mov_b32_e32 v1, v0 +; GFX11-NEXT: v_mov_b32_e32 v2, v0 +; GFX11-NEXT: v_mov_b32_e32 v3, v0 +; GFX11-NEXT: v_mov_b32_e32 v4, v0 +; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12 +; GFX11-NEXT: image_gather4 v[0:4], v[5:6], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_2d_tfe: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s14, exec_lo -; GFX12-NEXT: s_mov_b32 s0, s2 +; GFX12-NEXT: s_mov_b32 s12, exec_lo ; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo ; GFX12-NEXT: v_mov_b32_e32 v5, v0 ; GFX12-NEXT: v_mov_b32_e32 v0, 0 ; GFX12-NEXT: v_mov_b32_e32 v6, v1 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 ; GFX12-NEXT: v_mov_b32_e32 v1, v0 ; GFX12-NEXT: v_mov_b32_e32 v2, v0 ; GFX12-NEXT: v_mov_b32_e32 v3, v0 ; GFX12-NEXT: v_mov_b32_e32 v4, v0 -; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s14 +; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-NEXT: image_gather4 v[0:4], [v5, v6], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D tfe ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -205,23 +206,20 @@ define amdgpu_ps <4 x float> @gather4_cube(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_cube: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_mov_b32 s12, exec_lo +; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo +; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12 +; GFX11-NEXT: image_gather4 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_cube: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s1, exec_lo -; GFX12-NEXT: s_mov_b32 s0, s2 +; GFX12-NEXT: s_mov_b32 s12, exec_lo ; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s1 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 +; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-NEXT: image_gather4 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_CUBE ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -273,23 +271,20 @@ define amdgpu_ps <4 x float> @gather4_2darray(<8 x i32> inreg %rsrc, <4 x i32> i ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_2darray: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_mov_b32 s12, exec_lo +; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo +; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12 +; GFX11-NEXT: image_gather4 v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_2darray: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s1, exec_lo -; GFX12-NEXT: s_mov_b32 s0, s2 +; GFX12-NEXT: s_mov_b32 s12, exec_lo ; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s1 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 +; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-NEXT: image_gather4 v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D_ARRAY ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -341,23 +336,20 @@ define amdgpu_ps <4 x float> @gather4_c_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_c_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_mov_b32 s12, exec_lo +; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo +; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12 +; GFX11-NEXT: image_gather4_c v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_c_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s1, exec_lo -; GFX12-NEXT: s_mov_b32 s0, s2 +; GFX12-NEXT: s_mov_b32 s12, exec_lo ; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s1 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 +; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-NEXT: image_gather4_c v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -409,23 +401,20 @@ define amdgpu_ps <4 x float> @gather4_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_cl_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_mov_b32 s12, exec_lo +; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo +; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12 +; GFX11-NEXT: image_gather4_cl v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_cl_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s1, exec_lo -; GFX12-NEXT: s_mov_b32 s0, s2 +; GFX12-NEXT: s_mov_b32 s12, exec_lo ; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s1 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 +; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-NEXT: image_gather4_cl v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -477,23 +466,20 @@ define amdgpu_ps <4 x float> @gather4_c_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_c_cl_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_mov_b32 s12, exec_lo +; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo +; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12 +; GFX11-NEXT: image_gather4_c_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_c_cl_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s1, exec_lo -; GFX12-NEXT: s_mov_b32 s0, s2 +; GFX12-NEXT: s_mov_b32 s12, exec_lo ; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s1 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 +; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-NEXT: image_gather4_c_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -545,23 +531,20 @@ define amdgpu_ps <4 x float> @gather4_b_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_b_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_mov_b32 s12, exec_lo +; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo +; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12 +; GFX11-NEXT: image_gather4_b v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_b_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s1, exec_lo -; GFX12-NEXT: s_mov_b32 s0, s2 +; GFX12-NEXT: s_mov_b32 s12, exec_lo ; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s1 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 +; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-NEXT: image_gather4_b v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -613,23 +596,20 @@ define amdgpu_ps <4 x float> @gather4_c_b_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_c_b_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_mov_b32 s12, exec_lo +; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo +; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12 +; GFX11-NEXT: image_gather4_c_b v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_c_b_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s1, exec_lo -; GFX12-NEXT: s_mov_b32 s0, s2 +; GFX12-NEXT: s_mov_b32 s12, exec_lo ; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s1 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 +; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-NEXT: image_gather4_c_b v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -681,23 +661,20 @@ define amdgpu_ps <4 x float> @gather4_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> i ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_b_cl_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_mov_b32 s12, exec_lo +; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo +; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12 +; GFX11-NEXT: image_gather4_b_cl v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_b_cl_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s1, exec_lo -; GFX12-NEXT: s_mov_b32 s0, s2 +; GFX12-NEXT: s_mov_b32 s12, exec_lo ; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s1 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 +; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-NEXT: image_gather4_b_cl v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -749,23 +726,20 @@ define amdgpu_ps <4 x float> @gather4_c_b_cl_2d(<8 x i32> inreg %rsrc, <4 x i32> ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_c_b_cl_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_mov_b32 s12, exec_lo +; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo +; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12 +; GFX11-NEXT: image_gather4_c_b_cl v[0:3], v[0:4], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_c_b_cl_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s1, exec_lo -; GFX12-NEXT: s_mov_b32 s0, s2 +; GFX12-NEXT: s_mov_b32 s12, exec_lo ; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s1 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 +; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-NEXT: image_gather4_c_b_cl v[0:3], [v0, v1, v2, v[3:4]], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -811,20 +785,14 @@ define amdgpu_ps <4 x float> @gather4_l_2d(<8 x i32> inreg %rsrc, <4 x i32> inre ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_l_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_gather4_l v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_l_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 ; GFX12-NEXT: image_gather4_l v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -870,20 +838,14 @@ define amdgpu_ps <4 x float> @gather4_c_l_2d(<8 x i32> inreg %rsrc, <4 x i32> in ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_c_l_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_gather4_c_l v[0:3], v[0:3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_c_l_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 ; GFX12-NEXT: image_gather4_c_l v[0:3], [v0, v1, v2, v3], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -929,20 +891,14 @@ define amdgpu_ps <4 x float> @gather4_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> inr ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_lz_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_gather4_lz v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_lz_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 ; GFX12-NEXT: image_gather4_lz v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -988,20 +944,14 @@ define amdgpu_ps <4 x float> @gather4_c_lz_2d(<8 x i32> inreg %rsrc, <4 x i32> i ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_c_lz_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_gather4_c_lz v[0:3], v[0:2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_c_lz_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 ; GFX12-NEXT: image_gather4_c_lz v[0:3], [v0, v1, v2], s[0:7], s[8:11] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -1053,23 +1003,20 @@ define amdgpu_ps <4 x float> @gather4_2d_dmask_2(<8 x i32> inreg %rsrc, <4 x i32 ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_2d_dmask_2: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_mov_b32 s12, exec_lo +; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo +; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12 +; GFX11-NEXT: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x2 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_2d_dmask_2: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s1, exec_lo -; GFX12-NEXT: s_mov_b32 s0, s2 +; GFX12-NEXT: s_mov_b32 s12, exec_lo ; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s1 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 +; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-NEXT: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x2 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -1121,23 +1068,20 @@ define amdgpu_ps <4 x float> @gather4_2d_dmask_4(<8 x i32> inreg %rsrc, <4 x i32 ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_2d_dmask_4: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_mov_b32 s12, exec_lo +; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo +; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12 +; GFX11-NEXT: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_2d_dmask_4: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s1, exec_lo -; GFX12-NEXT: s_mov_b32 s0, s2 +; GFX12-NEXT: s_mov_b32 s12, exec_lo ; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s1 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 +; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-NEXT: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x4 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -1189,23 +1133,20 @@ define amdgpu_ps <4 x float> @gather4_2d_dmask_8(<8 x i32> inreg %rsrc, <4 x i32 ; GFX10NSA-NEXT: s_waitcnt vmcnt(0) ; GFX10NSA-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: gather4_2d_dmask_8: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: s_mov_b32 s12, exec_lo +; GFX11-NEXT: s_wqm_b32 exec_lo, exec_lo +; GFX11-NEXT: s_and_b32 exec_lo, exec_lo, s12 +; GFX11-NEXT: image_gather4 v[0:3], v[0:1], s[0:7], s[8:11] dmask:0x8 dim:SQ_RSRC_IMG_2D +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: gather4_2d_dmask_8: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s1, exec_lo -; GFX12-NEXT: s_mov_b32 s0, s2 +; GFX12-NEXT: s_mov_b32 s12, exec_lo ; GFX12-NEXT: s_wqm_b32 exec_lo, exec_lo -; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s1 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 -; GFX12-NEXT: s_mov_b32 s8, s10 -; GFX12-NEXT: s_mov_b32 s9, s11 -; GFX12-NEXT: s_mov_b32 s10, s12 -; GFX12-NEXT: s_mov_b32 s11, s13 +; GFX12-NEXT: s_and_b32 exec_lo, exec_lo, s12 ; GFX12-NEXT: image_gather4 v[0:3], [v0, v1], s[0:7], s[8:11] dmask:0x8 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: ; return to shader part epilog diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll index 6cf7e721605a30..52e36fbf61b0b9 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.a16.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu9.00-mesa-mesa3d < %s | FileCheck -check-prefix=GFX9 %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefix=GFX10 %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX10 %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=-real-true16 < %s | FileCheck -check-prefix=GFX11 %s ; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX12 %s define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, i16 %mip) { @@ -21,18 +21,36 @@ define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, i16 %mip) { ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: ; return to shader part epilog ; +; GFX10-LABEL: getresinfo_1d: +; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: v_lshlrev_b32_e64 v1, 16, s0 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: getresinfo_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_lshl_or_b32 v0, s0, 16, v0 +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm a16 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_1d: ; GFX12: ; %bb.0: ; %main_body ; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_lshl_or_b32 v0, s0, 16, v0 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D a16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -58,18 +76,36 @@ define amdgpu_ps <4 x float> @getresinfo_2d(<8 x i32> inreg %rsrc, i16 %mip) { ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: ; return to shader part epilog ; +; GFX10-LABEL: getresinfo_2d: +; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: v_lshlrev_b32_e64 v1, 16, s0 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: getresinfo_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_lshl_or_b32 v0, s0, 16, v0 +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm a16 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_2d: ; GFX12: ; %bb.0: ; %main_body ; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_lshl_or_b32 v0, s0, 16, v0 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D a16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -95,18 +131,36 @@ define amdgpu_ps <4 x float> @getresinfo_3d(<8 x i32> inreg %rsrc, i16 %mip) { ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: ; return to shader part epilog ; +; GFX10-LABEL: getresinfo_3d: +; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: v_lshlrev_b32_e64 v1, 16, s0 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: getresinfo_3d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_lshl_or_b32 v0, s0, 16, v0 +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_3d: ; GFX12: ; %bb.0: ; %main_body ; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_lshl_or_b32 v0, s0, 16, v0 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -132,18 +186,36 @@ define amdgpu_ps <4 x float> @getresinfo_cube(<8 x i32> inreg %rsrc, i16 %mip) { ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: ; return to shader part epilog ; +; GFX10-LABEL: getresinfo_cube: +; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: v_lshlrev_b32_e64 v1, 16, s0 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm a16 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: getresinfo_cube: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_lshl_or_b32 v0, s0, 16, v0 +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm a16 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_cube: ; GFX12: ; %bb.0: ; %main_body ; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_lshl_or_b32 v0, s0, 16, v0 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE a16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -169,18 +241,36 @@ define amdgpu_ps <4 x float> @getresinfo_1darray(<8 x i32> inreg %rsrc, i16 %mip ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: ; return to shader part epilog ; +; GFX10-LABEL: getresinfo_1darray: +; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: v_lshlrev_b32_e64 v1, 16, s0 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm a16 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: getresinfo_1darray: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_lshl_or_b32 v0, s0, 16, v0 +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm a16 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_1darray: ; GFX12: ; %bb.0: ; %main_body ; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_lshl_or_b32 v0, s0, 16, v0 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY a16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -206,18 +296,36 @@ define amdgpu_ps <4 x float> @getresinfo_2darray(<8 x i32> inreg %rsrc, i16 %mip ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: ; return to shader part epilog ; +; GFX10-LABEL: getresinfo_2darray: +; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: v_lshlrev_b32_e64 v1, 16, s0 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm a16 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: getresinfo_2darray: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_lshl_or_b32 v0, s0, 16, v0 +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm a16 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_2darray: ; GFX12: ; %bb.0: ; %main_body ; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_lshl_or_b32 v0, s0, 16, v0 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY a16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -243,18 +351,36 @@ define amdgpu_ps <4 x float> @getresinfo_2dmsaa(<8 x i32> inreg %rsrc, i16 %mip) ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: ; return to shader part epilog ; +; GFX10-LABEL: getresinfo_2dmsaa: +; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: v_lshlrev_b32_e64 v1, 16, s0 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA unorm a16 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: getresinfo_2dmsaa: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_lshl_or_b32 v0, s0, 16, v0 +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA unorm a16 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_2dmsaa: ; GFX12: ; %bb.0: ; %main_body ; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_lshl_or_b32 v0, s0, 16, v0 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA a16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -280,18 +406,36 @@ define amdgpu_ps <4 x float> @getresinfo_2darraymsaa(<8 x i32> inreg %rsrc, i16 ; GFX9-NEXT: s_waitcnt vmcnt(0) ; GFX9-NEXT: ; return to shader part epilog ; +; GFX10-LABEL: getresinfo_2darraymsaa: +; GFX10: ; %bb.0: ; %main_body +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: v_lshlrev_b32_e64 v1, 16, s0 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_0 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: getresinfo_2darraymsaa: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-NEXT: v_lshl_or_b32 v0, s0, 16, v0 +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_2darraymsaa: ; GFX12: ; %bb.0: ; %main_body ; GFX12-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_lshl_or_b32 v0, s0, 16, v0 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -309,6 +453,10 @@ define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x floa ; GFX10: ; %bb.0: ; %main_body ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: getresinfo_dmask0: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_dmask0: ; GFX12: ; %bb.0: ; %main_body ; GFX12-NEXT: ; return to shader part epilog diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll index 51320df9f3490b..8d74988348d671 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.getresinfo.ll @@ -2,7 +2,7 @@ ; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d < %s | FileCheck -check-prefix=GFX6 %s ; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d < %s | FileCheck -check-prefix=GFX8 %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefix=GFX10 %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d < %s | FileCheck -check-prefix=GFX10 %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d < %s | FileCheck -check-prefix=GFX11 %s ; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d < %s | FileCheck -check-prefix=GFX12 %s define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, i32 %mip) { @@ -48,16 +48,14 @@ define amdgpu_ps <4 x float> @getresinfo_1d(<8 x i32> inreg %rsrc, i32 %mip) { ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: getresinfo_1d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_1d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -109,16 +107,14 @@ define amdgpu_ps <4 x float> @getresinfo_2d(<8 x i32> inreg %rsrc, i32 %mip) { ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: getresinfo_2d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_2d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -170,16 +166,14 @@ define amdgpu_ps <4 x float> @getresinfo_3d(<8 x i32> inreg %rsrc, i32 %mip) { ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: getresinfo_3d: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_3d: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -231,16 +225,14 @@ define amdgpu_ps <4 x float> @getresinfo_cube(<8 x i32> inreg %rsrc, i32 %mip) { ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: getresinfo_cube: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE unorm +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_cube: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_CUBE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -292,16 +284,14 @@ define amdgpu_ps <4 x float> @getresinfo_1darray(<8 x i32> inreg %rsrc, i32 %mip ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: getresinfo_1darray: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY unorm +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_1darray: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D_ARRAY ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -353,16 +343,14 @@ define amdgpu_ps <4 x float> @getresinfo_2darray(<8 x i32> inreg %rsrc, i32 %mip ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: getresinfo_2darray: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY unorm +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_2darray: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_ARRAY ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -414,16 +402,14 @@ define amdgpu_ps <4 x float> @getresinfo_2dmsaa(<8 x i32> inreg %rsrc, i32 %mip) ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: getresinfo_2dmsaa: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA unorm +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_2dmsaa: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -475,16 +461,14 @@ define amdgpu_ps <4 x float> @getresinfo_2darraymsaa(<8 x i32> inreg %rsrc, i32 ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: getresinfo_2darraymsaa: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_2darraymsaa: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -536,16 +520,14 @@ define amdgpu_ps <3 x float> @getresinfo_dmask7(<8 x i32> inreg %rsrc, <4 x floa ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: getresinfo_dmask7: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_get_resinfo v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_dmask7: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -597,16 +579,14 @@ define amdgpu_ps <2 x float> @getresinfo_dmask3(<8 x i32> inreg %rsrc, <4 x floa ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: getresinfo_dmask3: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_get_resinfo v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_dmask3: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -658,16 +638,14 @@ define amdgpu_ps float @getresinfo_dmask1(<8 x i32> inreg %rsrc, <4 x float> %vd ; GFX10-NEXT: s_waitcnt vmcnt(0) ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: getresinfo_dmask1: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: image_get_resinfo v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_dmask1: ; GFX12: ; %bb.0: ; %main_body -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_get_resinfo v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -689,6 +667,10 @@ define amdgpu_ps <4 x float> @getresinfo_dmask0(<8 x i32> inreg %rsrc, <4 x floa ; GFX10: ; %bb.0: ; %main_body ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: getresinfo_dmask0: +; GFX11: ; %bb.0: ; %main_body +; GFX11-NEXT: ; return to shader part epilog +; ; GFX12-LABEL: getresinfo_dmask0: ; GFX12: ; %bb.0: ; %main_body ; GFX12-NEXT: ; return to shader part epilog diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll index 0c1195ff3f640c..26d5304923643f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.d16.ll @@ -65,28 +65,12 @@ define amdgpu_ps half @load_1d_f16_x(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_f16_x: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_f16_x: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D d16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -153,28 +137,12 @@ define amdgpu_ps half @load_1d_f16_y(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_f16_y: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D unorm d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_f16_y: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D d16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -241,28 +209,12 @@ define amdgpu_ps half @load_1d_f16_z(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_f16_z: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_1D unorm d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_f16_z: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_1D d16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -329,28 +281,12 @@ define amdgpu_ps half @load_1d_f16_w(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_f16_w: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D unorm d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_f16_w: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D d16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -420,28 +356,12 @@ define amdgpu_ps <2 x half> @load_1d_v2f16_xy(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_v2f16_xy: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_v2f16_xy: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D d16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -511,28 +431,12 @@ define amdgpu_ps <2 x half> @load_1d_v2f16_xz(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_v2f16_xz: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x5 dim:SQ_RSRC_IMG_1D unorm d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_v2f16_xz: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x5 dim:SQ_RSRC_IMG_1D d16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -602,28 +506,12 @@ define amdgpu_ps <2 x half> @load_1d_v2f16_xw(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_v2f16_xw: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D unorm d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_v2f16_xw: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D d16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -693,28 +581,12 @@ define amdgpu_ps <2 x half> @load_1d_v2f16_yz(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_v2f16_yz: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D unorm d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_v2f16_yz: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D d16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -786,28 +658,12 @@ define amdgpu_ps <3 x half> @load_1d_v3f16_xyz(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_v3f16_xyz: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_v3f16_xyz: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D d16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -880,28 +736,12 @@ define amdgpu_ps <4 x half> @load_1d_v4f16_xyzw(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_v4f16_xyzw: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_v4f16_xyzw: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v[0:1], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D d16 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -981,14 +821,7 @@ define amdgpu_ps float @load_1d_f16_tfe_dmask_x(<8 x i32> inreg %rsrc, i32 %s) { ; GFX11-LABEL: load_1d_f16_tfe_dmask_x: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 ; GFX11-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -998,18 +831,10 @@ define amdgpu_ps float @load_1d_f16_tfe_dmask_x(<8 x i32> inreg %rsrc, i32 %s) { ; GFX12-LABEL: load_1d_f16_tfe_dmask_x: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v2, v1 ; GFX12-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe d16 ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v2 ; GFX12-NEXT: ; return to shader part epilog %v = call { half, i32 } @llvm.amdgcn.image.load.1d.sl_f16i32s.i32(i32 1, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) @@ -1091,14 +916,7 @@ define amdgpu_ps float @load_1d_v2f16_tfe_dmask_xy(<8 x i32> inreg %rsrc, i32 %s ; GFX11-LABEL: load_1d_v2f16_tfe_dmask_xy: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 ; GFX11-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1108,18 +926,10 @@ define amdgpu_ps float @load_1d_v2f16_tfe_dmask_xy(<8 x i32> inreg %rsrc, i32 %s ; GFX12-LABEL: load_1d_v2f16_tfe_dmask_xy: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v2, v1 ; GFX12-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe d16 ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v2 ; GFX12-NEXT: ; return to shader part epilog %v = call { <2 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f16i32s.i32(i32 3, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) @@ -1205,14 +1015,7 @@ define amdgpu_ps float @load_1d_v3f16_tfe_dmask_xyz(<8 x i32> inreg %rsrc, i32 % ; GFX11-LABEL: load_1d_v3f16_tfe_dmask_xyz: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 ; GFX11-NEXT: v_mov_b32_e32 v3, v1 ; GFX11-NEXT: image_load v[1:3], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm tfe d16 @@ -1223,18 +1026,10 @@ define amdgpu_ps float @load_1d_v3f16_tfe_dmask_xyz(<8 x i32> inreg %rsrc, i32 % ; GFX12-LABEL: load_1d_v3f16_tfe_dmask_xyz: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v3, v1 ; GFX12-NEXT: image_load v[1:3], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D tfe d16 ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v3 ; GFX12-NEXT: ; return to shader part epilog %v = call { <3 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v3f16i32s.i32(i32 7, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) @@ -1315,14 +1110,7 @@ define amdgpu_ps float @load_1d_v4f16_tfe_dmask_xyzw(<8 x i32> inreg %rsrc, i32 ; GFX11-LABEL: load_1d_v4f16_tfe_dmask_xyzw: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 ; GFX11-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x10 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1332,18 +1120,10 @@ define amdgpu_ps float @load_1d_v4f16_tfe_dmask_xyzw(<8 x i32> inreg %rsrc, i32 ; GFX12-LABEL: load_1d_v4f16_tfe_dmask_xyzw: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v2, v1 ; GFX12-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x10 dim:SQ_RSRC_IMG_1D tfe d16 ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v2 ; GFX12-NEXT: ; return to shader part epilog %v = call { <4 x half>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f16i32s.i32(i32 16, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll index edbc80802353f7..88d48304c5a6ee 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.1d.ll @@ -51,28 +51,12 @@ define amdgpu_ps float @load_1d_f32_x(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_f32_x: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_f32_x: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -125,28 +109,12 @@ define amdgpu_ps float @load_1d_f32_y(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_f32_y: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D unorm ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_f32_y: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -199,28 +167,12 @@ define amdgpu_ps float @load_1d_f32_z(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_f32_z: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_1D unorm ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_f32_z: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -273,28 +225,12 @@ define amdgpu_ps float @load_1d_f32_w(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_f32_w: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D unorm ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_f32_w: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v0, v0, s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -347,28 +283,12 @@ define amdgpu_ps <2 x float> @load_1d_v2f32_xy(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_v2f32_xy: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_v2f32_xy: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -421,28 +341,12 @@ define amdgpu_ps <2 x float> @load_1d_v2f32_xz(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_v2f32_xz: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x5 dim:SQ_RSRC_IMG_1D unorm ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_v2f32_xz: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x5 dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -495,28 +399,12 @@ define amdgpu_ps <2 x float> @load_1d_v2f32_xw(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_v2f32_xw: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D unorm ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_v2f32_xw: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x9 dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -569,28 +457,12 @@ define amdgpu_ps <2 x float> @load_1d_v2f32_yz(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_v2f32_yz: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D unorm ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_v2f32_yz: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v[0:1], v0, s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -643,28 +515,12 @@ define amdgpu_ps <3 x float> @load_1d_v3f32_xyz(<8 x i32> inreg %rsrc, i32 %s) { ; ; GFX11-LABEL: load_1d_v3f32_xyz: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_v3f32_xyz: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v[0:2], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -717,28 +573,12 @@ define amdgpu_ps <4 x float> @load_1d_v4f32_xyzw(<8 x i32> inreg %rsrc, i32 %s) ; ; GFX11-LABEL: load_1d_v4f32_xyzw: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_1d_v4f32_xyzw: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v[0:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -800,14 +640,7 @@ define amdgpu_ps float @load_1d_f32_tfe_dmask_x(<8 x i32> inreg %rsrc, i32 %s) { ; GFX11-LABEL: load_1d_f32_tfe_dmask_x: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 ; GFX11-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -817,18 +650,10 @@ define amdgpu_ps float @load_1d_f32_tfe_dmask_x(<8 x i32> inreg %rsrc, i32 %s) { ; GFX12-LABEL: load_1d_f32_tfe_dmask_x: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v2, v1 ; GFX12-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v2 ; GFX12-NEXT: ; return to shader part epilog %v = call { float, i32 } @llvm.amdgcn.image.load.1d.sl_f32i32s.i32(i32 1, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) @@ -893,14 +718,7 @@ define amdgpu_ps float @load_1d_v2f32_tfe_dmask_xy(<8 x i32> inreg %rsrc, i32 %s ; GFX11-LABEL: load_1d_v2f32_tfe_dmask_xy: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 ; GFX11-NEXT: v_mov_b32_e32 v3, v1 ; GFX11-NEXT: image_load v[1:3], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm tfe @@ -911,18 +729,10 @@ define amdgpu_ps float @load_1d_v2f32_tfe_dmask_xy(<8 x i32> inreg %rsrc, i32 %s ; GFX12-LABEL: load_1d_v2f32_tfe_dmask_xy: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v3, v1 ; GFX12-NEXT: image_load v[1:3], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D tfe ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v3 ; GFX12-NEXT: ; return to shader part epilog %v = call { <2 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v2f32i32s.i32(i32 3, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) @@ -989,14 +799,7 @@ define amdgpu_ps float @load_1d_v3f32_tfe_dmask_xyz(<8 x i32> inreg %rsrc, i32 % ; GFX11-LABEL: load_1d_v3f32_tfe_dmask_xyz: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 ; GFX11-NEXT: v_mov_b32_e32 v3, v1 ; GFX11-NEXT: v_mov_b32_e32 v4, v1 @@ -1008,19 +811,11 @@ define amdgpu_ps float @load_1d_v3f32_tfe_dmask_xyz(<8 x i32> inreg %rsrc, i32 % ; GFX12-LABEL: load_1d_v3f32_tfe_dmask_xyz: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v3, v1 ; GFX12-NEXT: v_mov_b32_e32 v4, v1 ; GFX12-NEXT: image_load v[1:4], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D tfe ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v4 ; GFX12-NEXT: ; return to shader part epilog %v = call { <3 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v3f32i32s.i32(i32 7, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) @@ -1083,14 +878,7 @@ define amdgpu_ps float @load_1d_v4f32_tfe_dmask_xyzw(<8 x i32> inreg %rsrc, i32 ; GFX11-LABEL: load_1d_v4f32_tfe_dmask_xyzw: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 ; GFX11-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x10 dim:SQ_RSRC_IMG_1D unorm tfe ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1100,18 +888,10 @@ define amdgpu_ps float @load_1d_v4f32_tfe_dmask_xyzw(<8 x i32> inreg %rsrc, i32 ; GFX12-LABEL: load_1d_v4f32_tfe_dmask_xyzw: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v2, v1 ; GFX12-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x10 dim:SQ_RSRC_IMG_1D tfe ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v2 ; GFX12-NEXT: ; return to shader part epilog %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.1d.sl_v4f32i32s.i32(i32 16, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) @@ -1174,14 +954,7 @@ define amdgpu_ps float @load_1d_f32_tfe_dmask_0(<8 x i32> inreg %rsrc, i32 %s) { ; GFX11-LABEL: load_1d_f32_tfe_dmask_0: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 ; GFX11-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1191,18 +964,10 @@ define amdgpu_ps float @load_1d_f32_tfe_dmask_0(<8 x i32> inreg %rsrc, i32 %s) { ; GFX12-LABEL: load_1d_f32_tfe_dmask_0: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v2, v1 ; GFX12-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D tfe ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v2 ; GFX12-NEXT: ; return to shader part epilog %v = call { float, i32 } @llvm.amdgcn.image.load.1d.sl_f32i32s.i32(i32 0, i32 %s, <8 x i32> %rsrc, i32 1, i32 0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll index 81d48b48b8b50f..3fc31d0732adb1 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2d.ll @@ -19,30 +19,28 @@ define amdgpu_ps <4 x float> @load_2d_v4f32_xyzw(<8 x i32> inreg %rsrc, i32 %s, ; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: load_2d_v4f32_xyzw: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_mov_b32 s6, s8 -; GFX10PLUS-NEXT: s_mov_b32 s7, s9 -; GFX10PLUS-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm -; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: load_2d_v4f32_xyzw: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: load_2d_v4f32_xyzw: +; GFX11: ; %bb.0: +; GFX11-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_2d_v4f32_xyzw: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -109,48 +107,34 @@ define amdgpu_ps <4 x float> @load_2d_v4f32_xyzw_tfe(<8 x i32> inreg %rsrc, ptr ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v7, 0 ; GFX11-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_mov_b32_e32 v8, v7 ; GFX11-NEXT: v_mov_b32_e32 v9, v7 ; GFX11-NEXT: v_mov_b32_e32 v10, v7 ; GFX11-NEXT: v_mov_b32_e32 v11, v7 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10 ; GFX11-NEXT: v_mov_b32_e32 v4, v11 ; GFX11-NEXT: image_load v[0:4], v[5:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b32 v7, v4, s[10:11] +; GFX11-NEXT: global_store_b32 v7, v4, s[8:9] ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_2d_v4f32_xyzw_tfe: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v7, 0 ; GFX12-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v9, v7 ; GFX12-NEXT: v_dual_mov_b32 v10, v7 :: v_dual_mov_b32 v11, v7 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-NEXT: v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10 ; GFX12-NEXT: v_mov_b32_e32 v4, v11 ; GFX12-NEXT: image_load v[0:4], [v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D tfe ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b32 v7, v4, s[10:11] +; GFX12-NEXT: global_store_b32 v7, v4, s[8:9] ; GFX12-NEXT: ; return to shader part epilog %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 1, i32 0) %v.vec = extractvalue { <4 x float>, i32 } %v, 0 @@ -218,48 +202,34 @@ define amdgpu_ps <4 x float> @load_2d_v4f32_xyzw_tfe_lwe(<8 x i32> inreg %rsrc, ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v7, 0 ; GFX11-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_mov_b32_e32 v8, v7 ; GFX11-NEXT: v_mov_b32_e32 v9, v7 ; GFX11-NEXT: v_mov_b32_e32 v10, v7 ; GFX11-NEXT: v_mov_b32_e32 v11, v7 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10 ; GFX11-NEXT: v_mov_b32_e32 v4, v11 ; GFX11-NEXT: image_load v[0:4], v[5:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm tfe lwe ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b32 v7, v4, s[10:11] +; GFX11-NEXT: global_store_b32 v7, v4, s[8:9] ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_2d_v4f32_xyzw_tfe_lwe: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v7, 0 ; GFX12-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v9, v7 ; GFX12-NEXT: v_dual_mov_b32 v10, v7 :: v_dual_mov_b32 v11, v7 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-NEXT: v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10 ; GFX12-NEXT: v_mov_b32_e32 v4, v11 ; GFX12-NEXT: image_load v[0:4], [v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D tfe ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b32 v7, v4, s[10:11] +; GFX12-NEXT: global_store_b32 v7, v4, s[8:9] ; GFX12-NEXT: ; return to shader part epilog %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 3, i32 0) %v.vec = extractvalue { <4 x float>, i32 } %v, 0 @@ -272,3 +242,5 @@ declare <4 x float> @llvm.amdgcn.image.load.2d.v4f32.i32(i32 immarg, i32, i32, < declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2d.sl_v4f32i32s.i32(i32 immarg, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 attributes #0 = { nounwind readonly } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX10PLUS: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll index 7ca3ae1561b2f2..b698db93830fbc 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.a16.ll @@ -49,14 +49,6 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw(<8 x i32> inreg %rsrc, ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v2 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.h, v1.l ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v3.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_load v[0:3], v[4:5], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -65,16 +57,9 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw(<8 x i32> inreg %rsrc, ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -83,14 +68,6 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw(<8 x i32> inreg %rsrc, ; GFX12-TRUE16: ; %bb.0: ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v2.h, v3.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_load v[0:3], [v0, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -99,16 +76,9 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw(<8 x i32> inreg %rsrc, ; GFX12-FAKE16: ; %bb.0: ; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, v3, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -187,14 +157,6 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, v7 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v7 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, v7 -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v7 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v8 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v9 @@ -202,7 +164,7 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v11 ; GFX11-TRUE16-NEXT: image_load v[0:4], v[5:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: global_store_b32 v7, v4, s[10:11] +; GFX11-TRUE16-NEXT: global_store_b32 v7, v4, s[8:9] ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: load_2darraymsaa_v4f32_xyzw_tfe: @@ -210,20 +172,13 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, 0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, v5 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v5 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, v5 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, v5 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v1, 16, v0 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v3, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v5 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, v6 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, v7 @@ -231,7 +186,7 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v9 ; GFX11-FAKE16-NEXT: image_load v[0:4], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: global_store_b32 v5, v4, s[10:11] +; GFX11-FAKE16-NEXT: global_store_b32 v5, v4, s[8:9] ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: load_2darraymsaa_v4f32_xyzw_tfe: @@ -245,14 +200,6 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v9, v7 ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v10, v7 ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v11, v7 -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, v7 ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v8 ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v9 @@ -260,7 +207,7 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v11 ; GFX12-TRUE16-NEXT: image_load v[0:4], [v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 tfe ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: global_store_b32 v7, v4, s[10:11] +; GFX12-TRUE16-NEXT: global_store_b32 v7, v4, s[8:9] ; GFX12-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-FAKE16-LABEL: load_2darraymsaa_v4f32_xyzw_tfe: @@ -268,20 +215,13 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, 0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5 ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v7, v5 ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v8, v5 ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v9, v5 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v10, v1, 16, v0 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v11, v3, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, v5 ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v6 ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v7 @@ -289,7 +229,7 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v9 ; GFX12-FAKE16-NEXT: image_load v[0:4], [v10, v11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 tfe ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-FAKE16-NEXT: global_store_b32 v5, v4, s[10:11] +; GFX12-FAKE16-NEXT: global_store_b32 v5, v4, s[8:9] ; GFX12-FAKE16-NEXT: ; return to shader part epilog %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 1, i32 0) %v.vec = extractvalue { <4 x float>, i32 } %v, 0 @@ -369,14 +309,6 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, v7 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v7 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, v7 -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v7 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, v8 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, v9 @@ -384,7 +316,7 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v11 ; GFX11-TRUE16-NEXT: image_load v[0:4], v[5:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe lwe ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: global_store_b32 v7, v4, s[10:11] +; GFX11-TRUE16-NEXT: global_store_b32 v7, v4, s[8:9] ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe: @@ -392,20 +324,13 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v5, 0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, v5 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v5 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, v5 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, v5 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v1, 16, v0 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, v3, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v5 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, v6 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v2, v7 @@ -413,7 +338,7 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v9 ; GFX11-FAKE16-NEXT: image_load v[0:4], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm a16 tfe lwe ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: global_store_b32 v5, v4, s[10:11] +; GFX11-FAKE16-NEXT: global_store_b32 v5, v4, s[8:9] ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe: @@ -427,14 +352,6 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v9, v7 ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v10, v7 ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v11, v7 -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v0, v7 ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v1, v8 ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v2, v9 @@ -442,7 +359,7 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v11 ; GFX12-TRUE16-NEXT: image_load v[0:4], [v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 tfe ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: global_store_b32 v7, v4, s[10:11] +; GFX12-TRUE16-NEXT: global_store_b32 v7, v4, s[8:9] ; GFX12-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-FAKE16-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe: @@ -450,20 +367,13 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v5, 0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_3) ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v6, v5 ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v7, v5 ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v8, v5 ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v9, v5 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v10, v1, 16, v0 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v11, v3, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v0, v5 ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v1, v6 ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v2, v7 @@ -471,7 +381,7 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v9 ; GFX12-FAKE16-NEXT: image_load v[0:4], [v10, v11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY a16 tfe ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-FAKE16-NEXT: global_store_b32 v5, v4, s[10:11] +; GFX12-FAKE16-NEXT: global_store_b32 v5, v4, s[8:9] ; GFX12-FAKE16-NEXT: ; return to shader part epilog %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %slice, i16 %fragid, <8 x i32> %rsrc, i32 3, i32 0) %v.vec = extractvalue { <4 x float>, i32 } %v, 0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll index 355c09ccde714a..e3d3ae02f52684 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.2darraymsaa.ll @@ -19,30 +19,28 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw(<8 x i32> inreg %rsrc, ; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: load_2darraymsaa_v4f32_xyzw: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_mov_b32 s6, s8 -; GFX10PLUS-NEXT: s_mov_b32 s7, s9 -; GFX10PLUS-NEXT: image_load v[0:3], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm -; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: load_2darraymsaa_v4f32_xyzw: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: image_load v[0:3], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: load_2darraymsaa_v4f32_xyzw: +; GFX11: ; %bb.0: +; GFX11-NEXT: image_load v[0:3], v[0:3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_2darraymsaa_v4f32_xyzw: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v[0:3], [v0, v1, v2, v3], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -114,25 +112,18 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r ; GFX11-NEXT: v_mov_b32_e32 v9, 0 ; GFX11-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1 ; GFX11-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v8, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_mov_b32_e32 v10, v9 ; GFX11-NEXT: v_mov_b32_e32 v11, v9 ; GFX11-NEXT: v_mov_b32_e32 v12, v9 ; GFX11-NEXT: v_mov_b32_e32 v13, v9 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12 ; GFX11-NEXT: v_mov_b32_e32 v4, v13 ; GFX11-NEXT: image_load v[0:4], v[5:8], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b32 v9, v4, s[10:11] +; GFX11-NEXT: global_store_b32 v9, v4, s[8:9] ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_2darraymsaa_v4f32_xyzw_tfe: @@ -140,23 +131,16 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe(<8 x i32> inreg %r ; GFX12-NEXT: v_mov_b32_e32 v9, 0 ; GFX12-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1 ; GFX12-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v8, v3 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_dual_mov_b32 v10, v9 :: v_dual_mov_b32 v11, v9 ; GFX12-NEXT: v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v9 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-NEXT: v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12 ; GFX12-NEXT: v_mov_b32_e32 v4, v13 ; GFX12-NEXT: image_load v[0:4], [v5, v6, v7, v8], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY tfe ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b32 v9, v4, s[10:11] +; GFX12-NEXT: global_store_b32 v9, v4, s[8:9] ; GFX12-NEXT: ; return to shader part epilog %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 1, i32 0) %v.vec = extractvalue { <4 x float>, i32 } %v, 0 @@ -229,25 +213,18 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre ; GFX11-NEXT: v_mov_b32_e32 v9, 0 ; GFX11-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1 ; GFX11-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v8, v3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_mov_b32_e32 v10, v9 ; GFX11-NEXT: v_mov_b32_e32 v11, v9 ; GFX11-NEXT: v_mov_b32_e32 v12, v9 ; GFX11-NEXT: v_mov_b32_e32 v13, v9 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12 ; GFX11-NEXT: v_mov_b32_e32 v4, v13 ; GFX11-NEXT: image_load v[0:4], v[5:8], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY unorm tfe lwe ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b32 v9, v4, s[10:11] +; GFX11-NEXT: global_store_b32 v9, v4, s[8:9] ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_2darraymsaa_v4f32_xyzw_tfe_lwe: @@ -255,23 +232,16 @@ define amdgpu_ps <4 x float> @load_2darraymsaa_v4f32_xyzw_tfe_lwe(<8 x i32> inre ; GFX12-NEXT: v_mov_b32_e32 v9, 0 ; GFX12-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1 ; GFX12-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v8, v3 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_dual_mov_b32 v10, v9 :: v_dual_mov_b32 v11, v9 ; GFX12-NEXT: v_dual_mov_b32 v12, v9 :: v_dual_mov_b32 v13, v9 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: v_dual_mov_b32 v0, v9 :: v_dual_mov_b32 v1, v10 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-NEXT: v_dual_mov_b32 v2, v11 :: v_dual_mov_b32 v3, v12 ; GFX12-NEXT: v_mov_b32_e32 v4, v13 ; GFX12-NEXT: image_load v[0:4], [v5, v6, v7, v8], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D_MSAA_ARRAY tfe ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b32 v9, v4, s[10:11] +; GFX12-NEXT: global_store_b32 v9, v4, s[8:9] ; GFX12-NEXT: ; return to shader part epilog %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %slice, i32 %fragid, <8 x i32> %rsrc, i32 3, i32 0) %v.vec = extractvalue { <4 x float>, i32 } %v, 0 @@ -284,3 +254,5 @@ declare <4 x float> @llvm.amdgcn.image.load.2darraymsaa.v4f32.i32(i32 immarg, i3 declare { <4 x float>, i32 } @llvm.amdgcn.image.load.2darraymsaa.sl_v4f32i32s.i32(i32 immarg, i32, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 attributes #0 = { nounwind readonly } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX10PLUS: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll index 1bd95c656c6e89..455d69eb492636 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.a16.ll @@ -46,14 +46,6 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw(<8 x i32> inreg %rsrc, i16 %s, ; GFX11-TRUE16-LABEL: load_3d_v4f32_xyzw: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: image_load v[0:3], [v0, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -62,16 +54,9 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw(<8 x i32> inreg %rsrc, i16 %s, ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: image_load v[0:3], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -79,14 +64,6 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw(<8 x i32> inreg %rsrc, i16 %s, ; GFX12-TRUE16-LABEL: load_3d_v4f32_xyzw: ; GFX12-TRUE16: ; %bb.0: ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v0.h, v1.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: image_load v[0:3], [v0, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-TRUE16-NEXT: ; return to shader part epilog @@ -95,16 +72,9 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw(<8 x i32> inreg %rsrc, i16 %s, ; GFX12-FAKE16: ; %bb.0: ; GFX12-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v1, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: image_load v[0:3], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-FAKE16-NEXT: ; return to shader part epilog @@ -177,51 +147,36 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe(<8 x i32> inreg %rsrc, ptr ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v7, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v0 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v1.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, v7 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, v7 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v7 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, v7 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v11 ; GFX11-TRUE16-NEXT: image_load v[0:4], v[5:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: global_store_b32 v7, v4, s[10:11] +; GFX11-TRUE16-NEXT: global_store_b32 v7, v4, s[8:9] ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: load_3d_v4f32_xyzw_tfe: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0xffff, v0 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_and_b32 v2, 0xffff, v2 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, v5 -; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v5 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, v5 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, v5 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v1, 16, v0 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v9 ; GFX11-FAKE16-NEXT: image_load v[0:4], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: global_store_b32 v5, v4, s[10:11] +; GFX11-FAKE16-NEXT: global_store_b32 v5, v4, s[8:9] ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: load_3d_v4f32_xyzw_tfe: @@ -229,48 +184,35 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe(<8 x i32> inreg %rsrc, ptr ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, 0 ; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v2 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v1.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v9, v7 ; GFX12-TRUE16-NEXT: v_dual_mov_b32 v10, v7 :: v_dual_mov_b32 v11, v7 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10 ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v11 ; GFX12-TRUE16-NEXT: image_load v[0:4], [v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 tfe ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: global_store_b32 v7, v4, s[10:11] +; GFX12-TRUE16-NEXT: global_store_b32 v7, v4, s[8:9] ; GFX12-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-FAKE16-LABEL: load_3d_v4f32_xyzw_tfe: ; GFX12-FAKE16: ; %bb.0: ; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0xffff, v0 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX12-FAKE16-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_and_b32 v2, 0xffff, v2 ; GFX12-FAKE16-NEXT: v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v9, v5 -; GFX12-FAKE16-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v8, v5 +; GFX12-FAKE16-NEXT: v_mov_b32_e32 v8, v5 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v10, v1, 16, v0 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v11, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v9 ; GFX12-FAKE16-NEXT: image_load v[0:4], [v10, v11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 tfe ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-FAKE16-NEXT: global_store_b32 v5, v4, s[10:11] +; GFX12-FAKE16-NEXT: global_store_b32 v5, v4, s[8:9] ; GFX12-FAKE16-NEXT: ; return to shader part epilog %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 1, i32 0) %v.vec = extractvalue { <4 x float>, i32 } %v, 0 @@ -344,51 +286,36 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe_lwe(<8 x i32> inreg %rsrc, ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v6, v2 :: v_dual_mov_b32 v7, 0 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v5, v0 ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.h, v1.l -; GFX11-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX11-TRUE16-NEXT: s_mov_b32 s1, s3 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, v7 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, v7 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v7 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, v7 -; GFX11-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX11-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX11-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX11-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX11-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8 +; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-TRUE16-NEXT: v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10 ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v11 ; GFX11-TRUE16-NEXT: image_load v[0:4], v[5:6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe lwe ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-TRUE16-NEXT: global_store_b32 v7, v4, s[10:11] +; GFX11-TRUE16-NEXT: global_store_b32 v7, v4, s[8:9] ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: load_3d_v4f32_xyzw_tfe_lwe: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0xffff, v0 -; GFX11-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX11-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-FAKE16-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_and_b32 v2, 0xffff, v2 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v6, v5 -; GFX11-FAKE16-NEXT: v_mov_b32_e32 v7, v5 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v8, v5 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v9, v5 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v10, v1, 16, v0 ; GFX11-FAKE16-NEXT: v_lshl_or_b32 v11, s0, 16, v2 -; GFX11-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX11-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX11-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX11-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX11-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX11-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6 ; GFX11-FAKE16-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v4, v9 ; GFX11-FAKE16-NEXT: image_load v[0:4], v[10:11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm a16 tfe lwe ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) -; GFX11-FAKE16-NEXT: global_store_b32 v5, v4, s[10:11] +; GFX11-FAKE16-NEXT: global_store_b32 v5, v4, s[8:9] ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-TRUE16-LABEL: load_3d_v4f32_xyzw_tfe_lwe: @@ -396,48 +323,35 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe_lwe(<8 x i32> inreg %rsrc, ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v7, 0 ; GFX12-TRUE16-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v2 ; GFX12-TRUE16-NEXT: v_mov_b16_e32 v5.h, v1.l -; GFX12-TRUE16-NEXT: s_mov_b32 s0, s2 -; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-TRUE16-NEXT: v_dual_mov_b32 v8, v7 :: v_dual_mov_b32 v9, v7 ; GFX12-TRUE16-NEXT: v_dual_mov_b32 v10, v7 :: v_dual_mov_b32 v11, v7 -; GFX12-TRUE16-NEXT: s_mov_b32 s1, s3 -; GFX12-TRUE16-NEXT: s_mov_b32 s2, s4 -; GFX12-TRUE16-NEXT: s_mov_b32 s3, s5 -; GFX12-TRUE16-NEXT: s_mov_b32 s4, s6 -; GFX12-TRUE16-NEXT: s_mov_b32 s5, s7 -; GFX12-TRUE16-NEXT: s_mov_b32 s6, s8 -; GFX12-TRUE16-NEXT: s_mov_b32 s7, s9 ; GFX12-TRUE16-NEXT: v_dual_mov_b32 v0, v7 :: v_dual_mov_b32 v1, v8 +; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-TRUE16-NEXT: v_dual_mov_b32 v2, v9 :: v_dual_mov_b32 v3, v10 ; GFX12-TRUE16-NEXT: v_mov_b32_e32 v4, v11 ; GFX12-TRUE16-NEXT: image_load v[0:4], [v5, v6], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 tfe ; GFX12-TRUE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-TRUE16-NEXT: global_store_b32 v7, v4, s[10:11] +; GFX12-TRUE16-NEXT: global_store_b32 v7, v4, s[8:9] ; GFX12-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-FAKE16-LABEL: load_3d_v4f32_xyzw_tfe_lwe: ; GFX12-FAKE16: ; %bb.0: ; GFX12-FAKE16-NEXT: v_dual_mov_b32 v5, 0 :: v_dual_and_b32 v0, 0xffff, v0 -; GFX12-FAKE16-NEXT: v_and_b32_e32 v2, 0xffff, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s0, s2 -; GFX12-FAKE16-NEXT: s_mov_b32 s1, s3 -; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_4) +; GFX12-FAKE16-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_and_b32 v2, 0xffff, v2 ; GFX12-FAKE16-NEXT: v_dual_mov_b32 v6, v5 :: v_dual_mov_b32 v9, v5 -; GFX12-FAKE16-NEXT: v_dual_mov_b32 v7, v5 :: v_dual_mov_b32 v8, v5 +; GFX12-FAKE16-NEXT: v_mov_b32_e32 v8, v5 ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v10, v1, 16, v0 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4) ; GFX12-FAKE16-NEXT: v_lshl_or_b32 v11, s0, 16, v2 -; GFX12-FAKE16-NEXT: s_mov_b32 s2, s4 -; GFX12-FAKE16-NEXT: s_mov_b32 s3, s5 -; GFX12-FAKE16-NEXT: s_mov_b32 s4, s6 -; GFX12-FAKE16-NEXT: s_mov_b32 s5, s7 -; GFX12-FAKE16-NEXT: s_mov_b32 s6, s8 -; GFX12-FAKE16-NEXT: s_mov_b32 s7, s9 ; GFX12-FAKE16-NEXT: v_dual_mov_b32 v0, v5 :: v_dual_mov_b32 v1, v6 +; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_4) ; GFX12-FAKE16-NEXT: v_dual_mov_b32 v2, v7 :: v_dual_mov_b32 v3, v8 ; GFX12-FAKE16-NEXT: v_mov_b32_e32 v4, v9 ; GFX12-FAKE16-NEXT: image_load v[0:4], [v10, v11], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D a16 tfe ; GFX12-FAKE16-NEXT: s_wait_loadcnt 0x0 -; GFX12-FAKE16-NEXT: global_store_b32 v5, v4, s[10:11] +; GFX12-FAKE16-NEXT: global_store_b32 v5, v4, s[8:9] ; GFX12-FAKE16-NEXT: ; return to shader part epilog %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i16(i32 15, i16 %s, i16 %t, i16 %r, <8 x i32> %rsrc, i32 3, i32 0) %v.vec = extractvalue { <4 x float>, i32 } %v, 0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll index da86f3d384e944..3c91ef163f1219 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.load.3d.ll @@ -19,30 +19,28 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw(<8 x i32> inreg %rsrc, i32 %s, ; GFX6-NEXT: s_waitcnt vmcnt(0) ; GFX6-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: load_3d_v4f32_xyzw: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: s_mov_b32 s4, s6 -; GFX10PLUS-NEXT: s_mov_b32 s5, s7 -; GFX10PLUS-NEXT: s_mov_b32 s6, s8 -; GFX10PLUS-NEXT: s_mov_b32 s7, s9 -; GFX10PLUS-NEXT: image_load v[0:3], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm -; GFX10PLUS-NEXT: s_waitcnt vmcnt(0) -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: load_3d_v4f32_xyzw: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: s_mov_b32 s4, s6 +; GFX10-NEXT: s_mov_b32 s5, s7 +; GFX10-NEXT: s_mov_b32 s6, s8 +; GFX10-NEXT: s_mov_b32 s7, s9 +; GFX10-NEXT: image_load v[0:3], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: load_3d_v4f32_xyzw: +; GFX11: ; %bb.0: +; GFX11-NEXT: image_load v[0:3], v[0:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_3d_v4f32_xyzw: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_load v[0:3], [v0, v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -111,48 +109,34 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe(<8 x i32> inreg %rsrc, ptr ; GFX11: ; %bb.0: ; GFX11-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v8, 0 ; GFX11-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_mov_b32_e32 v9, v8 ; GFX11-NEXT: v_mov_b32_e32 v10, v8 ; GFX11-NEXT: v_mov_b32_e32 v11, v8 ; GFX11-NEXT: v_mov_b32_e32 v12, v8 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11 ; GFX11-NEXT: v_mov_b32_e32 v4, v12 ; GFX11-NEXT: image_load v[0:4], v[5:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b32 v8, v4, s[10:11] +; GFX11-NEXT: global_store_b32 v8, v4, s[8:9] ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_3d_v4f32_xyzw_tfe: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v8, 0 ; GFX12-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_dual_mov_b32 v9, v8 :: v_dual_mov_b32 v10, v8 ; GFX12-NEXT: v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v12, v8 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11 ; GFX12-NEXT: v_mov_b32_e32 v4, v12 ; GFX12-NEXT: image_load v[0:4], [v5, v6, v7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D tfe ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b32 v8, v4, s[10:11] +; GFX12-NEXT: global_store_b32 v8, v4, s[8:9] ; GFX12-NEXT: ; return to shader part epilog %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 1, i32 0) %v.vec = extractvalue { <4 x float>, i32 } %v, 0 @@ -222,48 +206,34 @@ define amdgpu_ps <4 x float> @load_3d_v4f32_xyzw_tfe_lwe(<8 x i32> inreg %rsrc, ; GFX11: ; %bb.0: ; GFX11-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v8, 0 ; GFX11-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_3) | instid1(VALU_DEP_4) ; GFX11-NEXT: v_mov_b32_e32 v9, v8 ; GFX11-NEXT: v_mov_b32_e32 v10, v8 ; GFX11-NEXT: v_mov_b32_e32 v11, v8 ; GFX11-NEXT: v_mov_b32_e32 v12, v8 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX11-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11 ; GFX11-NEXT: v_mov_b32_e32 v4, v12 ; GFX11-NEXT: image_load v[0:4], v[5:7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D unorm tfe lwe ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b32 v8, v4, s[10:11] +; GFX11-NEXT: global_store_b32 v8, v4, s[8:9] ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: load_3d_v4f32_xyzw_tfe_lwe: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v8, 0 ; GFX12-NEXT: v_dual_mov_b32 v5, v0 :: v_dual_mov_b32 v6, v1 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2) ; GFX12-NEXT: v_dual_mov_b32 v9, v8 :: v_dual_mov_b32 v10, v8 ; GFX12-NEXT: v_dual_mov_b32 v11, v8 :: v_dual_mov_b32 v12, v8 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: v_dual_mov_b32 v0, v8 :: v_dual_mov_b32 v1, v9 +; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_3) ; GFX12-NEXT: v_dual_mov_b32 v2, v10 :: v_dual_mov_b32 v3, v11 ; GFX12-NEXT: v_mov_b32_e32 v4, v12 ; GFX12-NEXT: image_load v[0:4], [v5, v6, v7], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_3D tfe ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b32 v8, v4, s[10:11] +; GFX12-NEXT: global_store_b32 v8, v4, s[8:9] ; GFX12-NEXT: ; return to shader part epilog %v = call { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i32(i32 15, i32 %s, i32 %t, i32 %r, <8 x i32> %rsrc, i32 3, i32 0) %v.vec = extractvalue { <4 x float>, i32 } %v, 0 @@ -276,3 +246,5 @@ declare <4 x float> @llvm.amdgcn.image.load.3d.v4f32.i32(i32 immarg, i32, i32, i declare { <4 x float>, i32 } @llvm.amdgcn.image.load.3d.sl_v4f32i32s.i32(i32 immarg, i32, i32, i32, <8 x i32>, i32 immarg, i32 immarg) #0 attributes #0 = { nounwind readonly } +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: +; GFX10PLUS: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll index 96d75029cafd65..31a62503ac1dac 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.image.store.2d.ll @@ -47,27 +47,11 @@ define amdgpu_ps void @image_store_f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, fl ; ; GFX11-LABEL: image_store_f32: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_store v2, v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: image_store_f32: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_store v2, [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_endpgm call void @llvm.amdgcn.image.store.2d.f32.i32(float %data, i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) @@ -116,27 +100,11 @@ define amdgpu_ps void @image_store_v2f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ; ; GFX11-LABEL: image_store_v2f32: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_store v[2:3], v[0:1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: image_store_v2f32: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_store v[2:3], [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_endpgm call void @llvm.amdgcn.image.store.2d.v2f32.i32(<2 x float> %in, i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) @@ -185,27 +153,11 @@ define amdgpu_ps void @image_store_v3f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ; ; GFX11-LABEL: image_store_v3f32: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_store v[2:4], v[0:1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D unorm ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: image_store_v3f32: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_store v[2:4], [v0, v1], s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_endpgm call void @llvm.amdgcn.image.store.2d.v3f32.i32(<3 x float> %in, i32 7, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) @@ -254,27 +206,11 @@ define amdgpu_ps void @image_store_v4f32(<8 x i32> inreg %rsrc, i32 %s, i32 %t, ; ; GFX11-LABEL: image_store_v4f32: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_store v[2:5], v[0:1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: image_store_v4f32: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_endpgm call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %in, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) @@ -323,27 +259,11 @@ define amdgpu_ps void @image_store_v4f32_dmask_0001(<8 x i32> inreg %rsrc, i32 % ; ; GFX11-LABEL: image_store_v4f32_dmask_0001: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_store v[2:5], v[0:1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D unorm ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: image_store_v4f32_dmask_0001: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_endpgm call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %in, i32 1, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) @@ -392,27 +312,11 @@ define amdgpu_ps void @image_store_v4f32_dmask_0010(<8 x i32> inreg %rsrc, i32 % ; ; GFX11-LABEL: image_store_v4f32_dmask_0010: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_store v[2:5], v[0:1], s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_2D unorm ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: image_store_v4f32_dmask_0010: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0x2 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_endpgm call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %in, i32 2, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) @@ -461,27 +365,11 @@ define amdgpu_ps void @image_store_v4f32_dmask_0100(<8 x i32> inreg %rsrc, i32 % ; ; GFX11-LABEL: image_store_v4f32_dmask_0100: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_store v[2:5], v[0:1], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D unorm ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: image_store_v4f32_dmask_0100: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0x4 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_endpgm call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %in, i32 4, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) @@ -530,27 +418,11 @@ define amdgpu_ps void @image_store_v4f32_dmask_1000(<8 x i32> inreg %rsrc, i32 % ; ; GFX11-LABEL: image_store_v4f32_dmask_1000: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_store v[2:5], v[0:1], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_2D unorm ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: image_store_v4f32_dmask_1000: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0x8 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_endpgm call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %in, i32 8, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) @@ -599,27 +471,11 @@ define amdgpu_ps void @image_store_v4f32_dmask_0011(<8 x i32> inreg %rsrc, i32 % ; ; GFX11-LABEL: image_store_v4f32_dmask_0011: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_store v[2:5], v[0:1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D unorm ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: image_store_v4f32_dmask_0011: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_endpgm call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %in, i32 3, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) @@ -668,27 +524,11 @@ define amdgpu_ps void @image_store_v4f32_dmask_0110(<8 x i32> inreg %rsrc, i32 % ; ; GFX11-LABEL: image_store_v4f32_dmask_0110: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 ; GFX11-NEXT: image_store v[2:5], v[0:1], s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_2D unorm ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: image_store_v4f32_dmask_0110: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 ; GFX12-NEXT: image_store v[2:5], [v0, v1], s[0:7] dmask:0x6 dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_endpgm call void @llvm.amdgcn.image.store.2d.v4f32.i32(<4 x float> %in, i32 6, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) @@ -743,29 +583,13 @@ define amdgpu_ps void @image_store_f32_dmask_1111(<8 x i32> inreg %rsrc, i32 inr ; ; GFX11-LABEL: image_store_f32_dmask_1111: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_dual_mov_b32 v1, s10 :: v_dual_mov_b32 v2, s11 -; GFX11-NEXT: s_mov_b32 s0, s2 -; GFX11-NEXT: s_mov_b32 s1, s3 -; GFX11-NEXT: s_mov_b32 s2, s4 -; GFX11-NEXT: s_mov_b32 s3, s5 -; GFX11-NEXT: s_mov_b32 s4, s6 -; GFX11-NEXT: s_mov_b32 s5, s7 -; GFX11-NEXT: s_mov_b32 s6, s8 -; GFX11-NEXT: s_mov_b32 s7, s9 +; GFX11-NEXT: v_dual_mov_b32 v1, s8 :: v_dual_mov_b32 v2, s9 ; GFX11-NEXT: image_store v0, v[1:2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D unorm ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: image_store_f32_dmask_1111: ; GFX12: ; %bb.0: -; GFX12-NEXT: v_dual_mov_b32 v1, s10 :: v_dual_mov_b32 v2, s11 -; GFX12-NEXT: s_mov_b32 s0, s2 -; GFX12-NEXT: s_mov_b32 s1, s3 -; GFX12-NEXT: s_mov_b32 s2, s4 -; GFX12-NEXT: s_mov_b32 s3, s5 -; GFX12-NEXT: s_mov_b32 s4, s6 -; GFX12-NEXT: s_mov_b32 s5, s7 -; GFX12-NEXT: s_mov_b32 s6, s8 -; GFX12-NEXT: s_mov_b32 s7, s9 +; GFX12-NEXT: v_dual_mov_b32 v1, s8 :: v_dual_mov_b32 v2, s9 ; GFX12-NEXT: image_store v0, [v1, v2], s[0:7] dmask:0xf dim:SQ_RSRC_IMG_2D ; GFX12-NEXT: s_endpgm tail call void @llvm.amdgcn.image.store.2d.f32.i32(float %in, i32 15, i32 %s, i32 %t, <8 x i32> %rsrc, i32 0, i32 0) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ptr.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ptr.s.buffer.load.ll index 72bc174397922f..e4797843dd2288 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ptr.s.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.ptr.s.buffer.load.ll @@ -59,13 +59,13 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32(ptr addrspace(8) inreg %rsrc, i32 in ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] @@ -127,13 +127,13 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_glc(ptr addrspace(8) inreg %rsrc, i3 ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_glc ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] @@ -210,13 +210,13 @@ define amdgpu_ps <2 x i32> @ptr_s_buffer_load_v2i32(ptr addrspace(8) inreg %rsrc ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v2i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (<2 x i32>) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM]].sub0 @@ -313,13 +313,13 @@ define amdgpu_ps <3 x i32> @ptr_s_buffer_load_v3i32(ptr addrspace(8) inreg %rsrc ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v3i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM:%[0-9]+]]:sgpr_96 = S_BUFFER_LOAD_DWORDX3_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (<3 x i32>) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub0 @@ -477,13 +477,13 @@ define amdgpu_ps <8 x i32> @ptr_s_buffer_load_v8i32(ptr addrspace(8) inreg %rsrc ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v8i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (<8 x i32>) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub0 @@ -757,13 +757,13 @@ define amdgpu_ps <16 x i32> @ptr_s_buffer_load_v16i32(ptr addrspace(8) inreg %rs ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v16i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (<16 x i32>) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub0 @@ -885,12 +885,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1(ptr addrspace(8) inreg %rsr ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -949,12 +949,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_glc_4(ptr addrspace(8) inreg ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_glc_4 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 4, 1 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1015,12 +1015,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_255(ptr addrspace(8) inreg %r ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_255 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 255, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1079,12 +1079,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_256(ptr addrspace(8) inreg %r ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_256 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 256, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1143,12 +1143,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1020(ptr addrspace(8) inreg % ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1020 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1020, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1209,12 +1209,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1023(ptr addrspace(8) inreg % ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1023 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1023, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1274,12 +1274,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1024(ptr addrspace(8) inreg % ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1024 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1024, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1340,12 +1340,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_1025(ptr addrspace(8) inreg % ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_1025 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1025, 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1407,12 +1407,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg1(ptr addrspace(8) inreg % ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg1 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) @@ -1474,12 +1474,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg4(ptr addrspace(8) inreg % ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg4 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) @@ -1541,12 +1541,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg8(ptr addrspace(8) inreg % ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg8 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) @@ -1608,12 +1608,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit31(ptr addrspace(8) inreg ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit31 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) @@ -1675,12 +1675,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_glc_bit30(ptr addrspace(8) in ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_glc_bit30 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741824 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 1 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) @@ -1742,12 +1742,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit29(ptr addrspace(8) inreg ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit29 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 536870912 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) @@ -1809,12 +1809,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit21(ptr addrspace(8) inreg ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit21 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 2097152, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1875,12 +1875,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit20(ptr addrspace(8) inreg ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit20 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1048576, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1941,12 +1941,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg_bit20(ptr addrspace(8) in ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit20 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1048576 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) @@ -2007,12 +2007,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_bit19(ptr addrspace(8) inreg ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_bit19 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 524288, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -2073,12 +2073,12 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32_offset_neg_bit19(ptr addrspace(8) in ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32_offset_neg_bit19 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -524288 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (i32) from %ir.desc, align 1, addrspace 8) @@ -2139,12 +2139,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset(ptr addrspace(8) inreg ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) @@ -2211,12 +2211,12 @@ define amdgpu_ps <2 x float> @ptr_s_buffer_load_v2f32_vgpr_offset(ptr addrspace( ; ; GFX1200-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8) @@ -2228,12 +2228,12 @@ define amdgpu_ps <2 x float> @ptr_s_buffer_load_v2f32_vgpr_offset(ptr addrspace( ; ; GFX1250-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s64) from %ir.rsrc, align 1, addrspace 8) @@ -2312,12 +2312,12 @@ define amdgpu_ps <3 x float> @ptr_s_buffer_load_v3f32_vgpr_offset(ptr addrspace( ; ; GFX1200-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8) @@ -2331,12 +2331,12 @@ define amdgpu_ps <3 x float> @ptr_s_buffer_load_v3f32_vgpr_offset(ptr addrspace( ; ; GFX1250-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:%[0-9]+]]:vreg_96_align2 = BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s96) from %ir.rsrc, align 1, addrspace 8) @@ -2420,12 +2420,12 @@ define amdgpu_ps <4 x float> @ptr_s_buffer_load_v4f32_vgpr_offset(ptr addrspace( ; ; GFX1200-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) @@ -2441,12 +2441,12 @@ define amdgpu_ps <4 x float> @ptr_s_buffer_load_v4f32_vgpr_offset(ptr addrspace( ; ; GFX1250-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) @@ -2562,12 +2562,12 @@ define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset(ptr addrspace( ; ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) @@ -2593,12 +2593,12 @@ define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset(ptr addrspace( ; ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) @@ -2778,12 +2778,12 @@ define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset(ptr addrspac ; ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) @@ -2827,12 +2827,12 @@ define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset(ptr addrspac ; ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) @@ -2925,12 +2925,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4092(ptr addrspace ; ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) @@ -2939,12 +2939,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4092(ptr addrspace ; ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4092 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] @@ -3006,12 +3006,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4095(ptr addrspace ; ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4095, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) @@ -3020,12 +3020,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4095(ptr addrspace ; ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] @@ -3087,12 +3087,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4092_nuw(ptr addrs ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092_nuw ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) @@ -3151,12 +3151,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4096(ptr addrspace ; ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4096, 0, 0, implicit $exec :: (dereferenceable invariant load (s32) from %ir.rsrc, align 1, addrspace 8) @@ -3165,12 +3165,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4096(ptr addrspace ; ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] @@ -3284,12 +3284,12 @@ define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4064(ptr a ; ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) @@ -3315,12 +3315,12 @@ define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4064(ptr a ; ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4064 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] @@ -3451,12 +3451,12 @@ define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4068(ptr a ; ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) @@ -3482,12 +3482,12 @@ define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4068(ptr a ; ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] @@ -3671,12 +3671,12 @@ define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4032(ptr ; ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4032, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) @@ -3720,12 +3720,12 @@ define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4032(ptr ; ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4032 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] @@ -3927,12 +3927,12 @@ define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4036(ptr ; ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4036, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from %ir.rsrc, align 1, addrspace 8) @@ -3976,12 +3976,12 @@ define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4036(ptr ; ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4036 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll index 42e12f504b7f2d..fbc189f9500f39 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.add.ll @@ -23,16 +23,16 @@ define amdgpu_ps float @raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_vof ; ; GFX12-LABEL: name: raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -59,16 +59,16 @@ define amdgpu_ps void @raw_buffer_atomic_add_i32_noret__vgpr_val__sgpr_rsrc__vgp ; ; GFX12-LABEL: name: raw_buffer_atomic_add_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_ATOMIC_ADD_VBUFFER_OFFEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.add.i32(i32 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -99,18 +99,18 @@ define amdgpu_ps <2 x float> @raw_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc__vg ; ; GFX1200-LABEL: name: raw_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN]].sub0 ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN]].sub1 @@ -120,18 +120,18 @@ define amdgpu_ps <2 x float> @raw_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc__vg ; ; GFX1250-LABEL: name: raw_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_64_align2 = BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN]].sub0 ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN]].sub1 @@ -163,35 +163,35 @@ define amdgpu_ps void @raw_buffer_atomic_add_i64_noret__vgpr_val__sgpr_rsrc__vgp ; ; GFX1200-LABEL: name: raw_buffer_atomic_add_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_atomic_add_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 %ret = call i64 @llvm.amdgcn.raw.buffer.atomic.add.i64(i64 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -256,15 +256,15 @@ define amdgpu_ps float @raw_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_vof ; GFX1200-LABEL: name: raw_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -309,15 +309,15 @@ define amdgpu_ps float @raw_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_vof ; GFX1250-LABEL: name: raw_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -420,15 +420,15 @@ define amdgpu_ps void @raw_buffer_atomic_add_i32_noret__sgpr_val__vgpr_rsrc__sgp ; GFX1200-LABEL: name: raw_buffer_atomic_add_i32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -472,15 +472,15 @@ define amdgpu_ps void @raw_buffer_atomic_add_i32_noret__sgpr_val__vgpr_rsrc__sgp ; GFX1250-LABEL: name: raw_buffer_atomic_add_i32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -543,32 +543,32 @@ define amdgpu_ps float @raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_vof ; ; GFX1200-LABEL: name: raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN]] ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; ; GFX1250-LABEL: name: raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec @@ -601,16 +601,16 @@ define amdgpu_ps float @raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_vof ; ; GFX12-LABEL: name: raw_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 3, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll index e98f878d95840e..bc380ed06a0896 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.cmpswap.ll @@ -27,17 +27,17 @@ define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_ ; ; GFX1200-LABEL: name: raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN]].sub0 @@ -46,17 +46,17 @@ define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_ ; ; GFX1250-LABEL: name: raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_64_align2 = BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN]].sub0 @@ -88,34 +88,34 @@ define amdgpu_ps void @raw_buffer_atomic_cmpswap_i32_noret__vgpr_val__vgpr_cmp__ ; ; GFX1200-LABEL: name: raw_buffer_atomic_cmpswap_i32_noret__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_atomic_cmpswap_i32_noret__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -185,16 +185,16 @@ define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_ ; GFX1200-LABEL: name: raw_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] @@ -242,16 +242,16 @@ define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_ ; GFX1250-LABEL: name: raw_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] @@ -360,16 +360,16 @@ define amdgpu_ps void @raw_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cmp__ ; GFX1200-LABEL: name: raw_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] @@ -415,16 +415,16 @@ define amdgpu_ps void @raw_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cmp__ ; GFX1250-LABEL: name: raw_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] @@ -492,17 +492,17 @@ define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_ ; ; GFX1200-LABEL: name: raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN]].sub0 @@ -511,17 +511,17 @@ define amdgpu_ps float @raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_ ; ; GFX1250-LABEL: name: raw_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY6]], [[COPY8]], 0, implicit $exec @@ -566,7 +566,7 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr ; ; GFX1200-LABEL: name: raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -574,13 +574,13 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3 ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0_sub1 @@ -592,7 +592,7 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr ; ; GFX1250-LABEL: name: raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -600,13 +600,13 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3 ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128_align2 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vreg_64_align2 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0_sub1 @@ -645,7 +645,7 @@ define amdgpu_ps void @raw_buffer_atomic_cmpswap_i64_noret__vgpr_val__vgpr_cmp__ ; ; GFX1200-LABEL: name: raw_buffer_atomic_cmpswap_i64_noret__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -653,20 +653,20 @@ define amdgpu_ps void @raw_buffer_atomic_cmpswap_i64_noret__vgpr_val__vgpr_cmp__ ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3 ; GFX1200-NEXT: BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_atomic_cmpswap_i64_noret__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -674,13 +674,13 @@ define amdgpu_ps void @raw_buffer_atomic_cmpswap_i64_noret__vgpr_val__vgpr_cmp__ ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3 ; GFX1250-NEXT: BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -757,20 +757,20 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__vgpr ; GFX1200-LABEL: name: raw_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]] ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]] @@ -821,20 +821,20 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__vgpr ; GFX1250-LABEL: name: raw_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]] ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]] @@ -950,20 +950,20 @@ define amdgpu_ps void @raw_buffer_atomic_cmpswap_i64_noret__sgpr_val__sgpr_cmp__ ; GFX1200-LABEL: name: raw_buffer_atomic_cmpswap_i64_noret__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]] ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]] @@ -1009,20 +1009,20 @@ define amdgpu_ps void @raw_buffer_atomic_cmpswap_i64_noret__sgpr_val__sgpr_cmp__ ; GFX1250-LABEL: name: raw_buffer_atomic_cmpswap_i64_noret__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]] ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]] @@ -1097,7 +1097,7 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr ; ; GFX1200-LABEL: name: raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1105,13 +1105,13 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3 ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE3]], [[COPY8]], [[REG_SEQUENCE2]], [[COPY9]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN]].sub0_sub1 @@ -1123,7 +1123,7 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr ; ; GFX1250-LABEL: name: raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1131,13 +1131,13 @@ define amdgpu_ps double @raw_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY8]], [[COPY10]], 0, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.sub.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.sub.ll index 34abbec319f10a..b6f41de62d95da 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.sub.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.sub.ll @@ -23,16 +23,16 @@ define amdgpu_ps float @raw_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_vof ; ; GFX12-LABEL: name: raw_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -59,16 +59,16 @@ define amdgpu_ps void @raw_buffer_atomic_sub_i32_noret__vgpr_val__sgpr_rsrc__vgp ; ; GFX12-LABEL: name: raw_buffer_atomic_sub_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_ATOMIC_SUB_VBUFFER_OFFEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.sub.i32(i32 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -99,18 +99,18 @@ define amdgpu_ps <2 x float> @raw_buffer_atomic_sub_i64__vgpr_val__sgpr_rsrc__vg ; ; GFX1200-LABEL: name: raw_buffer_atomic_sub_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN]].sub0 ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN]].sub1 @@ -120,18 +120,18 @@ define amdgpu_ps <2 x float> @raw_buffer_atomic_sub_i64__vgpr_val__sgpr_rsrc__vg ; ; GFX1250-LABEL: name: raw_buffer_atomic_sub_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_64_align2 = BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN]].sub0 ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN]].sub1 @@ -163,35 +163,35 @@ define amdgpu_ps void @raw_buffer_atomic_sub_i64_noret__vgpr_val__sgpr_rsrc__vgp ; ; GFX1200-LABEL: name: raw_buffer_atomic_sub_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_atomic_sub_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 %ret = call i64 @llvm.amdgcn.raw.buffer.atomic.sub.i64(i64 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -256,15 +256,15 @@ define amdgpu_ps float @raw_buffer_atomic_sub_i32__sgpr_val__vgpr_rsrc__sgpr_vof ; GFX1200-LABEL: name: raw_buffer_atomic_sub_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -309,15 +309,15 @@ define amdgpu_ps float @raw_buffer_atomic_sub_i32__sgpr_val__vgpr_rsrc__sgpr_vof ; GFX1250-LABEL: name: raw_buffer_atomic_sub_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -420,15 +420,15 @@ define amdgpu_ps void @raw_buffer_atomic_sub_i32_noret__sgpr_val__vgpr_rsrc__sgp ; GFX1200-LABEL: name: raw_buffer_atomic_sub_i32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -472,15 +472,15 @@ define amdgpu_ps void @raw_buffer_atomic_sub_i32_noret__sgpr_val__vgpr_rsrc__sgp ; GFX1250-LABEL: name: raw_buffer_atomic_sub_i32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -543,32 +543,32 @@ define amdgpu_ps float @raw_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_vof ; ; GFX1200-LABEL: name: raw_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN]] ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; ; GFX1250-LABEL: name: raw_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec @@ -601,16 +601,16 @@ define amdgpu_ps float @raw_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_vof ; ; GFX12-LABEL: name: raw_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 3, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.swap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.swap.ll index 57049eafb644a3..cc972ff2216ab0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.swap.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.atomic.swap.ll @@ -21,16 +21,16 @@ define amdgpu_ps float @raw_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr_vo ; ; GFX12-LABEL: name: raw_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -57,16 +57,16 @@ define amdgpu_ps void @raw_buffer_atomic_swap_i32_noret__vgpr_val__sgpr_rsrc__vg ; ; GFX12-LABEL: name: raw_buffer_atomic_swap_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 %ret = call i32 @llvm.amdgcn.raw.buffer.atomic.swap.i32(i32 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -97,18 +97,18 @@ define amdgpu_ps <2 x float> @raw_buffer_atomic_swap_i64__vgpr_val__sgpr_rsrc__v ; ; GFX1200-LABEL: name: raw_buffer_atomic_swap_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN]].sub0 ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN]].sub1 @@ -118,18 +118,18 @@ define amdgpu_ps <2 x float> @raw_buffer_atomic_swap_i64__vgpr_val__sgpr_rsrc__v ; ; GFX1250-LABEL: name: raw_buffer_atomic_swap_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN:%[0-9]+]]:vreg_64_align2 = BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN]].sub0 ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN]].sub1 @@ -161,35 +161,35 @@ define amdgpu_ps void @raw_buffer_atomic_swap_i64_noret__vgpr_val__sgpr_rsrc__vg ; ; GFX1200-LABEL: name: raw_buffer_atomic_swap_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_atomic_swap_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 %ret = call i64 @llvm.amdgcn.raw.buffer.atomic.swap.i64(i64 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -253,15 +253,15 @@ define amdgpu_ps float @raw_buffer_atomic_swap_i32__sgpr_val__vgpr_rsrc__sgpr_vo ; GFX1200-LABEL: name: raw_buffer_atomic_swap_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -306,15 +306,15 @@ define amdgpu_ps float @raw_buffer_atomic_swap_i32__sgpr_val__vgpr_rsrc__sgpr_vo ; GFX1250-LABEL: name: raw_buffer_atomic_swap_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -416,15 +416,15 @@ define amdgpu_ps void @raw_buffer_atomic_swap_i32_noret__sgpr_val__vgpr_rsrc__sg ; GFX1200-LABEL: name: raw_buffer_atomic_swap_i32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -468,15 +468,15 @@ define amdgpu_ps void @raw_buffer_atomic_swap_i32_noret__sgpr_val__vgpr_rsrc__sg ; GFX1250-LABEL: name: raw_buffer_atomic_swap_i32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -539,32 +539,32 @@ define amdgpu_ps float @raw_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr_vo ; ; GFX1200-LABEL: name: raw_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN]] ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; ; GFX1250-LABEL: name: raw_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec @@ -596,16 +596,16 @@ define amdgpu_ps float @raw_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr_vo ; ; GFX12-LABEL: name: raw_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 3, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll index baf510e8ebfe1d..b854410dafedd4 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.f16.ll @@ -37,15 +37,15 @@ define amdgpu_ps half @raw_buffer_load_format_f16__sgpr_rsrc__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_load_format_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -97,15 +97,15 @@ define amdgpu_ps <2 x half> @raw_buffer_load_format_v2f16__sgpr_rsrc__vgpr_voffs ; ; GFX12-LABEL: name: raw_buffer_load_format_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f16>), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -176,15 +176,15 @@ define amdgpu_ps <4 x half> @raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffs ; ; GFX12-LABEL: name: raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN]].sub0 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN]].sub1 @@ -302,14 +302,14 @@ define amdgpu_ps half @raw_buffer_load_format_f16__vgpr_rsrc__sgpr_voffset__vgpr ; GFX12-LABEL: name: raw_buffer_load_format_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo @@ -410,15 +410,15 @@ define amdgpu_ps <4 x half> @raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffs ; ; GFX12-LABEL: name: raw_buffer_load_format_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add_4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN]].sub0 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN]].sub1 @@ -465,15 +465,15 @@ define amdgpu_ps half @raw_buffer_load_format_f16__sgpr_rsrc__sgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_load_format_f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN]] @@ -527,15 +527,15 @@ define amdgpu_ps <2 x half> @raw_buffer_load_format_v2f16__sgpr_rsrc__sgpr_voffs ; ; GFX12-LABEL: name: raw_buffer_load_format_v2f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f16>), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN]] @@ -601,15 +601,15 @@ define amdgpu_ps <4 x half> @raw_buffer_load_format_v4f16__sgpr_rsrc__sgpr_voffs ; ; GFX12-LABEL: name: raw_buffer_load_format_v4f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN]].sub0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll index 242172df80adcd..4857b43f095b21 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.format.ll @@ -21,15 +21,15 @@ define amdgpu_ps float @raw_buffer_load_format_f32__sgpr_rsrc__vgpr_voffset__sgp ; ; GFX12-LABEL: name: raw_buffer_load_format_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -58,15 +58,15 @@ define amdgpu_ps <2 x float> @raw_buffer_load_format_v2f32__sgpr_rsrc__vgpr_voff ; ; GFX12-LABEL: name: raw_buffer_load_format_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN]].sub0 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN]].sub1 @@ -100,15 +100,15 @@ define amdgpu_ps <3 x float> @raw_buffer_load_format_v3f32__sgpr_rsrc__vgpr_voff ; ; GFX12-LABEL: name: raw_buffer_load_format_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN]].sub0 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN]].sub1 @@ -146,15 +146,15 @@ define amdgpu_ps <4 x float> @raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voff ; ; GFX12-LABEL: name: raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN]].sub0 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN]].sub1 @@ -198,15 +198,15 @@ define amdgpu_ps <4 x i32> @raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_v4i32 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x i32>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN]].sub0 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN]].sub1 @@ -281,14 +281,14 @@ define amdgpu_ps float @raw_buffer_load_format_f32__vgpr_rsrc__sgpr_voffset__vgp ; GFX12-LABEL: name: raw_buffer_load_format_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo @@ -357,15 +357,15 @@ define amdgpu_ps <4 x float> @raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voff ; ; GFX12-LABEL: name: raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add_4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN]].sub0 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN]].sub1 @@ -410,15 +410,15 @@ define amdgpu_ps <4 x i32> @raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_load_format_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add_4095_v4i32 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, implicit $exec :: (dereferenceable load (<4 x i32>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN]].sub0 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN]].sub1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll index b235ff983ff1ac..48a0393dd9e4fb 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll @@ -23,15 +23,15 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -59,15 +59,15 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] @@ -128,7 +128,7 @@ define amdgpu_ps float @raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffs ; GFX1200-LABEL: name: raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -136,7 +136,7 @@ define amdgpu_ps float @raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffs ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: bb.2: @@ -175,7 +175,7 @@ define amdgpu_ps float @raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffs ; GFX1250-LABEL: name: raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -183,7 +183,7 @@ define amdgpu_ps float @raw_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffs ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: bb.2: @@ -396,15 +396,15 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 1, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -431,15 +431,15 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 2, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -466,15 +466,15 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 4, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -501,15 +501,15 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_dlc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 6, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -536,15 +536,15 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_dlc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 5, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -571,15 +571,15 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_slc_dlc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 7, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -609,15 +609,15 @@ define amdgpu_ps <2 x float> @raw_buffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sg ; ; GFX1200-LABEL: name: raw_buffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub0 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub1 @@ -627,15 +627,15 @@ define amdgpu_ps <2 x float> @raw_buffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sg ; ; GFX1250-LABEL: name: raw_buffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub0 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub1 @@ -669,15 +669,15 @@ define amdgpu_ps <3 x float> @raw_buffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sg ; ; GFX1200-LABEL: name: raw_buffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub0 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub1 @@ -689,15 +689,15 @@ define amdgpu_ps <3 x float> @raw_buffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sg ; ; GFX1250-LABEL: name: raw_buffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:%[0-9]+]]:vreg_96_align2 = BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub0 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub1 @@ -735,15 +735,15 @@ define amdgpu_ps <4 x float> @raw_buffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sg ; ; GFX1200-LABEL: name: raw_buffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub0 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub1 @@ -757,15 +757,15 @@ define amdgpu_ps <4 x float> @raw_buffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sg ; ; GFX1250-LABEL: name: raw_buffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub0 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub1 @@ -798,15 +798,15 @@ define amdgpu_ps half @raw_buffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffse ; ; GFX12-LABEL: name: raw_buffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_USHORT_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_USHORT_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -832,15 +832,15 @@ define amdgpu_ps <2 x half> @raw_buffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgp ; ; GFX12-LABEL: name: raw_buffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f16>), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -875,15 +875,15 @@ define amdgpu_ps <4 x half> @raw_buffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgp ; ; GFX1200-LABEL: name: raw_buffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub0 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub1 @@ -893,15 +893,15 @@ define amdgpu_ps <4 x half> @raw_buffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgp ; ; GFX1250-LABEL: name: raw_buffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub0 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub1 @@ -930,15 +930,15 @@ define amdgpu_ps float @raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffse ; ; GFX12-LABEL: name: raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_zext ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (i8), addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -966,15 +966,15 @@ define amdgpu_ps float @raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffse ; ; GFX12-LABEL: name: raw_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_sext ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_SBYTE_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (i8), addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_SBYTE_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -1002,15 +1002,15 @@ define amdgpu_ps float @raw_buffer_load_i16__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_i16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_zext ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_USHORT_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_USHORT_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -1038,15 +1038,15 @@ define amdgpu_ps float @raw_buffer_load_i16__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_i16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_sext ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_SSHORT_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_SSHORT_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_SSHORT_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -1108,7 +1108,7 @@ define amdgpu_ps half @raw_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffse ; GFX1200-LABEL: name: raw_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1116,7 +1116,7 @@ define amdgpu_ps half @raw_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffse ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: bb.2: @@ -1155,7 +1155,7 @@ define amdgpu_ps half @raw_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffse ; GFX1250-LABEL: name: raw_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1163,7 +1163,7 @@ define amdgpu_ps half @raw_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffse ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: bb.2: @@ -1254,7 +1254,7 @@ define amdgpu_ps float @raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffse ; GFX1200-LABEL: name: raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1262,7 +1262,7 @@ define amdgpu_ps float @raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffse ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: bb.2: @@ -1301,7 +1301,7 @@ define amdgpu_ps float @raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffse ; GFX1250-LABEL: name: raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1309,7 +1309,7 @@ define amdgpu_ps float @raw_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffse ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: bb.2: @@ -1367,14 +1367,14 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFSET [[REG_SEQUENCE]], [[COPY4]], 0, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFSET]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -1399,14 +1399,14 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFSET [[REG_SEQUENCE]], [[COPY4]], 4095, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFSET]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -1433,14 +1433,14 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFSET [[REG_SEQUENCE]], [[COPY4]], 4096, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFSET]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -1466,30 +1466,30 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX1200-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 16, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; ; GFX1250-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec @@ -1519,30 +1519,30 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX1200-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; ; GFX1250-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec @@ -1575,30 +1575,30 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX1200-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4096, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; ; GFX1250-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec @@ -1628,12 +1628,12 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 @@ -1662,12 +1662,12 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 @@ -1698,15 +1698,15 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 ; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) @@ -1737,15 +1737,15 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) @@ -1776,15 +1776,15 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 ; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX12-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) @@ -1849,7 +1849,7 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; GFX1200-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000 ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1857,7 +1857,7 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000 ; GFX1200-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX1200-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo @@ -1898,7 +1898,7 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; GFX1250-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000 ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1906,7 +1906,7 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000 ; GFX1250-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX1250-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo @@ -2003,7 +2003,7 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; GFX1200-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add5000 ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -2011,7 +2011,7 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: bb.2: @@ -2050,7 +2050,7 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; GFX1250-LABEL: name: raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add5000 ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -2058,7 +2058,7 @@ define amdgpu_ps float @raw_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll index 881d1656a4d702..e98e39286cc699 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f16.ll @@ -36,16 +36,16 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -83,15 +83,15 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_409 ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.format.f16(half %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0) @@ -135,16 +135,16 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x f16>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.format.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -193,18 +193,18 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x f16>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.format.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -319,7 +319,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse ; GFX12-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16 ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -330,7 +330,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: bb.2: @@ -405,12 +405,12 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -458,12 +458,12 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -511,16 +511,16 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 0, 0, implicit $exec :: (dereferenceable store (<2 x f16>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 %voffset.add = add i32 %voffset, 16 @@ -565,16 +565,16 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, implicit $exec :: (dereferenceable store (<2 x f16>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 %voffset.add = add i32 %voffset, 4095 @@ -625,16 +625,16 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_voffset_add_4096 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4096, 0, 0, implicit $exec :: (dereferenceable store (<2 x f16>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 %voffset.add = add i32 %voffset, 4096 @@ -757,7 +757,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse ; GFX12-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16_add_4096 ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -768,7 +768,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: bb.2: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll index 1ef955508f70ab..2db0959ecffd62 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.format.f32.ll @@ -21,16 +21,16 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -54,15 +54,15 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_409 ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__voffset_4095__sgpr_soffset_f32 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.format.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0) @@ -89,18 +89,18 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x f32>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.format.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -128,19 +128,19 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x f32>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.format.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -169,12 +169,12 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -182,7 +182,7 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY8]], [[REG_SEQUENCE]], [[COPY9]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x f32>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.format.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -244,7 +244,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse ; GFX12-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32 ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -257,7 +257,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr7 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr8 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: bb.2: @@ -315,12 +315,12 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -353,12 +353,12 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_soffset4096 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -391,18 +391,18 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 16, 0, 0, implicit $exec :: (dereferenceable store (<2 x f32>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 %voffset.add = add i32 %voffset, 16 @@ -430,18 +430,18 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 4095, 0, 0, implicit $exec :: (dereferenceable store (<2 x f32>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 %voffset.add = add i32 %voffset, 4095 @@ -472,18 +472,18 @@ define amdgpu_ps void @raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffse ; ; GFX12-LABEL: name: raw_buffer_store_format__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32_voffset_add_4096 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 4096, 0, 0, implicit $exec :: (dereferenceable store (<2 x f32>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 %voffset.add = add i32 %voffset, 4096 @@ -551,7 +551,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse ; GFX12-LABEL: name: raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32_add_4096 ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -564,7 +564,7 @@ define amdgpu_ps void @raw_buffer_store_format__vgpr_rsrc__vgpr_val__vgpr_voffse ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr7 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr8 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: bb.2: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll index 5b337085621293..7cbda6b0f9c9e6 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.store.ll @@ -23,16 +23,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -60,16 +60,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__sgpr_val__sgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $sgpr8 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr8 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX12-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY7]], [[COPY8]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) @@ -130,7 +130,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX1200-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -139,7 +139,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: bb.2: @@ -177,7 +177,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX1250-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -186,7 +186,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: bb.2: @@ -267,12 +267,12 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__vgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -478,16 +478,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 1) @@ -512,16 +512,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 2, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 2) @@ -546,16 +546,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 3, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 3) @@ -580,16 +580,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_dlc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 4, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 4) @@ -614,16 +614,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_slc_dlc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 6, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 6) @@ -648,16 +648,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_dlc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 5, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 5) @@ -682,16 +682,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_glc_slc_dlc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 7, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 7) @@ -718,35 +718,35 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX1200-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x f32>), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f32 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x f32>), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -774,37 +774,37 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX1200-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x f32>), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v3f32 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY7]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x f32>), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -833,12 +833,12 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX1200-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -846,18 +846,18 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY8]], [[REG_SEQUENCE]], [[COPY9]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x f32>), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f32 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -865,7 +865,7 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY8]], [[REG_SEQUENCE]], [[COPY9]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x f32>), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -890,16 +890,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i8 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_BYTE_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 %val.trunc = trunc i32 %val to i8 @@ -925,16 +925,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_i16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_SHORT_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (i16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 %val.trunc = trunc i32 %val to i16 @@ -960,16 +960,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_SHORT_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -994,16 +994,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_bf16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_SHORT_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (bf16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.bf16(bfloat %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -1028,16 +1028,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x f16>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -1064,35 +1064,35 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX1200-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x f16>), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x f16>), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -1117,16 +1117,16 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2bf16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x bf16>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.v2bf16(<2 x bfloat> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -1153,35 +1153,35 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX1200-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4bf16 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x bf16>), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4bf16 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact [[REG_SEQUENCE1]], [[COPY6]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x bf16>), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.v4bf16(<4 x bfloat> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0) @@ -1241,7 +1241,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX1200-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16 ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1252,7 +1252,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: bb.2: @@ -1290,7 +1290,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX1250-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v4f16 ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1301,7 +1301,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: bb.2: @@ -1356,15 +1356,15 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_v ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4095, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 0) @@ -1390,15 +1390,15 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_v ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__sgpr_soffset_f32_voffset4096 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 4096, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.buffer.store.f32(float %val, <4 x i32> %rsrc, i32 4096, i32 %soffset, i32 0) @@ -1423,31 +1423,31 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX1200-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_16 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_16 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec @@ -1476,31 +1476,31 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX1200-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec @@ -1532,31 +1532,31 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX1200-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4096 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4096, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_f32_voffset_add_4096 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec @@ -1585,12 +1585,12 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1619,12 +1619,12 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX12-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset4096 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1653,31 +1653,31 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX1200-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_16 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 0, 0, implicit $exec :: (dereferenceable store (<2 x f16>), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_16 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec @@ -1706,31 +1706,31 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX1200-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, implicit $exec :: (dereferenceable store (<2 x f16>), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec @@ -1762,31 +1762,31 @@ define amdgpu_ps void @raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; ; GFX1200-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4096 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact [[COPY4]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4096, 0, 0, implicit $exec :: (dereferenceable store (<2 x f16>), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: raw_buffer_store__sgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_v2f16_soffset_add_4096 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec @@ -1852,7 +1852,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX1200-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_offset_add_5000 ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1861,7 +1861,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: bb.2: @@ -1899,7 +1899,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX1250-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr_soffset_offset_add_5000 ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1908,7 +1908,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__vgpr_voffset__sgpr ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec @@ -2003,7 +2003,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__5000_voffset__sgpr ; GFX1200-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__5000_voffset__sgpr_soffset_offset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -2011,7 +2011,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__5000_voffset__sgpr ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: bb.2: @@ -2049,7 +2049,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__5000_voffset__sgpr ; GFX1250-LABEL: name: raw_buffer_store__vgpr_rsrc__vgpr_val__5000_voffset__sgpr_soffset_offset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -2057,7 +2057,7 @@ define amdgpu_ps void @raw_buffer_store__vgpr_rsrc__vgpr_val__5000_voffset__sgpr ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: bb.2: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll index c1da44fa1b1070..bec2104244b355 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll @@ -22,14 +22,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] @@ -58,14 +58,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__sgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 - ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1250-NEXT: {{ $}} + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) @@ -127,14 +127,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_s ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1250-NEXT: {{ $}} @@ -298,14 +298,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 1, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] @@ -333,14 +333,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 2, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] @@ -368,14 +368,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 4, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] @@ -403,14 +403,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_dlc ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 6, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] @@ -438,14 +438,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_dlc ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 5, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] @@ -473,14 +473,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc_slc_dlc ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 7, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] @@ -507,14 +507,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_volatile ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (volatile dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] @@ -545,14 +545,14 @@ define amdgpu_ps <2 x float> @raw_ptr_buffer_load_v2f32__sgpr_rsrc__vgpr_voffset ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub0 @@ -587,14 +587,14 @@ define amdgpu_ps <3 x float> @raw_ptr_buffer_load_v3f32__sgpr_rsrc__vgpr_voffset ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:%[0-9]+]]:vreg_96_align2 = BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN]].sub0 @@ -633,14 +633,14 @@ define amdgpu_ps <4 x float> @raw_ptr_buffer_load_v4f32__sgpr_rsrc__vgpr_voffset ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN]].sub0 @@ -674,14 +674,14 @@ define amdgpu_ps half @raw_ptr_buffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_so ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_USHORT_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (f16) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_USHORT_VBUFFER_OFFEN]] @@ -708,14 +708,14 @@ define amdgpu_ps <2 x half> @raw_ptr_buffer_load_v2f16__sgpr_rsrc__vgpr_voffset_ ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f16>) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] @@ -751,14 +751,14 @@ define amdgpu_ps <4 x half> @raw_ptr_buffer_load_v4f16__sgpr_rsrc__vgpr_voffset_ ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN]].sub0 @@ -788,14 +788,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_so ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_zext ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (i8) from %ir.rsrc, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_VBUFFER_OFFEN]] @@ -824,14 +824,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_so ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset_sext ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_SBYTE_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (i8) from %ir.rsrc, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_SBYTE_VBUFFER_OFFEN]] @@ -860,14 +860,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_i16__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_i16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_zext ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_USHORT_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_USHORT_VBUFFER_OFFEN]] @@ -896,14 +896,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_i16__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_i16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_sext ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_SSHORT_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_SSHORT_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_SSHORT_VBUFFER_OFFEN]] @@ -966,14 +966,14 @@ define amdgpu_ps half @raw_ptr_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_so ; GFX1250-LABEL: name: raw_ptr_buffer_load_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1250-NEXT: {{ $}} @@ -1065,14 +1065,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_so ; GFX1250-LABEL: name: raw_ptr_buffer_load_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1250-NEXT: {{ $}} @@ -1131,13 +1131,13 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vdpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFSET [[REG_SEQUENCE]], [[COPY4]], 0, 0, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFSET]] @@ -1163,13 +1163,13 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFSET [[REG_SEQUENCE]], [[COPY4]], 4095, 0, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFSET]] @@ -1197,13 +1197,13 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFSET:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFSET [[REG_SEQUENCE]], [[COPY4]], 4096, 0, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFSET]] @@ -1231,12 +1231,12 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__voffset67108860_soff ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__voffset67108860_soffset0 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 58720256 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] @@ -1265,14 +1265,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec @@ -1303,14 +1303,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec @@ -1344,14 +1344,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec @@ -1382,12 +1382,12 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 @@ -1416,12 +1416,12 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 @@ -1452,14 +1452,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 ; GFX1250-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 @@ -1491,14 +1491,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 @@ -1530,14 +1530,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 ; GFX1250-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 @@ -1603,14 +1603,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000 ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000 ; GFX1250-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY5]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 @@ -1708,14 +1708,14 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_s ; GFX1250-LABEL: name: raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add5000 ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll index b93f53a1e45696..272d36a5b6de0a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.offset-split.ll @@ -21,10 +21,6 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__voffset67108860_soff ; GFX1250-NEXT: v_nop ; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-NEXT: v_mov_b32_e32 v0, 0x3800000 -; GFX1250-NEXT: s_mov_b32 s0, s2 -; GFX1250-NEXT: s_mov_b32 s1, s3 -; GFX1250-NEXT: s_mov_b32 s2, s4 -; GFX1250-NEXT: s_mov_b32 s3, s5 ; GFX1250-NEXT: s_mov_b32 s4, 16 ; GFX1250-NEXT: buffer_load_b32 v0, v0, s[0:3], s4 offen offset:8388604 ; GFX1250-NEXT: s_wait_loadcnt 0x0 @@ -52,10 +48,6 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__voffset67108860_soff ; GFX1250-NEXT: v_nop ; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-NEXT: v_mov_b32_e32 v0, 0x3800000 -; GFX1250-NEXT: s_mov_b32 s0, s2 -; GFX1250-NEXT: s_mov_b32 s1, s3 -; GFX1250-NEXT: s_mov_b32 s2, s4 -; GFX1250-NEXT: s_mov_b32 s3, s5 ; GFX1250-NEXT: s_mov_b32 s4, -16 ; GFX1250-NEXT: buffer_load_b32 v0, v0, s[0:3], s4 offen offset:8388604 ; GFX1250-NEXT: s_wait_loadcnt 0x0 @@ -84,12 +76,8 @@ define amdgpu_ps float @raw_ptr_buffer_load_f32__sgpr_rsrc__vgpr_voffset__or6710 ; GFX1250-NEXT: v_nop ; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-NEXT: v_and_b32_e32 v0, 0xfc000000, v0 -; GFX1250-NEXT: s_mov_b32 s0, s2 -; GFX1250-NEXT: s_mov_b32 s1, s3 -; GFX1250-NEXT: s_mov_b32 s2, s4 -; GFX1250-NEXT: s_mov_b32 s3, s5 -; GFX1250-NEXT: v_add_nc_u32_e32 v0, 0x3800000, v0 ; GFX1250-NEXT: s_mov_b32 s4, 16 +; GFX1250-NEXT: v_add_nc_u32_e32 v0, 0x3800000, v0 ; GFX1250-NEXT: buffer_load_b32 v0, v0, s[0:3], s4 offen offset:8388604 ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: ; return to shader part epilog diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll index e9bc3eec0b09bb..f590e4c6a108ac 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.load.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX11 %s define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) { ; CHECK-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset @@ -17,6 +17,21 @@ define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX11-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 %val = call float @llvm.amdgcn.raw.ptr.tbuffer.load.f32(ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) ret float %val } @@ -39,6 +54,24 @@ define amdgpu_ps <2 x float> @raw_tbuffer_load_v2f32__sgpr_rsrc__vgpr_voffset__s ; CHECK-NEXT: $vgpr0 = COPY [[COPY6]] ; CHECK-NEXT: $vgpr1 = COPY [[COPY7]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; + ; GFX11-LABEL: name: raw_tbuffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_XY_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_XY_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_OFFEN]].sub0 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_OFFEN]].sub1 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY6]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY7]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 %val = call <2 x float> @llvm.amdgcn.raw.ptr.tbuffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) ret <2 x float> %val } @@ -63,6 +96,26 @@ define amdgpu_ps <3 x float> @raw_tbuffer_load_v3f32__sgpr_rsrc__vgpr_voffset__s ; CHECK-NEXT: $vgpr1 = COPY [[COPY7]] ; CHECK-NEXT: $vgpr2 = COPY [[COPY8]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + ; + ; GFX11-LABEL: name: raw_tbuffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN:%[0-9]+]]:vreg_96 = TBUFFER_LOAD_FORMAT_XYZ_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub0 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub1 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub2 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY6]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY7]] + ; GFX11-NEXT: $vgpr2 = COPY [[COPY8]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 %val = call <3 x float> @llvm.amdgcn.raw.ptr.tbuffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) ret <3 x float> %val } @@ -89,6 +142,28 @@ define amdgpu_ps <4 x float> @raw_tbuffer_load_v4f32__sgpr_rsrc__vgpr_voffset__s ; CHECK-NEXT: $vgpr2 = COPY [[COPY8]] ; CHECK-NEXT: $vgpr3 = COPY [[COPY9]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; + ; GFX11-LABEL: name: raw_tbuffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub0 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub1 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub2 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub3 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY6]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY7]] + ; GFX11-NEXT: $vgpr2 = COPY [[COPY8]] + ; GFX11-NEXT: $vgpr3 = COPY [[COPY9]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 %val = call <4 x float> @llvm.amdgcn.raw.ptr.tbuffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) ret <4 x float> %val } @@ -144,6 +219,57 @@ define amdgpu_ps float @raw_tbuffer_load_f32__vgpr_rsrc__sgpr_voffset__vgpr_soff ; CHECK-NEXT: bb.5: ; CHECK-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX11-LABEL: name: raw_tbuffer_load_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY5]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[S_AND_B32_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 [[S_AND_B32_1]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY6]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 %val = call float @llvm.amdgcn.raw.ptr.tbuffer.load.f32(ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) ret float %val } @@ -163,6 +289,21 @@ define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX11-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 %val = call float @llvm.amdgcn.raw.ptr.tbuffer.load.f32(ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1) ret float %val } @@ -182,6 +323,21 @@ define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 2, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX11-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 2, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 %val = call float @llvm.amdgcn.raw.ptr.tbuffer.load.f32(ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2) ret float %val } @@ -201,6 +357,21 @@ define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 3, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX11-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 3, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 %val = call float @llvm.amdgcn.raw.ptr.tbuffer.load.f32(ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3) ret float %val } @@ -220,6 +391,21 @@ define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 4, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX11-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 4, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 %val = call float @llvm.amdgcn.raw.ptr.tbuffer.load.f32(ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4) ret float %val } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll index 596154fb72b3dc..0ae2189a39db28 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.tbuffer.store.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX11 %s ; Natural mapping define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(float %val, ptr addrspace(8) inreg %rsrc, i32 %voffset, i32 inreg %soffset) { @@ -18,6 +18,21 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) ret void } @@ -40,6 +55,23 @@ define amdgpu_ps void @raw_tbuffer_store_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_so ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<2 x f32>) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<2 x f32>) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.v2f32(<2 x float> %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) ret void } @@ -63,6 +95,24 @@ define amdgpu_ps void @raw_tbuffer_store_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_so ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact [[REG_SEQUENCE]], [[COPY7]], [[REG_SEQUENCE1]], [[COPY8]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<3 x f32>) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact [[REG_SEQUENCE]], [[COPY7]], [[REG_SEQUENCE1]], [[COPY8]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<3 x f32>) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.v3f32(<3 x float> %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) ret void } @@ -87,6 +137,25 @@ define amdgpu_ps void @raw_tbuffer_store_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_so ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact [[REG_SEQUENCE]], [[COPY8]], [[REG_SEQUENCE1]], [[COPY9]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<4 x f32>) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact [[REG_SEQUENCE]], [[COPY8]], [[REG_SEQUENCE1]], [[COPY9]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<4 x f32>) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.v4f32(<4 x float> %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) ret void } @@ -108,6 +177,22 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__sgpr_voffset__sgpr_soff ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY7]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY7]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0) ret void } @@ -160,6 +245,53 @@ define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 [[S_AND_B32_]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE1]], [[COPY6]], 0, 94, 1, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 1) ret void } @@ -215,6 +347,56 @@ define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__vgpr_soff ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__vgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[S_AND_B32_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 [[S_AND_B32_1]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0) ret void } @@ -271,6 +453,57 @@ define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__sgpr_voffset__vgpr_soff ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[S_AND_B32_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 [[S_AND_B32_1]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY7]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) ret void } @@ -291,6 +524,21 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1) ret void } @@ -311,6 +559,21 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 2, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 2, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2) ret void } @@ -331,6 +594,21 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 3, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 3, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3) ret void } @@ -351,6 +629,21 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 4, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 4, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4) ret void } @@ -371,6 +664,20 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vdpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 0, i32 %soffset, i32 94, i32 0) ret void } @@ -389,6 +696,20 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 4095, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 4095, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 4095, i32 %soffset, i32 94, i32 0) ret void } @@ -409,6 +730,22 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 4096, i32 %soffset, i32 94, i32 0) ret void } @@ -428,6 +765,21 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 %voffset = add i32 %voffset.base, 16 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0) ret void @@ -448,6 +800,21 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 %voffset = add i32 %voffset.base, 4095 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0) ret void @@ -471,6 +838,24 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX11-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 %voffset = add i32 %voffset.base, 4096 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0) ret void @@ -491,6 +876,21 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 4095, i32 94, i32 0) ret void } @@ -510,6 +910,21 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 4096, i32 94, i32 0) ret void } @@ -531,6 +946,23 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 + ; GFX11-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def dead $scc + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 %soffset = add i32 %soffset.base, 16 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0) ret void @@ -553,6 +985,23 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 + ; GFX11-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def dead $scc + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 %soffset = add i32 %soffset.base, 4095 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0) ret void @@ -575,6 +1024,23 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; CHECK-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 + ; GFX11-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def dead $scc + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 %soffset = add i32 %soffset.base, 4096 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0) ret void @@ -630,6 +1096,55 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000 + ; GFX11-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def dead $scc + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 [[S_AND_B32_]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE1]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_1]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: S_ENDPGM 0 %soffset = add i32 %soffset.base, 5000 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0) ret void @@ -686,6 +1201,56 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: bb.5: ; CHECK-NEXT: S_ENDPGM 0 + ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add5000 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX11-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec + ; GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 [[S_AND_B32_]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[V_ADD_U32_e64_]], [[REG_SEQUENCE1]], [[COPY6]], 904, 94, 0, 0, implicit $exec :: (dereferenceable store (f32) into %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_1]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: S_ENDPGM 0 %voffset = add i32 %voffset.base, 5000 call void @llvm.amdgcn.raw.ptr.tbuffer.store.f32(float %val, ptr addrspace(8) %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0) ret void diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll index 9a69fdeb83047c..6c69ad67aabe08 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.f16.ll @@ -36,15 +36,15 @@ define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -96,15 +96,15 @@ define amdgpu_ps <2 x half> @raw_tbuffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sg ; ; GFX12-LABEL: name: raw_tbuffer_load_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<2 x f16>), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -175,15 +175,15 @@ define amdgpu_ps <4 x half> @raw_tbuffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sg ; ; GFX12-LABEL: name: raw_tbuffer_load_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN]].sub0 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN]].sub1 @@ -300,14 +300,14 @@ define amdgpu_ps half @raw_tbuffer_load_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffs ; GFX12-LABEL: name: raw_tbuffer_load_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo @@ -384,15 +384,15 @@ define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -433,15 +433,15 @@ define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 2, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -482,15 +482,15 @@ define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 3, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -531,15 +531,15 @@ define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 4, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -582,15 +582,15 @@ define amdgpu_ps half @raw_tbuffer_load_f16__sgpr_rsrc__sgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_tbuffer_load_f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN]] @@ -644,15 +644,15 @@ define amdgpu_ps <2 x half> @raw_tbuffer_load_v2f16__sgpr_rsrc__sgpr_voffset__sg ; ; GFX12-LABEL: name: raw_tbuffer_load_v2f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<2 x f16>), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN]] @@ -718,15 +718,15 @@ define amdgpu_ps <4 x half> @raw_tbuffer_load_v4f16__sgpr_rsrc__sgpr_voffset__sg ; ; GFX12-LABEL: name: raw_tbuffer_load_v4f16__sgpr_rsrc__sgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN]].sub0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll index 6493bdc1eaae0a..b4b4ec0d86467f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.load.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX10_GFX11 %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX10_GFX11 %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX11 %s ; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX12 %s define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset) { @@ -19,17 +19,32 @@ define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] ; GFX10_GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -56,17 +71,35 @@ define amdgpu_ps <2 x float> @raw_tbuffer_load_v2f32__sgpr_rsrc__vgpr_voffset__s ; GFX10_GFX11-NEXT: $vgpr1 = COPY [[COPY7]] ; GFX10_GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 ; + ; GFX11-LABEL: name: raw_tbuffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_XY_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_XY_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>), align 1, addrspace 8) + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_OFFEN]].sub0 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_OFFEN]].sub1 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY6]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY7]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; ; GFX12-LABEL: name: raw_tbuffer_load_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN]].sub0 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN]].sub1 @@ -98,17 +131,37 @@ define amdgpu_ps <3 x float> @raw_tbuffer_load_v3f32__sgpr_rsrc__vgpr_voffset__s ; GFX10_GFX11-NEXT: $vgpr2 = COPY [[COPY8]] ; GFX10_GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 ; + ; GFX11-LABEL: name: raw_tbuffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN:%[0-9]+]]:vreg_96 = TBUFFER_LOAD_FORMAT_XYZ_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>), align 1, addrspace 8) + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub0 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub1 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_OFFEN]].sub2 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY6]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY7]] + ; GFX11-NEXT: $vgpr2 = COPY [[COPY8]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + ; ; GFX12-LABEL: name: raw_tbuffer_load_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN:%[0-9]+]]:vreg_96 = TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN]].sub0 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN]].sub1 @@ -144,17 +197,39 @@ define amdgpu_ps <4 x float> @raw_tbuffer_load_v4f32__sgpr_rsrc__vgpr_voffset__s ; GFX10_GFX11-NEXT: $vgpr3 = COPY [[COPY9]] ; GFX10_GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: raw_tbuffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_XYZW_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8) + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub0 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub1 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub2 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_OFFEN]].sub3 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY6]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY7]] + ; GFX11-NEXT: $vgpr2 = COPY [[COPY8]] + ; GFX11-NEXT: $vgpr3 = COPY [[COPY9]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; GFX12-LABEL: name: raw_tbuffer_load_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN]].sub0 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN]].sub1 @@ -221,17 +296,68 @@ define amdgpu_ps float @raw_tbuffer_load_f32__vgpr_rsrc__sgpr_voffset__vgpr_soff ; GFX10_GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] ; GFX10_GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: raw_tbuffer_load_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY5]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[S_AND_B32_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 [[S_AND_B32_1]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY6]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) + ; GFX11-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: raw_tbuffer_load_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo @@ -291,17 +417,32 @@ define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] ; GFX10_GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 1, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -325,17 +466,32 @@ define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] ; GFX10_GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 2, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 2, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -359,17 +515,32 @@ define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] ; GFX10_GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 3, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 3, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 @@ -393,17 +564,32 @@ define amdgpu_ps float @raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] ; GFX10_GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 4, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_OFFEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: raw_tbuffer_load_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 4, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN]] ; GFX12-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll index 65d4b63483cc61..585fa6a499f7cd 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.f16.ll @@ -36,16 +36,16 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff ; ; GFX12-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) @@ -89,16 +89,16 @@ define amdgpu_ps void @raw_tbuffer_store_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_so ; ; GFX12-LABEL: name: raw_tbuffer_store_v2f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<2 x f16>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.v2f16(<2 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) @@ -145,18 +145,18 @@ define amdgpu_ps void @raw_tbuffer_store_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_so ; ; GFX12-LABEL: name: raw_tbuffer_store_v3f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_OFFEN_exact [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<3 x f16>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.v3f16(<3 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) @@ -205,18 +205,18 @@ define amdgpu_ps void @raw_tbuffer_store_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_so ; ; GFX12-LABEL: name: raw_tbuffer_store_v4f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_exact [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<4 x f16>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.v4f16(<4 x half> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) @@ -322,7 +322,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX12-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -331,7 +331,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: bb.2: @@ -631,7 +631,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soff ; GFX12-LABEL: name: raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -639,7 +639,7 @@ define amdgpu_ps void @raw_tbuffer_store_f16__vgpr_rsrc__sgpr_voffset__vgpr_soff ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo @@ -715,16 +715,16 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff ; ; GFX12-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1) @@ -764,16 +764,16 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff ; ; GFX12-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 2, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2) @@ -813,16 +813,16 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff ; ; GFX12-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 3, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3) @@ -862,16 +862,16 @@ define amdgpu_ps void @raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soff ; ; GFX12-LABEL: name: raw_tbuffer_store_f16__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 4, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f16(half %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll index 6d105f7f89e8f8..01a3ce51e4219d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.i8.ll @@ -36,16 +36,16 @@ define amdgpu_ps void @raw_tbuffer_store_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffs ; ; GFX12-LABEL: name: raw_tbuffer_store_i8__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.i8(i8 %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 94, i32 0) @@ -151,7 +151,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffs ; GFX12-LABEL: name: raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -160,7 +160,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__vgpr_voffset__sgpr_soffs ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: bb.2: @@ -460,7 +460,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__sgpr_voffset__vgpr_soffs ; GFX12-LABEL: name: raw_tbuffer_store_i8__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -468,7 +468,7 @@ define amdgpu_ps void @raw_tbuffer_store_i8__vgpr_rsrc__sgpr_voffset__vgpr_soffs ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll index ec533df1c4c8b4..3753c257490357 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.tbuffer.store.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX10_GFX11 %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX10_GFX11 %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX11 %s ; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX12 %s ; Natural mapping @@ -20,18 +20,33 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) @@ -57,20 +72,37 @@ define amdgpu_ps void @raw_tbuffer_store_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_so ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<2 x f32>), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_XY_OFFEN_exact [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<2 x f32>), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_v2f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact [[REG_SEQUENCE]], [[COPY6]], [[REG_SEQUENCE1]], [[COPY7]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<2 x f32>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.v2f32(<2 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) @@ -97,21 +129,39 @@ define amdgpu_ps void @raw_tbuffer_store_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_so ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact [[REG_SEQUENCE]], [[COPY7]], [[REG_SEQUENCE1]], [[COPY8]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<3 x f32>), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact [[REG_SEQUENCE]], [[COPY7]], [[REG_SEQUENCE1]], [[COPY8]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<3 x f32>), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_v3f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact [[REG_SEQUENCE]], [[COPY7]], [[REG_SEQUENCE1]], [[COPY8]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<3 x f32>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.v3f32(<3 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) @@ -139,22 +189,41 @@ define amdgpu_ps void @raw_tbuffer_store_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_so ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact [[REG_SEQUENCE]], [[COPY8]], [[REG_SEQUENCE1]], [[COPY9]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<4 x f32>), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact [[REG_SEQUENCE]], [[COPY8]], [[REG_SEQUENCE1]], [[COPY9]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<4 x f32>), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_v4f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact [[REG_SEQUENCE]], [[COPY8]], [[REG_SEQUENCE1]], [[COPY9]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (<4 x f32>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.v4f32(<4 x float> %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 0) @@ -179,18 +248,34 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__sgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY7]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY7]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__sgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY7]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 @@ -247,10 +332,57 @@ define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: bb.5: ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 [[S_AND_B32_]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE1]], [[COPY6]], 0, 94, 1, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -259,7 +391,7 @@ define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: bb.2: @@ -349,6 +481,56 @@ define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__vgpr_soff ; GFX10_GFX11-NEXT: bb.5: ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__vgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[S_AND_B32_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 [[S_AND_B32_1]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__vgpr_rsrc__vgpr_voffset__vgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) @@ -455,10 +637,61 @@ define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__sgpr_voffset__vgpr_soff ; GFX10_GFX11-NEXT: bb.5: ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[S_AND_B32_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 [[S_AND_B32_1]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY7]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -466,7 +699,7 @@ define amdgpu_ps void @raw_tbuffer_store_f32__vgpr_rsrc__sgpr_voffset__vgpr_soff ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr5 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo @@ -526,18 +759,33 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_glc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 1, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 1) @@ -561,18 +809,33 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 2, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 2, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 2, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 2) @@ -596,18 +859,33 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 3, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 3, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc_glc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 3, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 3) @@ -631,18 +909,33 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 4, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 4, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_dlc ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 4, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 78, i32 4) @@ -666,17 +959,31 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vdpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vdpr_voffset__sgpr_soffset__voffset0 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 0, i32 %soffset, i32 94, i32 0) @@ -698,17 +1005,31 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 4095, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 4095, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 4095, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 4095, i32 %soffset, i32 94, i32 0) @@ -732,17 +1053,33 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY6]], [[REG_SEQUENCE]], [[COPY5]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset4096 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact [[COPY]], [[REG_SEQUENCE]], [[COPY5]], 4096, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 call void @llvm.amdgcn.raw.tbuffer.store.f32(float %val, <4 x i32> %rsrc, i32 4096, i32 %soffset, i32 94, i32 0) @@ -765,18 +1102,33 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 16, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 %voffset = add i32 %voffset.base, 16 @@ -800,18 +1152,33 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4095, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 %voffset = add i32 %voffset.base, 4095 @@ -838,18 +1205,36 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX11-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], [[COPY6]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset__voffset_add4096 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[COPY6]], 4096, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 %voffset = add i32 %voffset.base, 4096 @@ -873,15 +1258,30 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 @@ -907,15 +1307,30 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset4096 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 @@ -943,18 +1358,35 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 + ; GFX11-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def dead $scc + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add16 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 16 ; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) @@ -982,18 +1414,35 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 + ; GFX11-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def dead $scc + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) @@ -1021,18 +1470,35 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 + ; GFX11-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def dead $scc + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add4096 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 ; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX12-NEXT: TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) @@ -1093,10 +1559,59 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: bb.5: ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000 + ; GFX11-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def dead $scc + ; GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY9]], [[COPY7]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 [[S_AND_B32_]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[COPY5]], [[REG_SEQUENCE1]], [[S_ADD_I32_]], 0, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_1]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_soffset_add5000 ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1105,7 +1620,7 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 5000 ; GFX12-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY6]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX12-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo @@ -1198,10 +1713,60 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX10_GFX11-NEXT: bb.5: ; GFX10_GFX11-NEXT: S_ENDPGM 0 ; + ; GFX11-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add5000 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX11-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec + ; GFX11-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY4]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY10]], [[COPY8]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec + ; GFX11-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_B32 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_AND_SAVEEXEC_B32 [[S_AND_B32_]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: TBUFFER_STORE_FORMAT_X_OFFEN_exact [[COPY]], [[V_ADD_U32_e64_]], [[REG_SEQUENCE1]], [[COPY6]], 904, 94, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) + ; GFX11-NEXT: $exec_lo = S_XOR_B32_term $exec_lo, [[S_AND_SAVEEXEC_B32_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec_lo = S_MOV_B32_term [[S_MOV_B32_1]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: S_ENDPGM 0 + ; ; GFX12-LABEL: name: raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add5000 ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1210,7 +1775,7 @@ define amdgpu_ps void @raw_tbuffer_store_f32__sgpr_rsrc__vgpr_voffset__sgpr_soff ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: bb.2: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll index fd87656878190c..eaa8fc972ddb31 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.s.buffer.load.ll @@ -59,14 +59,14 @@ define amdgpu_ps i32 @s_buffer_load_i32(<4 x i32> inreg %rsrc, i32 inreg %soffse ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (s32)) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec @@ -127,14 +127,14 @@ define amdgpu_ps i32 @s_buffer_load_i32_glc(<4 x i32> inreg %rsrc, i32 inreg %so ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_glc ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 1 :: (dereferenceable invariant load (s32)) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_SGPR_IMM]] ; GFX1200_1250-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY5]], implicit $exec @@ -210,14 +210,14 @@ define amdgpu_ps <2 x i32> @s_buffer_load_v2i32(<4 x i32> inreg %rsrc, i32 inreg ; ; GFX1200_1250-LABEL: name: s_buffer_load_v2i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM:%[0-9]+]]:sreg_64_xexec = S_BUFFER_LOAD_DWORDX2_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (s64)) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM]].sub0 ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX2_SGPR_IMM]].sub1 @@ -313,14 +313,14 @@ define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg ; ; GFX1200_1250-LABEL: name: s_buffer_load_v3i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM:%[0-9]+]]:sgpr_96 = S_BUFFER_LOAD_DWORDX3_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (s96), align 16) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub0 ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX3_SGPR_IMM]].sub1 @@ -477,14 +477,14 @@ define amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg ; ; GFX1200_1250-LABEL: name: s_buffer_load_v8i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM:%[0-9]+]]:sgpr_256 = S_BUFFER_LOAD_DWORDX8_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (s256)) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub0 ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX8_SGPR_IMM]].sub1 @@ -757,14 +757,14 @@ define amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inr ; ; GFX1200_1250-LABEL: name: s_buffer_load_v16i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM:%[0-9]+]]:sgpr_512 = S_BUFFER_LOAD_DWORDX16_SGPR_IMM [[REG_SEQUENCE]], [[COPY4]], 0, 0 :: (dereferenceable invariant load (s512)) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub0 ; GFX1200_1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[S_BUFFER_LOAD_DWORDX16_SGPR_IMM]].sub1 @@ -885,12 +885,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_1(<4 x i32> inreg %rsrc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_1 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1, 0 :: (dereferenceable invariant load (s32)) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -949,12 +949,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_glc_4(<4 x i32> inreg %rsrc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_glc_4 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 4, 1 :: (dereferenceable invariant load (s32)) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1015,12 +1015,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_255(<4 x i32> inreg %rsrc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_255 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 255, 0 :: (dereferenceable invariant load (s32)) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1079,12 +1079,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_256(<4 x i32> inreg %rsrc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_256 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 256, 0 :: (dereferenceable invariant load (s32)) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1143,12 +1143,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_1020(<4 x i32> inreg %rsrc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_1020 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1020, 0 :: (dereferenceable invariant load (s32)) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1209,12 +1209,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_1023(<4 x i32> inreg %rsrc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_1023 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1023, 0 :: (dereferenceable invariant load (s32)) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1274,12 +1274,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_1024(<4 x i32> inreg %rsrc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_1024 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1024, 0 :: (dereferenceable invariant load (s32)) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1340,12 +1340,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_1025(<4 x i32> inreg %rsrc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_1025 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1025, 0 :: (dereferenceable invariant load (s32)) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1407,12 +1407,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_neg1(<4 x i32> inreg %desc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_neg1 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (s32)) @@ -1474,12 +1474,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_neg4(<4 x i32> inreg %desc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_neg4 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (s32)) @@ -1541,12 +1541,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_neg8(<4 x i32> inreg %desc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_neg8 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -8 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (s32)) @@ -1608,12 +1608,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_bit31(<4 x i32> inreg %desc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_bit31 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (s32)) @@ -1675,12 +1675,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_glc_bit30(<4 x i32> inreg %desc) ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_glc_bit30 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1073741824 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 1 :: (dereferenceable invariant load (s32)) @@ -1742,12 +1742,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_bit29(<4 x i32> inreg %desc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_bit29 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 536870912 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (s32)) @@ -1809,12 +1809,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_bit21(<4 x i32> inreg %desc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_bit21 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 2097152, 0 :: (dereferenceable invariant load (s32)) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1875,12 +1875,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_bit20(<4 x i32> inreg %desc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_bit20 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 1048576, 0 :: (dereferenceable invariant load (s32)) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -1941,12 +1941,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_neg_bit20(<4 x i32> inreg %desc) ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_neg_bit20 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -1048576 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (s32)) @@ -2007,12 +2007,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_bit19(<4 x i32> inreg %desc) { ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_bit19 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_IMM [[REG_SEQUENCE]], 524288, 0 :: (dereferenceable invariant load (s32)) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_BUFFER_LOAD_DWORD_IMM]] @@ -2073,12 +2073,12 @@ define amdgpu_ps i32 @s_buffer_load_i32_offset_neg_bit19(<4 x i32> inreg %desc) ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32_offset_neg_bit19 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -524288 ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_MOV_B32_]], 0, 0 :: (dereferenceable invariant load (s32)) @@ -2139,12 +2139,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 ; ; GFX1200_1250-LABEL: name: s_buffer_load_f32_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200_1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32)) @@ -2211,12 +2211,12 @@ define amdgpu_ps <2 x float> @s_buffer_load_v2f32_vgpr_offset(<4 x i32> inreg %r ; ; GFX1200-LABEL: name: s_buffer_load_v2f32_vgpr_offset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s64)) @@ -2228,12 +2228,12 @@ define amdgpu_ps <2 x float> @s_buffer_load_v2f32_vgpr_offset(<4 x i32> inreg %r ; ; GFX1250-LABEL: name: s_buffer_load_v2f32_vgpr_offset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s64)) @@ -2312,12 +2312,12 @@ define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %r ; ; GFX1200-LABEL: name: s_buffer_load_v3f32_vgpr_offset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s96), align 16) @@ -2331,12 +2331,12 @@ define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %r ; ; GFX1250-LABEL: name: s_buffer_load_v3f32_vgpr_offset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:%[0-9]+]]:vreg_96_align2 = BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s96), align 16) @@ -2420,12 +2420,12 @@ define amdgpu_ps <4 x float> @s_buffer_load_v4f32_vgpr_offset(<4 x i32> inreg %r ; ; GFX1200-LABEL: name: s_buffer_load_v4f32_vgpr_offset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) @@ -2441,12 +2441,12 @@ define amdgpu_ps <4 x float> @s_buffer_load_v4f32_vgpr_offset(<4 x i32> inreg %r ; ; GFX1250-LABEL: name: s_buffer_load_v4f32_vgpr_offset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128)) @@ -2562,12 +2562,12 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset(<4 x i32> inreg %r ; ; GFX1200-LABEL: name: s_buffer_load_v8f32_vgpr_offset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128), align 32) @@ -2593,12 +2593,12 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset(<4 x i32> inreg %r ; ; GFX1250-LABEL: name: s_buffer_load_v8f32_vgpr_offset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128), align 32) @@ -2778,12 +2778,12 @@ define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset(<4 x i32> inreg ; ; GFX1200-LABEL: name: s_buffer_load_v16f32_vgpr_offset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128), align 64) @@ -2827,12 +2827,12 @@ define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset(<4 x i32> inreg ; ; GFX1250-LABEL: name: s_buffer_load_v16f32_vgpr_offset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128), align 64) @@ -2925,12 +2925,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4092(<4 x i32> inreg % ; ; GFX1200-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32)) @@ -2939,12 +2939,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4092(<4 x i32> inreg % ; ; GFX1250-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4092 @@ -3006,12 +3006,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4095(<4 x i32> inreg % ; ; GFX1200-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4095, 0, 0, implicit $exec :: (dereferenceable invariant load (s32)) @@ -3020,12 +3020,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4095(<4 x i32> inreg % ; ; GFX1250-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 @@ -3087,12 +3087,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4092_nuw(<4 x i32> inr ; ; GFX1200_1250-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092_nuw ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200_1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4092, 0, 0, implicit $exec :: (dereferenceable invariant load (s32)) @@ -3151,12 +3151,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4096(<4 x i32> inreg % ; ; GFX1200-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4096, 0, 0, implicit $exec :: (dereferenceable invariant load (s32)) @@ -3165,12 +3165,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4096(<4 x i32> inreg % ; ; GFX1250-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 @@ -3284,12 +3284,12 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4064(<4 x i32> ; ; GFX1200-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4064, 0, 0, implicit $exec :: (dereferenceable invariant load (s128), align 32) @@ -3315,12 +3315,12 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4064(<4 x i32> ; ; GFX1250-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4064 @@ -3451,12 +3451,12 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4068(<4 x i32> ; ; GFX1200-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4068, 0, 0, implicit $exec :: (dereferenceable invariant load (s128), align 32) @@ -3482,12 +3482,12 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4068(<4 x i32> ; ; GFX1250-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068 @@ -3671,12 +3671,12 @@ define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4032(<4 x i3 ; ; GFX1200-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4032, 0, 0, implicit $exec :: (dereferenceable invariant load (s128), align 64) @@ -3720,12 +3720,12 @@ define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4032(<4 x i3 ; ; GFX1250-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4032 @@ -3927,12 +3927,12 @@ define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4036(<4 x i3 ; ; GFX1200-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], $sgpr_null, 4036, 0, 0, implicit $exec :: (dereferenceable invariant load (s128), align 64) @@ -3976,12 +3976,12 @@ define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4036(<4 x i3 ; ; GFX1250-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4036 @@ -4179,14 +4179,14 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg % ; GFX1200-LABEL: name: s_buffer_load_f32_vgpr_rsrc ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1200-NEXT: {{ $}} @@ -4226,14 +4226,14 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg % ; GFX1250-LABEL: name: s_buffer_load_f32_vgpr_rsrc ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1250-NEXT: {{ $}} @@ -4416,14 +4416,14 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> % ; GFX1200-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092 ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: bb.2: @@ -4462,14 +4462,14 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> % ; GFX1250-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092 ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4092 ; GFX1250-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]] @@ -4667,14 +4667,14 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> % ; GFX1200-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096 ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: bb.2: @@ -4713,14 +4713,14 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> % ; GFX1250-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096 ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 ; GFX1250-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]] @@ -5432,14 +5432,14 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> % ; GFX1200-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064 ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: bb.2: @@ -5495,14 +5495,14 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> % ; GFX1250-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064 ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4064 ; GFX1250-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]] @@ -5769,14 +5769,14 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> % ; GFX1200-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068 ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: bb.2: @@ -5832,14 +5832,14 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> % ; GFX1250-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068 ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4068 ; GFX1250-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]] @@ -6104,14 +6104,14 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> % ; GFX1200-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096 ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_MOV_B32 $exec_lo ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: bb.2: @@ -6167,14 +6167,14 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> % ; GFX1250-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096 ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4096 ; GFX1250-NEXT: [[S_ADD_I32_:%[0-9]+]]:sreg_32 = S_ADD_I32 [[COPY4]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_I32_]] @@ -7577,30 +7577,30 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr(<4 x i32> inreg % ; ; GFX1200-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32)) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; ; GFX1250-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32)) @@ -7659,30 +7659,30 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr(<4 x i32> inreg % ; ; GFX1200-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[COPY4]], [[REG_SEQUENCE]], [[COPY5]], 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32)) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN]] ; GFX1200-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; ; GFX1250-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY6]], [[COPY4]], 0, implicit $exec ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s32)) @@ -7750,15 +7750,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr_imm(<4 x i32> inr ; ; GFX1200-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX1200-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 1024, 0, 0, implicit $exec :: (dereferenceable invariant load (s32)) @@ -7767,15 +7767,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr_imm(<4 x i32> inr ; ; GFX1250-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] @@ -7846,15 +7846,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr_imm(<4 x i32> inr ; ; GFX1200-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX1200-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY6]], [[COPY4]], 0, implicit $exec ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 1024, 0, 0, implicit $exec :: (dereferenceable invariant load (s32)) @@ -7863,15 +7863,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr_imm(<4 x i32> inr ; ; GFX1250-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] @@ -7943,15 +7943,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_sgpr_vgpr(<4 x i32> inr ; ; GFX1200-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX1200-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY6]], [[COPY4]], 0, implicit $exec ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 1024, 0, 0, implicit $exec :: (dereferenceable invariant load (s32)) @@ -7960,15 +7960,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_sgpr_vgpr(<4 x i32> inr ; ; GFX1250-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] @@ -8039,15 +8039,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_vgpr_sgpr(<4 x i32> inr ; ; GFX1200-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX1200-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY4]], [[COPY6]], 0, implicit $exec ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_OFFEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_OFFEN [[V_ADD_U32_e64_]], [[REG_SEQUENCE]], $sgpr_null, 1024, 0, 0, implicit $exec :: (dereferenceable invariant load (s32)) @@ -8056,15 +8056,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_vgpr_sgpr(<4 x i32> inr ; ; GFX1250-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1024 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] @@ -8129,14 +8129,14 @@ define amdgpu_ps float @s_buffer_load_f32_offset_or_vgpr_imm(<4 x i32> inreg %rs ; ; GFX1200_1250-LABEL: name: s_buffer_load_f32_offset_or_vgpr_imm ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200_1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200_1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -2147483648 ; GFX1200_1250-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[COPY4]], [[S_MOV_B32_]], implicit-def dead $scc ; GFX1200_1250-NEXT: [[S_BUFFER_LOAD_DWORD_SGPR_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_BUFFER_LOAD_DWORD_SGPR_IMM [[REG_SEQUENCE]], [[S_OR_B32_]], 0, 0 :: (dereferenceable invariant load (s32)) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll index dc3d641b6d8d0b..1116951f8d74f1 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.add.ll @@ -25,17 +25,17 @@ define amdgpu_ps float @struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_ ; ; GFX1200-LABEL: name: struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN]] @@ -43,17 +43,17 @@ define amdgpu_ps float @struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_ ; ; GFX1250-LABEL: name: struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN]] @@ -83,34 +83,34 @@ define amdgpu_ps void @struct_buffer_atomic_add_i32_noret__vgpr_val__sgpr_rsrc__ ; ; GFX1200-LABEL: name: struct_buffer_atomic_add_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_atomic_add_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -144,19 +144,19 @@ define amdgpu_ps <2 x float> @struct_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc_ ; ; GFX1200-LABEL: name: struct_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN]].sub0 @@ -167,19 +167,19 @@ define amdgpu_ps <2 x float> @struct_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc_ ; ; GFX1250-LABEL: name: struct_buffer_atomic_add_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_64_align2 = BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN]].sub0 @@ -214,38 +214,38 @@ define amdgpu_ps void @struct_buffer_atomic_add_i64_noret__vgpr_val__sgpr_rsrc__ ; ; GFX1200-LABEL: name: struct_buffer_atomic_add_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_atomic_add_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -314,16 +314,16 @@ define amdgpu_ps float @struct_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_ ; GFX1200-LABEL: name: struct_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -370,16 +370,16 @@ define amdgpu_ps float @struct_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_ ; GFX1250-LABEL: name: struct_buffer_atomic_add_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -487,16 +487,16 @@ define amdgpu_ps void @struct_buffer_atomic_add_i32_noret__sgpr_val__vgpr_rsrc__ ; GFX1200-LABEL: name: struct_buffer_atomic_add_i32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -542,16 +542,16 @@ define amdgpu_ps void @struct_buffer_atomic_add_i32_noret__sgpr_val__vgpr_rsrc__ ; GFX1250-LABEL: name: struct_buffer_atomic_add_i32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -619,17 +619,17 @@ define amdgpu_ps float @struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_ ; ; GFX1200-LABEL: name: struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 3, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN]] @@ -637,17 +637,17 @@ define amdgpu_ps float @struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_ ; ; GFX1250-LABEL: name: struct_buffer_atomic_add_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 3, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN]] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll index 7682096d78c1de..9dcd64f8ca0505 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.cmpswap.ll @@ -28,18 +28,18 @@ define amdgpu_ps float @struct_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sg ; ; GFX1200-LABEL: name: struct_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY8]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) @@ -49,18 +49,18 @@ define amdgpu_ps float @struct_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sg ; ; GFX1250-LABEL: name: struct_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_64_align2 = BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY8]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) @@ -95,18 +95,18 @@ define amdgpu_ps void @struct_buffer_atomic_cmpswap_noret_i32__vgpr_val__vgpr_cm ; ; GFX1200-LABEL: name: struct_buffer_atomic_cmpswap_noret_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) @@ -114,18 +114,18 @@ define amdgpu_ps void @struct_buffer_atomic_cmpswap_noret_i32__vgpr_val__vgpr_cm ; ; GFX1250-LABEL: name: struct_buffer_atomic_cmpswap_noret_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY8]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) @@ -199,17 +199,17 @@ define amdgpu_ps float @struct_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vg ; GFX1200-LABEL: name: struct_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] @@ -259,17 +259,17 @@ define amdgpu_ps float @struct_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vg ; GFX1250-LABEL: name: struct_buffer_atomic_cmpswap_i32__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] @@ -383,17 +383,17 @@ define amdgpu_ps void @struct_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cm ; GFX1200-LABEL: name: struct_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] @@ -441,17 +441,17 @@ define amdgpu_ps void @struct_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cm ; GFX1250-LABEL: name: struct_buffer_atomic_cmpswap_i32_noret__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[COPY1]] @@ -523,18 +523,18 @@ define amdgpu_ps float @struct_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sg ; ; GFX1200-LABEL: name: struct_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY8]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) @@ -544,18 +544,18 @@ define amdgpu_ps float @struct_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sg ; ; GFX1250-LABEL: name: struct_buffer_atomic_cmpswap_i32__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY7]], [[COPY9]], 0, implicit $exec @@ -603,7 +603,7 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__s ; ; GFX1200-LABEL: name: struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -611,14 +611,14 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__s ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 ; GFX1200-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3 ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) @@ -631,7 +631,7 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__s ; ; GFX1250-LABEL: name: struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -639,14 +639,14 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__s ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 ; GFX1250-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3 ; GFX1250-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128_align2 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) @@ -688,7 +688,7 @@ define amdgpu_ps void @struct_buffer_atomic_cmpswap_noret_i64__vgpr_val__vgpr_cm ; ; GFX1200-LABEL: name: struct_buffer_atomic_cmpswap_noret_i64__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -696,14 +696,14 @@ define amdgpu_ps void @struct_buffer_atomic_cmpswap_noret_i64__vgpr_val__vgpr_cm ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 ; GFX1200-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3 ; GFX1200-NEXT: BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) @@ -711,7 +711,7 @@ define amdgpu_ps void @struct_buffer_atomic_cmpswap_noret_i64__vgpr_val__vgpr_cm ; ; GFX1250-LABEL: name: struct_buffer_atomic_cmpswap_noret_i64__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -719,14 +719,14 @@ define amdgpu_ps void @struct_buffer_atomic_cmpswap_noret_i64__vgpr_val__vgpr_cm ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 ; GFX1250-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3 ; GFX1250-NEXT: BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) @@ -807,21 +807,21 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__v ; GFX1200-LABEL: name: struct_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]] ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]] @@ -874,21 +874,21 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__v ; GFX1250-LABEL: name: struct_buffer_atomic_cmpswap_i64__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]] ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]] @@ -1009,21 +1009,21 @@ define amdgpu_ps void @struct_buffer_atomic_cmpswap_i64_noret__sgpr_val__sgpr_cm ; GFX1200-LABEL: name: struct_buffer_atomic_cmpswap_i64_noret__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]] ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]] @@ -1071,21 +1071,21 @@ define amdgpu_ps void @struct_buffer_atomic_cmpswap_i64_noret__sgpr_val__sgpr_cm ; GFX1250-LABEL: name: struct_buffer_atomic_cmpswap_i64_noret__sgpr_val__sgpr_cmp__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]] ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]] @@ -1164,7 +1164,7 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__s ; ; GFX1200-LABEL: name: struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1172,14 +1172,14 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__s ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 ; GFX1200-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3 ; GFX1200-NEXT: [[BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_128 = BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE4]], [[REG_SEQUENCE3]], [[REG_SEQUENCE2]], [[COPY10]], 4095, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) @@ -1192,7 +1192,7 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__s ; ; GFX1250-LABEL: name: struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__sgpr_rsrc__vgpr_voffset__sgpr_soffset_voffset_add4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -1200,14 +1200,14 @@ define amdgpu_ps double @struct_buffer_atomic_cmpswap_i64__vgpr_val__vgpr_cmp__s ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY9]], [[COPY11]], 0, implicit $exec diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.sub.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.sub.ll index bc14287f2e1eab..50258cee3d12d8 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.sub.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.sub.ll @@ -25,17 +25,17 @@ define amdgpu_ps float @struct_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_ ; ; GFX1200-LABEL: name: struct_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN]] @@ -43,17 +43,17 @@ define amdgpu_ps float @struct_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_ ; ; GFX1250-LABEL: name: struct_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN]] @@ -83,34 +83,34 @@ define amdgpu_ps void @struct_buffer_atomic_sub_i32_noret__vgpr_val__sgpr_rsrc__ ; ; GFX1200-LABEL: name: struct_buffer_atomic_sub_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_atomic_sub_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -144,19 +144,19 @@ define amdgpu_ps <2 x float> @struct_buffer_atomic_sub_i64__vgpr_val__sgpr_rsrc_ ; ; GFX1200-LABEL: name: struct_buffer_atomic_sub_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN]].sub0 @@ -167,19 +167,19 @@ define amdgpu_ps <2 x float> @struct_buffer_atomic_sub_i64__vgpr_val__sgpr_rsrc_ ; ; GFX1250-LABEL: name: struct_buffer_atomic_sub_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_64_align2 = BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN]].sub0 @@ -214,38 +214,38 @@ define amdgpu_ps void @struct_buffer_atomic_sub_i64_noret__vgpr_val__sgpr_rsrc__ ; ; GFX1200-LABEL: name: struct_buffer_atomic_sub_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_atomic_sub_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -314,16 +314,16 @@ define amdgpu_ps float @struct_buffer_atomic_sub_i32__sgpr_val__vgpr_rsrc__sgpr_ ; GFX1200-LABEL: name: struct_buffer_atomic_sub_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -370,16 +370,16 @@ define amdgpu_ps float @struct_buffer_atomic_sub_i32__sgpr_val__vgpr_rsrc__sgpr_ ; GFX1250-LABEL: name: struct_buffer_atomic_sub_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -487,16 +487,16 @@ define amdgpu_ps void @struct_buffer_atomic_sub_i32_noret__sgpr_val__vgpr_rsrc__ ; GFX1200-LABEL: name: struct_buffer_atomic_sub_i32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -542,16 +542,16 @@ define amdgpu_ps void @struct_buffer_atomic_sub_i32_noret__sgpr_val__vgpr_rsrc__ ; GFX1250-LABEL: name: struct_buffer_atomic_sub_i32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -619,17 +619,17 @@ define amdgpu_ps float @struct_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_ ; ; GFX1200-LABEL: name: struct_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 3, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN]] @@ -637,17 +637,17 @@ define amdgpu_ps float @struct_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_ ; ; GFX1250-LABEL: name: struct_buffer_atomic_sub_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 3, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN]] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.swap.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.swap.ll index dc574bf62d657b..66e67e5d515e03 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.swap.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.atomic.swap.ll @@ -23,17 +23,17 @@ define amdgpu_ps float @struct_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr ; ; GFX1200-LABEL: name: struct_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN]] @@ -41,17 +41,17 @@ define amdgpu_ps float @struct_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr ; ; GFX1250-LABEL: name: struct_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN]] @@ -81,34 +81,34 @@ define amdgpu_ps void @struct_buffer_atomic_swap_i32_noret__vgpr_val__sgpr_rsrc_ ; ; GFX1200-LABEL: name: struct_buffer_atomic_swap_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_atomic_swap_i32_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -142,19 +142,19 @@ define amdgpu_ps <2 x float> @struct_buffer_atomic_swap_i64__vgpr_val__sgpr_rsrc ; ; GFX1200-LABEL: name: struct_buffer_atomic_swap_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_64 = BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN]].sub0 @@ -165,19 +165,19 @@ define amdgpu_ps <2 x float> @struct_buffer_atomic_swap_i64__vgpr_val__sgpr_rsrc ; ; GFX1250-LABEL: name: struct_buffer_atomic_swap_i64__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vreg_64_align2 = BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 1, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN]].sub0 @@ -212,38 +212,38 @@ define amdgpu_ps void @struct_buffer_atomic_swap_i64_noret__vgpr_val__sgpr_rsrc_ ; ; GFX1200-LABEL: name: struct_buffer_atomic_swap_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_atomic_swap_i64_noret__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, implicit $exec :: (volatile dereferenceable load store (i64), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -311,16 +311,16 @@ define amdgpu_ps float @struct_buffer_atomic_swap_i32__sgpr_val__vgpr_rsrc__sgpr ; GFX1200-LABEL: name: struct_buffer_atomic_swap_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -367,16 +367,16 @@ define amdgpu_ps float @struct_buffer_atomic_swap_i32__sgpr_val__vgpr_rsrc__sgpr ; GFX1250-LABEL: name: struct_buffer_atomic_swap_i32__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -483,16 +483,16 @@ define amdgpu_ps void @struct_buffer_atomic_swap_i32_noret__sgpr_val__vgpr_rsrc_ ; GFX1200-LABEL: name: struct_buffer_atomic_swap_i32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -538,16 +538,16 @@ define amdgpu_ps void @struct_buffer_atomic_swap_i32_noret__sgpr_val__vgpr_rsrc_ ; GFX1250-LABEL: name: struct_buffer_atomic_swap_i32_noret__sgpr_val__vgpr_rsrc__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -614,17 +614,17 @@ define amdgpu_ps float @struct_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr ; ; GFX1200-LABEL: name: struct_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 3, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN]] @@ -632,17 +632,17 @@ define amdgpu_ps float @struct_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr ; ; GFX1250-LABEL: name: struct_buffer_atomic_swap_i32__vgpr_val__sgpr_rsrc__vgpr_voffset__sgpr_soffset_slc ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN:%[0-9]+]]:vgpr_32 = BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 3, implicit $exec :: (volatile dereferenceable load store (i32), align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN]] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll index c0d5876ad5b152..fb7ee6cf7071a6 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.f16.ll @@ -40,16 +40,16 @@ define amdgpu_ps half @struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vg ; ; GFX12-LABEL: name: struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN]] @@ -106,16 +106,16 @@ define amdgpu_ps <2 x half> @struct_buffer_load_format_v2f16__sgpr_rsrc__vgpr_vi ; ; GFX12-LABEL: name: struct_buffer_load_format_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f16>), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN]] @@ -191,16 +191,16 @@ define amdgpu_ps <4 x half> @struct_buffer_load_format_v4f16__sgpr_rsrc__vgpr_vi ; ; GFX12-LABEL: name: struct_buffer_load_format_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN]].sub0 @@ -349,15 +349,15 @@ define amdgpu_ps <4 x half> @struct_buffer_load_format_v4f16__vpr_rsrc__sgpr_vin ; GFX12-LABEL: name: struct_buffer_load_format_v4f16__vpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -443,16 +443,16 @@ define amdgpu_ps half @struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vg ; ; GFX12-LABEL: name: struct_buffer_load_format_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffsset_add_4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN]] @@ -499,16 +499,16 @@ define amdgpu_ps half @struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vg ; ; GFX12-LABEL: name: struct_buffer_load_format_i16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8) ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_16 = COPY [[BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN]].lo16 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll index 941cd6abe1494e..285237083b84d1 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.format.ll @@ -23,16 +23,16 @@ define amdgpu_ps float @struct_buffer_load_format_f32__sgpr_rsrc__vgpr_vindex__v ; ; GFX12-LABEL: name: struct_buffer_load_format_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN]] @@ -64,16 +64,16 @@ define amdgpu_ps <2 x float> @struct_buffer_load_format_v2f32__sgpr_rsrc__vgpr_v ; ; GFX12-LABEL: name: struct_buffer_load_format_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN]].sub0 @@ -110,16 +110,16 @@ define amdgpu_ps <3 x float> @struct_buffer_load_format_v3f32__sgpr_rsrc__vgpr_v ; ; GFX12-LABEL: name: struct_buffer_load_format_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN]].sub0 @@ -160,16 +160,16 @@ define amdgpu_ps <4 x float> @struct_buffer_load_format_v4f32__sgpr_rsrc__vgpr_v ; ; GFX12-LABEL: name: struct_buffer_load_format_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN]].sub0 @@ -251,15 +251,15 @@ define amdgpu_ps <4 x float> @struct_buffer_load_format_v4f32__vpr_rsrc__sgpr_vi ; GFX12-LABEL: name: struct_buffer_load_format_v4f32__vpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -332,16 +332,16 @@ define amdgpu_ps float @struct_buffer_load_format_f32__sgpr_rsrc__vgpr_vindex__v ; ; GFX12-LABEL: name: struct_buffer_load_format_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffsset_add_4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN]] @@ -371,16 +371,16 @@ define amdgpu_ps float @struct_buffer_load_format_i32__sgpr_rsrc__vgpr_vindex__v ; ; GFX12-LABEL: name: struct_buffer_load_format_i32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i32), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN]] @@ -426,12 +426,12 @@ define amdgpu_cs void @struct_buffer_load_format_v4i32_tfe(<4 x i32> inreg %rsrc ; ; GFX12-LABEL: name: struct_buffer_load_format_v4i32_tfe ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -501,12 +501,12 @@ define amdgpu_cs void @struct_buffer_load_format_v3i32_tfe(<4 x i32> inreg %rsrc ; ; GFX12-LABEL: name: struct_buffer_load_format_v3i32_tfe ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -567,12 +567,12 @@ define amdgpu_cs void @struct_buffer_load_format_i32_tfe(<4 x i32> inreg %rsrc, ; ; GFX12-LABEL: name: struct_buffer_load_format_i32_tfe ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll index 33f97c8f97c077..0fa3de8e76c61a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll @@ -24,16 +24,16 @@ define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vof ; ; GFX1200-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_BOTHEN]] @@ -41,16 +41,16 @@ define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vof ; ; GFX1250-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_BOTHEN]] @@ -83,16 +83,16 @@ define amdgpu_ps <2 x float> @struct_buffer_load_v2f32__sgpr_rsrc__vgpr_vindex__ ; ; GFX1200-LABEL: name: struct_buffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN]].sub0 @@ -103,16 +103,16 @@ define amdgpu_ps <2 x float> @struct_buffer_load_v2f32__sgpr_rsrc__vgpr_vindex__ ; ; GFX1250-LABEL: name: struct_buffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN]].sub0 @@ -150,16 +150,16 @@ define amdgpu_ps <3 x float> @struct_buffer_load_v3f32__sgpr_rsrc__vgpr_vindex__ ; ; GFX1200-LABEL: name: struct_buffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN:%[0-9]+]]:vreg_96 = BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN]].sub0 @@ -172,16 +172,16 @@ define amdgpu_ps <3 x float> @struct_buffer_load_v3f32__sgpr_rsrc__vgpr_vindex__ ; ; GFX1250-LABEL: name: struct_buffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN:%[0-9]+]]:vreg_96_align2 = BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN]].sub0 @@ -223,16 +223,16 @@ define amdgpu_ps <4 x float> @struct_buffer_load_v4f32__sgpr_rsrc__vgpr_vindex__ ; ; GFX1200-LABEL: name: struct_buffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN]].sub0 @@ -247,16 +247,16 @@ define amdgpu_ps <4 x float> @struct_buffer_load_v4f32__sgpr_rsrc__vgpr_vindex__ ; ; GFX1250-LABEL: name: struct_buffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN:%[0-9]+]]:vreg_128_align2 = BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN]].sub0 @@ -294,15 +294,15 @@ define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vof ; ; GFX1200-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1 @@ -312,15 +312,15 @@ define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vof ; ; GFX1250-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1 @@ -352,16 +352,16 @@ define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vof ; ; GFX1200-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_BOTHEN]] @@ -369,16 +369,16 @@ define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vof ; ; GFX1250-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 4095 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX1250-NEXT: [[V_ADD_U32_e64_:%[0-9]+]]:vgpr_32 = V_ADD_U32_e64 [[COPY5]], [[COPY7]], 0, implicit $exec @@ -411,12 +411,12 @@ define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vof ; ; GFX1200-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_soffset_64 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -428,12 +428,12 @@ define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vof ; ; GFX1250-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_soffset_64 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 @@ -505,15 +505,15 @@ define amdgpu_ps float @struct_buffer_load_f32__vgpr_rsrc__sgpr_vindex__sgpr_vof ; GFX1200-LABEL: name: struct_buffer_load_f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -559,15 +559,15 @@ define amdgpu_ps float @struct_buffer_load_f32__vgpr_rsrc__sgpr_vindex__sgpr_vof ; GFX1250-LABEL: name: struct_buffer_load_f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -633,16 +633,16 @@ define amdgpu_ps float @struct_buffer_load_i8_zext__sgpr_rsrc__vgpr_vindex__vgpr ; ; GFX1200-LABEL: name: struct_buffer_load_i8_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i8), addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN]] @@ -650,16 +650,16 @@ define amdgpu_ps float @struct_buffer_load_i8_zext__sgpr_rsrc__vgpr_vindex__vgpr ; ; GFX1250-LABEL: name: struct_buffer_load_i8_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i8), addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN]] @@ -690,16 +690,16 @@ define amdgpu_ps float @struct_buffer_load_i8_sext__sgpr_rsrc__vgpr_vindex__vgpr ; ; GFX1200-LABEL: name: struct_buffer_load_i8_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i8), addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN]] @@ -707,16 +707,16 @@ define amdgpu_ps float @struct_buffer_load_i8_sext__sgpr_rsrc__vgpr_vindex__vgpr ; ; GFX1250-LABEL: name: struct_buffer_load_i8_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i8), addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN]] @@ -748,16 +748,16 @@ define amdgpu_ps float @struct_buffer_load_i8_sext_wrong_width(<4 x i32> inreg % ; ; GFX1200-LABEL: name: struct_buffer_load_i8_sext_wrong_width ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i8), addrspace 8) ; GFX1200-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN]], 0, 4, implicit $exec @@ -766,16 +766,16 @@ define amdgpu_ps float @struct_buffer_load_i8_sext_wrong_width(<4 x i32> inreg % ; ; GFX1250-LABEL: name: struct_buffer_load_i8_sext_wrong_width ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i8), addrspace 8) ; GFX1250-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN]], 0, 4, implicit $exec @@ -808,16 +808,16 @@ define amdgpu_ps float @struct_buffer_load_i16_zext__sgpr_rsrc__vgpr_vindex__vgp ; ; GFX1200-LABEL: name: struct_buffer_load_i16_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_USHORT_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_USHORT_VBUFFER_BOTHEN]] @@ -825,16 +825,16 @@ define amdgpu_ps float @struct_buffer_load_i16_zext__sgpr_rsrc__vgpr_vindex__vgp ; ; GFX1250-LABEL: name: struct_buffer_load_i16_zext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_LOAD_USHORT_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_USHORT_VBUFFER_BOTHEN]] @@ -865,16 +865,16 @@ define amdgpu_ps float @struct_buffer_load_i16_sext__sgpr_rsrc__vgpr_vindex__vgp ; ; GFX1200-LABEL: name: struct_buffer_load_i16_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN]] @@ -882,16 +882,16 @@ define amdgpu_ps float @struct_buffer_load_i16_sext__sgpr_rsrc__vgpr_vindex__vgp ; ; GFX1250-LABEL: name: struct_buffer_load_i16_sext__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN]] @@ -923,16 +923,16 @@ define amdgpu_ps float @struct_buffer_load_i16_sext_wrong_width(<4 x i32> inreg ; ; GFX1200-LABEL: name: struct_buffer_load_i16_sext_wrong_width ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_USHORT_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8) ; GFX1200-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[BUFFER_LOAD_USHORT_VBUFFER_BOTHEN]], 0, 8, implicit $exec @@ -941,16 +941,16 @@ define amdgpu_ps float @struct_buffer_load_i16_sext_wrong_width(<4 x i32> inreg ; ; GFX1250-LABEL: name: struct_buffer_load_i16_sext_wrong_width ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_LOAD_USHORT_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (i16), align 1, addrspace 8) ; GFX1250-NEXT: [[V_BFE_I32_e64_:%[0-9]+]]:vgpr_32 = V_BFE_I32_e64 [[BUFFER_LOAD_USHORT_VBUFFER_BOTHEN]], 0, 8, implicit $exec @@ -984,16 +984,16 @@ define amdgpu_ps half @struct_buffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voff ; ; GFX1200-LABEL: name: struct_buffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_USHORT_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_USHORT_VBUFFER_BOTHEN]] @@ -1001,16 +1001,16 @@ define amdgpu_ps half @struct_buffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voff ; ; GFX1250-LABEL: name: struct_buffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_LOAD_USHORT_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_USHORT_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_USHORT_VBUFFER_BOTHEN]] @@ -1040,16 +1040,16 @@ define amdgpu_ps <2 x half> @struct_buffer_load_v2f16__sgpr_rsrc__vgpr_vindex__v ; ; GFX1200-LABEL: name: struct_buffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f16>), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_BOTHEN]] @@ -1057,16 +1057,16 @@ define amdgpu_ps <2 x half> @struct_buffer_load_v2f16__sgpr_rsrc__vgpr_vindex__v ; ; GFX1250-LABEL: name: struct_buffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<2 x f16>), align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_BOTHEN]] @@ -1105,16 +1105,16 @@ define amdgpu_ps <4 x half> @struct_buffer_load_v4f16__sgpr_rsrc__vgpr_vindex__v ; ; GFX1200-LABEL: name: struct_buffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:%[0-9]+]]:vreg_64 = BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>), align 1, addrspace 8) ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN]].sub0 @@ -1125,16 +1125,16 @@ define amdgpu_ps <4 x half> @struct_buffer_load_v4f16__sgpr_rsrc__vgpr_vindex__v ; ; GFX1250-LABEL: name: struct_buffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:%[0-9]+]]:vreg_64_align2 = BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>), align 1, addrspace 8) ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN]].sub0 @@ -1167,16 +1167,16 @@ define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vof ; ; GFX1200-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_glc ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1200-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX1200-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_BOTHEN]] @@ -1184,16 +1184,16 @@ define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vof ; ; GFX1250-LABEL: name: struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_glc ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX1250-NEXT: [[BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = BUFFER_LOAD_DWORD_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 1, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; GFX1250-NEXT: $vgpr0 = COPY [[BUFFER_LOAD_DWORD_VBUFFER_BOTHEN]] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll index 58a58a99c535cd..1cb1a7bbffd753 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f16.ll @@ -40,17 +40,17 @@ define amdgpu_ps void @struct_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr ; ; GFX12-LABEL: name: struct_buffer_store_format_f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (f16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 @@ -99,17 +99,17 @@ define amdgpu_ps void @struct_buffer_store_format_v2f16__vgpr_val__sgpr_rsrc__vg ; ; GFX12-LABEL: name: struct_buffer_store_format_v2f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x f16>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 @@ -161,19 +161,19 @@ define amdgpu_ps void @struct_buffer_store_format_v3f16__vgpr_val__sgpr_rsrc__vg ; ; GFX12-LABEL: name: struct_buffer_store_format_v3f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_XYZ_VBUFFER_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x f16>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 @@ -227,19 +227,19 @@ define amdgpu_ps void @struct_buffer_store_format_v4f16__vgpr_val__sgpr_rsrc__vg ; ; GFX12-LABEL: name: struct_buffer_store_format_v4f16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x f16>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 @@ -361,16 +361,16 @@ define amdgpu_ps void @struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr ; GFX12-LABEL: name: struct_buffer_store_format_f16__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -453,17 +453,17 @@ define amdgpu_ps void @struct_buffer_store_format_i16__vgpr_val__sgpr_rsrc__vgpr ; ; GFX12-LABEL: name: struct_buffer_store_format_i16__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX12-NEXT: BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (i16), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll index aeb1f30e3a345f..87901f41676d78 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.format.f32.ll @@ -22,17 +22,17 @@ define amdgpu_ps void @struct_buffer_store_format_f32__vgpr_val__sgpr_rsrc__vgpr ; ; GFX12-LABEL: name: struct_buffer_store_format_f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX12-NEXT: BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 @@ -62,19 +62,19 @@ define amdgpu_ps void @struct_buffer_store_format_v2f32__vgpr_val__sgpr_rsrc__vg ; ; GFX12-LABEL: name: struct_buffer_store_format_v2f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX12-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX12-NEXT: BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x f32>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 @@ -105,20 +105,20 @@ define amdgpu_ps void @struct_buffer_store_format_v3f32__vgpr_val__sgpr_rsrc__vg ; ; GFX12-LABEL: name: struct_buffer_store_format_v3f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX12-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1 ; GFX12-NEXT: BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY9]], 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x f32>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 @@ -150,21 +150,21 @@ define amdgpu_ps void @struct_buffer_store_format_v4f32__vgpr_val__sgpr_rsrc__vg ; ; GFX12-LABEL: name: struct_buffer_store_format_v4f32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX12-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 ; GFX12-NEXT: BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY10]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x f32>), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 @@ -231,16 +231,16 @@ define amdgpu_ps void @struct_buffer_store_format_f32__sgpr_val__vgpr_rsrc__sgpr ; GFX12-LABEL: name: struct_buffer_store_format_f32__sgpr_val__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY]] ; GFX12-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -306,17 +306,17 @@ define amdgpu_ps void @struct_buffer_store_format_i32__vgpr_val__sgpr_rsrc__vgpr ; ; GFX12-LABEL: name: struct_buffer_store_format_i32__vgpr_val__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX12-NEXT: BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (i32), align 1, addrspace 8) ; GFX12-NEXT: S_ENDPGM 0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll index 048a2acebbe6ed..8ef9dbea9dd32b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.store.ll @@ -24,34 +24,34 @@ define amdgpu_ps void @struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex_ ; ; GFX1200-LABEL: name: struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -81,38 +81,38 @@ define amdgpu_ps void @struct_buffer_store_v2f32_sgpr_rsrc__vgpr_val__vgpr_vinde ; ; GFX1200-LABEL: name: struct_buffer_store_v2f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x f32>), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_store_v2f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x f32>), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -143,40 +143,40 @@ define amdgpu_ps void @struct_buffer_store_v3f32_sgpr_rsrc__vgpr_val__vgpr_vinde ; ; GFX1200-LABEL: name: struct_buffer_store_v3f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY9]], 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x f32>), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_store_v3f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY3]], %subreg.sub0, [[COPY4]], %subreg.sub1, [[COPY5]], %subreg.sub2, [[COPY6]], %subreg.sub3 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 - ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY9]], 0, 0, 0, implicit $exec :: (dereferenceable store (<3 x f32>), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -208,42 +208,42 @@ define amdgpu_ps void @struct_buffer_store_v4f32_sgpr_rsrc__vgpr_val__vgpr_vinde ; ; GFX1200-LABEL: name: struct_buffer_store_v4f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY10]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x f32>), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_store_v4f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr5 - ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY8]], %subreg.sub0, [[COPY9]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY10]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x f32>), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -314,20 +314,20 @@ define amdgpu_ps void @struct_buffer_store_v4f32_vgpr_rsrc__sgpr_val__sgpr_vinde ; GFX1200-LABEL: name: struct_buffer_store_v4f32_vgpr_rsrc__sgpr_val__sgpr_vindex__sgpr_voffset__vgpr_soffset ; GFX1200: bb.1 (%ir-block.0): ; GFX1200-NEXT: successors: %bb.2(0x80000000) - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1200-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX1200-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1200-NEXT: [[COPY11:%[0-9]+]]:vreg_128 = COPY [[REG_SEQUENCE]] ; GFX1200-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] @@ -373,20 +373,20 @@ define amdgpu_ps void @struct_buffer_store_v4f32_vgpr_rsrc__sgpr_val__sgpr_vinde ; GFX1250-LABEL: name: struct_buffer_store_v4f32_vgpr_rsrc__sgpr_val__sgpr_vindex__sgpr_voffset__vgpr_soffset ; GFX1250: bb.1 (%ir-block.0): ; GFX1250-NEXT: successors: %bb.2(0x80000000) - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $sgpr7, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1, [[COPY6]], %subreg.sub2, [[COPY7]], %subreg.sub3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 - ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr7 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX1250-NEXT: [[COPY9:%[0-9]+]]:sreg_32 = COPY $sgpr5 ; GFX1250-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX1250-NEXT: [[COPY11:%[0-9]+]]:vreg_128_align2 = COPY [[REG_SEQUENCE]] ; GFX1250-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY [[COPY8]] @@ -452,34 +452,34 @@ define amdgpu_ps void @struct_buffer_store_i8_sgpr_rsrc__vgpr_val__vgpr_vindex__ ; ; GFX1200-LABEL: name: struct_buffer_store_i8_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_STORE_BYTE_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_store_i8_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_STORE_BYTE_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (i8), addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -508,34 +508,34 @@ define amdgpu_ps void @struct_buffer_store_i16_sgpr_rsrc__vgpr_val__vgpr_vindex_ ; ; GFX1200-LABEL: name: struct_buffer_store_i16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_STORE_SHORT_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (i16), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_store_i16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_STORE_SHORT_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (i16), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -564,34 +564,34 @@ define amdgpu_ps void @struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex_ ; ; GFX1200-LABEL: name: struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset_glc ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_store_f32_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset_glc ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 1, 0, implicit $exec :: (dereferenceable store (f32), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -619,34 +619,34 @@ define amdgpu_ps void @struct_buffer_store_v2f16_sgpr_rsrc__vgpr_val__vgpr_vinde ; ; GFX1200-LABEL: name: struct_buffer_store_v2f16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x f16>), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_store_v2f16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY2]], %subreg.sub1, [[COPY3]], %subreg.sub2, [[COPY4]], %subreg.sub3 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 - ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY5]], %subreg.sub0, [[COPY6]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact [[COPY]], [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY7]], 0, 0, 0, implicit $exec :: (dereferenceable store (<2 x f16>), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 @@ -682,38 +682,38 @@ define amdgpu_ps void @struct_buffer_store_v4f16_sgpr_rsrc__vgpr_val__vgpr_vinde ; ; GFX1200-LABEL: name: struct_buffer_store_v4f16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1200-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1200-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1200-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1200-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1200-NEXT: BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x f16>), align 1, addrspace 8) ; GFX1200-NEXT: S_ENDPGM 0 ; ; GFX1250-LABEL: name: struct_buffer_store_v4f16_sgpr_rsrc__vgpr_val__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX1250-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX1250-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY4]], %subreg.sub2, [[COPY5]], %subreg.sub3 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX1250-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr3 - ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY8:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX1250-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY7]], %subreg.sub1 ; GFX1250-NEXT: BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact [[REG_SEQUENCE]], [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[COPY8]], 0, 0, 0, implicit $exec :: (dereferenceable store (<4 x f16>), align 1, addrspace 8) ; GFX1250-NEXT: S_ENDPGM 0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll index 2b64786289d789..4d5ed154766b9a 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu8.10-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX11 %s ; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=UNPACKED %s define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { @@ -22,6 +22,23 @@ define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_vof ; PACKED-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]] ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f16) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; UNPACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; UNPACKED: bb.1 (%ir-block.0): ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 @@ -60,6 +77,23 @@ define amdgpu_ps <2 x half> @struct_tbuffer_load_v2f16__sgpr_rsrc__vgpr_vindex__ ; PACKED-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN]] ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: struct_tbuffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<2 x f16>) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; UNPACKED-LABEL: name: struct_tbuffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; UNPACKED: bb.1 (%ir-block.0): ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 @@ -118,6 +152,26 @@ define amdgpu_ps <4 x half> @struct_tbuffer_load_v4f16__sgpr_rsrc__vgpr_vindex__ ; PACKED-NEXT: $vgpr1 = COPY [[COPY8]] ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 ; + ; GFX11-LABEL: name: struct_tbuffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub0 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub1 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY7]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY8]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; ; UNPACKED-LABEL: name: struct_tbuffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; UNPACKED: bb.1 (%ir-block.0): ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 @@ -178,6 +232,24 @@ define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_vof ; PACKED-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]] ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f16) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; UNPACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0 ; UNPACKED: bb.1 (%ir-block.0): ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 @@ -257,6 +329,63 @@ define amdgpu_ps <4 x half> @struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__ ; PACKED-NEXT: $vgpr1 = COPY [[COPY14]] ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 ; + ; GFX11-LABEL: name: struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX11-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY12]], [[COPY10]], implicit $exec + ; GFX11-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec + ; GFX11-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[S_AND_B64_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 [[S_AND_B64_1]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub0 + ; GFX11-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub1 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY13]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY14]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; ; UNPACKED-LABEL: name: struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset ; UNPACKED: bb.1 (%ir-block.0): ; UNPACKED-NEXT: successors: %bb.2(0x80000000) @@ -353,6 +482,23 @@ define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_vof ; PACKED-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]] ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 78, 0, 0, implicit $exec :: (dereferenceable load (f16) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; UNPACKED-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095 ; UNPACKED: bb.1 (%ir-block.0): ; UNPACKED-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll index 12c7b363747096..f2fa4da5ded740 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.tbuffer.load.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck --check-prefixes=CHECK %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck --check-prefixes=CHECK %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck --check-prefixes=CHECK %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck --check-prefix=GFX11 %s define amdgpu_ps float @struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { ; CHECK-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset @@ -20,6 +20,23 @@ define amdgpu_ps float @struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vo ; CHECK-NEXT: [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX11-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 %val = call float @llvm.amdgcn.struct.ptr.tbuffer.load.f32(ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0) ret float %val } @@ -44,6 +61,26 @@ define amdgpu_ps <2 x float> @struct_tbuffer_load_v2f32__sgpr_rsrc__vgpr_vindex_ ; CHECK-NEXT: $vgpr0 = COPY [[COPY7]] ; CHECK-NEXT: $vgpr1 = COPY [[COPY8]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; + ; GFX11-LABEL: name: struct_tbuffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_XY_BOTHEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_XY_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_BOTHEN]].sub0 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_BOTHEN]].sub1 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY7]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY8]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 %val = call <2 x float> @llvm.amdgcn.struct.ptr.tbuffer.load.v2f32(ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0) ret <2 x float> %val } @@ -70,6 +107,28 @@ define amdgpu_ps <3 x float> @struct_tbuffer_load_v3f32__sgpr_rsrc__vgpr_vindex_ ; CHECK-NEXT: $vgpr1 = COPY [[COPY8]] ; CHECK-NEXT: $vgpr2 = COPY [[COPY9]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + ; + ; GFX11-LABEL: name: struct_tbuffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN:%[0-9]+]]:vreg_96 = TBUFFER_LOAD_FORMAT_XYZ_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub0 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub1 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub2 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY7]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY8]] + ; GFX11-NEXT: $vgpr2 = COPY [[COPY9]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 %val = call <3 x float> @llvm.amdgcn.struct.ptr.tbuffer.load.v3f32(ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0) ret <3 x float> %val } @@ -98,6 +157,30 @@ define amdgpu_ps <4 x float> @struct_tbuffer_load_v4f32__sgpr_rsrc__vgpr_vindex_ ; CHECK-NEXT: $vgpr2 = COPY [[COPY9]] ; CHECK-NEXT: $vgpr3 = COPY [[COPY10]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; + ; GFX11-LABEL: name: struct_tbuffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_XYZW_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub0 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub1 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub2 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub3 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY7]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY8]] + ; GFX11-NEXT: $vgpr2 = COPY [[COPY9]] + ; GFX11-NEXT: $vgpr3 = COPY [[COPY10]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 %val = call <4 x float> @llvm.amdgcn.struct.ptr.tbuffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0) ret <4 x float> %val } @@ -120,6 +203,24 @@ define amdgpu_ps float @struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vo ; CHECK-NEXT: [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX11-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 %val = call float @llvm.amdgcn.struct.ptr.tbuffer.load.f32(ptr addrspace(8) %rsrc, i32 0, i32 %voffset, i32 %soffset, i32 78, i32 0) ret float %val } @@ -185,6 +286,67 @@ define amdgpu_ps <4 x float> @struct_tbuffer_load_v4f32__vgpr_rsrc__sgpr_vindex_ ; CHECK-NEXT: $vgpr2 = COPY [[COPY15]] ; CHECK-NEXT: $vgpr3 = COPY [[COPY16]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; + ; GFX11-LABEL: name: struct_tbuffer_load_v4f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX11-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY12]], [[COPY10]], implicit $exec + ; GFX11-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec + ; GFX11-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[S_AND_B64_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 [[S_AND_B64_1]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_XYZW_BOTHEN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub0 + ; GFX11-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub1 + ; GFX11-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub2 + ; GFX11-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub3 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY13]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY14]] + ; GFX11-NEXT: $vgpr2 = COPY [[COPY15]] + ; GFX11-NEXT: $vgpr3 = COPY [[COPY16]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 %val = call <4 x float> @llvm.amdgcn.struct.ptr.tbuffer.load.v4f32(ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0) ret <4 x float> %val } @@ -206,6 +368,23 @@ define amdgpu_ps float @struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vo ; CHECK-NEXT: [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 78, 0, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) ; CHECK-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; + ; GFX11-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 78, 0, 0, implicit $exec :: (dereferenceable load (f32) from %ir.rsrc, align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 %voffset = add i32 %voffset.base, 4095 %val = call float @llvm.amdgcn.struct.ptr.tbuffer.load.f32(ptr addrspace(8) %rsrc, i32 %vindex, i32 %voffset, i32 %soffset, i32 78, i32 0) ret float %val diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll index f3d4fa3d62d273..afba6ceb338411 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.f16.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu8.10-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=PACKED %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX11 %s ; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12 %s ; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=UNPACKED %s @@ -23,18 +23,35 @@ define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_vof ; PACKED-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]] ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN]] @@ -78,18 +95,35 @@ define amdgpu_ps <2 x half> @struct_tbuffer_load_v2f16__sgpr_rsrc__vgpr_vindex__ ; PACKED-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN]] ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: struct_tbuffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<2 x f16>), align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: struct_tbuffer_load_v2f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<2 x f16>), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN]] @@ -153,18 +187,38 @@ define amdgpu_ps <4 x half> @struct_tbuffer_load_v4f16__sgpr_rsrc__vgpr_vindex__ ; PACKED-NEXT: $vgpr1 = COPY [[COPY8]] ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 ; + ; GFX11-LABEL: name: struct_tbuffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>), align 1, addrspace 8) + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub0 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub1 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY7]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY8]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; ; GFX12-LABEL: name: struct_tbuffer_load_v4f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>), align 1, addrspace 8) ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN]].sub0 @@ -233,17 +287,35 @@ define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_vof ; PACKED-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]] ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1 @@ -330,18 +402,75 @@ define amdgpu_ps <4 x half> @struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__ ; PACKED-NEXT: $vgpr1 = COPY [[COPY14]] ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 ; + ; GFX11-LABEL: name: struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX11-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY12]], [[COPY10]], implicit $exec + ; GFX11-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec + ; GFX11-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[S_AND_B64_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 [[S_AND_B64_1]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f16>), align 1, addrspace 8) + ; GFX11-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub0 + ; GFX11-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN]].sub1 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY13]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY14]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; ; GFX12-LABEL: name: struct_tbuffer_load_v4f16__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset ; GFX12: bb.1 (%ir-block.0): ; GFX12-NEXT: successors: %bb.2(0x80000000) - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; GFX12-NEXT: {{ $}} ; GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -483,18 +612,35 @@ define amdgpu_ps half @struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_vof ; PACKED-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]] ; PACKED-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 78, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_BOTHEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; GFX12-LABEL: name: struct_tbuffer_load_f16__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095 ; GFX12: bb.1 (%ir-block.0): - ; GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; GFX12-NEXT: {{ $}} - ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 78, 0, 0, implicit $exec :: (dereferenceable load (f16), align 1, addrspace 8) ; GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN]] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll index 4e7e2eed1c248e..40b7ebde286e3f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.tbuffer.load.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py ; RUN: llc -global-isel -mtriple=amdgpu6.00-mesa-mesa3d -stop-after=instruction-select -o - %s | FileCheck --check-prefixes=CHECK %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck --check-prefixes=CHECK %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck --check-prefixes=CHECK %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck --check-prefix=GFX11 %s ; RUN: llc -global-isel -mtriple=amdgpu12.00-mesa-mesa3d -mattr=+wavefrontsize64 -stop-after=instruction-select -o - %s | FileCheck --check-prefixes=CHECK-GFX12 %s define amdgpu_ps float @struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) { @@ -22,18 +22,35 @@ define amdgpu_ps float @struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vo ; CHECK-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; CHECK-GFX12-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; CHECK-GFX12: bb.1 (%ir-block.0): - ; CHECK-GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; CHECK-GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; CHECK-GFX12-NEXT: {{ $}} - ; CHECK-GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; CHECK-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; CHECK-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; CHECK-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; CHECK-GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; CHECK-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; CHECK-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; CHECK-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; CHECK-GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; CHECK-GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK-GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; CHECK-GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; CHECK-GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; CHECK-GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; CHECK-GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; CHECK-GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN]] @@ -63,18 +80,38 @@ define amdgpu_ps <2 x float> @struct_tbuffer_load_v2f32__sgpr_rsrc__vgpr_vindex_ ; CHECK-NEXT: $vgpr1 = COPY [[COPY8]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 ; + ; GFX11-LABEL: name: struct_tbuffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_XY_BOTHEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_XY_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>), align 1, addrspace 8) + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_BOTHEN]].sub0 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_BOTHEN]].sub1 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY7]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY8]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1 + ; ; CHECK-GFX12-LABEL: name: struct_tbuffer_load_v2f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; CHECK-GFX12: bb.1 (%ir-block.0): - ; CHECK-GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; CHECK-GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; CHECK-GFX12-NEXT: {{ $}} - ; CHECK-GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; CHECK-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; CHECK-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; CHECK-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; CHECK-GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; CHECK-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; CHECK-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; CHECK-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; CHECK-GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; CHECK-GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK-GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; CHECK-GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; CHECK-GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; CHECK-GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; CHECK-GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN:%[0-9]+]]:vreg_64 = TBUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<2 x f32>), align 1, addrspace 8) ; CHECK-GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN]].sub0 @@ -109,18 +146,40 @@ define amdgpu_ps <3 x float> @struct_tbuffer_load_v3f32__sgpr_rsrc__vgpr_vindex_ ; CHECK-NEXT: $vgpr2 = COPY [[COPY9]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 ; + ; GFX11-LABEL: name: struct_tbuffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN:%[0-9]+]]:vreg_96 = TBUFFER_LOAD_FORMAT_XYZ_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>), align 1, addrspace 8) + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub0 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub1 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_BOTHEN]].sub2 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY7]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY8]] + ; GFX11-NEXT: $vgpr2 = COPY [[COPY9]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2 + ; ; CHECK-GFX12-LABEL: name: struct_tbuffer_load_v3f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; CHECK-GFX12: bb.1 (%ir-block.0): - ; CHECK-GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; CHECK-GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; CHECK-GFX12-NEXT: {{ $}} - ; CHECK-GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; CHECK-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; CHECK-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; CHECK-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; CHECK-GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; CHECK-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; CHECK-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; CHECK-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; CHECK-GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; CHECK-GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK-GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; CHECK-GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; CHECK-GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; CHECK-GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; CHECK-GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN:%[0-9]+]]:vreg_96 = TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<3 x f32>), align 1, addrspace 8) ; CHECK-GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN]].sub0 @@ -159,18 +218,42 @@ define amdgpu_ps <4 x float> @struct_tbuffer_load_v4f32__sgpr_rsrc__vgpr_vindex_ ; CHECK-NEXT: $vgpr3 = COPY [[COPY10]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: struct_tbuffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_XYZW_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8) + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub0 + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub1 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub2 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub3 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY7]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY8]] + ; GFX11-NEXT: $vgpr2 = COPY [[COPY9]] + ; GFX11-NEXT: $vgpr3 = COPY [[COPY10]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; CHECK-GFX12-LABEL: name: struct_tbuffer_load_v4f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset ; CHECK-GFX12: bb.1 (%ir-block.0): - ; CHECK-GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; CHECK-GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; CHECK-GFX12-NEXT: {{ $}} - ; CHECK-GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; CHECK-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; CHECK-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; CHECK-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; CHECK-GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; CHECK-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; CHECK-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; CHECK-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; CHECK-GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; CHECK-GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK-GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; CHECK-GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; CHECK-GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; CHECK-GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; CHECK-GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8) ; CHECK-GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN]].sub0 @@ -205,17 +288,35 @@ define amdgpu_ps float @struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vo ; CHECK-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY5]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; CHECK-GFX12-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_vindex0 ; CHECK-GFX12: bb.1 (%ir-block.0): - ; CHECK-GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; CHECK-GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; CHECK-GFX12-NEXT: {{ $}} - ; CHECK-GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; CHECK-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; CHECK-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; CHECK-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; CHECK-GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; CHECK-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; CHECK-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; CHECK-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; CHECK-GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; CHECK-GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; CHECK-GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; CHECK-GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; CHECK-GFX12-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0 ; CHECK-GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] ; CHECK-GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY6]], %subreg.sub0, [[COPY4]], %subreg.sub1 @@ -288,18 +389,79 @@ define amdgpu_ps <4 x float> @struct_tbuffer_load_v4f32__vgpr_rsrc__sgpr_vindex_ ; CHECK-NEXT: $vgpr3 = COPY [[COPY16]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 ; + ; GFX11-LABEL: name: struct_tbuffer_load_v4f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: successors: %bb.2(0x80000000) + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; GFX11-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] + ; GFX11-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] + ; GFX11-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.2: + ; GFX11-NEXT: successors: %bb.3(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_2:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY2]], implicit $exec + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_3:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY3]], implicit $exec + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1, [[V_READFIRSTLANE_B32_2]], %subreg.sub2, [[V_READFIRSTLANE_B32_3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY9:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub0_sub1 + ; GFX11-NEXT: [[COPY10:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]].sub2_sub3 + ; GFX11-NEXT: [[COPY11:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub0_sub1 + ; GFX11-NEXT: [[COPY12:%[0-9]+]]:sreg_64 = COPY [[REG_SEQUENCE1]].sub2_sub3 + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY11]], [[COPY9]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U64_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U64_e64 [[COPY12]], [[COPY10]], implicit $exec + ; GFX11-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U64_e64_]], [[V_CMP_EQ_U64_e64_1]], implicit-def dead $scc + ; GFX11-NEXT: [[V_READFIRSTLANE_B32_4:%[0-9]+]]:sreg_32_xm0 = V_READFIRSTLANE_B32 [[COPY6]], implicit $exec + ; GFX11-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[V_READFIRSTLANE_B32_4]], [[COPY6]], implicit $exec + ; GFX11-NEXT: [[S_AND_B64_1:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[S_AND_B64_]], [[V_CMP_EQ_U32_e64_]], implicit-def dead $scc + ; GFX11-NEXT: [[S_AND_SAVEEXEC_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_SAVEEXEC_B64 [[S_AND_B64_1]], implicit-def $exec, implicit-def dead $scc, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.3: + ; GFX11-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY7]], %subreg.sub0, [[COPY8]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN:%[0-9]+]]:vreg_128 = TBUFFER_LOAD_FORMAT_XYZW_BOTHEN [[REG_SEQUENCE2]], [[REG_SEQUENCE1]], [[V_READFIRSTLANE_B32_4]], 0, 78, 0, 0, implicit $exec :: (dereferenceable load (<4 x f32>), align 1, addrspace 8) + ; GFX11-NEXT: $exec = S_XOR_B64_term $exec, [[S_AND_SAVEEXEC_B64_]], implicit-def dead $scc + ; GFX11-NEXT: SI_WATERFALL_LOOP %bb.2, implicit $exec + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.4: + ; GFX11-NEXT: successors: %bb.5(0x80000000) + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: $exec = S_MOV_B64_term [[S_MOV_B64_]] + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: bb.5: + ; GFX11-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub0 + ; GFX11-NEXT: [[COPY14:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub1 + ; GFX11-NEXT: [[COPY15:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub2 + ; GFX11-NEXT: [[COPY16:%[0-9]+]]:vgpr_32 = COPY [[TBUFFER_LOAD_FORMAT_XYZW_BOTHEN]].sub3 + ; GFX11-NEXT: $vgpr0 = COPY [[COPY13]] + ; GFX11-NEXT: $vgpr1 = COPY [[COPY14]] + ; GFX11-NEXT: $vgpr2 = COPY [[COPY15]] + ; GFX11-NEXT: $vgpr3 = COPY [[COPY16]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0, implicit $vgpr1, implicit $vgpr2, implicit $vgpr3 + ; ; CHECK-GFX12-LABEL: name: struct_tbuffer_load_v4f32__vgpr_rsrc__sgpr_vindex__sgpr_voffset__vgpr_soffset ; CHECK-GFX12: bb.1 (%ir-block.0): ; CHECK-GFX12-NEXT: successors: %bb.2(0x80000000) - ; CHECK-GFX12-NEXT: liveins: $sgpr2, $sgpr3, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 + ; CHECK-GFX12-NEXT: liveins: $sgpr0, $sgpr1, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4 ; CHECK-GFX12-NEXT: {{ $}} ; CHECK-GFX12-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK-GFX12-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 ; CHECK-GFX12-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 ; CHECK-GFX12-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 ; CHECK-GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 - ; CHECK-GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; CHECK-GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; CHECK-GFX12-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; CHECK-GFX12-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY $sgpr1 ; CHECK-GFX12-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr4 ; CHECK-GFX12-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY4]] ; CHECK-GFX12-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY [[COPY5]] @@ -370,18 +532,35 @@ define amdgpu_ps float @struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_vo ; CHECK-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]] ; CHECK-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 ; + ; GFX11-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095 + ; GFX11: bb.1 (%ir-block.0): + ; GFX11-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 + ; GFX11-NEXT: {{ $}} + ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 + ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 + ; GFX11-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; GFX11-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; GFX11-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 + ; GFX11-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 + ; GFX11-NEXT: [[TBUFFER_LOAD_FORMAT_X_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 78, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) + ; GFX11-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_BOTHEN]] + ; GFX11-NEXT: SI_RETURN_TO_EPILOG implicit $vgpr0 + ; ; CHECK-GFX12-LABEL: name: struct_tbuffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset_voffset_add4095 ; CHECK-GFX12: bb.1 (%ir-block.0): - ; CHECK-GFX12-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0, $vgpr1 + ; CHECK-GFX12-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0, $vgpr1 ; CHECK-GFX12-NEXT: {{ $}} - ; CHECK-GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr2 - ; CHECK-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr3 - ; CHECK-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr4 - ; CHECK-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr5 + ; CHECK-GFX12-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 + ; CHECK-GFX12-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1 + ; CHECK-GFX12-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr2 + ; CHECK-GFX12-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY $sgpr3 ; CHECK-GFX12-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY3]], %subreg.sub3 ; CHECK-GFX12-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; CHECK-GFX12-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr1 - ; CHECK-GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr6 + ; CHECK-GFX12-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY $sgpr4 ; CHECK-GFX12-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY5]], %subreg.sub1 ; CHECK-GFX12-NEXT: [[TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN:%[0-9]+]]:vgpr_32 = TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN [[REG_SEQUENCE1]], [[REG_SEQUENCE]], [[COPY6]], 4095, 78, 0, 0, implicit $exec :: (dereferenceable load (f32), align 1, addrspace 8) ; CHECK-GFX12-NEXT: $vgpr0 = COPY [[TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN]] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll index d15aa27ad0f9d0..5b49e8fa991c84 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.writelane.ll @@ -2,7 +2,7 @@ ; RUN: llc -global-isel -mtriple=amdgpu7.00-mesa-mesa3d < %s | FileCheck -check-prefix=GFX7 %s ; RUN: llc -global-isel -mtriple=amdgpu8.03-mesa-mesa3d < %s | FileCheck -check-prefix=GFX8 %s ; RUN: llc -global-isel -mtriple=amdgpu10.10-mesa-mesa3d < %s | FileCheck -check-prefix=GFX10 %s -; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX10 %s +; RUN: llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefix=GFX11 %s define amdgpu_ps float @test_writelane_s_s_s(i32 inreg %data, i32 inreg %lane, i32 inreg %vdst.in) #0 { ; GFX7-LABEL: test_writelane_s_s_s: @@ -24,6 +24,12 @@ define amdgpu_ps float @test_writelane_s_s_s(i32 inreg %data, i32 inreg %lane, i ; GFX10-NEXT: v_mov_b32_e32 v0, s4 ; GFX10-NEXT: v_writelane_b32 v0, s2, s3 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: test_writelane_s_s_s: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: v_writelane_b32 v0, s0, s1 +; GFX11-NEXT: ; return to shader part epilog %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 %lane, i32 %vdst.in) %writelane.cast = bitcast i32 %writelane to float ret float %writelane.cast @@ -49,6 +55,12 @@ define amdgpu_ps float @test_writelane_s_s_imm(i32 inreg %data, i32 inreg %lane) ; GFX10-NEXT: v_mov_b32_e32 v0, 42 ; GFX10-NEXT: v_writelane_b32 v0, s2, s3 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: test_writelane_s_s_imm: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_mov_b32_e32 v0, 42 +; GFX11-NEXT: v_writelane_b32 v0, s0, s1 +; GFX11-NEXT: ; return to shader part epilog %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 %lane, i32 42) %writelane.cast = bitcast i32 %writelane to float ret float %writelane.cast @@ -75,6 +87,12 @@ define amdgpu_ps float @test_writelane_k_s_v(i32 inreg %lane, i32 %vdst.in) #0 { ; GFX10-NEXT: s_movk_i32 s0, 0x3e7 ; GFX10-NEXT: v_writelane_b32 v0, s0, s2 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: test_writelane_k_s_v: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_movk_i32 s1, 0x3e7 +; GFX11-NEXT: v_writelane_b32 v0, s1, s0 +; GFX11-NEXT: ; return to shader part epilog %writelane = call i32 @llvm.amdgcn.writelane(i32 999, i32 %lane, i32 %vdst.in) %writelane.cast = bitcast i32 %writelane to float ret float %writelane.cast @@ -96,6 +114,11 @@ define amdgpu_ps float @test_writelane_imm_s_v(i32 inreg %lane, i32 %vdst.in) #0 ; GFX10: ; %bb.0: ; GFX10-NEXT: v_writelane_b32 v0, 42, s2 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: test_writelane_imm_s_v: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_writelane_b32 v0, 42, s0 +; GFX11-NEXT: ; return to shader part epilog %writelane = call i32 @llvm.amdgcn.writelane(i32 42, i32 %lane, i32 %vdst.in) %writelane.cast = bitcast i32 %writelane to float ret float %writelane.cast @@ -119,6 +142,11 @@ define amdgpu_ps float @test_writelane_imminv2pi_s_v(i32 inreg %lane, i32 %vdst. ; GFX10: ; %bb.0: ; GFX10-NEXT: v_writelane_b32 v0, 0.15915494, s2 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: test_writelane_imminv2pi_s_v: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_writelane_b32 v0, 0.15915494, s0 +; GFX11-NEXT: ; return to shader part epilog %writelane = call i32 @llvm.amdgcn.writelane(i32 bitcast (float 0x3FC45F3060000000 to i32), i32 %lane, i32 %vdst.in) %writelane.cast = bitcast i32 %writelane to float ret float %writelane.cast @@ -141,6 +169,11 @@ define amdgpu_ps float @test_writelane_s_imm_v(i32 inreg %data, i32 %vdst.in) #0 ; GFX10: ; %bb.0: ; GFX10-NEXT: v_writelane_b32 v0, s2, 23 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: test_writelane_s_imm_v: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_writelane_b32 v0, s0, 23 +; GFX11-NEXT: ; return to shader part epilog %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 23, i32 %vdst.in) %writelane.cast = bitcast i32 %writelane to float ret float %writelane.cast @@ -163,6 +196,12 @@ define amdgpu_ps float @test_writelane_s_k0_v(i32 inreg %data, i32 %vdst.in) #0 ; GFX10-NEXT: s_movk_i32 s0, 0x43 ; GFX10-NEXT: v_writelane_b32 v0, s2, s0 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: test_writelane_s_k0_v: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_movk_i32 s1, 0x43 +; GFX11-NEXT: v_writelane_b32 v0, s0, s1 +; GFX11-NEXT: ; return to shader part epilog %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 67, i32 %vdst.in) %writelane.cast = bitcast i32 %writelane to float ret float %writelane.cast @@ -184,6 +223,11 @@ define amdgpu_ps float @test_writelane_s_k1_v(i32 inreg %data, i32 %vdst.in) #0 ; GFX10: ; %bb.0: ; GFX10-NEXT: v_writelane_b32 v0, s2, 32 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: test_writelane_s_k1_v: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_writelane_b32 v0, s0, 32 +; GFX11-NEXT: ; return to shader part epilog %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 32, i32 %vdst.in) %writelane.cast = bitcast i32 %writelane to float ret float %writelane.cast @@ -215,6 +259,14 @@ define amdgpu_ps float @test_writelane_v_v_v(i32 %data, i32 %lane, i32 %vdst.in) ; GFX10-NEXT: v_writelane_b32 v2, s0, s1 ; GFX10-NEXT: v_mov_b32_e32 v0, v2 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: test_writelane_v_v_v: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_readfirstlane_b32 s0, v0 +; GFX11-NEXT: v_readfirstlane_b32 s1, v1 +; GFX11-NEXT: v_writelane_b32 v2, s0, s1 +; GFX11-NEXT: v_mov_b32_e32 v0, v2 +; GFX11-NEXT: ; return to shader part epilog %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 %lane, i32 %vdst.in) %writelane.cast = bitcast i32 %writelane to float ret float %writelane.cast @@ -243,6 +295,13 @@ define amdgpu_ps float @test_writelane_v_s_v(i32 %data, i32 inreg %lane, i32 %vd ; GFX10-NEXT: v_writelane_b32 v1, s0, s2 ; GFX10-NEXT: v_mov_b32_e32 v0, v1 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: test_writelane_v_s_v: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_readfirstlane_b32 s1, v0 +; GFX11-NEXT: v_writelane_b32 v1, s1, s0 +; GFX11-NEXT: v_mov_b32_e32 v0, v1 +; GFX11-NEXT: ; return to shader part epilog %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 inreg %lane, i32 %vdst.in) %writelane.cast = bitcast i32 %writelane to float ret float %writelane.cast @@ -278,6 +337,14 @@ define amdgpu_ps float @test_writelane_m0_s_v(i32 inreg %lane, i32 %vdst.in) #0 ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: v_writelane_b32 v0, m0, s2 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: test_writelane_m0_s_v: +; GFX11: ; %bb.0: +; GFX11-NEXT: ;;#ASMSTART +; GFX11-NEXT: s_mov_b32 m0, -1 +; GFX11-NEXT: ;;#ASMEND +; GFX11-NEXT: v_writelane_b32 v0, m0, s0 +; GFX11-NEXT: ; return to shader part epilog %m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"() %writelane = call i32 @llvm.amdgcn.writelane(i32 %m0, i32 %lane, i32 %vdst.in) %writelane.cast = bitcast i32 %writelane to float @@ -308,6 +375,14 @@ define amdgpu_ps float @test_writelane_s_m0_v(i32 inreg %data, i32 %vdst.in) #0 ; GFX10-NEXT: ;;#ASMEND ; GFX10-NEXT: v_writelane_b32 v0, s2, m0 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: test_writelane_s_m0_v: +; GFX11: ; %bb.0: +; GFX11-NEXT: ;;#ASMSTART +; GFX11-NEXT: s_mov_b32 m0, -1 +; GFX11-NEXT: ;;#ASMEND +; GFX11-NEXT: v_writelane_b32 v0, s0, m0 +; GFX11-NEXT: ; return to shader part epilog %m0 = call i32 asm "s_mov_b32 m0, -1", "={m0}"() %writelane = call i32 @llvm.amdgcn.writelane(i32 %data, i32 %m0, i32 %vdst.in) %writelane.cast = bitcast i32 %writelane to float diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll index 3054c485eee11d..4c6043fc8db3bc 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mubuf-global.ll @@ -30,7 +30,7 @@ define amdgpu_ps void @mubuf_store_sgpr_ptr(ptr addrspace(1) inreg %ptr) { ; GFX12-LABEL: mubuf_store_sgpr_ptr: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-NEXT: global_store_b32 v0, v0, s[2:3] +; GFX12-NEXT: global_store_b32 v0, v0, s[0:1] ; GFX12-NEXT: s_endpgm store i32 0, ptr addrspace(1) %ptr ret void @@ -62,7 +62,7 @@ define amdgpu_ps void @mubuf_store_sgpr_ptr_offset4095(ptr addrspace(1) inreg %p ; GFX12-LABEL: mubuf_store_sgpr_ptr_offset4095: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-NEXT: global_store_b32 v0, v0, s[2:3] offset:16380 +; GFX12-NEXT: global_store_b32 v0, v0, s[0:1] offset:16380 ; GFX12-NEXT: s_endpgm %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4095 store i32 0, ptr addrspace(1) %gep @@ -96,8 +96,8 @@ define amdgpu_ps void @mubuf_store_sgpr_ptr_offset4294967296(ptr addrspace(1) in ; ; GFX12-LABEL: mubuf_store_sgpr_ptr_offset4294967296: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_add_co_u32 s0, s2, 0 -; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4 +; GFX12-NEXT: s_add_co_u32 s0, s0, 0 +; GFX12-NEXT: s_add_co_ci_u32 s1, s1, 4 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 @@ -135,8 +135,8 @@ define amdgpu_ps void @mubuf_store_sgpr_ptr_offset4294967297(ptr addrspace(1) in ; ; GFX12-LABEL: mubuf_store_sgpr_ptr_offset4294967297: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_add_co_u32 s0, s2, 4 -; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4 +; GFX12-NEXT: s_add_co_u32 s0, s0, 4 +; GFX12-NEXT: s_add_co_ci_u32 s1, s1, 4 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s1 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 @@ -173,7 +173,7 @@ define amdgpu_ps void @mubuf_store_sgpr_ptr_offset4096(ptr addrspace(1) inreg %p ; GFX12-LABEL: mubuf_store_sgpr_ptr_offset4096: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-NEXT: global_store_b32 v0, v0, s[2:3] offset:16384 +; GFX12-NEXT: global_store_b32 v0, v0, s[0:1] offset:16384 ; GFX12-NEXT: s_endpgm %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4096 store i32 0, ptr addrspace(1) %gep @@ -341,12 +341,12 @@ define amdgpu_ps void @mubuf_store_sgpr_ptr_sgpr_offset(ptr addrspace(1) inreg % ; ; GFX12-LABEL: mubuf_store_sgpr_ptr_sgpr_offset: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_ashr_i32 s5, s4, 31 +; GFX12-NEXT: s_ashr_i32 s3, s2, 31 ; GFX12-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-NEXT: s_lshl_b64 s[0:1], s[4:5], 2 +; GFX12-NEXT: s_lshl_b64 s[2:3], s[2:3], 2 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-NEXT: s_add_co_u32 s0, s2, s0 -; GFX12-NEXT: s_add_co_ci_u32 s1, s3, s1 +; GFX12-NEXT: s_add_co_u32 s0, s0, s2 +; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s3 ; GFX12-NEXT: global_store_b32 v0, v0, s[0:1] ; GFX12-NEXT: s_endpgm %gep = getelementptr i32, ptr addrspace(1) %ptr, i32 %soffset @@ -377,9 +377,9 @@ define amdgpu_ps void @mubuf_store_vgpr_ptr_sgpr_offset(ptr addrspace(1) %ptr, i ; ; GFX12-LABEL: mubuf_store_vgpr_ptr_sgpr_offset: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_ashr_i32 s3, s2, 31 +; GFX12-NEXT: s_ashr_i32 s1, s0, 31 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX12-NEXT: s_lshl_b64 s[0:1], s[2:3], 2 +; GFX12-NEXT: s_lshl_b64 s[0:1], s[0:1], 2 ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 @@ -415,9 +415,9 @@ define amdgpu_ps void @mubuf_store_vgpr_ptr_sgpr_offset_offset256(ptr addrspace( ; ; GFX12-LABEL: mubuf_store_vgpr_ptr_sgpr_offset_offset256: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_ashr_i32 s3, s2, 31 +; GFX12-NEXT: s_ashr_i32 s1, s0, 31 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX12-NEXT: s_lshl_b64 s[0:1], s[2:3], 2 +; GFX12-NEXT: s_lshl_b64 s[0:1], s[0:1], 2 ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 @@ -454,9 +454,9 @@ define amdgpu_ps void @mubuf_store_vgpr_ptr_sgpr_offset256_offset(ptr addrspace( ; ; GFX12-LABEL: mubuf_store_vgpr_ptr_sgpr_offset256_offset: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_ashr_i32 s3, s2, 31 +; GFX12-NEXT: s_ashr_i32 s1, s0, 31 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX12-NEXT: s_lshl_b64 s[0:1], s[2:3], 2 +; GFX12-NEXT: s_lshl_b64 s[0:1], s[0:1], 2 ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 @@ -498,7 +498,7 @@ define amdgpu_ps void @mubuf_store_sgpr_ptr_vgpr_offset(ptr addrspace(1) inreg % ; GFX12-LABEL: mubuf_store_sgpr_ptr_vgpr_offset: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1] ; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -542,7 +542,7 @@ define amdgpu_ps void @mubuf_store_sgpr_ptr_vgpr_offset_offset4095(ptr addrspace ; GFX12-LABEL: mubuf_store_sgpr_ptr_vgpr_offset_offset4095: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1] ; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -586,7 +586,7 @@ define amdgpu_ps void @mubuf_store_sgpr_ptr_offset4095_vgpr_offset(ptr addrspace ; GFX12-LABEL: mubuf_store_sgpr_ptr_offset4095_vgpr_offset: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1] ; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -625,7 +625,7 @@ define amdgpu_ps float @mubuf_load_sgpr_ptr(ptr addrspace(1) inreg %ptr) { ; GFX12-LABEL: mubuf_load_sgpr_ptr: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] scope:SCOPE_SYS +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] scope:SCOPE_SYS ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %val = load volatile float, ptr addrspace(1) %ptr @@ -658,7 +658,7 @@ define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4095(ptr addrspace(1) inreg %p ; GFX12-LABEL: mubuf_load_sgpr_ptr_offset4095: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:16380 scope:SCOPE_SYS +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] offset:16380 scope:SCOPE_SYS ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %gep = getelementptr float, ptr addrspace(1) %ptr, i64 4095 @@ -693,8 +693,8 @@ define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4294967296(ptr addrspace(1) in ; ; GFX12-LABEL: mubuf_load_sgpr_ptr_offset4294967296: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_add_co_u32 s0, s2, 0 -; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4 +; GFX12-NEXT: s_add_co_u32 s0, s0, 0 +; GFX12-NEXT: s_add_co_ci_u32 s1, s1, 4 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_SYS @@ -732,8 +732,8 @@ define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4294967297(ptr addrspace(1) in ; ; GFX12-LABEL: mubuf_load_sgpr_ptr_offset4294967297: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_add_co_u32 s0, s2, 4 -; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4 +; GFX12-NEXT: s_add_co_u32 s0, s0, 4 +; GFX12-NEXT: s_add_co_ci_u32 s1, s1, 4 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-NEXT: global_load_b32 v0, v[0:1], off scope:SCOPE_SYS @@ -770,7 +770,7 @@ define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4096(ptr addrspace(1) inreg %p ; GFX12-LABEL: mubuf_load_sgpr_ptr_offset4096: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:16384 scope:SCOPE_SYS +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] offset:16384 scope:SCOPE_SYS ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %gep = getelementptr float, ptr addrspace(1) %ptr, i64 4096 @@ -939,12 +939,12 @@ define amdgpu_ps float @mubuf_load_sgpr_ptr_sgpr_offset(ptr addrspace(1) inreg % ; ; GFX12-LABEL: mubuf_load_sgpr_ptr_sgpr_offset: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_ashr_i32 s5, s4, 31 +; GFX12-NEXT: s_ashr_i32 s3, s2, 31 ; GFX12-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-NEXT: s_lshl_b64 s[0:1], s[4:5], 2 +; GFX12-NEXT: s_lshl_b64 s[2:3], s[2:3], 2 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-NEXT: s_add_co_u32 s0, s2, s0 -; GFX12-NEXT: s_add_co_ci_u32 s1, s3, s1 +; GFX12-NEXT: s_add_co_u32 s0, s0, s2 +; GFX12-NEXT: s_add_co_ci_u32 s1, s1, s3 ; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] scope:SCOPE_SYS ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog @@ -976,9 +976,9 @@ define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset(ptr addrspace(1) %ptr, i ; ; GFX12-LABEL: mubuf_load_vgpr_ptr_sgpr_offset: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_ashr_i32 s3, s2, 31 +; GFX12-NEXT: s_ashr_i32 s1, s0, 31 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX12-NEXT: s_lshl_b64 s[0:1], s[2:3], 2 +; GFX12-NEXT: s_lshl_b64 s[0:1], s[0:1], 2 ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 @@ -1014,9 +1014,9 @@ define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset_offset256(ptr addrspace( ; ; GFX12-LABEL: mubuf_load_vgpr_ptr_sgpr_offset_offset256: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_ashr_i32 s3, s2, 31 +; GFX12-NEXT: s_ashr_i32 s1, s0, 31 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX12-NEXT: s_lshl_b64 s[0:1], s[2:3], 2 +; GFX12-NEXT: s_lshl_b64 s[0:1], s[0:1], 2 ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 @@ -1053,9 +1053,9 @@ define amdgpu_ps float @mubuf_load_vgpr_ptr_sgpr_offset256_offset(ptr addrspace( ; ; GFX12-LABEL: mubuf_load_vgpr_ptr_sgpr_offset256_offset: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_ashr_i32 s3, s2, 31 +; GFX12-NEXT: s_ashr_i32 s1, s0, 31 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX12-NEXT: s_lshl_b64 s[0:1], s[2:3], 2 +; GFX12-NEXT: s_lshl_b64 s[0:1], s[0:1], 2 ; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 @@ -1097,7 +1097,7 @@ define amdgpu_ps float @mubuf_load_sgpr_ptr_vgpr_offset(ptr addrspace(1) inreg % ; GFX12-LABEL: mubuf_load_sgpr_ptr_vgpr_offset: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1] ; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -1141,7 +1141,7 @@ define amdgpu_ps float @mubuf_load_sgpr_ptr_vgpr_offset_offset4095(ptr addrspace ; GFX12-LABEL: mubuf_load_sgpr_ptr_vgpr_offset_offset4095: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1] ; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -1185,7 +1185,7 @@ define amdgpu_ps float @mubuf_load_sgpr_ptr_offset4095_vgpr_offset(ptr addrspace ; GFX12-LABEL: mubuf_load_sgpr_ptr_offset4095_vgpr_offset: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1] ; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -1231,7 +1231,7 @@ define amdgpu_ps float @mubuf_atomicrmw_sgpr_ptr_offset4095(ptr addrspace(1) inr ; GFX12-LABEL: mubuf_atomicrmw_sgpr_ptr_offset4095: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_dual_mov_b32 v0, 2 :: v_dual_mov_b32 v1, 0 -; GFX12-NEXT: global_atomic_add_u32 v0, v1, v0, s[2:3] offset:16380 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_add_u32 v0, v1, v0, s[0:1] offset:16380 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1273,8 +1273,8 @@ define amdgpu_ps float @mubuf_atomicrmw_sgpr_ptr_offset4294967296(ptr addrspace( ; ; GFX12-LABEL: mubuf_atomicrmw_sgpr_ptr_offset4294967296: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_add_co_u32 s0, s2, 0 -; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4 +; GFX12-NEXT: s_add_co_u32 s0, s0, 0 +; GFX12-NEXT: s_add_co_ci_u32 s1, s1, 4 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX12-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-NEXT: v_mov_b32_e32 v2, 2 @@ -1406,7 +1406,7 @@ define amdgpu_ps float @mubuf_atomicrmw_sgpr_ptr_vgpr_offset(ptr addrspace(1) in ; GFX12-LABEL: mubuf_atomicrmw_sgpr_ptr_vgpr_offset: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 +; GFX12-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1] ; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -1457,7 +1457,7 @@ define amdgpu_ps float @mubuf_cmpxchg_sgpr_ptr_offset4095(ptr addrspace(1) inreg ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v2, v0 ; GFX12-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v0, v[1:2], s[2:3] offset:16380 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v0, v[1:2], s[0:1] offset:16380 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1502,8 +1502,8 @@ define amdgpu_ps float @mubuf_cmpxchg_sgpr_ptr_offset4294967296(ptr addrspace(1) ; ; GFX12-LABEL: mubuf_cmpxchg_sgpr_ptr_offset4294967296: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_add_co_u32 s0, s2, 0 -; GFX12-NEXT: s_add_co_ci_u32 s1, s3, 4 +; GFX12-NEXT: s_add_co_u32 s0, s0, 0 +; GFX12-NEXT: s_add_co_ci_u32 s1, s1, 4 ; GFX12-NEXT: v_dual_mov_b32 v2, v0 :: v_dual_mov_b32 v3, s0 ; GFX12-NEXT: v_mov_b32_e32 v4, s1 ; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[3:4], v[1:2], off th:TH_ATOMIC_RETURN scope:SCOPE_DEV @@ -1637,9 +1637,9 @@ define amdgpu_ps float @mubuf_cmpxchg_sgpr_ptr_vgpr_offset(ptr addrspace(1) inre ; ; GFX12-LABEL: mubuf_cmpxchg_sgpr_ptr_vgpr_offset: ; GFX12: ; %bb.0: -; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v4, s2 +; GFX12-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v4, s0 ; GFX12-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GFX12-NEXT: v_mov_b32_e32 v5, s3 +; GFX12-NEXT: v_mov_b32_e32 v5, s1 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1] ; GFX12-NEXT: v_add_co_u32 v0, vcc_lo, v4, v0 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll index c226f7f9289eec..5aa9ea8cacdcf0 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll @@ -22,7 +22,7 @@ define amdgpu_ps i32 @s_orn2_i32(i32 inreg %src0, i32 inreg %src1) { ; ; GFX11-LABEL: s_orn2_i32: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b32 s0, s2, s3 +; GFX11-NEXT: s_or_not1_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i32 %src1, -1 %or = or i32 %src0, %not.src1 @@ -42,7 +42,7 @@ define amdgpu_ps i32 @s_orn2_i32_commute(i32 inreg %src0, i32 inreg %src1) { ; ; GFX11-LABEL: s_orn2_i32_commute: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b32 s0, s2, s3 +; GFX11-NEXT: s_or_not1_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i32 %src1, -1 %or = or i32 %not.src1, %src0 @@ -64,8 +64,8 @@ define amdgpu_ps { i32, i32 } @s_orn2_i32_multi_use(i32 inreg %src0, i32 inreg % ; ; GFX11-LABEL: s_orn2_i32_multi_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b32 s0, s2, s3 -; GFX11-NEXT: s_not_b32 s1, s3 +; GFX11-NEXT: s_or_not1_b32 s0, s0, s1 +; GFX11-NEXT: s_not_b32 s1, s1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i32 %src1, -1 %or = or i32 %src0, %not.src1 @@ -89,8 +89,8 @@ define amdgpu_ps { i32, i32 } @s_orn2_i32_multi_foldable_use(i32 inreg %src0, i3 ; ; GFX11-LABEL: s_orn2_i32_multi_foldable_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b32 s0, s2, s4 -; GFX11-NEXT: s_or_not1_b32 s1, s3, s4 +; GFX11-NEXT: s_or_not1_b32 s0, s0, s2 +; GFX11-NEXT: s_or_not1_b32 s1, s1, s2 ; GFX11-NEXT: ; return to shader part epilog %not.src2 = xor i32 %src2, -1 %or0 = or i32 %src0, %not.src2 @@ -123,10 +123,15 @@ define amdgpu_ps float @v_orn2_i32_sv(i32 inreg %src0, i32 %src1) { ; GCN-NEXT: v_bfi_b32 v0, v0, s2, -1 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: v_orn2_i32_sv: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_bfi_b32 v0, v0, s2, -1 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: v_orn2_i32_sv: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_bfi_b32 v0, v0, s2, -1 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: v_orn2_i32_sv: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_bfi_b32 v0, v0, s0, -1 +; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i32 %src1, -1 %or = or i32 %src0, %not.src1 %cast = bitcast i32 %or to float @@ -139,10 +144,15 @@ define amdgpu_ps float @v_orn2_i32_vs(i32 %src0, i32 inreg %src1) { ; GCN-NEXT: v_bfi_b32 v0, s2, v0, -1 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: v_orn2_i32_vs: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_bfi_b32 v0, s2, v0, -1 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: v_orn2_i32_vs: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_bfi_b32 v0, s2, v0, -1 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: v_orn2_i32_vs: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_bfi_b32 v0, s0, v0, -1 +; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i32 %src1, -1 %or = or i32 %src0, %not.src1 %cast = bitcast i32 %or to float @@ -162,7 +172,7 @@ define amdgpu_ps i64 @s_orn2_i64(i64 inreg %src0, i64 inreg %src1) { ; ; GFX11-LABEL: s_orn2_i64: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b64 s[0:1], s[2:3], s[4:5] +; GFX11-NEXT: s_or_not1_b64 s[0:1], s[0:1], s[2:3] ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i64 %src1, -1 %or = or i64 %src0, %not.src1 @@ -182,7 +192,7 @@ define amdgpu_ps i64 @s_orn2_i64_commute(i64 inreg %src0, i64 inreg %src1) { ; ; GFX11-LABEL: s_orn2_i64_commute: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b64 s[0:1], s[2:3], s[4:5] +; GFX11-NEXT: s_or_not1_b64 s[0:1], s[0:1], s[2:3] ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i64 %src1, -1 %or = or i64 %not.src1, %src0 @@ -204,8 +214,8 @@ define amdgpu_ps { i64, i64 } @s_orn2_i64_multi_foldable_use(i64 inreg %src0, i6 ; ; GFX11-LABEL: s_orn2_i64_multi_foldable_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b64 s[0:1], s[2:3], s[6:7] -; GFX11-NEXT: s_or_not1_b64 s[2:3], s[4:5], s[6:7] +; GFX11-NEXT: s_or_not1_b64 s[0:1], s[0:1], s[4:5] +; GFX11-NEXT: s_or_not1_b64 s[2:3], s[2:3], s[4:5] ; GFX11-NEXT: ; return to shader part epilog %not.src2 = xor i64 %src2, -1 %or0 = or i64 %src0, %not.src2 @@ -232,8 +242,8 @@ define amdgpu_ps { i64, i64 } @s_orn2_i64_multi_use(i64 inreg %src0, i64 inreg % ; ; GFX11-LABEL: s_orn2_i64_multi_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b64 s[0:1], s[2:3], s[4:5] -; GFX11-NEXT: s_not_b64 s[2:3], s[4:5] +; GFX11-NEXT: s_or_not1_b64 s[0:1], s[0:1], s[2:3] +; GFX11-NEXT: s_not_b64 s[2:3], s[2:3] ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i64 %src1, -1 %or = or i64 %src0, %not.src1 @@ -274,13 +284,21 @@ define amdgpu_ps <2 x float> @v_orn2_i64_sv(i64 inreg %src0, i64 %src1) { ; GCN-NEXT: v_or_b32_e32 v1, s3, v1 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: v_orn2_i64_sv: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_xor_b32_e32 v0, -1, v0 -; GFX10PLUS-NEXT: v_xor_b32_e32 v1, -1, v1 -; GFX10PLUS-NEXT: v_or_b32_e32 v0, s2, v0 -; GFX10PLUS-NEXT: v_or_b32_e32 v1, s3, v1 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: v_orn2_i64_sv: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_xor_b32_e32 v0, -1, v0 +; GFX10-NEXT: v_xor_b32_e32 v1, -1, v1 +; GFX10-NEXT: v_or_b32_e32 v0, s2, v0 +; GFX10-NEXT: v_or_b32_e32 v1, s3, v1 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: v_orn2_i64_sv: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_xor_b32_e32 v0, -1, v0 +; GFX11-NEXT: v_xor_b32_e32 v1, -1, v1 +; GFX11-NEXT: v_or_b32_e32 v0, s0, v0 +; GFX11-NEXT: v_or_b32_e32 v1, s1, v1 +; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i64 %src1, -1 %or = or i64 %src0, %not.src1 %cast = bitcast i64 %or to <2 x float> @@ -308,7 +326,7 @@ define amdgpu_ps <2 x float> @v_orn2_i64_vs(i64 %src0, i64 inreg %src1) { ; ; GFX11-LABEL: v_orn2_i64_vs: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_not_b64 s[0:1], s[2:3] +; GFX11-NEXT: s_not_b64 s[0:1], s[0:1] ; GFX11-NEXT: v_dual_mov_b32 v3, s1 :: v_dual_mov_b32 v2, s0 ; GFX11-NEXT: v_or_b32_e32 v1, v1, v3 ; GFX11-NEXT: v_or_b32_e32 v0, v0, v2 @@ -332,7 +350,7 @@ define amdgpu_ps <2 x i32> @s_orn2_v2i32(<2 x i32> inreg %src0, <2 x i32> inreg ; ; GFX11-LABEL: s_orn2_v2i32: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b64 s[0:1], s[2:3], s[4:5] +; GFX11-NEXT: s_or_not1_b64 s[0:1], s[0:1], s[2:3] ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <2 x i32> %src1, %or = or <2 x i32> %src0, %not.src1 @@ -352,7 +370,7 @@ define amdgpu_ps <2 x i32> @s_orn2_v2i32_commute(<2 x i32> inreg %src0, <2 x i32 ; ; GFX11-LABEL: s_orn2_v2i32_commute: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b64 s[0:1], s[2:3], s[4:5] +; GFX11-NEXT: s_or_not1_b64 s[0:1], s[0:1], s[2:3] ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <2 x i32> %src1, %or = or <2 x i32> %not.src1, %src0 @@ -372,7 +390,7 @@ define amdgpu_ps i16 @s_orn2_i16(i16 inreg %src0, i16 inreg %src1) { ; ; GFX11-LABEL: s_orn2_i16: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b32 s0, s2, s3 +; GFX11-NEXT: s_or_not1_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i16 %src1, -1 %or = or i16 %src0, %not.src1 @@ -392,7 +410,7 @@ define amdgpu_ps i16 @s_orn2_i16_commute(i16 inreg %src0, i16 inreg %src1) { ; ; GFX11-LABEL: s_orn2_i16_commute: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b32 s0, s2, s3 +; GFX11-NEXT: s_or_not1_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i16 %src1, -1 %or = or i16 %not.src1, %src0 @@ -414,8 +432,8 @@ define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_use(i16 inreg %src0, i16 inreg % ; ; GFX11-LABEL: s_orn2_i16_multi_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b32 s0, s2, s3 -; GFX11-NEXT: s_xor_b32 s1, s3, -1 +; GFX11-NEXT: s_or_not1_b32 s0, s0, s1 +; GFX11-NEXT: s_xor_b32 s1, s1, -1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor i16 %src1, -1 %or = or i16 %src0, %not.src1 @@ -439,8 +457,8 @@ define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_foldable_use(i16 inreg %src0, i1 ; ; GFX11-LABEL: s_orn2_i16_multi_foldable_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b32 s0, s2, s4 -; GFX11-NEXT: s_or_not1_b32 s1, s3, s4 +; GFX11-NEXT: s_or_not1_b32 s0, s0, s2 +; GFX11-NEXT: s_or_not1_b32 s1, s1, s2 ; GFX11-NEXT: ; return to shader part epilog %not.src2 = xor i16 %src2, -1 %or0 = or i16 %src0, %not.src2 @@ -501,14 +519,14 @@ define amdgpu_ps float @v_orn2_i16_sv(i16 inreg %src0, i16 %src1) { ; GFX11-TRUE16-LABEL: v_orn2_i16_sv: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: v_xor_b16 v0.l, v0.l, -1 -; GFX11-TRUE16-NEXT: v_or_b16 v0.l, s2, v0.l +; GFX11-TRUE16-NEXT: v_or_b16 v0.l, s0, v0.l ; GFX11-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: v_orn2_i16_sv: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: v_xor_b32_e32 v0, -1, v0 -; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, s2, v0 +; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, s0, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: ; return to shader part epilog %not.src1 = xor i16 %src1, -1 @@ -535,14 +553,14 @@ define amdgpu_ps float @v_orn2_i16_vs(i16 %src0, i16 inreg %src1) { ; ; GFX11-TRUE16-LABEL: v_orn2_i16_vs: ; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_xor_b32 s0, s2, -1 +; GFX11-TRUE16-NEXT: s_xor_b32 s0, s0, -1 ; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v0.l, s0 ; GFX11-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: v_orn2_i16_vs: ; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_xor_b32 s0, s2, -1 +; GFX11-FAKE16-NEXT: s_xor_b32 s0, s0, -1 ; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, s0, v0 ; GFX11-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -572,7 +590,7 @@ define amdgpu_ps i32 @s_orn2_v2i16(<2 x i16> inreg %src0, <2 x i16> inreg %src1) ; ; GFX11-LABEL: s_orn2_v2i16: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b32 s0, s2, s3 +; GFX11-NEXT: s_or_not1_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <2 x i16> %src1, %or = or <2 x i16> %src0, %not.src1 @@ -599,7 +617,7 @@ define amdgpu_ps i32 @s_orn2_v2i16_commute(<2 x i16> inreg %src0, <2 x i16> inre ; ; GFX11-LABEL: s_orn2_v2i16_commute: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b32 s0, s2, s3 +; GFX11-NEXT: s_or_not1_b32 s0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <2 x i16> %src1, %or = or <2 x i16> %not.src1, %src0 @@ -628,8 +646,8 @@ define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_use(<2 x i16> inreg %src0, <2 ; ; GFX11-LABEL: s_orn2_v2i16_multi_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b32 s0, s2, s3 -; GFX11-NEXT: s_xor_b32 s1, s3, -1 +; GFX11-NEXT: s_or_not1_b32 s0, s0, s1 +; GFX11-NEXT: s_xor_b32 s1, s1, -1 ; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <2 x i16> %src1, %or = or <2 x i16> %src0, %not.src1 @@ -663,8 +681,8 @@ define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_foldable_use(<2 x i16> inreg % ; ; GFX11-LABEL: s_orn2_v2i16_multi_foldable_use: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_or_not1_b32 s0, s2, s4 -; GFX11-NEXT: s_or_not1_b32 s1, s3, s4 +; GFX11-NEXT: s_or_not1_b32 s0, s0, s2 +; GFX11-NEXT: s_or_not1_b32 s1, s1, s2 ; GFX11-NEXT: ; return to shader part epilog %not.src2 = xor <2 x i16> %src2, %or0 = or <2 x i16> %src0, %not.src2 @@ -746,18 +764,18 @@ define amdgpu_ps i48 @s_orn2_v3i16(<3 x i16> inreg %src0, <3 x i16> inreg %src1) ; ; GFX11-TRUE16-LABEL: s_orn2_v3i16: ; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1 -; GFX11-TRUE16-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] -; GFX11-TRUE16-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] +; GFX11-TRUE16-NEXT: s_mov_b64 s[4:5], -1 +; GFX11-TRUE16-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-TRUE16-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] ; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16 ; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2 ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: s_orn2_v3i16: ; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_mov_b64 s[0:1], -1 -; GFX11-FAKE16-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] -; GFX11-FAKE16-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] +; GFX11-FAKE16-NEXT: s_mov_b64 s[4:5], -1 +; GFX11-FAKE16-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-FAKE16-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] ; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s0, 16 ; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff ; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16 @@ -820,18 +838,18 @@ define amdgpu_ps i48 @s_orn2_v3i16_commute(<3 x i16> inreg %src0, <3 x i16> inre ; ; GFX11-TRUE16-LABEL: s_orn2_v3i16_commute: ; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1 -; GFX11-TRUE16-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] -; GFX11-TRUE16-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX11-TRUE16-NEXT: s_mov_b64 s[4:5], -1 +; GFX11-TRUE16-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-TRUE16-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16 ; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2 ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: s_orn2_v3i16_commute: ; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_mov_b64 s[0:1], -1 -; GFX11-FAKE16-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] -; GFX11-FAKE16-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX11-FAKE16-NEXT: s_mov_b64 s[4:5], -1 +; GFX11-FAKE16-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-FAKE16-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s0, 16 ; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff ; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16 @@ -909,31 +927,30 @@ define amdgpu_ps { i48, i48 } @s_orn2_v3i16_multi_use(<3 x i16> inreg %src0, <3 ; ; GFX11-TRUE16-LABEL: s_orn2_v3i16_multi_use: ; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: s_mov_b64 s[0:1], -1 -; GFX11-TRUE16-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1] -; GFX11-TRUE16-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5] -; GFX11-TRUE16-NEXT: s_lshr_b32 s3, s4, 16 -; GFX11-TRUE16-NEXT: s_lshr_b32 s2, s0, 16 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s2 -; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s4, s3 -; GFX11-TRUE16-NEXT: s_mov_b32 s3, s5 +; GFX11-TRUE16-NEXT: s_mov_b64 s[4:5], -1 +; GFX11-TRUE16-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-TRUE16-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX11-TRUE16-NEXT: s_lshr_b32 s5, s2, 16 +; GFX11-TRUE16-NEXT: s_lshr_b32 s4, s0, 16 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s2, s2, s5 +; GFX11-TRUE16-NEXT: s_pack_ll_b32_b16 s0, s0, s4 ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: s_orn2_v3i16_multi_use: ; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: s_mov_b64 s[0:1], -1 -; GFX11-FAKE16-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1] -; GFX11-FAKE16-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5] -; GFX11-FAKE16-NEXT: s_lshr_b32 s3, s4, 16 -; GFX11-FAKE16-NEXT: s_lshr_b32 s2, s0, 16 +; GFX11-FAKE16-NEXT: s_mov_b64 s[4:5], -1 +; GFX11-FAKE16-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-FAKE16-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX11-FAKE16-NEXT: s_lshr_b32 s5, s2, 16 +; GFX11-FAKE16-NEXT: s_lshr_b32 s4, s0, 16 ; GFX11-FAKE16-NEXT: s_and_b32 s0, s0, 0xffff -; GFX11-FAKE16-NEXT: s_lshl_b32 s2, s2, 16 -; GFX11-FAKE16-NEXT: s_lshl_b32 s3, s3, 16 -; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s2 -; GFX11-FAKE16-NEXT: s_and_b32 s2, s4, 0xffff +; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s4, 16 +; GFX11-FAKE16-NEXT: s_and_b32 s2, s2, 0xffff +; GFX11-FAKE16-NEXT: s_or_b32 s0, s0, s4 +; GFX11-FAKE16-NEXT: s_lshl_b32 s4, s5, 16 ; GFX11-FAKE16-NEXT: s_and_b32 s1, s1, 0xffff -; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s3 -; GFX11-FAKE16-NEXT: s_and_b32 s3, s5, 0xffff +; GFX11-FAKE16-NEXT: s_or_b32 s2, s2, s4 +; GFX11-FAKE16-NEXT: s_and_b32 s3, s3, 0xffff ; GFX11-FAKE16-NEXT: ; return to shader part epilog %not.src1 = xor <3 x i16> %src1, %or = or <3 x i16> %src0, %not.src1 @@ -1022,13 +1039,21 @@ define amdgpu_ps i64 @s_orn2_v4i16(<4 x i16> inreg %src0, <4 x i16> inreg %src1) ; GFX9-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_orn2_v4i16: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_mov_b32 s0, -1 -; GFX10PLUS-NEXT: s_mov_b32 s1, s0 -; GFX10PLUS-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] -; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_orn2_v4i16: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, -1 +; GFX10-NEXT: s_mov_b32 s1, s0 +; GFX10-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] +; GFX10-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_orn2_v4i16: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s4, -1 +; GFX11-NEXT: s_mov_b32 s5, s4 +; GFX11-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <4 x i16> %src1, %or = or <4 x i16> %src0, %not.src1 %cast = bitcast <4 x i16> %or to i64 @@ -1066,13 +1091,21 @@ define amdgpu_ps i64 @s_orn2_v4i16_commute(<4 x i16> inreg %src0, <4 x i16> inre ; GFX9-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_orn2_v4i16_commute: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_mov_b32 s0, -1 -; GFX10PLUS-NEXT: s_mov_b32 s1, s0 -; GFX10PLUS-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] -; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_orn2_v4i16_commute: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, -1 +; GFX10-NEXT: s_mov_b32 s1, s0 +; GFX10-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] +; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_orn2_v4i16_commute: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s4, -1 +; GFX11-NEXT: s_mov_b32 s5, s4 +; GFX11-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_or_b64 s[0:1], s[2:3], s[0:1] +; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <4 x i16> %src1, %or = or <4 x i16> %not.src1, %src0 %cast = bitcast <4 x i16> %or to i64 @@ -1112,15 +1145,23 @@ define amdgpu_ps { i64, i64 } @s_orn2_v4i16_multi_use(<4 x i16> inreg %src0, <4 ; GFX9-NEXT: s_mov_b32 s3, s5 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_orn2_v4i16_multi_use: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_mov_b32 s0, -1 -; GFX10PLUS-NEXT: s_mov_b32 s1, s0 -; GFX10PLUS-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1] -; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5] -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_orn2_v4i16_multi_use: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, -1 +; GFX10-NEXT: s_mov_b32 s1, s0 +; GFX10-NEXT: s_xor_b64 s[4:5], s[4:5], s[0:1] +; GFX10-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5] +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_orn2_v4i16_multi_use: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s4, -1 +; GFX11-NEXT: s_mov_b32 s5, s4 +; GFX11-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX11-NEXT: ; return to shader part epilog %not.src1 = xor <4 x i16> %src1, %or = or <4 x i16> %src0, %not.src1 @@ -1172,14 +1213,23 @@ define amdgpu_ps { i64, i64 } @s_orn2_v4i16_multi_foldable_use(<4 x i16> inreg % ; GFX9-NEXT: s_or_b64 s[2:3], s[4:5], s[6:7] ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_orn2_v4i16_multi_foldable_use: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_mov_b32 s0, -1 -; GFX10PLUS-NEXT: s_mov_b32 s1, s0 -; GFX10PLUS-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1] -; GFX10PLUS-NEXT: s_or_b64 s[0:1], s[2:3], s[6:7] -; GFX10PLUS-NEXT: s_or_b64 s[2:3], s[4:5], s[6:7] -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_orn2_v4i16_multi_foldable_use: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s0, -1 +; GFX10-NEXT: s_mov_b32 s1, s0 +; GFX10-NEXT: s_xor_b64 s[6:7], s[6:7], s[0:1] +; GFX10-NEXT: s_or_b64 s[0:1], s[2:3], s[6:7] +; GFX10-NEXT: s_or_b64 s[2:3], s[4:5], s[6:7] +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_orn2_v4i16_multi_foldable_use: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_mov_b32 s6, -1 +; GFX11-NEXT: s_mov_b32 s7, s6 +; GFX11-NEXT: s_xor_b64 s[4:5], s[4:5], s[6:7] +; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] +; GFX11-NEXT: s_or_b64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: ; return to shader part epilog %not.src2 = xor <4 x i16> %src2, %or0 = or <4 x i16> %src0, %not.src2 %or1 = or <4 x i16> %src1, %not.src2 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll index 37060571106b3b..29aa11cca61edc 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.ptr.s.buffer.load.ll @@ -23,13 +23,13 @@ define amdgpu_ps i32 @ptr_s_buffer_load_i32(ptr addrspace(8) inreg %rsrc, i32 in ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(i32) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (i32) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[AMDGPU_S_BUFFER_LOAD]](i32) @@ -63,13 +63,13 @@ define amdgpu_ps <2 x i32> @ptr_s_buffer_load_v2i32(ptr addrspace(8) inreg %rsrc ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v2i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<2 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<2 x i32>) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<2 x i32>) @@ -110,13 +110,13 @@ define amdgpu_ps <3 x i32> @ptr_s_buffer_load_v3i32(ptr addrspace(8) inreg %rsrc ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v3i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<3 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<3 x i32>) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<3 x i32>) @@ -175,13 +175,13 @@ define amdgpu_ps <8 x i32> @ptr_s_buffer_load_v8i32(ptr addrspace(8) inreg %rsrc ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v8i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<8 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<8 x i32>) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32), [[UV3:%[0-9]+]]:sgpr(i32), [[UV4:%[0-9]+]]:sgpr(i32), [[UV5:%[0-9]+]]:sgpr(i32), [[UV6:%[0-9]+]]:sgpr(i32), [[UV7:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<8 x i32>) @@ -279,13 +279,13 @@ define amdgpu_ps <16 x i32> @ptr_s_buffer_load_v16i32(ptr addrspace(8) inreg %rs ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v16i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<16 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (<16 x i32>) from %ir.rsrc, align 1, addrspace 8) ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32), [[UV3:%[0-9]+]]:sgpr(i32), [[UV4:%[0-9]+]]:sgpr(i32), [[UV5:%[0-9]+]]:sgpr(i32), [[UV6:%[0-9]+]]:sgpr(i32), [[UV7:%[0-9]+]]:sgpr(i32), [[UV8:%[0-9]+]]:sgpr(i32), [[UV9:%[0-9]+]]:sgpr(i32), [[UV10:%[0-9]+]]:sgpr(i32), [[UV11:%[0-9]+]]:sgpr(i32), [[UV12:%[0-9]+]]:sgpr(i32), [[UV13:%[0-9]+]]:sgpr(i32), [[UV14:%[0-9]+]]:sgpr(i32), [[UV15:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<16 x i32>) @@ -363,12 +363,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset(ptr addrspace(8) inreg ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 @@ -403,12 +403,12 @@ define amdgpu_ps <2 x float> @ptr_s_buffer_load_v2f32_vgpr_offset(ptr addrspace( ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v2f32_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 @@ -446,12 +446,12 @@ define amdgpu_ps <3 x float> @ptr_s_buffer_load_v3f32_vgpr_offset(ptr addrspace( ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v3f32_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 @@ -491,12 +491,12 @@ define amdgpu_ps <4 x float> @ptr_s_buffer_load_v4f32_vgpr_offset(ptr addrspace( ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v4f32_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 @@ -542,12 +542,12 @@ define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset(ptr addrspace( ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 @@ -608,12 +608,12 @@ define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset(ptr addrspac ; ; GFX1200_1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 @@ -668,12 +668,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4092(ptr addrspace ; ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4092 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) @@ -688,12 +688,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4092(ptr addrspace ; ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4092 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4092 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) @@ -733,12 +733,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4095(ptr addrspace ; ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4095 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) @@ -753,12 +753,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4095(ptr addrspace ; ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4095 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) @@ -797,12 +797,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4096(ptr addrspace ; ; GFX1200-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4096 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) @@ -817,12 +817,12 @@ define amdgpu_ps float @ptr_s_buffer_load_f32_vgpr_offset_add_4096(ptr addrspace ; ; GFX1250-LABEL: name: ptr_s_buffer_load_f32_vgpr_offset_add_4096 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4096 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) @@ -872,12 +872,12 @@ define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4064(ptr a ; ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4064 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) @@ -901,12 +901,12 @@ define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4064(ptr a ; ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4064 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4064 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) @@ -965,12 +965,12 @@ define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4068(ptr a ; ; GFX1200-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4068 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) @@ -994,12 +994,12 @@ define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset_add_4068(ptr a ; ; GFX1250-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset_add_4068 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4068 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) @@ -1067,12 +1067,12 @@ define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4032(ptr ; ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4032 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) @@ -1106,12 +1106,12 @@ define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4032(ptr ; ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4032 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4032 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) @@ -1189,12 +1189,12 @@ define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4036(ptr ; ; GFX1200-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4036 ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) @@ -1228,12 +1228,12 @@ define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset_add_4036(ptr ; ; GFX1250-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset_add_4036 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4036 ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[C]](i32) diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll index e516917d9b4e42..758f7d281f81ed 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-amdgcn.s.buffer.load.ll @@ -23,14 +23,14 @@ define amdgpu_ps i32 @s_buffer_load_i32(<4 x i32> inreg %rsrc, i32 inreg %soffse ; ; GFX1200_1250-LABEL: name: s_buffer_load_i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(i32) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (s32)) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[AMDGPU_S_BUFFER_LOAD]](i32) ; GFX1200_1250-NEXT: [[INTRINSIC_CONVERGENT:%[0-9]+]]:sgpr(i32) = G_INTRINSIC_CONVERGENT intrinsic(@llvm.amdgcn.readfirstlane), [[COPY5]](i32) @@ -63,14 +63,14 @@ define amdgpu_ps <2 x i32> @s_buffer_load_v2i32(<4 x i32> inreg %rsrc, i32 inreg ; ; GFX1200_1250-LABEL: name: s_buffer_load_v2i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<2 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (s64)) ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<2 x i32>) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32) @@ -110,14 +110,14 @@ define amdgpu_ps <3 x i32> @s_buffer_load_v3i32(<4 x i32> inreg %rsrc, i32 inreg ; ; GFX1200_1250-LABEL: name: s_buffer_load_v3i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<3 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (s96), align 16) ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<3 x i32>) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32) @@ -175,14 +175,14 @@ define amdgpu_ps <8 x i32> @s_buffer_load_v8i32(<4 x i32> inreg %rsrc, i32 inreg ; ; GFX1200_1250-LABEL: name: s_buffer_load_v8i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<8 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (s256)) ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32), [[UV3:%[0-9]+]]:sgpr(i32), [[UV4:%[0-9]+]]:sgpr(i32), [[UV5:%[0-9]+]]:sgpr(i32), [[UV6:%[0-9]+]]:sgpr(i32), [[UV7:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<8 x i32>) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32) @@ -279,14 +279,14 @@ define amdgpu_ps <16 x i32> @s_buffer_load_v16i32(<4 x i32> inreg %rsrc, i32 inr ; ; GFX1200_1250-LABEL: name: s_buffer_load_v16i32 ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200_1250-NEXT: [[AMDGPU_S_BUFFER_LOAD:%[0-9]+]]:sgpr(<16 x i32>) = G_AMDGPU_S_BUFFER_LOAD [[BUILD_VECTOR]](<4 x i32>), [[COPY4]](i32), 0 :: (dereferenceable invariant load (s512)) ; GFX1200_1250-NEXT: [[UV:%[0-9]+]]:sgpr(i32), [[UV1:%[0-9]+]]:sgpr(i32), [[UV2:%[0-9]+]]:sgpr(i32), [[UV3:%[0-9]+]]:sgpr(i32), [[UV4:%[0-9]+]]:sgpr(i32), [[UV5:%[0-9]+]]:sgpr(i32), [[UV6:%[0-9]+]]:sgpr(i32), [[UV7:%[0-9]+]]:sgpr(i32), [[UV8:%[0-9]+]]:sgpr(i32), [[UV9:%[0-9]+]]:sgpr(i32), [[UV10:%[0-9]+]]:sgpr(i32), [[UV11:%[0-9]+]]:sgpr(i32), [[UV12:%[0-9]+]]:sgpr(i32), [[UV13:%[0-9]+]]:sgpr(i32), [[UV14:%[0-9]+]]:sgpr(i32), [[UV15:%[0-9]+]]:sgpr(i32) = G_UNMERGE_VALUES [[AMDGPU_S_BUFFER_LOAD]](<16 x i32>) ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[UV]](i32) @@ -363,12 +363,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 ; ; GFX1200_1250-LABEL: name: s_buffer_load_f32_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 @@ -403,12 +403,12 @@ define amdgpu_ps <2 x float> @s_buffer_load_v2f32_vgpr_offset(<4 x i32> inreg %r ; ; GFX1200_1250-LABEL: name: s_buffer_load_v2f32_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 @@ -446,12 +446,12 @@ define amdgpu_ps <3 x float> @s_buffer_load_v3f32_vgpr_offset(<4 x i32> inreg %r ; ; GFX1200_1250-LABEL: name: s_buffer_load_v3f32_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 @@ -491,12 +491,12 @@ define amdgpu_ps <4 x float> @s_buffer_load_v4f32_vgpr_offset(<4 x i32> inreg %r ; ; GFX1200_1250-LABEL: name: s_buffer_load_v4f32_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 @@ -542,12 +542,12 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset(<4 x i32> inreg %r ; ; GFX1200_1250-LABEL: name: s_buffer_load_v8f32_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 @@ -608,12 +608,12 @@ define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset(<4 x i32> inreg ; ; GFX1200_1250-LABEL: name: s_buffer_load_v16f32_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 @@ -667,12 +667,12 @@ define amdgpu_ps void @s_buffer_load_i96_vgpr_offset(<4 x i32> inreg %rsrc, i32 ; ; GFX1200_1250-LABEL: name: s_buffer_load_i96_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF @@ -714,12 +714,12 @@ define amdgpu_ps void @s_buffer_load_i256_vgpr_offset(<4 x i32> inreg %rsrc, i32 ; ; GFX1200_1250-LABEL: name: s_buffer_load_i256_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF @@ -774,12 +774,12 @@ define amdgpu_ps void @s_buffer_load_i512_vgpr_offset(<4 x i32> inreg %rsrc, i32 ; ; GFX1200_1250-LABEL: name: s_buffer_load_i512_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF @@ -834,12 +834,12 @@ define amdgpu_ps void @s_buffer_load_v16i16_vgpr_offset(<4 x i32> inreg %rsrc, i ; ; GFX1200_1250-LABEL: name: s_buffer_load_v16i16_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF @@ -894,12 +894,12 @@ define amdgpu_ps void @s_buffer_load_v32i16_vgpr_offset(<4 x i32> inreg %rsrc, i ; ; GFX1200_1250-LABEL: name: s_buffer_load_v32i16_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF @@ -954,12 +954,12 @@ define amdgpu_ps void @s_buffer_load_v4i64_vgpr_offset(<4 x i32> inreg %rsrc, i3 ; ; GFX1200_1250-LABEL: name: s_buffer_load_v4i64_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF @@ -1014,12 +1014,12 @@ define amdgpu_ps void @s_buffer_load_v8i64_vgpr_offset(<4 x i32> inreg %rsrc, i3 ; ; GFX1200_1250-LABEL: name: s_buffer_load_v8i64_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF @@ -1074,12 +1074,12 @@ define amdgpu_ps void @s_buffer_load_v4p1_vgpr_offset(<4 x i32> inreg %rsrc, i32 ; ; GFX1200_1250-LABEL: name: s_buffer_load_v4p1_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF @@ -1134,12 +1134,12 @@ define amdgpu_ps void @s_buffer_load_v8p1_vgpr_offset(<4 x i32> inreg %rsrc, i32 ; ; GFX1200_1250-LABEL: name: s_buffer_load_v8p1_vgpr_offset ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200_1250-NEXT: {{ $}} - ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[DEF:%[0-9]+]]:sgpr(p1) = G_IMPLICIT_DEF @@ -1190,12 +1190,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4092(<4 x i32> inreg % ; ; GFX1200-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4092 @@ -1210,12 +1210,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4092(<4 x i32> inreg % ; ; GFX1250-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4092 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4092 @@ -1254,12 +1254,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4095(<4 x i32> inreg % ; ; GFX1200-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4095 @@ -1274,12 +1274,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4095(<4 x i32> inreg % ; ; GFX1250-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4095 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4095 @@ -1318,12 +1318,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4096(<4 x i32> inreg % ; ; GFX1200-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4096 @@ -1338,12 +1338,12 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_offset_add_4096(<4 x i32> inreg % ; ; GFX1250-LABEL: name: s_buffer_load_f32_vgpr_offset_add_4096 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4096 @@ -1393,12 +1393,12 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4064(<4 x i32> ; ; GFX1200-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4064 @@ -1422,12 +1422,12 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4064(<4 x i32> ; ; GFX1250-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4064 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4064 @@ -1485,12 +1485,12 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4068(<4 x i32> ; ; GFX1200-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4068 @@ -1514,12 +1514,12 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset_add_4068(<4 x i32> ; ; GFX1250-LABEL: name: s_buffer_load_v8f32_vgpr_offset_add_4068 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4068 @@ -1587,12 +1587,12 @@ define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4032(<4 x i3 ; ; GFX1200-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4032 @@ -1626,12 +1626,12 @@ define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4032(<4 x i3 ; ; GFX1250-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4032 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4032 @@ -1708,12 +1708,12 @@ define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4036(<4 x i3 ; ; GFX1200-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4036 @@ -1747,12 +1747,12 @@ define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset_add_4036(<4 x i3 ; ; GFX1250-LABEL: name: s_buffer_load_v16f32_vgpr_offset_add_4036 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4036 @@ -1838,14 +1838,14 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc(<4 x i32> %rsrc, i32 inreg % ; ; GFX1200_1250-LABEL: name: s_buffer_load_f32_vgpr_rsrc ; GFX1200_1250: bb.1 (%ir-block.0): - ; GFX1200_1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200_1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200_1250-NEXT: {{ $}} ; GFX1200_1250-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200_1250-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1 ; GFX1200_1250-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2 ; GFX1200_1250-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3 ; GFX1200_1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200_1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 ; GFX1200_1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[COPY4]](i32) ; GFX1200_1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 ; GFX1200_1250-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 @@ -1935,14 +1935,14 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> % ; ; GFX1200-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4092 ; GFX1200-NEXT: [[ADD:%[0-9]+]]:sgpr(i32) = G_ADD [[COPY4]], [[C]] ; GFX1200-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 @@ -1981,14 +1981,14 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4092(<4 x i32> % ; ; GFX1250-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4092 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4092 ; GFX1250-NEXT: [[ADD:%[0-9]+]]:sgpr(i32) = G_ADD [[COPY4]], [[C]] ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[ADD]](i32) @@ -2083,14 +2083,14 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> % ; ; GFX1200-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4096 ; GFX1200-NEXT: [[ADD:%[0-9]+]]:sgpr(i32) = G_ADD [[COPY4]], [[C]] ; GFX1200-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 @@ -2129,14 +2129,14 @@ define amdgpu_ps float @s_buffer_load_f32_vgpr_rsrc_soffset_add_4096(<4 x i32> % ; ; GFX1250-LABEL: name: s_buffer_load_f32_vgpr_rsrc_soffset_add_4096 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4096 ; GFX1250-NEXT: [[ADD:%[0-9]+]]:sgpr(i32) = G_ADD [[COPY4]], [[C]] ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[ADD]](i32) @@ -2431,14 +2431,14 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> % ; ; GFX1200-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4064 ; GFX1200-NEXT: [[ADD:%[0-9]+]]:sgpr(i32) = G_ADD [[COPY4]], [[C]] ; GFX1200-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 @@ -2486,14 +2486,14 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4064(<4 x i32> % ; ; GFX1250-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4064 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4064 ; GFX1250-NEXT: [[ADD:%[0-9]+]]:sgpr(i32) = G_ADD [[COPY4]], [[C]] ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[ADD]](i32) @@ -2607,14 +2607,14 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> % ; ; GFX1200-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4068 ; GFX1200-NEXT: [[ADD:%[0-9]+]]:sgpr(i32) = G_ADD [[COPY4]], [[C]] ; GFX1200-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 @@ -2662,14 +2662,14 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4068(<4 x i32> % ; ; GFX1250-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4068 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4068 ; GFX1250-NEXT: [[ADD:%[0-9]+]]:sgpr(i32) = G_ADD [[COPY4]], [[C]] ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[ADD]](i32) @@ -2781,14 +2781,14 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> % ; ; GFX1200-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096 ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1200-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1200-NEXT: {{ $}} ; GFX1200-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1 ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2 ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4096 ; GFX1200-NEXT: [[ADD:%[0-9]+]]:sgpr(i32) = G_ADD [[COPY4]], [[C]] ; GFX1200-NEXT: [[C1:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 @@ -2836,14 +2836,14 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_rsrc_add_4096(<4 x i32> % ; ; GFX1250-LABEL: name: s_buffer_load_v8f32_vgpr_rsrc_add_4096 ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $vgpr0, $vgpr1, $vgpr2, $vgpr3 + ; GFX1250-NEXT: liveins: $sgpr0, $vgpr0, $vgpr1, $vgpr2, $vgpr3 ; GFX1250-NEXT: {{ $}} ; GFX1250-NEXT: [[COPY:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:vgpr(i32) = COPY $vgpr1 ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:vgpr(i32) = COPY $vgpr2 ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:vgpr(i32) = COPY $vgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:vgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) - ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 4096 ; GFX1250-NEXT: [[ADD:%[0-9]+]]:sgpr(i32) = G_ADD [[COPY4]], [[C]] ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:vgpr(i32) = COPY [[ADD]](i32) @@ -3554,15 +3554,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr(<4 x i32> inreg % ; ; GFX1200-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32) ; GFX1200-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY6]] ; GFX1200-NEXT: [[C:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 @@ -3573,15 +3573,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr(<4 x i32> inreg % ; ; GFX1250-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32) ; GFX1250-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY6]] ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 @@ -3617,15 +3617,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr(<4 x i32> inreg % ; ; GFX1200-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32) ; GFX1200-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY6]], [[COPY4]] ; GFX1200-NEXT: [[C:%[0-9]+]]:vgpr(i32) = G_CONSTANT i32 0 @@ -3636,15 +3636,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr(<4 x i32> inreg % ; ; GFX1250-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32) ; GFX1250-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY6]], [[COPY4]] ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 0 @@ -3684,15 +3684,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr_imm(<4 x i32> inr ; ; GFX1200-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32) ; GFX1200-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY6]] ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 1024 @@ -3707,15 +3707,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_vgpr_sgpr_imm(<4 x i32> inr ; ; GFX1250-LABEL: name: s_buffer_load_f32_offset_add_vgpr_sgpr_imm ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32) ; GFX1250-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY6]] ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 1024 @@ -3759,15 +3759,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr_imm(<4 x i32> inr ; ; GFX1200-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32) ; GFX1200-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY6]], [[COPY4]] ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 1024 @@ -3782,15 +3782,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_sgpr_vgpr_imm(<4 x i32> inr ; ; GFX1250-LABEL: name: s_buffer_load_f32_offset_add_sgpr_vgpr_imm ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32) ; GFX1250-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY6]], [[COPY4]] ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 1024 @@ -3835,15 +3835,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_sgpr_vgpr(<4 x i32> inr ; ; GFX1200-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32) ; GFX1200-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY6]], [[COPY4]] ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 1024 @@ -3858,15 +3858,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_sgpr_vgpr(<4 x i32> inr ; ; GFX1250-LABEL: name: s_buffer_load_f32_offset_add_imm_sgpr_vgpr ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32) ; GFX1250-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY6]], [[COPY4]] ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 1024 @@ -3910,15 +3910,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_vgpr_sgpr(<4 x i32> inr ; ; GFX1200-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr ; GFX1200: bb.1 (%ir-block.0): - ; GFX1200-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1200-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1200-NEXT: {{ $}} - ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1200-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1200-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1200-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1200-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1200-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1200-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 - ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1200-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1200-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32) ; GFX1200-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY6]] ; GFX1200-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 1024 @@ -3933,15 +3933,15 @@ define amdgpu_ps float @s_buffer_load_f32_offset_add_imm_vgpr_sgpr(<4 x i32> inr ; ; GFX1250-LABEL: name: s_buffer_load_f32_offset_add_imm_vgpr_sgpr ; GFX1250: bb.1 (%ir-block.0): - ; GFX1250-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $sgpr6, $vgpr0 + ; GFX1250-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $sgpr4, $vgpr0 ; GFX1250-NEXT: {{ $}} - ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 - ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 - ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 - ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr5 + ; GFX1250-NEXT: [[COPY:%[0-9]+]]:sgpr(i32) = COPY $sgpr0 + ; GFX1250-NEXT: [[COPY1:%[0-9]+]]:sgpr(i32) = COPY $sgpr1 + ; GFX1250-NEXT: [[COPY2:%[0-9]+]]:sgpr(i32) = COPY $sgpr2 + ; GFX1250-NEXT: [[COPY3:%[0-9]+]]:sgpr(i32) = COPY $sgpr3 ; GFX1250-NEXT: [[BUILD_VECTOR:%[0-9]+]]:sgpr(<4 x i32>) = G_BUILD_VECTOR [[COPY]](i32), [[COPY1]](i32), [[COPY2]](i32), [[COPY3]](i32) ; GFX1250-NEXT: [[COPY4:%[0-9]+]]:vgpr(i32) = COPY $vgpr0 - ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr6 + ; GFX1250-NEXT: [[COPY5:%[0-9]+]]:sgpr(i32) = COPY $sgpr4 ; GFX1250-NEXT: [[COPY6:%[0-9]+]]:vgpr(i32) = COPY [[COPY5]](i32) ; GFX1250-NEXT: [[ADD:%[0-9]+]]:vgpr(i32) = G_ADD [[COPY4]], [[COPY6]] ; GFX1250-NEXT: [[C:%[0-9]+]]:sgpr(i32) = G_CONSTANT i32 1024 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll index 43351a82178799..dbaef607d0e11f 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/true16-merge-values-s16.ll @@ -5,10 +5,10 @@ define amdgpu_ps i48 @test_merge_values_sgpr(<3 x i16> inreg %src0, <3 x i16> inreg %src1) { ; GFX11-LABEL: test_merge_values_sgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: s_mov_b64 s[0:1], -1 +; GFX11-NEXT: s_mov_b64 s[4:5], -1 ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX11-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] -; GFX11-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1] +; GFX11-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX11-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX11-NEXT: s_lshr_b32 s2, s0, 16 ; GFX11-NEXT: s_pack_ll_b32_b16 s0, s0, s2 @@ -16,10 +16,10 @@ define amdgpu_ps i48 @test_merge_values_sgpr(<3 x i16> inreg %src0, <3 x i16> in ; ; GFX12-LABEL: test_merge_values_sgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b64 s[0:1], -1 +; GFX12-NEXT: s_mov_b64 s[4:5], -1 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX12-NEXT: s_xor_b64 s[0:1], s[4:5], s[0:1] -; GFX12-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1] +; GFX12-NEXT: s_xor_b64 s[2:3], s[2:3], s[4:5] +; GFX12-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) ; GFX12-NEXT: s_lshr_b32 s2, s0, 16 ; GFX12-NEXT: s_pack_ll_b32_b16 s0, s0, s2 diff --git a/llvm/test/CodeGen/AMDGPU/add3.ll b/llvm/test/CodeGen/AMDGPU/add3.ll index 575ace3784fb6c..eaeb777daad9fa 100644 --- a/llvm/test/CodeGen/AMDGPU/add3.ll +++ b/llvm/test/CodeGen/AMDGPU/add3.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgpu8.03-amd-mesa3d | FileCheck -check-prefix=VI %s ; RUN: llc < %s -mtriple=amdgpu9.00-amd-mesa3d | FileCheck -check-prefix=GFX9 %s -; RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefix=GFX10 %s -; RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s +; RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefixes=GFX10P,GFX10 %s +; RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX10P,GFX11 %s ; =================================================================================== ; V_ADD3_U32 @@ -20,10 +20,10 @@ define amdgpu_ps float @add3(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_add3_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: add3: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: add3: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_add3_u32 v0, v0, v1, v2 +; GFX10P-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -44,11 +44,11 @@ define amdgpu_ps float @mad_no_add3(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e) { ; GFX9-NEXT: v_mad_u32_u24 v0, v2, v3, v0 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: mad_no_add3: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_mad_u32_u24 v0, v0, v1, v4 -; GFX10-NEXT: v_mad_u32_u24 v0, v2, v3, v0 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: mad_no_add3: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_mad_u32_u24 v0, v0, v1, v4 +; GFX10P-NEXT: v_mad_u32_u24 v0, v2, v3, v0 +; GFX10P-NEXT: ; return to shader part epilog %a0 = shl i32 %a, 8 %a1 = lshr i32 %a0, 8 %b0 = shl i32 %b, 8 @@ -87,6 +87,11 @@ define amdgpu_ps float @add3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_add3_u32 v0, s3, s2, v0 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: add3_vgpr_b: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_add3_u32 v0, s1, s0, v0 +; GFX11-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -105,10 +110,10 @@ define amdgpu_ps float @add3_vgpr_all2(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_add3_u32 v0, v1, v2, v0 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: add3_vgpr_all2: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_add3_u32 v0, v1, v2, v0 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: add3_vgpr_all2: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_add3_u32 v0, v1, v2, v0 +; GFX10P-NEXT: ; return to shader part epilog %x = add i32 %b, %c %result = add i32 %a, %x %bc = bitcast i32 %result to float @@ -131,6 +136,11 @@ define amdgpu_ps float @add3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_add3_u32 v0, s2, v0, v1 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: add3_vgpr_bc: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_add3_u32 v0, s0, v0, v1 +; GFX11-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -149,10 +159,10 @@ define amdgpu_ps float @add3_vgpr_const(i32 %a, i32 %b) { ; GFX9-NEXT: v_add3_u32 v0, v0, v1, 16 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: add3_vgpr_const: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_add3_u32 v0, v0, v1, 16 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: add3_vgpr_const: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_add3_u32 v0, v0, v1, 16 +; GFX10P-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = add i32 %x, 16 %bc = bitcast i32 %result to float @@ -173,11 +183,11 @@ define amdgpu_ps <2 x float> @add3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x ; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: add3_multiuse_outer: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_add3_u32 v0, v0, v1, v2 -; GFX10-NEXT: v_mul_lo_u32 v1, v0, v3 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: add3_multiuse_outer: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_add3_u32 v0, v0, v1, v2 +; GFX10P-NEXT: v_mul_lo_u32 v1, v0, v3 +; GFX10P-NEXT: ; return to shader part epilog %inner = add i32 %a, %b %outer = add i32 %inner, %c %x1 = mul i32 %outer, %x @@ -200,11 +210,11 @@ define amdgpu_ps <2 x float> @add3_multiuse_inner(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_add_u32_e32 v1, v0, v2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: add3_multiuse_inner: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 -; GFX10-NEXT: v_add_nc_u32_e32 v1, v0, v2 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: add3_multiuse_inner: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_add_nc_u32_e32 v0, v0, v1 +; GFX10P-NEXT: v_add_nc_u32_e32 v1, v0, v2 +; GFX10P-NEXT: ; return to shader part epilog %inner = add i32 %a, %b %outer = add i32 %inner, %c %r1 = insertelement <2 x i32> poison, i32 %inner, i32 0 @@ -244,6 +254,15 @@ define amdgpu_ps float @add3_uniform_vgpr(float inreg %a, float inreg %b, float ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v1 ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: add3_uniform_vgpr: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.0 +; GFX11-NEXT: v_add_f32_e64 v1, s1, 2.0 +; GFX11-NEXT: v_add_f32_e64 v2, s2, 0x40400000 +; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v1 +; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v2 +; GFX11-NEXT: ; return to shader part epilog %a1 = fadd float %a, 1.0 %b2 = fadd float %b, 2.0 %c3 = fadd float %c, 3.0 diff --git a/llvm/test/CodeGen/AMDGPU/add_shl.ll b/llvm/test/CodeGen/AMDGPU/add_shl.ll index d6502febe5906d..975f8da621f155 100644 --- a/llvm/test/CodeGen/AMDGPU/add_shl.ll +++ b/llvm/test/CodeGen/AMDGPU/add_shl.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgpu8.03-amd-mesa3d | FileCheck -check-prefix=VI %s ; RUN: llc < %s -mtriple=amdgpu9.00-amd-mesa3d | FileCheck -check-prefix=GFX9 %s -; RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefix=GFX10 %s -; RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s +; RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefixes=GFX10P,GFX10 %s +; RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX10P,GFX11 %s ; =================================================================================== ; V_ADD_LSHL_U32 @@ -20,10 +20,10 @@ define amdgpu_ps float @add_shl(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: add_shl: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, v2 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: add_shl: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_add_lshl_u32 v0, v0, v1, v2 +; GFX10P-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = shl i32 %x, %c %bc = bitcast i32 %result to float @@ -47,6 +47,11 @@ define amdgpu_ps float @add_shl_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_add_lshl_u32 v0, s2, s3, v0 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: add_shl_vgpr_c: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_add_lshl_u32 v0, s0, s1, v0 +; GFX11-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = shl i32 %x, %c %bc = bitcast i32 %result to float @@ -69,6 +74,11 @@ define amdgpu_ps float @add_shl_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_add_lshl_u32 v0, v0, s2, v1 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: add_shl_vgpr_ac: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_add_lshl_u32 v0, v0, s0, v1 +; GFX11-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = shl i32 %x, %c %bc = bitcast i32 %result to float @@ -87,10 +97,10 @@ define amdgpu_ps float @add_shl_vgpr_const(i32 %a, i32 %b) { ; GFX9-NEXT: v_add_lshl_u32 v0, v0, v1, 9 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: add_shl_vgpr_const: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_add_lshl_u32 v0, v0, v1, 9 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: add_shl_vgpr_const: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_add_lshl_u32 v0, v0, v1, 9 +; GFX10P-NEXT: ; return to shader part epilog %x = add i32 %a, %b %result = shl i32 %x, 9 %bc = bitcast i32 %result to float @@ -110,10 +120,10 @@ define amdgpu_ps float @add_shl_vgpr_const_inline_const(i32 %a) { ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: add_shl_vgpr_const_inline_const: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x7e800 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: add_shl_vgpr_const_inline_const: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_lshl_add_u32 v0, v0, 9, 0x7e800 +; GFX10P-NEXT: ; return to shader part epilog %x = add i32 %a, 1012 %result = shl i32 %x, 9 %bc = bitcast i32 %result to float @@ -136,10 +146,10 @@ define amdgpu_ps float @add_shl_vgpr_inline_const_x2(i32 %a) { ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 9, v1 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: add_shl_vgpr_inline_const_x2: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_lshl_add_u32 v0, v0, 9, 0x600 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: add_shl_vgpr_inline_const_x2: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_lshl_add_u32 v0, v0, 9, 0x600 +; GFX10P-NEXT: ; return to shader part epilog %x = add i32 %a, 3 %result = shl i32 %x, 9 %bc = bitcast i32 %result to float diff --git a/llvm/test/CodeGen/AMDGPU/and_or.ll b/llvm/test/CodeGen/AMDGPU/and_or.ll index 5781e797cce3cc..a52d2ce3f5e28e 100644 --- a/llvm/test/CodeGen/AMDGPU/and_or.ll +++ b/llvm/test/CodeGen/AMDGPU/and_or.ll @@ -2,7 +2,7 @@ ;RUN: llc < %s -mtriple=amdgpu8.03-amd-mesa3d | FileCheck -check-prefix=VI %s ;RUN: llc < %s -mtriple=amdgpu9.00-amd-mesa3d | FileCheck -check-prefix=GFX9 %s ;RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefix=GFX10 %s -;RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s +;RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX11 %s ; =================================================================================== ; V_AND_OR_B32 @@ -24,6 +24,11 @@ define amdgpu_ps float @and_or(i32 %a, i32 %b, i32 %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_and_or_b32 v0, v0, v1, v2 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: and_or: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_and_or_b32 v0, v0, v1, v2 +; GFX11-NEXT: ; return to shader part epilog %x = and i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -48,6 +53,11 @@ define amdgpu_ps float @and_or_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_and_or_b32 v0, s2, v0, s3 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: and_or_vgpr_b: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_and_or_b32 v0, s0, v0, s1 +; GFX11-NEXT: ; return to shader part epilog %x = and i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -70,6 +80,11 @@ define amdgpu_ps float @and_or_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_and_or_b32 v0, v0, v1, s2 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: and_or_vgpr_ab: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_and_or_b32 v0, v0, v1, s0 +; GFX11-NEXT: ; return to shader part epilog %x = and i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -92,6 +107,11 @@ define amdgpu_ps float @and_or_vgpr_const(i32 %a, i32 %b) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_and_or_b32 v0, v0, 4, v1 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: and_or_vgpr_const: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_and_or_b32 v0, v0, 4, v1 +; GFX11-NEXT: ; return to shader part epilog %x = and i32 4, %a %result = or i32 %x, %b %bc = bitcast i32 %result to float @@ -115,6 +135,11 @@ define amdgpu_ps float @and_or_vgpr_const_inline_const(i32 %a) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_and_or_b32 v0, v0, 20, 0x808 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: and_or_vgpr_const_inline_const: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_and_or_b32 v0, v0, 20, 0x808 +; GFX11-NEXT: ; return to shader part epilog %x = and i32 20, %a %result = or i32 %x, 2056 %bc = bitcast i32 %result to float @@ -137,6 +162,11 @@ define amdgpu_ps float @and_or_vgpr_inline_const_x2(i32 %a) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_and_or_b32 v0, v0, 4, 1 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: and_or_vgpr_inline_const_x2: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_and_or_b32 v0, v0, 4, 1 +; GFX11-NEXT: ; return to shader part epilog %x = and i32 4, %a %result = or i32 %x, 1 %bc = bitcast i32 %result to float @@ -166,6 +196,13 @@ define <2 x i32> @v_and_or_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) { ; GFX10-NEXT: v_and_or_b32 v0, v0, v2, v4 ; GFX10-NEXT: v_and_or_b32 v1, v1, v3, v5 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_and_or_v2i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_and_or_b32 v0, v0, v2, v4 +; GFX11-NEXT: v_and_or_b32 v1, v1, v3, v5 +; GFX11-NEXT: s_setpc_b64 s[30:31] %x = and <2 x i32> %a, %b %result = or <2 x i32> %x, %c ret <2 x i32> %result @@ -194,9 +231,16 @@ define <2 x i32> @v_and_or_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> i ; GFX10-LABEL: v_and_or_v2i32_b: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-DAG: v_and_or_b32 v0, s{{[0-9]+}}, v0, s{{[0-9]+}} -; GFX10-DAG: v_and_or_b32 v1, s{{[0-9]+}}, v1, s{{[0-9]+}} +; GFX10-NEXT: v_and_or_b32 v0, s16, v0, s18 +; GFX10-NEXT: v_and_or_b32 v1, s17, v1, s19 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_and_or_v2i32_b: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_and_or_b32 v0, s0, v0, s2 +; GFX11-NEXT: v_and_or_b32 v1, s1, v1, s3 +; GFX11-NEXT: s_setpc_b64 s[30:31] %x = and <2 x i32> %a, %b %result = or <2 x i32> %x, %c ret <2 x i32> %result @@ -222,9 +266,16 @@ define <2 x i32> @v_and_or_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg ; GFX10-LABEL: v_and_or_v2i32_ab: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-DAG: v_and_or_b32 v1, v1, v3, {{s[0-9]+}} -; GFX10-DAG: v_and_or_b32 v0, v0, v2, {{s[0-9]+}} +; GFX10-NEXT: v_and_or_b32 v0, v0, v2, s16 +; GFX10-NEXT: v_and_or_b32 v1, v1, v3, s17 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_and_or_v2i32_ab: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_and_or_b32 v0, v0, v2, s0 +; GFX11-NEXT: v_and_or_b32 v1, v1, v3, s1 +; GFX11-NEXT: s_setpc_b64 s[30:31] %x = and <2 x i32> %a, %b %result = or <2 x i32> %x, %c ret <2 x i32> %result @@ -253,6 +304,13 @@ define <2 x i32> @v_and_or_v2i32_const(<2 x i32> %a, <2 x i32> %b) { ; GFX10-NEXT: v_and_or_b32 v0, v0, 4, v2 ; GFX10-NEXT: v_and_or_b32 v1, v1, 16, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_and_or_v2i32_const: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_and_or_b32 v0, v0, 4, v2 +; GFX11-NEXT: v_and_or_b32 v1, v1, 16, v3 +; GFX11-NEXT: s_setpc_b64 s[30:31] %x = and <2 x i32> %a, %result = or <2 x i32> %x, %b ret <2 x i32> %result @@ -283,6 +341,13 @@ define <2 x i32> @v_and_or_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) { ; GFX10-NEXT: v_and_or_b32 v0, v0, 0x808, v2 ; GFX10-NEXT: v_and_or_b32 v1, v1, 0x809, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_and_or_v2i32_inline_const: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_and_or_b32 v0, v0, 0x808, v2 +; GFX11-NEXT: v_and_or_b32 v1, v1, 0x809, v3 +; GFX11-NEXT: s_setpc_b64 s[30:31] %x = and <2 x i32> %a, %result = or <2 x i32> %x, %b ret <2 x i32> %result @@ -313,6 +378,13 @@ define <2 x i32> @v_and_or_v2i32_inline_const_x2(<2 x i32> %a) { ; GFX10-NEXT: v_and_or_b32 v0, v0, 0x808, 4 ; GFX10-NEXT: v_and_or_b32 v1, v1, 0x809, 16 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_and_or_v2i32_inline_const_x2: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_and_or_b32 v0, v0, 0x808, 4 +; GFX11-NEXT: v_and_or_b32 v1, v1, 0x809, 16 +; GFX11-NEXT: s_setpc_b64 s[30:31] %x = and <2 x i32> %a, %result = or <2 x i32> %x, ret <2 x i32> %result @@ -340,9 +412,18 @@ define <2 x i32> @v_and_or_v2i32_inline_const_x3(<2 x i32> %a) { ; GFX10-LABEL: v_and_or_v2i32_inline_const_x3: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: s_movk_i32 [[SR:s[0-9]+]], 0x808 -; GFX10-DAG: v_and_or_b32 v0, v0, [[SR]], 0x81 -; GFX10-DAG: v_and_or_b32 v1, v1, 0x809, 16 +; GFX10-NEXT: s_movk_i32 s4, 0x808 +; GFX10-NEXT: v_and_or_b32 v1, v1, 0x809, 16 +; GFX10-NEXT: v_and_or_b32 v0, v0, s4, 0x81 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_and_or_v2i32_inline_const_x3: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_movk_i32 s0, 0x808 +; GFX11-NEXT: v_and_or_b32 v1, v1, 0x809, 16 +; GFX11-NEXT: v_and_or_b32 v0, v0, s0, 0x81 +; GFX11-NEXT: s_setpc_b64 s[30:31] %x = and <2 x i32> %a, %result = or <2 x i32> %x, ret <2 x i32> %result @@ -370,11 +451,20 @@ define <2 x i32> @v_and_or_v2i32_inline_const_x4(<2 x i32> %a) { ; GFX10-LABEL: v_and_or_v2i32_inline_const_x4: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-DAG: s_movk_i32 [[SR0:s[0-9]+]], 0x808 -; GFX10-DAG: s_movk_i32 [[SR1:s[0-9]+]], 0x809 -; GFX10-DAG: v_and_or_b32 v0, v0, [[SR0]], 0x81 -; GFX10-DAG: v_and_or_b32 v1, v1, [[SR1]], 0x101 +; GFX10-NEXT: s_movk_i32 s4, 0x808 +; GFX10-NEXT: s_movk_i32 s5, 0x809 +; GFX10-NEXT: v_and_or_b32 v0, v0, s4, 0x81 +; GFX10-NEXT: v_and_or_b32 v1, v1, s5, 0x101 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_and_or_v2i32_inline_const_x4: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: s_movk_i32 s0, 0x808 +; GFX11-NEXT: s_movk_i32 s1, 0x809 +; GFX11-NEXT: v_and_or_b32 v0, v0, s0, 0x81 +; GFX11-NEXT: v_and_or_b32 v1, v1, s1, 0x101 +; GFX11-NEXT: s_setpc_b64 s[30:31] %x = and <2 x i32> %a, %result = or <2 x i32> %x, ret <2 x i32> %result @@ -413,6 +503,17 @@ define <2 x i32> @v_and_or_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> ; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 ; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 ; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_and_or_v2i32_multi_use: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_and_b32_e32 v0, v0, v2 +; GFX11-NEXT: v_and_b32_e32 v1, v1, v3 +; GFX11-NEXT: v_or_b32_e32 v2, v0, v4 +; GFX11-NEXT: v_or_b32_e32 v3, v1, v5 +; GFX11-NEXT: v_add_nc_u32_e32 v0, v0, v2 +; GFX11-NEXT: v_add_nc_u32_e32 v1, v1, v3 +; GFX11-NEXT: s_setpc_b64 s[30:31] %x = and <2 x i32> %a, %b %y = or <2 x i32> %x, %c %result = add <2 x i32> %x, %y @@ -437,6 +538,12 @@ define amdgpu_ps <2 x i32> @s_and_or_v2i32(<2 x i32> inreg %a, <2 x i32> inreg % ; GFX10-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5] ; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[6:7] ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_and_or_v2i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] +; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] +; GFX11-NEXT: ; return to shader part epilog %x = and <2 x i32> %a, %b %result = or <2 x i32> %x, %c ret <2 x i32> %result diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll index a4855ef423e5ed..14eada25c1f646 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-atomics.ll @@ -16,7 +16,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_swap_b32 v[0:1], v2 scope:SCOPE_DEV @@ -31,7 +31,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -47,7 +47,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap v[0:1], v2 @@ -57,7 +57,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; ; GFX950-GISEL-LABEL: flat_xchg_saddr_i32_nortn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -83,7 +83,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn_offset_2047(ptr inreg %sbase, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_swap_b32 v[0:1], v2 offset:2047 scope:SCOPE_DEV @@ -98,7 +98,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn_offset_2047(ptr inreg %sbase, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -114,7 +114,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn_offset_2047(ptr inreg %sbase, i ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap v[0:1], v2 offset:2047 @@ -124,7 +124,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn_offset_2047(ptr inreg %sbase, i ; ; GFX950-GISEL-LABEL: flat_xchg_saddr_i32_nortn_offset_2047: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -151,7 +151,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn_offset_neg2048(ptr inreg %sbase ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_swap_b32 v[0:1], v2 offset:-2048 scope:SCOPE_DEV @@ -166,7 +166,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn_offset_neg2048(ptr inreg %sbase ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -182,7 +182,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn_offset_neg2048(ptr inreg %sbase ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff800, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -195,7 +195,7 @@ define amdgpu_ps void @flat_xchg_saddr_i32_nortn_offset_neg2048(ptr inreg %sbase ; ; GFX950-GISEL-LABEL: flat_xchg_saddr_i32_nortn_offset_neg2048: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -224,7 +224,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_DEV @@ -239,7 +239,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -255,7 +255,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap v0, v[0:1], v2 sc0 @@ -265,7 +265,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, ; ; GFX950-GISEL-LABEL: flat_xchg_saddr_i32_rtn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -291,7 +291,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn_2048(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 offset:2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV @@ -306,7 +306,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn_2048(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -322,7 +322,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn_2048(ptr inreg %sbase, i32 %voff ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_swap v0, v[0:1], v2 offset:2048 sc0 @@ -332,7 +332,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn_2048(ptr inreg %sbase, i32 %voff ; ; GFX950-GISEL-LABEL: flat_xchg_saddr_i32_rtn_2048: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -359,7 +359,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn_neg2048(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_swap_b32 v0, v[0:1], v2 offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV @@ -374,7 +374,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn_neg2048(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -390,7 +390,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn_neg2048(ptr inreg %sbase, i32 %v ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xfffff800, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -403,7 +403,7 @@ define amdgpu_ps float @flat_xchg_saddr_i32_rtn_neg2048(ptr inreg %sbase, i32 %v ; ; GFX950-GISEL-LABEL: flat_xchg_saddr_i32_rtn_neg2048: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -752,7 +752,7 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0 @@ -797,7 +797,7 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -844,9 +844,9 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn(ptr inreg %sbase, i32 %vof ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -882,13 +882,13 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn(ptr inreg %sbase, i32 %vof ; GFX950-GISEL-LABEL: flat_xchg_saddr_i64_rtn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -936,9 +936,10 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn_neg128(ptr inreg %sbase, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 @@ -985,7 +986,7 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn_neg128(ptr inreg %sbase, i ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v3, vcc_lo @@ -1035,12 +1036,12 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn_neg128(ptr inreg %sbase, i ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -1076,16 +1077,16 @@ define amdgpu_ps <2 x float> @flat_xchg_saddr_i64_rtn_neg128(ptr inreg %sbase, i ; GFX950-GISEL-LABEL: flat_xchg_saddr_i64_rtn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -1134,9 +1135,9 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4 @@ -1173,7 +1174,7 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -1212,9 +1213,9 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB12_3 @@ -1243,12 +1244,12 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-LABEL: flat_xchg_saddr_i64_nortn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB12_3 @@ -1288,9 +1289,10 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -1329,7 +1331,7 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -1371,12 +1373,12 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB13_3 @@ -1405,16 +1407,16 @@ define amdgpu_ps void @flat_xchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX950-GISEL-LABEL: flat_xchg_saddr_i64_nortn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB13_3 @@ -1459,7 +1461,7 @@ define amdgpu_ps float @flat_add_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_add_u32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_DEV @@ -1474,7 +1476,7 @@ define amdgpu_ps float @flat_add_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -1490,7 +1492,7 @@ define amdgpu_ps float @flat_add_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_add v0, v[0:1], v2 sc0 @@ -1500,7 +1502,7 @@ define amdgpu_ps float @flat_add_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; ; GFX950-GISEL-LABEL: flat_add_saddr_i32_rtn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -1526,7 +1528,7 @@ define amdgpu_ps float @flat_add_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_add_u32 v0, v[0:1], v2 offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV @@ -1541,7 +1543,7 @@ define amdgpu_ps float @flat_add_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -1557,7 +1559,7 @@ define amdgpu_ps float @flat_add_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -1570,7 +1572,7 @@ define amdgpu_ps float @flat_add_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; ; GFX950-GISEL-LABEL: flat_add_saddr_i32_rtn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -1600,7 +1602,7 @@ define amdgpu_ps void @flat_add_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_add_u32 v[0:1], v2 scope:SCOPE_DEV @@ -1615,7 +1617,7 @@ define amdgpu_ps void @flat_add_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -1631,7 +1633,7 @@ define amdgpu_ps void @flat_add_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_add v[0:1], v2 @@ -1641,7 +1643,7 @@ define amdgpu_ps void @flat_add_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; ; GFX950-GISEL-LABEL: flat_add_saddr_i32_nortn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -1666,7 +1668,7 @@ define amdgpu_ps void @flat_add_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_add_u32 v[0:1], v2 offset:-128 scope:SCOPE_DEV @@ -1681,7 +1683,7 @@ define amdgpu_ps void @flat_add_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -1697,7 +1699,7 @@ define amdgpu_ps void @flat_add_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -1710,7 +1712,7 @@ define amdgpu_ps void @flat_add_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; ; GFX950-GISEL-LABEL: flat_add_saddr_i32_nortn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -1740,7 +1742,7 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0 @@ -1786,7 +1788,7 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -1834,9 +1836,9 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -1873,13 +1875,13 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-GISEL-LABEL: flat_add_saddr_i64_rtn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -1930,9 +1932,10 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 @@ -1980,7 +1983,7 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v3, vcc_lo @@ -2031,12 +2034,12 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -2073,16 +2076,16 @@ define amdgpu_ps <2 x float> @flat_add_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-GISEL-LABEL: flat_add_saddr_i64_rtn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -2134,9 +2137,9 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4 @@ -2176,7 +2179,7 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -2218,9 +2221,9 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB20_3 @@ -2252,12 +2255,12 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-LABEL: flat_add_saddr_i64_nortn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB20_3 @@ -2302,9 +2305,10 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -2346,7 +2350,7 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -2391,12 +2395,12 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB21_3 @@ -2428,16 +2432,16 @@ define amdgpu_ps void @flat_add_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-LABEL: flat_add_saddr_i64_nortn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB21_3 @@ -2487,7 +2491,7 @@ define amdgpu_ps float @flat_sub_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_sub_u32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_DEV @@ -2502,7 +2506,7 @@ define amdgpu_ps float @flat_sub_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -2518,7 +2522,7 @@ define amdgpu_ps float @flat_sub_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_sub v0, v[0:1], v2 sc0 @@ -2528,7 +2532,7 @@ define amdgpu_ps float @flat_sub_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; ; GFX950-GISEL-LABEL: flat_sub_saddr_i32_rtn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -2554,7 +2558,7 @@ define amdgpu_ps float @flat_sub_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_sub_u32 v0, v[0:1], v2 offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV @@ -2569,7 +2573,7 @@ define amdgpu_ps float @flat_sub_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -2585,7 +2589,7 @@ define amdgpu_ps float @flat_sub_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -2598,7 +2602,7 @@ define amdgpu_ps float @flat_sub_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; ; GFX950-GISEL-LABEL: flat_sub_saddr_i32_rtn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -2628,7 +2632,7 @@ define amdgpu_ps void @flat_sub_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_sub_u32 v[0:1], v2 scope:SCOPE_DEV @@ -2643,7 +2647,7 @@ define amdgpu_ps void @flat_sub_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -2659,7 +2663,7 @@ define amdgpu_ps void @flat_sub_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_sub v[0:1], v2 @@ -2669,7 +2673,7 @@ define amdgpu_ps void @flat_sub_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; ; GFX950-GISEL-LABEL: flat_sub_saddr_i32_nortn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -2694,7 +2698,7 @@ define amdgpu_ps void @flat_sub_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_sub_u32 v[0:1], v2 offset:-128 scope:SCOPE_DEV @@ -2709,7 +2713,7 @@ define amdgpu_ps void @flat_sub_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -2725,7 +2729,7 @@ define amdgpu_ps void @flat_sub_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -2738,7 +2742,7 @@ define amdgpu_ps void @flat_sub_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; ; GFX950-GISEL-LABEL: flat_sub_saddr_i32_nortn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -2768,7 +2772,7 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0 @@ -2814,7 +2818,7 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -2862,9 +2866,9 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -2903,13 +2907,13 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-GISEL-LABEL: flat_sub_saddr_i64_rtn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -2960,9 +2964,10 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 @@ -3010,7 +3015,7 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v3, vcc_lo @@ -3061,12 +3066,12 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -3105,16 +3110,16 @@ define amdgpu_ps <2 x float> @flat_sub_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-GISEL-LABEL: flat_sub_saddr_i64_rtn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -3166,9 +3171,9 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4 @@ -3208,7 +3213,7 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -3250,9 +3255,9 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB28_3 @@ -3286,12 +3291,12 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-LABEL: flat_sub_saddr_i64_nortn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB28_3 @@ -3336,9 +3341,10 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -3380,7 +3386,7 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -3425,12 +3431,12 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB29_3 @@ -3464,16 +3470,16 @@ define amdgpu_ps void @flat_sub_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-LABEL: flat_sub_saddr_i64_nortn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB29_3 @@ -3523,7 +3529,7 @@ define amdgpu_ps float @flat_and_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_and_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_DEV @@ -3538,7 +3544,7 @@ define amdgpu_ps float @flat_and_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3554,7 +3560,7 @@ define amdgpu_ps float @flat_and_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_and v0, v[0:1], v2 sc0 @@ -3564,7 +3570,7 @@ define amdgpu_ps float @flat_and_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; ; GFX950-GISEL-LABEL: flat_and_saddr_i32_rtn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -3590,7 +3596,7 @@ define amdgpu_ps float @flat_and_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_and_b32 v0, v[0:1], v2 offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV @@ -3605,7 +3611,7 @@ define amdgpu_ps float @flat_and_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3621,7 +3627,7 @@ define amdgpu_ps float @flat_and_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -3634,7 +3640,7 @@ define amdgpu_ps float @flat_and_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; ; GFX950-GISEL-LABEL: flat_and_saddr_i32_rtn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -3664,7 +3670,7 @@ define amdgpu_ps void @flat_and_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_and_b32 v[0:1], v2 scope:SCOPE_DEV @@ -3679,7 +3685,7 @@ define amdgpu_ps void @flat_and_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3695,7 +3701,7 @@ define amdgpu_ps void @flat_and_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_and v[0:1], v2 @@ -3705,7 +3711,7 @@ define amdgpu_ps void @flat_and_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; ; GFX950-GISEL-LABEL: flat_and_saddr_i32_nortn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -3730,7 +3736,7 @@ define amdgpu_ps void @flat_and_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_and_b32 v[0:1], v2 offset:-128 scope:SCOPE_DEV @@ -3745,7 +3751,7 @@ define amdgpu_ps void @flat_and_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3761,7 +3767,7 @@ define amdgpu_ps void @flat_and_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -3774,7 +3780,7 @@ define amdgpu_ps void @flat_and_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; ; GFX950-GISEL-LABEL: flat_and_saddr_i32_nortn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -3804,7 +3810,7 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0 @@ -3851,7 +3857,7 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3900,9 +3906,9 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -3940,13 +3946,13 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-GISEL-LABEL: flat_and_saddr_i64_rtn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -3996,9 +4002,10 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 @@ -4047,7 +4054,7 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v3, vcc_lo @@ -4099,12 +4106,12 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -4142,16 +4149,16 @@ define amdgpu_ps <2 x float> @flat_and_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-GISEL-LABEL: flat_and_saddr_i64_rtn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -4202,9 +4209,9 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4 @@ -4245,7 +4252,7 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -4288,9 +4295,9 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB36_3 @@ -4323,12 +4330,12 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-LABEL: flat_and_saddr_i64_nortn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB36_3 @@ -4372,9 +4379,10 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -4417,7 +4425,7 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -4463,12 +4471,12 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB37_3 @@ -4501,16 +4509,16 @@ define amdgpu_ps void @flat_and_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-LABEL: flat_and_saddr_i64_nortn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB37_3 @@ -4559,7 +4567,7 @@ define amdgpu_ps float @flat_or_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i3 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_or_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_DEV @@ -4574,7 +4582,7 @@ define amdgpu_ps float @flat_or_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i3 ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4590,7 +4598,7 @@ define amdgpu_ps float @flat_or_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i3 ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_or v0, v[0:1], v2 sc0 @@ -4600,7 +4608,7 @@ define amdgpu_ps float @flat_or_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i3 ; ; GFX950-GISEL-LABEL: flat_or_saddr_i32_rtn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -4626,7 +4634,7 @@ define amdgpu_ps float @flat_or_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_or_b32 v0, v[0:1], v2 offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV @@ -4641,7 +4649,7 @@ define amdgpu_ps float @flat_or_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4657,7 +4665,7 @@ define amdgpu_ps float @flat_or_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %voff ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -4670,7 +4678,7 @@ define amdgpu_ps float @flat_or_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %voff ; ; GFX950-GISEL-LABEL: flat_or_saddr_i32_rtn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -4700,7 +4708,7 @@ define amdgpu_ps void @flat_or_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_or_b32 v[0:1], v2 scope:SCOPE_DEV @@ -4715,7 +4723,7 @@ define amdgpu_ps void @flat_or_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4731,7 +4739,7 @@ define amdgpu_ps void @flat_or_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_or v[0:1], v2 @@ -4741,7 +4749,7 @@ define amdgpu_ps void @flat_or_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, i ; ; GFX950-GISEL-LABEL: flat_or_saddr_i32_nortn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -4766,7 +4774,7 @@ define amdgpu_ps void @flat_or_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_or_b32 v[0:1], v2 offset:-128 scope:SCOPE_DEV @@ -4781,7 +4789,7 @@ define amdgpu_ps void @flat_or_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4797,7 +4805,7 @@ define amdgpu_ps void @flat_or_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -4810,7 +4818,7 @@ define amdgpu_ps void @flat_or_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vof ; ; GFX950-GISEL-LABEL: flat_or_saddr_i32_nortn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -4840,7 +4848,7 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn(ptr inreg %sbase, i32 %voffs ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0 @@ -4887,7 +4895,7 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn(ptr inreg %sbase, i32 %voffs ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4936,9 +4944,9 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn(ptr inreg %sbase, i32 %voffs ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -4976,13 +4984,13 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn(ptr inreg %sbase, i32 %voffs ; GFX950-GISEL-LABEL: flat_or_saddr_i64_rtn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -5032,9 +5040,10 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn_neg128(ptr inreg %sbase, i32 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 @@ -5083,7 +5092,7 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn_neg128(ptr inreg %sbase, i32 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v3, vcc_lo @@ -5135,12 +5144,12 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn_neg128(ptr inreg %sbase, i32 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -5178,16 +5187,16 @@ define amdgpu_ps <2 x float> @flat_or_saddr_i64_rtn_neg128(ptr inreg %sbase, i32 ; GFX950-GISEL-LABEL: flat_or_saddr_i64_rtn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -5238,9 +5247,9 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4 @@ -5281,7 +5290,7 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -5324,9 +5333,9 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB44_3 @@ -5359,12 +5368,12 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, i ; GFX950-GISEL-LABEL: flat_or_saddr_i64_nortn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB44_3 @@ -5408,9 +5417,10 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -5453,7 +5463,7 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -5499,12 +5509,12 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB45_3 @@ -5537,16 +5547,16 @@ define amdgpu_ps void @flat_or_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-GISEL-LABEL: flat_or_saddr_i64_nortn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB45_3 @@ -5595,7 +5605,7 @@ define amdgpu_ps float @flat_xor_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_xor_b32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_DEV @@ -5610,7 +5620,7 @@ define amdgpu_ps float @flat_xor_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -5626,7 +5636,7 @@ define amdgpu_ps float @flat_xor_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_xor v0, v[0:1], v2 sc0 @@ -5636,7 +5646,7 @@ define amdgpu_ps float @flat_xor_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; ; GFX950-GISEL-LABEL: flat_xor_saddr_i32_rtn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -5662,7 +5672,7 @@ define amdgpu_ps float @flat_xor_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_xor_b32 v0, v[0:1], v2 offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV @@ -5677,7 +5687,7 @@ define amdgpu_ps float @flat_xor_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -5693,7 +5703,7 @@ define amdgpu_ps float @flat_xor_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -5706,7 +5716,7 @@ define amdgpu_ps float @flat_xor_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; ; GFX950-GISEL-LABEL: flat_xor_saddr_i32_rtn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -5736,7 +5746,7 @@ define amdgpu_ps void @flat_xor_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_xor_b32 v[0:1], v2 scope:SCOPE_DEV @@ -5751,7 +5761,7 @@ define amdgpu_ps void @flat_xor_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -5767,7 +5777,7 @@ define amdgpu_ps void @flat_xor_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_xor v[0:1], v2 @@ -5777,7 +5787,7 @@ define amdgpu_ps void @flat_xor_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; ; GFX950-GISEL-LABEL: flat_xor_saddr_i32_nortn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -5802,7 +5812,7 @@ define amdgpu_ps void @flat_xor_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_xor_b32 v[0:1], v2 offset:-128 scope:SCOPE_DEV @@ -5817,7 +5827,7 @@ define amdgpu_ps void @flat_xor_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -5833,7 +5843,7 @@ define amdgpu_ps void @flat_xor_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -5846,7 +5856,7 @@ define amdgpu_ps void @flat_xor_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; ; GFX950-GISEL-LABEL: flat_xor_saddr_i32_nortn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -5876,7 +5886,7 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0 @@ -5923,7 +5933,7 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -5972,9 +5982,9 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -6012,13 +6022,13 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-GISEL-LABEL: flat_xor_saddr_i64_rtn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -6068,9 +6078,10 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 @@ -6119,7 +6130,7 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v3, vcc_lo @@ -6171,12 +6182,12 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -6214,16 +6225,16 @@ define amdgpu_ps <2 x float> @flat_xor_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-GISEL-LABEL: flat_xor_saddr_i64_rtn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -6274,9 +6285,9 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4 @@ -6317,7 +6328,7 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -6360,9 +6371,9 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB52_3 @@ -6395,12 +6406,12 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-LABEL: flat_xor_saddr_i64_nortn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB52_3 @@ -6444,9 +6455,10 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -6489,7 +6501,7 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -6535,12 +6547,12 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB53_3 @@ -6573,16 +6585,16 @@ define amdgpu_ps void @flat_xor_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-LABEL: flat_xor_saddr_i64_nortn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB53_3 @@ -6631,7 +6643,7 @@ define amdgpu_ps float @flat_max_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_max_i32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -6642,7 +6654,7 @@ define amdgpu_ps float @flat_max_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -6654,14 +6666,14 @@ define amdgpu_ps float @flat_max_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: flat_atomic_smax v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: ; return to shader part epilog ; ; GFX950-GISEL-LABEL: flat_max_saddr_i32_rtn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -6684,7 +6696,7 @@ define amdgpu_ps float @flat_max_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_max_i32 v0, v[0:1], v2 offset:-128 th:TH_ATOMIC_RETURN ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -6695,7 +6707,7 @@ define amdgpu_ps float @flat_max_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -6707,7 +6719,7 @@ define amdgpu_ps float @flat_max_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -6717,7 +6729,7 @@ define amdgpu_ps float @flat_max_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; ; GFX950-GISEL-LABEL: flat_max_saddr_i32_rtn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -6744,7 +6756,7 @@ define amdgpu_ps void @flat_max_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_max_i32 v[0:1], v2 ; GFX1250-SDAG-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: s_endpgm @@ -6755,7 +6767,7 @@ define amdgpu_ps void @flat_max_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -6767,14 +6779,14 @@ define amdgpu_ps void @flat_max_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: flat_atomic_smax v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0) ; GFX950-SDAG-NEXT: s_endpgm ; ; GFX950-GISEL-LABEL: flat_max_saddr_i32_nortn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -6796,7 +6808,7 @@ define amdgpu_ps void @flat_max_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_max_i32 v[0:1], v2 offset:-128 ; GFX1250-SDAG-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: s_endpgm @@ -6807,7 +6819,7 @@ define amdgpu_ps void @flat_max_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -6819,7 +6831,7 @@ define amdgpu_ps void @flat_max_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -6829,7 +6841,7 @@ define amdgpu_ps void @flat_max_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; ; GFX950-GISEL-LABEL: flat_max_saddr_i32_nortn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -6856,7 +6868,7 @@ define amdgpu_ps <2 x float> @flat_max_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0 @@ -6899,7 +6911,7 @@ define amdgpu_ps <2 x float> @flat_max_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -6944,9 +6956,9 @@ define amdgpu_ps <2 x float> @flat_max_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -6984,13 +6996,13 @@ define amdgpu_ps <2 x float> @flat_max_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-GISEL-LABEL: flat_max_saddr_i64_rtn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -7040,9 +7052,10 @@ define amdgpu_ps <2 x float> @flat_max_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 @@ -7087,7 +7100,7 @@ define amdgpu_ps <2 x float> @flat_max_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v3, vcc_lo @@ -7135,12 +7148,12 @@ define amdgpu_ps <2 x float> @flat_max_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -7178,16 +7191,16 @@ define amdgpu_ps <2 x float> @flat_max_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-GISEL-LABEL: flat_max_saddr_i64_rtn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -7238,9 +7251,9 @@ define amdgpu_ps void @flat_max_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4 @@ -7278,7 +7291,7 @@ define amdgpu_ps void @flat_max_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -7318,9 +7331,9 @@ define amdgpu_ps void @flat_max_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB60_3 @@ -7352,12 +7365,12 @@ define amdgpu_ps void @flat_max_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-LABEL: flat_max_saddr_i64_nortn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB60_3 @@ -7400,9 +7413,10 @@ define amdgpu_ps void @flat_max_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -7442,7 +7456,7 @@ define amdgpu_ps void @flat_max_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -7485,12 +7499,12 @@ define amdgpu_ps void @flat_max_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB61_3 @@ -7522,16 +7536,16 @@ define amdgpu_ps void @flat_max_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-LABEL: flat_max_saddr_i64_nortn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB61_3 @@ -7579,7 +7593,7 @@ define amdgpu_ps float @flat_min_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_min_i32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -7590,7 +7604,7 @@ define amdgpu_ps float @flat_min_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -7602,14 +7616,14 @@ define amdgpu_ps float @flat_min_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: flat_atomic_smin v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: ; return to shader part epilog ; ; GFX950-GISEL-LABEL: flat_min_saddr_i32_rtn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -7632,7 +7646,7 @@ define amdgpu_ps float @flat_min_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_min_i32 v0, v[0:1], v2 offset:-128 th:TH_ATOMIC_RETURN ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -7643,7 +7657,7 @@ define amdgpu_ps float @flat_min_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -7655,7 +7669,7 @@ define amdgpu_ps float @flat_min_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -7665,7 +7679,7 @@ define amdgpu_ps float @flat_min_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; ; GFX950-GISEL-LABEL: flat_min_saddr_i32_rtn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -7692,7 +7706,7 @@ define amdgpu_ps void @flat_min_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_min_i32 v[0:1], v2 ; GFX1250-SDAG-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: s_endpgm @@ -7703,7 +7717,7 @@ define amdgpu_ps void @flat_min_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -7715,14 +7729,14 @@ define amdgpu_ps void @flat_min_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: flat_atomic_smin v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0) ; GFX950-SDAG-NEXT: s_endpgm ; ; GFX950-GISEL-LABEL: flat_min_saddr_i32_nortn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -7744,7 +7758,7 @@ define amdgpu_ps void @flat_min_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_min_i32 v[0:1], v2 offset:-128 ; GFX1250-SDAG-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: s_endpgm @@ -7755,7 +7769,7 @@ define amdgpu_ps void @flat_min_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -7767,7 +7781,7 @@ define amdgpu_ps void @flat_min_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -7777,7 +7791,7 @@ define amdgpu_ps void @flat_min_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; ; GFX950-GISEL-LABEL: flat_min_saddr_i32_nortn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -7804,7 +7818,7 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0 @@ -7847,7 +7861,7 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -7892,9 +7906,9 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -7932,13 +7946,13 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-GISEL-LABEL: flat_min_saddr_i64_rtn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -7988,9 +8002,10 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 @@ -8035,7 +8050,7 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v3, vcc_lo @@ -8083,12 +8098,12 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -8126,16 +8141,16 @@ define amdgpu_ps <2 x float> @flat_min_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-GISEL-LABEL: flat_min_saddr_i64_rtn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -8186,9 +8201,9 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4 @@ -8226,7 +8241,7 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -8266,9 +8281,9 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB68_3 @@ -8300,12 +8315,12 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-LABEL: flat_min_saddr_i64_nortn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB68_3 @@ -8348,9 +8363,10 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -8390,7 +8406,7 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -8433,12 +8449,12 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB69_3 @@ -8470,16 +8486,16 @@ define amdgpu_ps void @flat_min_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-LABEL: flat_min_saddr_i64_nortn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB69_3 @@ -8527,7 +8543,7 @@ define amdgpu_ps float @flat_umax_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_max_u32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -8538,7 +8554,7 @@ define amdgpu_ps float @flat_umax_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -8550,14 +8566,14 @@ define amdgpu_ps float @flat_umax_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: flat_atomic_umax v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: ; return to shader part epilog ; ; GFX950-GISEL-LABEL: flat_umax_saddr_i32_rtn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -8580,7 +8596,7 @@ define amdgpu_ps float @flat_umax_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_max_u32 v0, v[0:1], v2 offset:-128 th:TH_ATOMIC_RETURN ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -8591,7 +8607,7 @@ define amdgpu_ps float @flat_umax_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -8603,7 +8619,7 @@ define amdgpu_ps float @flat_umax_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -8613,7 +8629,7 @@ define amdgpu_ps float @flat_umax_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vo ; ; GFX950-GISEL-LABEL: flat_umax_saddr_i32_rtn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -8640,7 +8656,7 @@ define amdgpu_ps void @flat_umax_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_max_u32 v[0:1], v2 ; GFX1250-SDAG-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: s_endpgm @@ -8651,7 +8667,7 @@ define amdgpu_ps void @flat_umax_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -8663,14 +8679,14 @@ define amdgpu_ps void @flat_umax_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: flat_atomic_umax v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0) ; GFX950-SDAG-NEXT: s_endpgm ; ; GFX950-GISEL-LABEL: flat_umax_saddr_i32_nortn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -8692,7 +8708,7 @@ define amdgpu_ps void @flat_umax_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_max_u32 v[0:1], v2 offset:-128 ; GFX1250-SDAG-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: s_endpgm @@ -8703,7 +8719,7 @@ define amdgpu_ps void @flat_umax_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -8715,7 +8731,7 @@ define amdgpu_ps void @flat_umax_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -8725,7 +8741,7 @@ define amdgpu_ps void @flat_umax_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %v ; ; GFX950-GISEL-LABEL: flat_umax_saddr_i32_nortn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -8752,7 +8768,7 @@ define amdgpu_ps <2 x float> @flat_umax_saddr_i64_rtn(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0 @@ -8795,7 +8811,7 @@ define amdgpu_ps <2 x float> @flat_umax_saddr_i64_rtn(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -8840,9 +8856,9 @@ define amdgpu_ps <2 x float> @flat_umax_saddr_i64_rtn(ptr inreg %sbase, i32 %vof ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -8880,13 +8896,13 @@ define amdgpu_ps <2 x float> @flat_umax_saddr_i64_rtn(ptr inreg %sbase, i32 %vof ; GFX950-GISEL-LABEL: flat_umax_saddr_i64_rtn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -8936,9 +8952,10 @@ define amdgpu_ps <2 x float> @flat_umax_saddr_i64_rtn_neg128(ptr inreg %sbase, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 @@ -8983,7 +9000,7 @@ define amdgpu_ps <2 x float> @flat_umax_saddr_i64_rtn_neg128(ptr inreg %sbase, i ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v3, vcc_lo @@ -9031,12 +9048,12 @@ define amdgpu_ps <2 x float> @flat_umax_saddr_i64_rtn_neg128(ptr inreg %sbase, i ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -9074,16 +9091,16 @@ define amdgpu_ps <2 x float> @flat_umax_saddr_i64_rtn_neg128(ptr inreg %sbase, i ; GFX950-GISEL-LABEL: flat_umax_saddr_i64_rtn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -9134,9 +9151,9 @@ define amdgpu_ps void @flat_umax_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4 @@ -9174,7 +9191,7 @@ define amdgpu_ps void @flat_umax_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -9214,9 +9231,9 @@ define amdgpu_ps void @flat_umax_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB76_3 @@ -9248,12 +9265,12 @@ define amdgpu_ps void @flat_umax_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-LABEL: flat_umax_saddr_i64_nortn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB76_3 @@ -9296,9 +9313,10 @@ define amdgpu_ps void @flat_umax_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -9338,7 +9356,7 @@ define amdgpu_ps void @flat_umax_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -9381,12 +9399,12 @@ define amdgpu_ps void @flat_umax_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB77_3 @@ -9418,16 +9436,16 @@ define amdgpu_ps void @flat_umax_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX950-GISEL-LABEL: flat_umax_saddr_i64_nortn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB77_3 @@ -9475,7 +9493,7 @@ define amdgpu_ps float @flat_umin_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_min_u32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -9486,7 +9504,7 @@ define amdgpu_ps float @flat_umin_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -9498,14 +9516,14 @@ define amdgpu_ps float @flat_umin_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: flat_atomic_umin v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: ; return to shader part epilog ; ; GFX950-GISEL-LABEL: flat_umin_saddr_i32_rtn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -9528,7 +9546,7 @@ define amdgpu_ps float @flat_umin_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_min_u32 v0, v[0:1], v2 offset:-128 th:TH_ATOMIC_RETURN ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -9539,7 +9557,7 @@ define amdgpu_ps float @flat_umin_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -9551,7 +9569,7 @@ define amdgpu_ps float @flat_umin_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -9561,7 +9579,7 @@ define amdgpu_ps float @flat_umin_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vo ; ; GFX950-GISEL-LABEL: flat_umin_saddr_i32_rtn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -9588,7 +9606,7 @@ define amdgpu_ps void @flat_umin_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_min_u32 v[0:1], v2 ; GFX1250-SDAG-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: s_endpgm @@ -9599,7 +9617,7 @@ define amdgpu_ps void @flat_umin_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -9611,14 +9629,14 @@ define amdgpu_ps void @flat_umin_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: flat_atomic_umin v[0:1], v2 ; GFX950-SDAG-NEXT: s_waitcnt lgkmcnt(0) ; GFX950-SDAG-NEXT: s_endpgm ; ; GFX950-GISEL-LABEL: flat_umin_saddr_i32_nortn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -9640,7 +9658,7 @@ define amdgpu_ps void @flat_umin_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_min_u32 v[0:1], v2 offset:-128 ; GFX1250-SDAG-NEXT: s_wait_storecnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: s_endpgm @@ -9651,7 +9669,7 @@ define amdgpu_ps void @flat_umin_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -9663,7 +9681,7 @@ define amdgpu_ps void @flat_umin_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -9673,7 +9691,7 @@ define amdgpu_ps void @flat_umin_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %v ; ; GFX950-GISEL-LABEL: flat_umin_saddr_i32_nortn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -9700,7 +9718,7 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0 @@ -9743,7 +9761,7 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -9788,9 +9806,9 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn(ptr inreg %sbase, i32 %vof ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -9828,13 +9846,13 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn(ptr inreg %sbase, i32 %vof ; GFX950-GISEL-LABEL: flat_umin_saddr_i64_rtn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -9884,9 +9902,10 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn_neg128(ptr inreg %sbase, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 @@ -9931,7 +9950,7 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn_neg128(ptr inreg %sbase, i ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v3, vcc_lo @@ -9979,12 +9998,12 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn_neg128(ptr inreg %sbase, i ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -10022,16 +10041,16 @@ define amdgpu_ps <2 x float> @flat_umin_saddr_i64_rtn_neg128(ptr inreg %sbase, i ; GFX950-GISEL-LABEL: flat_umin_saddr_i64_rtn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -10082,9 +10101,9 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4 @@ -10122,7 +10141,7 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -10162,9 +10181,9 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB84_3 @@ -10196,12 +10215,12 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-LABEL: flat_umin_saddr_i64_nortn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB84_3 @@ -10244,9 +10263,10 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -10286,7 +10306,7 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -10329,12 +10349,12 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB85_3 @@ -10366,16 +10386,16 @@ define amdgpu_ps void @flat_umin_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %v ; GFX950-GISEL-LABEL: flat_umin_saddr_i64_nortn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB85_3 @@ -10423,7 +10443,7 @@ define amdgpu_ps float @flat_cmpxchg_saddr_i32_rtn(ptr inreg %sbase, i32 %voffse ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS @@ -10438,7 +10458,7 @@ define amdgpu_ps float @flat_cmpxchg_saddr_i32_rtn(ptr inreg %sbase, i32 %voffse ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1] ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v3, v1 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v4, v0 @@ -10455,7 +10475,7 @@ define amdgpu_ps float @flat_cmpxchg_saddr_i32_rtn(ptr inreg %sbase, i32 %voffse ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc0 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_cmpswap v0, v[0:1], v[2:3] sc0 sc1 @@ -10465,7 +10485,7 @@ define amdgpu_ps float @flat_cmpxchg_saddr_i32_rtn(ptr inreg %sbase, i32 %voffse ; ; GFX950-GISEL-LABEL: flat_cmpxchg_saddr_i32_rtn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, v1 ; GFX950-GISEL-NEXT: s_nop 0 @@ -10493,7 +10513,7 @@ define amdgpu_ps float @flat_cmpxchg_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_cmpswap_b32 v0, v[0:1], v[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SYS @@ -10508,7 +10528,7 @@ define amdgpu_ps float @flat_cmpxchg_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1] ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v3, v1 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v4, v0 @@ -10525,7 +10545,7 @@ define amdgpu_ps float @flat_cmpxchg_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -10538,7 +10558,7 @@ define amdgpu_ps float @flat_cmpxchg_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 ; ; GFX950-GISEL-LABEL: flat_cmpxchg_saddr_i32_rtn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, v1 ; GFX950-GISEL-NEXT: s_nop 0 @@ -10570,7 +10590,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i32_nortn(ptr inreg %sbase, i32 %voffs ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] scope:SCOPE_SYS @@ -10585,7 +10605,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i32_nortn(ptr inreg %sbase, i32 %voffs ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1] ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v3, v1 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v4, v0 @@ -10602,7 +10622,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i32_nortn(ptr inreg %sbase, i32 %voffs ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: buffer_wbl2 sc0 sc1 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) ; GFX950-SDAG-NEXT: flat_atomic_cmpswap v[0:1], v[2:3] sc1 @@ -10612,7 +10632,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i32_nortn(ptr inreg %sbase, i32 %voffs ; ; GFX950-GISEL-LABEL: flat_cmpxchg_saddr_i32_nortn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, v1 ; GFX950-GISEL-NEXT: s_nop 0 @@ -10638,7 +10658,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_atomic_cmpswap_b32 v[0:1], v[2:3] offset:-128 scope:SCOPE_SYS @@ -10653,7 +10673,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1] ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v3, v1 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v4, v0 @@ -10670,7 +10690,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -10683,7 +10703,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 ; ; GFX950-GISEL-LABEL: flat_cmpxchg_saddr_i32_nortn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v4, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v3, v1 ; GFX950-GISEL-NEXT: s_nop 0 @@ -10715,7 +10735,7 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn(ptr inreg %sbase, i32 % ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v5, v4 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v4, v3 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v3 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0 @@ -10763,7 +10783,7 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn(ptr inreg %sbase, i32 % ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v9, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -10814,9 +10834,9 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn(ptr inreg %sbase, i32 % ; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, v4 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, v3 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, v2 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[2:3], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[2:3], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -10857,14 +10877,14 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn(ptr inreg %sbase, i32 % ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, v2 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, v3 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, v1 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, v4 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -10916,11 +10936,12 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn_neg128(ptr inreg %sbase ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v6, v1 -; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v5, v4 +; GFX1250-SDAG-NEXT: v_mov_b32_e32 v4, v3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v3 @@ -10970,7 +10991,7 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn_neg128(ptr inreg %sbase ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v9, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v5, null, 0, v3, vcc_lo @@ -11021,15 +11042,15 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn_neg128(ptr inreg %sbase ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, v4 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, v3 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, v2 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[2:3], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[2:3], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -11070,17 +11091,17 @@ define amdgpu_ps <2 x float> @flat_cmpxchg_saddr_i64_rtn_neg128(ptr inreg %sbase ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, v2 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, v3 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, v4 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -11135,9 +11156,9 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffs ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v6, v1 ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v5, v4 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v4, v3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v2, src_flat_scratch_base_hi, v1 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v2 @@ -11179,7 +11200,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffs ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v9, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -11221,12 +11242,12 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffs ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, v4 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, v3 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, v2 -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB92_3 @@ -11262,13 +11283,13 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn(ptr inreg %sbase, i32 %voffs ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, v2 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, v3 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, v1 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, v4 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB92_3 @@ -11313,11 +11334,12 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v7, v2 :: v_dual_mov_b32 v6, v1 -; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mov_b32 v5, v4 +; GFX1250-SDAG-NEXT: v_mov_b32_e32 v4, v3 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: v_dual_mov_b32 v5, v4 :: v_dual_mov_b32 v4, v3 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -11361,7 +11383,7 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v1 :: v_dual_mov_b32 v9, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v3 :: v_dual_mov_b32 v7, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -11406,15 +11428,15 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v6, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[2:3] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] ; GFX950-SDAG-NEXT: v_mov_b32_e32 v5, v4 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v4, v3 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v7, v2 -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB93_3 @@ -11450,17 +11472,17 @@ define amdgpu_ps void @flat_cmpxchg_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v9, v2 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v6, v3 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v8, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v7, v4 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB93_3 @@ -11511,7 +11533,7 @@ define amdgpu_ps float @flat_inc_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_inc_u32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -11522,7 +11544,7 @@ define amdgpu_ps float @flat_inc_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -11534,14 +11556,14 @@ define amdgpu_ps float @flat_inc_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: flat_atomic_inc v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: ; return to shader part epilog ; ; GFX950-GISEL-LABEL: flat_inc_saddr_i32_rtn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -11564,7 +11586,7 @@ define amdgpu_ps float @flat_inc_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_inc_u32 v0, v[0:1], v2 offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -11575,7 +11597,7 @@ define amdgpu_ps float @flat_inc_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -11587,7 +11609,7 @@ define amdgpu_ps float @flat_inc_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -11597,7 +11619,7 @@ define amdgpu_ps float @flat_inc_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; ; GFX950-GISEL-LABEL: flat_inc_saddr_i32_rtn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -11624,7 +11646,7 @@ define amdgpu_ps void @flat_inc_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_inc_u32 v[0:1], v2 scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -11634,7 +11656,7 @@ define amdgpu_ps void @flat_inc_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -11645,13 +11667,13 @@ define amdgpu_ps void @flat_inc_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: flat_atomic_inc v[0:1], v2 ; GFX950-SDAG-NEXT: s_endpgm ; ; GFX950-GISEL-LABEL: flat_inc_saddr_i32_nortn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -11672,7 +11694,7 @@ define amdgpu_ps void @flat_inc_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_inc_u32 v[0:1], v2 offset:-128 scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -11682,7 +11704,7 @@ define amdgpu_ps void @flat_inc_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -11693,7 +11715,7 @@ define amdgpu_ps void @flat_inc_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -11702,7 +11724,7 @@ define amdgpu_ps void @flat_inc_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; ; GFX950-GISEL-LABEL: flat_inc_saddr_i32_nortn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -11728,7 +11750,7 @@ define amdgpu_ps <2 x float> @flat_inc_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0 @@ -11774,7 +11796,7 @@ define amdgpu_ps <2 x float> @flat_inc_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -11824,9 +11846,9 @@ define amdgpu_ps <2 x float> @flat_inc_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -11865,13 +11887,13 @@ define amdgpu_ps <2 x float> @flat_inc_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-GISEL-LABEL: flat_inc_saddr_i64_rtn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -11924,9 +11946,10 @@ define amdgpu_ps <2 x float> @flat_inc_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 @@ -11974,7 +11997,7 @@ define amdgpu_ps <2 x float> @flat_inc_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v3, vcc_lo @@ -12027,12 +12050,12 @@ define amdgpu_ps <2 x float> @flat_inc_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -12071,16 +12094,16 @@ define amdgpu_ps <2 x float> @flat_inc_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-GISEL-LABEL: flat_inc_saddr_i64_rtn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -12134,9 +12157,9 @@ define amdgpu_ps void @flat_inc_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4 @@ -12174,7 +12197,7 @@ define amdgpu_ps void @flat_inc_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -12216,9 +12239,9 @@ define amdgpu_ps void @flat_inc_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB100_3 @@ -12250,12 +12273,12 @@ define amdgpu_ps void @flat_inc_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-LABEL: flat_inc_saddr_i64_nortn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB100_3 @@ -12300,9 +12323,10 @@ define amdgpu_ps void @flat_inc_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -12342,7 +12366,7 @@ define amdgpu_ps void @flat_inc_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -12387,12 +12411,12 @@ define amdgpu_ps void @flat_inc_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB101_3 @@ -12424,16 +12448,16 @@ define amdgpu_ps void @flat_inc_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-LABEL: flat_inc_saddr_i64_nortn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB101_3 @@ -12484,7 +12508,7 @@ define amdgpu_ps float @flat_dec_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_dec_u32 v0, v[0:1], v2 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -12495,7 +12519,7 @@ define amdgpu_ps float @flat_dec_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -12507,14 +12531,14 @@ define amdgpu_ps float @flat_dec_saddr_i32_rtn(ptr inreg %sbase, i32 %voffset, i ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: flat_atomic_dec v0, v[0:1], v2 sc0 ; GFX950-SDAG-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) ; GFX950-SDAG-NEXT: ; return to shader part epilog ; ; GFX950-GISEL-LABEL: flat_dec_saddr_i32_rtn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -12537,7 +12561,7 @@ define amdgpu_ps float @flat_dec_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_dec_u32 v0, v[0:1], v2 offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -12548,7 +12572,7 @@ define amdgpu_ps float @flat_dec_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -12560,7 +12584,7 @@ define amdgpu_ps float @flat_dec_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -12570,7 +12594,7 @@ define amdgpu_ps float @flat_dec_saddr_i32_rtn_neg128(ptr inreg %sbase, i32 %vof ; ; GFX950-GISEL-LABEL: flat_dec_saddr_i32_rtn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -12597,7 +12621,7 @@ define amdgpu_ps void @flat_dec_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_dec_u32 v[0:1], v2 scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -12607,7 +12631,7 @@ define amdgpu_ps void @flat_dec_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -12618,13 +12642,13 @@ define amdgpu_ps void @flat_dec_saddr_i32_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: flat_atomic_dec v[0:1], v2 ; GFX950-SDAG-NEXT: s_endpgm ; ; GFX950-GISEL-LABEL: flat_dec_saddr_i32_nortn: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -12645,7 +12669,7 @@ define amdgpu_ps void @flat_dec_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_atomic_dec_u32 v[0:1], v2 offset:-128 scope:SCOPE_DEV ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -12655,7 +12679,7 @@ define amdgpu_ps void @flat_dec_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -12666,7 +12690,7 @@ define amdgpu_ps void @flat_dec_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG: ; %bb.0: ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] ; GFX950-SDAG-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 ; GFX950-SDAG-NEXT: s_nop 1 ; GFX950-SDAG-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc @@ -12675,7 +12699,7 @@ define amdgpu_ps void @flat_dec_saddr_i32_nortn_neg128(ptr inreg %sbase, i32 %vo ; ; GFX950-GISEL-LABEL: flat_dec_saddr_i32_nortn_neg128: ; GFX950-GISEL: ; %bb.0: -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: s_nop 1 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc @@ -12701,7 +12725,7 @@ define amdgpu_ps <2 x float> @flat_dec_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_cmp_lt_u32_e32 vcc_lo, 0x3ffffff, v0 @@ -12749,7 +12773,7 @@ define amdgpu_ps <2 x float> @flat_dec_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -12799,9 +12823,9 @@ define amdgpu_ps <2 x float> @flat_dec_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -12843,13 +12867,13 @@ define amdgpu_ps <2 x float> @flat_dec_saddr_i64_rtn(ptr inreg %sbase, i32 %voff ; GFX950-GISEL-LABEL: flat_dec_saddr_i64_rtn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, v2, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -12903,9 +12927,10 @@ define amdgpu_ps <2 x float> @flat_dec_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v0, src_flat_scratch_base_hi, v5 @@ -12955,7 +12980,7 @@ define amdgpu_ps <2 x float> @flat_dec_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v6, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v7, null, 0, v3, vcc_lo @@ -13008,12 +13033,12 @@ define amdgpu_ps <2 x float> @flat_dec_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v5 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[4:5], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v5 ; GFX950-SDAG-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -13055,16 +13080,16 @@ define amdgpu_ps <2 x float> @flat_dec_saddr_i64_rtn_neg128(ptr inreg %sbase, i3 ; GFX950-GISEL-LABEL: flat_dec_saddr_i64_rtn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v2, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v3, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v3 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v3 ; GFX950-GISEL-NEXT: ; implicit-def: $vgpr0_vgpr1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] @@ -13119,9 +13144,9 @@ define amdgpu_ps void @flat_dec_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] ; GFX1250-SDAG-NEXT: v_xor_b32_e32 v4, src_flat_scratch_base_hi, v1 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_cmpx_lt_u32_e32 0x3ffffff, v4 @@ -13161,7 +13186,7 @@ define amdgpu_ps void @flat_dec_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -13203,9 +13228,9 @@ define amdgpu_ps void @flat_dec_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB108_3 @@ -13240,12 +13265,12 @@ define amdgpu_ps void @flat_dec_saddr_i64_nortn(ptr inreg %sbase, i32 %voffset, ; GFX950-GISEL-LABEL: flat_dec_saddr_i64_nortn: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB108_3 @@ -13291,9 +13316,10 @@ define amdgpu_ps void @flat_dec_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b64 s[0:1], 0xffffffffffffff80 -; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1) ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -13335,7 +13361,7 @@ define amdgpu_ps void @flat_dec_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_mov_b32 s0, exec_lo ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -13380,12 +13406,12 @@ define amdgpu_ps void @flat_dec_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-SDAG-NEXT: v_mov_b32_e32 v3, v2 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v2, v1 ; GFX950-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[2:3], 0, v[0:1] -; GFX950-SDAG-NEXT: s_movk_i32 s2, 0xff80 -; GFX950-SDAG-NEXT: s_mov_b32 s3, -1 -; GFX950-SDAG-NEXT: s_mov_b64 s[0:1], src_private_base -; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[2:3] -; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1] +; GFX950-SDAG-NEXT: s_movk_i32 s0, 0xff80 +; GFX950-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX950-SDAG-NEXT: s_mov_b64 s[2:3], src_private_base +; GFX950-SDAG-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, s[0:1] +; GFX950-SDAG-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-SDAG-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-SDAG-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-SDAG-NEXT: s_cbranch_execnz .LBB109_3 @@ -13420,16 +13446,16 @@ define amdgpu_ps void @flat_dec_saddr_i64_nortn_neg128(ptr inreg %sbase, i32 %vo ; GFX950-GISEL-LABEL: flat_dec_saddr_i64_nortn_neg128: ; GFX950-GISEL: ; %bb.0: ; GFX950-GISEL-NEXT: v_mov_b32_e32 v5, v2 -; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX950-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, v2, v0 ; GFX950-GISEL-NEXT: v_mov_b32_e32 v4, v1 ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v3, vcc ; GFX950-GISEL-NEXT: v_add_co_u32_e32 v0, vcc, 0xffffff80, v0 -; GFX950-GISEL-NEXT: s_mov_b64 s[0:1], src_private_base +; GFX950-GISEL-NEXT: s_mov_b64 s[2:3], src_private_base ; GFX950-GISEL-NEXT: s_nop 0 ; GFX950-GISEL-NEXT: v_addc_co_u32_e32 v1, vcc, -1, v1, vcc -; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s1, v1 +; GFX950-GISEL-NEXT: v_cmp_ne_u32_e32 vcc, s3, v1 ; GFX950-GISEL-NEXT: s_and_saveexec_b64 s[0:1], vcc ; GFX950-GISEL-NEXT: s_xor_b64 s[0:1], exec, s[0:1] ; GFX950-GISEL-NEXT: s_cbranch_execnz .LBB109_3 diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll index eae0e325e22e38..6d1cec4430f6ac 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-load.ll @@ -19,7 +19,7 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0(ptr inreg %sbase) { ; GFX1250-NEXT: v_nop ; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-NEXT: flat_load_u8 v0, v0, s[2:3] +; GFX1250-NEXT: flat_load_u8 v0, v0, s[0:1] ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: ; return to shader part epilog %load = load i8, ptr %sbase @@ -37,7 +37,7 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_8388607(ptr inreg %sbase) { ; GFX1250-NEXT: v_nop ; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-NEXT: flat_load_u8 v0, v0, s[2:3] offset:8388607 +; GFX1250-NEXT: flat_load_u8 v0, v0, s[0:1] offset:8388607 ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: ; return to shader part epilog %gep0 = getelementptr inbounds i8, ptr %sbase, i64 8388607 @@ -56,7 +56,7 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_8388608(ptr inreg %sbase) { ; GFX1250-NEXT: v_nop ; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-NEXT: v_mov_b32_e32 v0, 0x800000 -; GFX1250-NEXT: flat_load_u8 v0, v0, s[2:3] +; GFX1250-NEXT: flat_load_u8 v0, v0, s[0:1] ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: ; return to shader part epilog %gep0 = getelementptr inbounds i8, ptr %sbase, i64 8388608 @@ -75,7 +75,7 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_neg8388608(ptr inreg %sbase) { ; GFX1250-NEXT: v_nop ; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-NEXT: flat_load_u8 v0, v0, s[2:3] offset:-8388608 +; GFX1250-NEXT: flat_load_u8 v0, v0, s[0:1] offset:-8388608 ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: ; return to shader part epilog %gep0 = getelementptr inbounds i8, ptr %sbase, i64 -8388608 @@ -94,7 +94,7 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_neg8388609(ptr inreg %sbase) { ; GFX1250-NEXT: v_nop ; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-NEXT: v_mov_b32_e32 v0, 0xff800000 -; GFX1250-NEXT: flat_load_u8 v0, v0, s[2:3] offset:-1 +; GFX1250-NEXT: flat_load_u8 v0, v0, s[0:1] offset:-1 ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: ; return to shader part epilog %gep0 = getelementptr inbounds i8, ptr %sbase, i64 -8388609 @@ -113,7 +113,7 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_neg16777220(ptr inreg %sbase) ; GFX1250-NEXT: v_nop ; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-NEXT: v_mov_b32_e32 v0, 0xff000000 -; GFX1250-NEXT: flat_load_u8 v0, v0, s[2:3] offset:-4 +; GFX1250-NEXT: flat_load_u8 v0, v0, s[0:1] offset:-4 ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: ; return to shader part epilog %gep0 = getelementptr inbounds i8, ptr %sbase, i64 -16777220 @@ -130,9 +130,9 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0xFFFFFFFF(ptr inreg %sbase) { ; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-SDAG-NEXT: v_add_co_u32 v0, s0, 0xff800000, s2 +; GFX1250-SDAG-NEXT: v_add_co_u32 v0, s0, 0xff800000, s0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 0, s3, s0 +; GFX1250-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 0, s1, s0 ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:8388607 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -143,8 +143,8 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0xFFFFFFFF(ptr inreg %sbase) { ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s2, -1 -; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s3, 0 +; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s0, -1 +; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] @@ -165,8 +165,8 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000000(ptr inreg %sbase) ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-SDAG-NEXT: s_add_co_i32 s3, s3, 1 -; GFX1250-SDAG-NEXT: flat_load_u8 v0, v0, s[2:3] +; GFX1250-SDAG-NEXT: s_add_co_i32 s1, s1, 1 +; GFX1250-SDAG-NEXT: flat_load_u8 v0, v0, s[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog ; @@ -176,8 +176,8 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000000(ptr inreg %sbase) ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s2, 0 -; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s3, 1 +; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s0, 0 +; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 1 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] @@ -197,9 +197,9 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000001(ptr inreg %sbase) ; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s2 +; GFX1250-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s3, s0 +; GFX1250-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s1, s0 ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:1 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -210,8 +210,8 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000001(ptr inreg %sbase) ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s2, 1 -; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s3, 1 +; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s0, 1 +; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 1 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] @@ -231,9 +231,9 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000FFF(ptr inreg %sbase) ; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s2 +; GFX1250-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s3, s0 +; GFX1250-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s1, s0 ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:4095 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -244,8 +244,8 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100000FFF(ptr inreg %sbase) ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s2, 0xfff -; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s3, 1 +; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s0, 0xfff +; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 1 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] @@ -265,9 +265,9 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100001000(ptr inreg %sbase) ; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s2 +; GFX1250-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s3, s0 +; GFX1250-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s1, s0 ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:4096 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -278,8 +278,8 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_0x100001000(ptr inreg %sbase) ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s2, 0x1000 -; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s3, 1 +; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s0, 0x1000 +; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 1 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] @@ -299,9 +299,9 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_neg0xFFFFFFFF(ptr inreg %sbase ; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-SDAG-NEXT: v_add_co_u32 v0, s0, 0x800000, s2 +; GFX1250-SDAG-NEXT: v_add_co_u32 v0, s0, 0x800000, s0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s3, s0 +; GFX1250-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:-8388607 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -312,8 +312,8 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_neg0xFFFFFFFF(ptr inreg %sbase ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s2, 1 -; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s3, -1 +; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s0, 1 +; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] @@ -334,8 +334,8 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_neg0x100000000(ptr inreg %sbas ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-SDAG-NEXT: s_add_co_i32 s3, s3, -1 -; GFX1250-SDAG-NEXT: flat_load_u8 v0, v0, s[2:3] +; GFX1250-SDAG-NEXT: s_add_co_i32 s1, s1, -1 +; GFX1250-SDAG-NEXT: flat_load_u8 v0, v0, s[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog ; @@ -345,8 +345,8 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_neg0x100000000(ptr inreg %sbas ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s2, 0 -; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s3, -1 +; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s0, 0 +; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] @@ -366,9 +366,9 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_neg0x100000001(ptr inreg %sbas ; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s2 +; GFX1250-SDAG-NEXT: v_add_co_u32 v0, s0, 0, s0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s3, s0 +; GFX1250-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s0 ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:-1 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -379,8 +379,8 @@ define amdgpu_ps float @flat_load_saddr_i8_offset_neg0x100000001(ptr inreg %sbas ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s2, -1 -; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s3, -2 +; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s0, -1 +; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -2 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) ; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[0:1], s[0:1] ; GFX1250-GISEL-NEXT: flat_load_u8 v0, v[0:1] @@ -407,7 +407,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -418,7 +418,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -443,7 +443,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_8388607(ptr inreg %s ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:8388607 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -454,7 +454,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_8388607(ptr inreg %s ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -480,7 +480,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_8388608(ptr inreg %s ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_add_co_u32 v0, vcc_lo, 0x800000, v0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc_lo @@ -494,7 +494,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_8388608(ptr inreg %s ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -523,7 +523,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_neg8388608(ptr inreg ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:-8388608 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -534,7 +534,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_neg8388608(ptr inreg ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -560,7 +560,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_neg8388607(ptr inreg ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:-8388607 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -571,7 +571,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_neg8388607(ptr inreg ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -596,7 +596,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_8388607_gep_order(pt ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:8388607 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -607,7 +607,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_offset_8388607_gep_order(pt ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -633,7 +633,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint(ptr inreg %sbase, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -644,7 +644,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint(ptr inreg %sbase, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -671,7 +671,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add(ptr in ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -682,7 +682,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add(ptr in ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -709,7 +709,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_of ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0x80, v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -721,7 +721,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_of ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -752,7 +752,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_of ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], 0x80, v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 @@ -764,7 +764,7 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_of ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -881,9 +881,9 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_uniform_offset(ptr inreg %sbase, ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-SDAG-NEXT: s_mov_b32 s5, 0 +; GFX1250-SDAG-NEXT: s_mov_b32 s3, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[4:5] +; GFX1250-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v0, s[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -895,8 +895,8 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_uniform_offset(ptr inreg %sbase, ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s2, s4 -; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s3, 0 +; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s0, s2 +; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0 ; GFX1250-GISEL-NEXT: flat_load_u8 v0, v0, s[0:1] ; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-GISEL-NEXT: ; return to shader part epilog @@ -917,9 +917,9 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_uniform_offset_immoffset(ptr inr ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-SDAG-NEXT: s_mov_b32 s5, 0 +; GFX1250-SDAG-NEXT: s_mov_b32 s3, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[4:5] +; GFX1250-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v0, s[0:1] offset:-24 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -931,8 +931,8 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_uniform_offset_immoffset(ptr inr ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s2, s4 -; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s3, 0 +; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s0, s2 +; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0 ; GFX1250-GISEL-NEXT: flat_load_u8 v0, v0, s[0:1] offset:-24 ; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-GISEL-NEXT: ; return to shader part epilog @@ -954,9 +954,9 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add(ptr in ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-SDAG-NEXT: s_mov_b32 s5, 0 +; GFX1250-SDAG-NEXT: s_mov_b32 s3, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-SDAG-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[2:3] +; GFX1250-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v0, s[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -968,8 +968,8 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add(ptr in ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s2, s4 -; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s3, 0 +; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s0, s2 +; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0 ; GFX1250-GISEL-NEXT: flat_load_u8 v0, v0, s[0:1] ; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-GISEL-NEXT: ; return to shader part epilog @@ -992,9 +992,9 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_of ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-SDAG-NEXT: s_mov_b32 s5, 0 +; GFX1250-SDAG-NEXT: s_mov_b32 s3, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-SDAG-NEXT: s_add_nc_u64 s[0:1], s[4:5], s[2:3] +; GFX1250-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v0, s[0:1] offset:128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1006,8 +1006,8 @@ define amdgpu_ps float @flat_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_of ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s2, s4 -; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s3, 0 +; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s0, s2 +; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0 ; GFX1250-GISEL-NEXT: flat_load_u8 v0, v0, s[0:1] offset:128 ; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-GISEL-NEXT: ; return to shader part epilog @@ -1030,9 +1030,9 @@ define amdgpu_ps float @flat_load_i8_vgpr64_sgpr32(ptr %vbase, i32 inreg %soffse ; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-SDAG-NEXT: s_mov_b32 s3, 0 +; GFX1250-SDAG-NEXT: s_mov_b32 s1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1043,9 +1043,9 @@ define amdgpu_ps float @flat_load_i8_vgpr64_sgpr32(ptr %vbase, i32 inreg %soffse ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: s_mov_b32 s3, 0 +; GFX1250-GISEL-NEXT: s_mov_b32 s1, 0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo @@ -1068,9 +1068,9 @@ define amdgpu_ps float @flat_load_i8_vgpr64_sgpr32_offset_8388607(ptr %vbase, i3 ; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-SDAG-NEXT: s_mov_b32 s3, 0 +; GFX1250-SDAG-NEXT: s_mov_b32 s1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:8388607 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1081,9 +1081,9 @@ define amdgpu_ps float @flat_load_i8_vgpr64_sgpr32_offset_8388607(ptr %vbase, i3 ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: s_mov_b32 s3, 0 +; GFX1250-GISEL-NEXT: s_mov_b32 s1, 0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1) -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v0, v2 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc_lo @@ -1115,7 +1115,7 @@ define amdgpu_ps float @flat_load_saddr_f32_natural_addressing(ptr inreg %sbase, ; GFX1250-NEXT: v_mov_b32_e32 v3, 0 ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 2, s[2:3] +; GFX1250-NEXT: v_lshl_add_u64 v[2:3], v[2:3], 2, s[0:1] ; GFX1250-NEXT: flat_load_b32 v0, v[2:3] ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: ; return to shader part epilog @@ -1138,7 +1138,7 @@ define amdgpu_ps float @flat_load_saddr_f32_natural_addressing_immoffset(ptr inr ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v3, 0 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[2:3] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[2:3] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[2:3] offset:128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1150,7 +1150,7 @@ define amdgpu_ps float @flat_load_saddr_f32_natural_addressing_immoffset(ptr inr ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1] -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -1178,7 +1178,7 @@ define amdgpu_ps float @flat_load_f32_saddr_zext_vgpr_range(ptr inreg %sbase, pt ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[2:3] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[2:3] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[2:3] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1190,7 +1190,7 @@ define amdgpu_ps float @flat_load_f32_saddr_zext_vgpr_range(ptr inreg %sbase, pt ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1] -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-GISEL-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -1218,7 +1218,7 @@ define amdgpu_ps float @flat_load_f32_saddr_zext_vgpr_range_imm_offset(ptr inreg ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_lshlrev_b32 v2, 2, v0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[2:3] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[2:3] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[2:3] offset:400 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1230,7 +1230,7 @@ define amdgpu_ps float @flat_load_f32_saddr_zext_vgpr_range_imm_offset(ptr inreg ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1] -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-GISEL-NEXT: v_lshlrev_b32_e32 v4, 2, v0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) @@ -1257,7 +1257,7 @@ define amdgpu_ps float @flat_load_f32_saddr_zext_vgpr_range_too_large(ptr inreg ; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-NEXT: flat_load_b32 v0, v[0:1] ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-NEXT: flat_load_b32 v0, v0, s[2:3] scale_offset +; GFX1250-NEXT: flat_load_b32 v0, v0, s[0:1] scale_offset ; GFX1250-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-NEXT: ; return to shader part epilog %voffset = load i32, ptr %voffset.ptr, !range !1, !noundef !{} @@ -1280,7 +1280,7 @@ define amdgpu_ps half @flat_load_saddr_i16(ptr inreg %sbase, i32 %voffset) { ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u16 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1291,7 +1291,7 @@ define amdgpu_ps half @flat_load_saddr_i16(ptr inreg %sbase, i32 %voffset) { ; GFX1250-GISEL-FAKE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-FAKE16-NEXT: v_nop ; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1305,7 +1305,7 @@ define amdgpu_ps half @flat_load_saddr_i16(ptr inreg %sbase, i32 %voffset) { ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-TRUE16-NEXT: v_nop ; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -1328,7 +1328,7 @@ define amdgpu_ps half @flat_load_saddr_i16_immneg128(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u16 v0, v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1339,7 +1339,7 @@ define amdgpu_ps half @flat_load_saddr_i16_immneg128(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-FAKE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-FAKE16-NEXT: v_nop ; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1353,7 +1353,7 @@ define amdgpu_ps half @flat_load_saddr_i16_immneg128(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-TRUE16-NEXT: v_nop ; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -1377,7 +1377,7 @@ define amdgpu_ps half @flat_load_saddr_f16(ptr inreg %sbase, i32 %voffset) { ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u16 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1388,7 +1388,7 @@ define amdgpu_ps half @flat_load_saddr_f16(ptr inreg %sbase, i32 %voffset) { ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1410,7 +1410,7 @@ define amdgpu_ps half @flat_load_saddr_f16_immneg128(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u16 v0, v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1421,7 +1421,7 @@ define amdgpu_ps half @flat_load_saddr_f16_immneg128(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1444,7 +1444,7 @@ define amdgpu_ps float @flat_load_saddr_i32(ptr inreg %sbase, i32 %voffset) { ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1455,7 +1455,7 @@ define amdgpu_ps float @flat_load_saddr_i32(ptr inreg %sbase, i32 %voffset) { ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1478,7 +1478,7 @@ define amdgpu_ps float @flat_load_saddr_i32_immneg128(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1489,7 +1489,7 @@ define amdgpu_ps float @flat_load_saddr_i32_immneg128(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1513,7 +1513,7 @@ define amdgpu_ps float @flat_load_saddr_f32(ptr inreg %sbase, i32 %voffset) { ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1524,7 +1524,7 @@ define amdgpu_ps float @flat_load_saddr_f32(ptr inreg %sbase, i32 %voffset) { ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1546,7 +1546,7 @@ define amdgpu_ps float @flat_load_saddr_f32_immneg128(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1557,7 +1557,7 @@ define amdgpu_ps float @flat_load_saddr_f32_immneg128(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1580,7 +1580,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_v2i16(ptr inreg %sbase, i32 %voffse ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1591,7 +1591,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_v2i16(ptr inreg %sbase, i32 %voffse ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1614,7 +1614,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_v2i16_immneg128(ptr inreg %sbase, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1625,7 +1625,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_v2i16_immneg128(ptr inreg %sbase, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1649,7 +1649,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_v2f16(ptr inreg %sbase, i32 %voffse ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1660,7 +1660,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_v2f16(ptr inreg %sbase, i32 %voffse ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1682,7 +1682,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_v2f16_immneg128(ptr inreg %sbase, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1693,7 +1693,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_v2f16_immneg128(ptr inreg %sbase, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1716,7 +1716,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_p3(ptr inreg %sbase, i32 %voffset) ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1727,7 +1727,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_p3(ptr inreg %sbase, i32 %voffset) ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1751,7 +1751,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_p3_immneg128(ptr inreg %sbase, i32 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1762,7 +1762,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_p3_immneg128(ptr inreg %sbase, i32 ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1787,7 +1787,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_f64(ptr inreg %sbase, i32 %voffset ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1798,7 +1798,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_f64(ptr inreg %sbase, i32 %voffset ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1821,7 +1821,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_f64_immneg128(ptr inreg %sbase, i3 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1832,7 +1832,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_f64_immneg128(ptr inreg %sbase, i3 ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1856,7 +1856,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_i64(ptr inreg %sbase, i32 %voffset ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1867,7 +1867,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_i64(ptr inreg %sbase, i32 %voffset ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1890,7 +1890,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_i64_immneg128(ptr inreg %sbase, i3 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1901,7 +1901,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_i64_immneg128(ptr inreg %sbase, i3 ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1925,7 +1925,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v2f32(ptr inreg %sbase, i32 %voffs ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1936,7 +1936,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v2f32(ptr inreg %sbase, i32 %voffs ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1958,7 +1958,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v2f32_immneg128(ptr inreg %sbase, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -1969,7 +1969,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v2f32_immneg128(ptr inreg %sbase, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1992,7 +1992,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v2i32(ptr inreg %sbase, i32 %voffs ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2003,7 +2003,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v2i32(ptr inreg %sbase, i32 %voffs ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2026,7 +2026,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v2i32_immneg128(ptr inreg %sbase, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2037,7 +2037,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v2i32_immneg128(ptr inreg %sbase, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2061,7 +2061,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v4i16(ptr inreg %sbase, i32 %voffs ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2072,7 +2072,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v4i16(ptr inreg %sbase, i32 %voffs ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2095,7 +2095,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v4i16_immneg128(ptr inreg %sbase, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2106,7 +2106,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v4i16_immneg128(ptr inreg %sbase, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2130,7 +2130,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v4f16(ptr inreg %sbase, i32 %voffs ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2141,7 +2141,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v4f16(ptr inreg %sbase, i32 %voffs ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2164,7 +2164,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v4f16_immneg128(ptr inreg %sbase, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2175,7 +2175,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_v4f16_immneg128(ptr inreg %sbase, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2199,7 +2199,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_p1(ptr inreg %sbase, i32 %voffset) ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2210,7 +2210,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_p1(ptr inreg %sbase, i32 %voffset) ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2234,7 +2234,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_p1_immneg128(ptr inreg %sbase, i32 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2245,7 +2245,7 @@ define amdgpu_ps <2 x float> @flat_load_saddr_p1_immneg128(ptr inreg %sbase, i32 ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2270,7 +2270,7 @@ define amdgpu_ps <3 x float> @flat_load_saddr_v3f32(ptr inreg %sbase, i32 %voffs ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b96 v[0:2], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2281,7 +2281,7 @@ define amdgpu_ps <3 x float> @flat_load_saddr_v3f32(ptr inreg %sbase, i32 %voffs ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2303,7 +2303,7 @@ define amdgpu_ps <3 x float> @flat_load_saddr_v3f32_immneg128(ptr inreg %sbase, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b96 v[0:2], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2314,7 +2314,7 @@ define amdgpu_ps <3 x float> @flat_load_saddr_v3f32_immneg128(ptr inreg %sbase, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2337,7 +2337,7 @@ define amdgpu_ps <3 x float> @flat_load_saddr_v3i32(ptr inreg %sbase, i32 %voffs ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b96 v[0:2], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2348,7 +2348,7 @@ define amdgpu_ps <3 x float> @flat_load_saddr_v3i32(ptr inreg %sbase, i32 %voffs ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2371,7 +2371,7 @@ define amdgpu_ps <3 x float> @flat_load_saddr_v3i32_immneg128(ptr inreg %sbase, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b96 v[0:2], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2382,7 +2382,7 @@ define amdgpu_ps <3 x float> @flat_load_saddr_v3i32_immneg128(ptr inreg %sbase, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2406,7 +2406,7 @@ define amdgpu_ps <6 x half> @flat_load_saddr_v6f16(ptr inreg %sbase, i32 %voffse ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b96 v[0:2], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2417,7 +2417,7 @@ define amdgpu_ps <6 x half> @flat_load_saddr_v6f16(ptr inreg %sbase, i32 %voffse ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2439,7 +2439,7 @@ define amdgpu_ps <6 x half> @flat_load_saddr_v6f16_immneg128(ptr inreg %sbase, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b96 v[0:2], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2450,7 +2450,7 @@ define amdgpu_ps <6 x half> @flat_load_saddr_v6f16_immneg128(ptr inreg %sbase, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2473,7 +2473,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4f32(ptr inreg %sbase, i32 %voffs ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b128 v[0:3], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2484,7 +2484,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4f32(ptr inreg %sbase, i32 %voffs ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2506,7 +2506,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4f32_immneg128(ptr inreg %sbase, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2517,7 +2517,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4f32_immneg128(ptr inreg %sbase, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2540,7 +2540,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4i32(ptr inreg %sbase, i32 %voffs ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b128 v[0:3], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2551,7 +2551,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4i32(ptr inreg %sbase, i32 %voffs ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2574,7 +2574,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4i32_immneg128(ptr inreg %sbase, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2585,7 +2585,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4i32_immneg128(ptr inreg %sbase, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2609,7 +2609,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v2i64(ptr inreg %sbase, i32 %voffs ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b128 v[0:3], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2620,7 +2620,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v2i64(ptr inreg %sbase, i32 %voffs ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2643,7 +2643,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v2i64_immneg128(ptr inreg %sbase, ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2654,7 +2654,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v2i64_immneg128(ptr inreg %sbase, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2678,7 +2678,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_i128(ptr inreg %sbase, i32 %voffse ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b128 v[0:3], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2689,7 +2689,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_i128(ptr inreg %sbase, i32 %voffse ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2712,7 +2712,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_i128_immneg128(ptr inreg %sbase, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2723,7 +2723,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_i128_immneg128(ptr inreg %sbase, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2747,7 +2747,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v2p1(ptr inreg %sbase, i32 %voffse ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b128 v[0:3], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2758,7 +2758,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v2p1(ptr inreg %sbase, i32 %voffse ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2782,7 +2782,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v2p1_immneg128(ptr inreg %sbase, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2793,7 +2793,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v2p1_immneg128(ptr inreg %sbase, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2818,7 +2818,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4p3(ptr inreg %sbase, i32 %voffse ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b128 v[0:3], v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2829,7 +2829,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4p3(ptr inreg %sbase, i32 %voffse ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2853,7 +2853,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4p3_immneg128(ptr inreg %sbase, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b128 v[0:3], v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2864,7 +2864,7 @@ define amdgpu_ps <4 x float> @flat_load_saddr_v4p3_immneg128(ptr inreg %sbase, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2893,7 +2893,7 @@ define amdgpu_ps float @flat_sextload_saddr_i8(ptr inreg %sbase, i32 %voffset) { ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_i8 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2904,7 +2904,7 @@ define amdgpu_ps float @flat_sextload_saddr_i8(ptr inreg %sbase, i32 %voffset) { ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2928,7 +2928,7 @@ define amdgpu_ps float @flat_sextload_saddr_i8_immneg128(ptr inreg %sbase, i32 % ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_i8 v0, v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2939,7 +2939,7 @@ define amdgpu_ps float @flat_sextload_saddr_i8_immneg128(ptr inreg %sbase, i32 % ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2964,7 +2964,7 @@ define amdgpu_ps float @flat_sextload_saddr_i16(ptr inreg %sbase, i32 %voffset) ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_i16 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -2975,7 +2975,7 @@ define amdgpu_ps float @flat_sextload_saddr_i16(ptr inreg %sbase, i32 %voffset) ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -2999,7 +2999,7 @@ define amdgpu_ps float @flat_sextload_saddr_i16_immneg128(ptr inreg %sbase, i32 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_i16 v0, v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -3010,7 +3010,7 @@ define amdgpu_ps float @flat_sextload_saddr_i16_immneg128(ptr inreg %sbase, i32 ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -3035,7 +3035,7 @@ define amdgpu_ps float @flat_zextload_saddr_i8(ptr inreg %sbase, i32 %voffset) { ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -3046,7 +3046,7 @@ define amdgpu_ps float @flat_zextload_saddr_i8(ptr inreg %sbase, i32 %voffset) { ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -3070,7 +3070,7 @@ define amdgpu_ps float @flat_zextload_saddr_i8_immneg128(ptr inreg %sbase, i32 % ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u8 v0, v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -3081,7 +3081,7 @@ define amdgpu_ps float @flat_zextload_saddr_i8_immneg128(ptr inreg %sbase, i32 % ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -3106,7 +3106,7 @@ define amdgpu_ps float @flat_zextload_saddr_i16(ptr inreg %sbase, i32 %voffset) ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u16 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -3117,7 +3117,7 @@ define amdgpu_ps float @flat_zextload_saddr_i16(ptr inreg %sbase, i32 %voffset) ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -3141,7 +3141,7 @@ define amdgpu_ps float @flat_zextload_saddr_i16_immneg128(ptr inreg %sbase, i32 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u16 v0, v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -3152,7 +3152,7 @@ define amdgpu_ps float @flat_zextload_saddr_i16_immneg128(ptr inreg %sbase, i32 ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -3181,7 +3181,7 @@ define amdgpu_ps float @atomic_flat_load_saddr_i32(ptr inreg %sbase, i32 %voffse ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[0:1] scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: global_inv scope:SCOPE_SYS @@ -3194,7 +3194,7 @@ define amdgpu_ps float @atomic_flat_load_saddr_i32(ptr inreg %sbase, i32 %voffse ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -3219,7 +3219,7 @@ define amdgpu_ps float @atomic_flat_load_saddr_i32_immneg128(ptr inreg %sbase, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b32 v0, v[0:1] offset:-128 scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: global_inv scope:SCOPE_SYS @@ -3232,7 +3232,7 @@ define amdgpu_ps float @atomic_flat_load_saddr_i32_immneg128(ptr inreg %sbase, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -3258,7 +3258,7 @@ define amdgpu_ps <2 x float> @atomic_flat_load_saddr_i64(ptr inreg %sbase, i32 % ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: global_inv scope:SCOPE_SYS @@ -3271,7 +3271,7 @@ define amdgpu_ps <2 x float> @atomic_flat_load_saddr_i64(ptr inreg %sbase, i32 % ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -3296,7 +3296,7 @@ define amdgpu_ps <2 x float> @atomic_flat_load_saddr_i64_immneg128(ptr inreg %sb ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_b64 v[0:1], v[0:1] offset:-128 scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: global_inv scope:SCOPE_SYS @@ -3309,7 +3309,7 @@ define amdgpu_ps <2 x float> @atomic_flat_load_saddr_i64_immneg128(ptr inreg %sb ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -3339,7 +3339,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi(ptr inreg %sbase ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u16 v0, v[0:1] ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -3350,7 +3350,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi(ptr inreg %sbase ; GFX1250-GISEL-FAKE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-FAKE16-NEXT: v_nop ; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3367,7 +3367,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi(ptr inreg %sbase ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-TRUE16-NEXT: v_nop ; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -3391,7 +3391,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi_immneg128(ptr in ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_load_u16 v0, v[0:1] offset:-128 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -3402,7 +3402,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi_immneg128(ptr in ; GFX1250-GISEL-FAKE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-FAKE16-NEXT: v_nop ; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3419,7 +3419,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_undef_hi_immneg128(ptr in ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-TRUE16-NEXT: v_nop ; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -3444,7 +3444,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zero_hi(ptr inreg %sbase, ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_u16 v0, v[2:3] ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 @@ -3456,7 +3456,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zero_hi(ptr inreg %sbase, ; GFX1250-GISEL-FAKE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-FAKE16-NEXT: v_nop ; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3473,7 +3473,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zero_hi(ptr inreg %sbase, ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v0, v[2:3] ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l @@ -3485,7 +3485,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zero_hi(ptr inreg %sbase, ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-TRUE16-NEXT: v_nop ; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3510,7 +3510,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zero_hi_immneg128(ptr inr ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_u16 v0, v[2:3] offset:-128 ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 @@ -3522,7 +3522,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zero_hi_immneg128(ptr inr ; GFX1250-GISEL-FAKE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-FAKE16-NEXT: v_nop ; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3539,7 +3539,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zero_hi_immneg128(ptr inr ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v0, v[2:3] offset:-128 ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l @@ -3551,7 +3551,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zero_hi_immneg128(ptr inr ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-TRUE16-NEXT: v_nop ; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3577,7 +3577,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_reg_hi(ptr inreg %sbase, ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_u16 v0, v[4:5] ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v2 @@ -3589,7 +3589,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_reg_hi(ptr inreg %sbase, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3606,7 +3606,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_reg_hi(ptr inreg %sbase, ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v0, v[4:5] ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h @@ -3628,7 +3628,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_reg_hi_immneg128(ptr inre ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_u16 v0, v[4:5] offset:-128 ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v2 @@ -3640,7 +3640,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_reg_hi_immneg128(ptr inre ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3657,7 +3657,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_reg_hi_immneg128(ptr inre ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v0, v[4:5] offset:-128 ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h @@ -3680,7 +3680,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zexti8_reg_hi(ptr inreg % ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[4:5] ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v2 @@ -3692,7 +3692,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zexti8_reg_hi(ptr inreg % ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3709,7 +3709,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zexti8_reg_hi(ptr inreg % ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_u8 v0, v[4:5] ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h @@ -3732,7 +3732,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128(p ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[4:5] offset:-128 ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v2 @@ -3744,7 +3744,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128(p ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3761,7 +3761,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128(p ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_u8 v0, v[4:5] offset:-128 ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h @@ -3785,7 +3785,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_sexti8_reg_hi(ptr inreg % ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_i8 v0, v[4:5] ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v2 @@ -3797,7 +3797,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_sexti8_reg_hi(ptr inreg % ; GFX1250-GISEL-FAKE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-FAKE16-NEXT: v_nop ; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3816,7 +3816,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_sexti8_reg_hi(ptr inreg % ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_i8 v0, v[4:5] ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h @@ -3828,7 +3828,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_sexti8_reg_hi(ptr inreg % ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-TRUE16-NEXT: v_nop ; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3856,7 +3856,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128(p ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_i8 v0, v[4:5] offset:-128 ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_bfi_b32 v0, 0xffff, v0, v2 @@ -3868,7 +3868,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128(p ; GFX1250-GISEL-FAKE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-FAKE16-NEXT: v_nop ; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3887,7 +3887,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128(p ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_i8 v0, v[4:5] offset:-128 ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v2.h @@ -3899,7 +3899,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128(p ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-TRUE16-NEXT: v_nop ; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3932,7 +3932,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi(ptr inreg %sbase ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_u16 v0, v[2:3] ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 @@ -3944,7 +3944,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi(ptr inreg %sbase ; GFX1250-GISEL-FAKE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-FAKE16-NEXT: v_nop ; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-FAKE16-NEXT: v_and_b32_e64 v1, 0xffff, s0 ; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -3962,7 +3962,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi(ptr inreg %sbase ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v0, v[2:3] ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l @@ -3974,7 +3974,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi(ptr inreg %sbase ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-TRUE16-NEXT: v_nop ; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -3999,7 +3999,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi_immneg128(ptr in ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_u16 v0, v[2:3] offset:-128 ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 @@ -4011,7 +4011,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi_immneg128(ptr in ; GFX1250-GISEL-FAKE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-FAKE16-NEXT: v_nop ; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-FAKE16-NEXT: v_and_b32_e64 v1, 0xffff, s0 ; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 @@ -4029,7 +4029,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi_immneg128(ptr in ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v0, v[2:3] offset:-128 ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v0.h, v0.l @@ -4041,7 +4041,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_undef_hi_immneg128(ptr in ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-TRUE16-NEXT: v_nop ; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4067,7 +4067,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zero_hi(ptr inreg %sbase, ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_u16 v0, v[2:3] ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, 0, 0x5040100 @@ -4079,7 +4079,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zero_hi(ptr inreg %sbase, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4096,7 +4096,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zero_hi(ptr inreg %sbase, ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v1, v[2:3] ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1 @@ -4118,7 +4118,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zero_hi_immneg128(ptr inr ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_u16 v0, v[2:3] offset:-128 ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, 0, 0x5040100 @@ -4130,7 +4130,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zero_hi_immneg128(ptr inr ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4147,7 +4147,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zero_hi_immneg128(ptr inr ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[2:3], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[2:3], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v1, v[2:3] offset:-128 ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v1 @@ -4170,7 +4170,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_reg_hi(ptr inreg %sbase, ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_u16 v0, v[4:5] ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 @@ -4182,7 +4182,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_reg_hi(ptr inreg %sbase, ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4201,7 +4201,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_reg_hi(ptr inreg %sbase, ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v0, v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l @@ -4224,7 +4224,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_reg_hi_immneg128(ptr inre ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_u16 v0, v[4:5] offset:-128 ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 @@ -4236,7 +4236,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_reg_hi_immneg128(ptr inre ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4255,7 +4255,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_reg_hi_immneg128(ptr inre ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_u16 v0, v[0:1] offset:-128 ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l @@ -4279,7 +4279,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zexti8_reg_hi(ptr inreg % ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[4:5] ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 @@ -4291,7 +4291,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zexti8_reg_hi(ptr inreg % ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4310,7 +4310,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zexti8_reg_hi(ptr inreg % ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_u8 v0, v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l @@ -4334,7 +4334,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128(p ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_u8 v0, v[4:5] offset:-128 ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 @@ -4346,7 +4346,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128(p ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4365,7 +4365,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128(p ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_u8 v0, v[0:1] offset:-128 ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l @@ -4390,7 +4390,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_sexti8_reg_hi(ptr inreg % ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_i8 v0, v[4:5] ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 @@ -4402,7 +4402,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_sexti8_reg_hi(ptr inreg % ; GFX1250-GISEL-FAKE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-FAKE16-NEXT: v_nop ; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4422,7 +4422,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_sexti8_reg_hi(ptr inreg % ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_i8 v0, v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l @@ -4435,7 +4435,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_sexti8_reg_hi(ptr inreg % ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-TRUE16-NEXT: v_nop ; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4464,7 +4464,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128(p ; GFX1250-SDAG-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-FAKE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[0:1] +; GFX1250-SDAG-FAKE16-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[0:1] ; GFX1250-SDAG-FAKE16-NEXT: flat_load_i8 v0, v[4:5] offset:-128 ; GFX1250-SDAG-FAKE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-FAKE16-NEXT: v_perm_b32 v0, v0, v2, 0x5040100 @@ -4476,7 +4476,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128(p ; GFX1250-GISEL-FAKE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-FAKE16-NEXT: v_nop ; GFX1250-GISEL-FAKE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-FAKE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-FAKE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4496,7 +4496,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128(p ; GFX1250-SDAG-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-TRUE16-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_3) | instid1(VALU_DEP_1) -; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-TRUE16-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-TRUE16-NEXT: flat_load_i8 v0, v[0:1] offset:-128 ; GFX1250-SDAG-TRUE16-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-TRUE16-NEXT: v_mov_b16_e32 v2.h, v0.l @@ -4509,7 +4509,7 @@ define amdgpu_ps <2 x half> @flat_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128(p ; GFX1250-GISEL-TRUE16-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-TRUE16-NEXT: v_nop ; GFX1250-GISEL-TRUE16-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-TRUE16-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-TRUE16-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -4589,15 +4589,15 @@ define amdgpu_ps void @flat_addr_64bit_lsr_iv(ptr inreg %arg) { ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-SDAG-NEXT: s_movk_i32 s0, 0x100 +; GFX1250-SDAG-NEXT: s_movk_i32 s2, 0x100 ; GFX1250-SDAG-NEXT: .LBB117_1: ; %bb3 ; GFX1250-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0 -; GFX1250-SDAG-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS +; GFX1250-SDAG-NEXT: flat_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0 -; GFX1250-SDAG-NEXT: s_add_co_i32 s0, s0, -1 -; GFX1250-SDAG-NEXT: s_add_nc_u64 s[2:3], s[2:3], 4 -; GFX1250-SDAG-NEXT: s_cmp_eq_u32 s0, 0 +; GFX1250-SDAG-NEXT: s_add_co_i32 s2, s2, -1 +; GFX1250-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], 4 +; GFX1250-SDAG-NEXT: s_cmp_eq_u32 s2, 0 ; GFX1250-SDAG-NEXT: s_cbranch_scc0 .LBB117_1 ; GFX1250-SDAG-NEXT: ; %bb.2: ; %bb2 ; GFX1250-SDAG-NEXT: s_endpgm @@ -4609,16 +4609,16 @@ define amdgpu_ps void @flat_addr_64bit_lsr_iv(ptr inreg %arg) { ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-GISEL-NEXT: s_movk_i32 s0, 0x100 +; GFX1250-GISEL-NEXT: s_movk_i32 s2, 0x100 ; GFX1250-GISEL-NEXT: .LBB117_1: ; %bb3 ; GFX1250-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0 -; GFX1250-GISEL-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS +; GFX1250-GISEL-NEXT: flat_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS ; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0 -; GFX1250-GISEL-NEXT: s_add_co_i32 s0, s0, -1 -; GFX1250-GISEL-NEXT: s_add_co_u32 s2, s2, 4 -; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s3, s3, 0 -; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s0, 0 +; GFX1250-GISEL-NEXT: s_add_co_i32 s2, s2, -1 +; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s0, 4 +; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0 +; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s2, 0 ; GFX1250-GISEL-NEXT: s_cbranch_scc0 .LBB117_1 ; GFX1250-GISEL-NEXT: ; %bb.2: ; %bb2 ; GFX1250-GISEL-NEXT: s_endpgm @@ -4648,17 +4648,17 @@ define amdgpu_ps void @flat_addr_64bit_lsr_iv_multiload(ptr inreg %arg, ptr inre ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-SDAG-NEXT: s_movk_i32 s0, 0x100 +; GFX1250-SDAG-NEXT: s_movk_i32 s2, 0x100 ; GFX1250-SDAG-NEXT: .LBB118_1: ; %bb3 ; GFX1250-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-SDAG-NEXT: s_wait_dscnt 0x0 -; GFX1250-SDAG-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS +; GFX1250-SDAG-NEXT: flat_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-SDAG-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS +; GFX1250-SDAG-NEXT: flat_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0 -; GFX1250-SDAG-NEXT: s_add_co_i32 s0, s0, -1 -; GFX1250-SDAG-NEXT: s_add_nc_u64 s[2:3], s[2:3], 4 -; GFX1250-SDAG-NEXT: s_cmp_eq_u32 s0, 0 +; GFX1250-SDAG-NEXT: s_add_co_i32 s2, s2, -1 +; GFX1250-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], 4 +; GFX1250-SDAG-NEXT: s_cmp_eq_u32 s2, 0 ; GFX1250-SDAG-NEXT: s_cbranch_scc0 .LBB118_1 ; GFX1250-SDAG-NEXT: ; %bb.2: ; %bb2 ; GFX1250-SDAG-NEXT: s_endpgm @@ -4670,18 +4670,18 @@ define amdgpu_ps void @flat_addr_64bit_lsr_iv_multiload(ptr inreg %arg, ptr inre ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v0, 0 -; GFX1250-GISEL-NEXT: s_movk_i32 s0, 0x100 +; GFX1250-GISEL-NEXT: s_movk_i32 s2, 0x100 ; GFX1250-GISEL-NEXT: .LBB118_1: ; %bb3 ; GFX1250-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX1250-GISEL-NEXT: s_wait_dscnt 0x0 -; GFX1250-GISEL-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS +; GFX1250-GISEL-NEXT: flat_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS ; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 -; GFX1250-GISEL-NEXT: flat_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS +; GFX1250-GISEL-NEXT: flat_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS ; GFX1250-GISEL-NEXT: s_wait_loadcnt 0x0 -; GFX1250-GISEL-NEXT: s_add_co_i32 s0, s0, -1 -; GFX1250-GISEL-NEXT: s_add_co_u32 s2, s2, 4 -; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s3, s3, 0 -; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s0, 0 +; GFX1250-GISEL-NEXT: s_add_co_i32 s2, s2, -1 +; GFX1250-GISEL-NEXT: s_add_co_u32 s0, s0, 4 +; GFX1250-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0 +; GFX1250-GISEL-NEXT: s_cmp_eq_u32 s2, 0 ; GFX1250-GISEL-NEXT: s_cbranch_scc0 .LBB118_1 ; GFX1250-GISEL-NEXT: ; %bb.2: ; %bb2 ; GFX1250-GISEL-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll b/llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll index 0e90b55dabd326..bb0ec48bc51ad9 100644 --- a/llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll +++ b/llvm/test/CodeGen/AMDGPU/flat-saddr-store.ll @@ -17,7 +17,7 @@ define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr(ptr inreg %sbase, ptr %voff ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v5, 0 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[4:5] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[4:5] ; GFX1250-SDAG-NEXT: flat_store_b8 v[4:5], v2 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -28,7 +28,7 @@ define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr(ptr inreg %sbase, ptr %voff ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1] -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1] ; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v4, v0 @@ -54,7 +54,7 @@ define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr_offset_2047(ptr inreg %sbas ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v5, 0 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[4:5] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[4:5] ; GFX1250-SDAG-NEXT: flat_store_b8 v[4:5], v2 offset:2047 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -65,7 +65,7 @@ define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr_offset_2047(ptr inreg %sbas ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1] -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1] ; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v4, v0 @@ -92,7 +92,7 @@ define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr_offset_neg2048(ptr inreg %s ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v5, 0 ; GFX1250-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[2:3], v[4:5] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[4:5], s[0:1], v[4:5] ; GFX1250-SDAG-NEXT: flat_store_b8 v[4:5], v2 offset:-2048 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -103,7 +103,7 @@ define amdgpu_ps void @flat_store_saddr_i8_zext_vgpr_offset_neg2048(ptr inreg %s ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: flat_load_b32 v0, v[0:1] -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[4:5], s[0:1] ; GFX1250-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v4, vcc_lo, v4, v0 @@ -210,7 +210,7 @@ define amdgpu_ps void @flat_store_saddr_i16_zext_vgpr(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b16 v[0:1], v2 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -220,7 +220,7 @@ define amdgpu_ps void @flat_store_saddr_i16_zext_vgpr(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -241,7 +241,7 @@ define amdgpu_ps void @flat_store_saddr_i16_zext_vgpr_offset_neg128(ptr inreg %s ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b16 v[0:1], v2 offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -251,7 +251,7 @@ define amdgpu_ps void @flat_store_saddr_i16_zext_vgpr_offset_neg128(ptr inreg %s ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -273,7 +273,7 @@ define amdgpu_ps void @flat_store_saddr_f16_zext_vgpr(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b16 v[0:1], v2 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -283,7 +283,7 @@ define amdgpu_ps void @flat_store_saddr_f16_zext_vgpr(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -304,7 +304,7 @@ define amdgpu_ps void @flat_store_saddr_f16_zext_vgpr_offset_neg128(ptr inreg %s ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b16 v[0:1], v2 offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -314,7 +314,7 @@ define amdgpu_ps void @flat_store_saddr_f16_zext_vgpr_offset_neg128(ptr inreg %s ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -336,7 +336,7 @@ define amdgpu_ps void @flat_store_saddr_i32_zext_vgpr(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b32 v[0:1], v2 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -346,7 +346,7 @@ define amdgpu_ps void @flat_store_saddr_i32_zext_vgpr(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -367,7 +367,7 @@ define amdgpu_ps void @flat_store_saddr_i32_zext_vgpr_offset_neg128(ptr inreg %s ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b32 v[0:1], v2 offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -377,7 +377,7 @@ define amdgpu_ps void @flat_store_saddr_i32_zext_vgpr_offset_neg128(ptr inreg %s ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -399,7 +399,7 @@ define amdgpu_ps void @flat_store_saddr_f32_zext_vgpr(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b32 v[0:1], v2 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -409,7 +409,7 @@ define amdgpu_ps void @flat_store_saddr_f32_zext_vgpr(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -430,7 +430,7 @@ define amdgpu_ps void @flat_store_saddr_f32_zext_vgpr_offset_neg128(ptr inreg %s ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b32 v[0:1], v2 offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -440,7 +440,7 @@ define amdgpu_ps void @flat_store_saddr_f32_zext_vgpr_offset_neg128(ptr inreg %s ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -462,7 +462,7 @@ define amdgpu_ps void @flat_store_saddr_p3_zext_vgpr(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b32 v[0:1], v2 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -472,7 +472,7 @@ define amdgpu_ps void @flat_store_saddr_p3_zext_vgpr(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -493,7 +493,7 @@ define amdgpu_ps void @flat_store_saddr_p3_zext_vgpr_offset_neg128(ptr inreg %sb ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b32 v[0:1], v2 offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -503,7 +503,7 @@ define amdgpu_ps void @flat_store_saddr_p3_zext_vgpr_offset_neg128(ptr inreg %sb ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -526,7 +526,7 @@ define amdgpu_ps void @flat_store_saddr_i64_zext_vgpr(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -537,7 +537,7 @@ define amdgpu_ps void @flat_store_saddr_i64_zext_vgpr(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -559,7 +559,7 @@ define amdgpu_ps void @flat_store_saddr_i64_zext_vgpr_offset_neg128(ptr inreg %s ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -570,7 +570,7 @@ define amdgpu_ps void @flat_store_saddr_i64_zext_vgpr_offset_neg128(ptr inreg %s ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -593,7 +593,7 @@ define amdgpu_ps void @flat_store_saddr_f64_zext_vgpr(ptr inreg %sbase, i32 %vof ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -604,7 +604,7 @@ define amdgpu_ps void @flat_store_saddr_f64_zext_vgpr(ptr inreg %sbase, i32 %vof ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -626,7 +626,7 @@ define amdgpu_ps void @flat_store_saddr_f64_zext_vgpr_offset_neg128(ptr inreg %s ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -637,7 +637,7 @@ define amdgpu_ps void @flat_store_saddr_f64_zext_vgpr_offset_neg128(ptr inreg %s ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -660,7 +660,7 @@ define amdgpu_ps void @flat_store_saddr_v2i32_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -671,7 +671,7 @@ define amdgpu_ps void @flat_store_saddr_v2i32_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -693,7 +693,7 @@ define amdgpu_ps void @flat_store_saddr_v2i32_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -704,7 +704,7 @@ define amdgpu_ps void @flat_store_saddr_v2i32_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -727,7 +727,7 @@ define amdgpu_ps void @flat_store_saddr_v2f32_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -738,7 +738,7 @@ define amdgpu_ps void @flat_store_saddr_v2f32_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -760,7 +760,7 @@ define amdgpu_ps void @flat_store_saddr_v2f32_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -771,7 +771,7 @@ define amdgpu_ps void @flat_store_saddr_v2f32_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -794,7 +794,7 @@ define amdgpu_ps void @flat_store_saddr_v4i16_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -805,7 +805,7 @@ define amdgpu_ps void @flat_store_saddr_v4i16_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -827,7 +827,7 @@ define amdgpu_ps void @flat_store_saddr_v4i16_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -838,7 +838,7 @@ define amdgpu_ps void @flat_store_saddr_v4i16_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -861,7 +861,7 @@ define amdgpu_ps void @flat_store_saddr_v4f16_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -872,7 +872,7 @@ define amdgpu_ps void @flat_store_saddr_v4f16_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -894,7 +894,7 @@ define amdgpu_ps void @flat_store_saddr_v4f16_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -905,7 +905,7 @@ define amdgpu_ps void @flat_store_saddr_v4f16_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -928,7 +928,7 @@ define amdgpu_ps void @flat_store_saddr_p1_zext_vgpr(ptr inreg %sbase, i32 %voff ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -939,7 +939,7 @@ define amdgpu_ps void @flat_store_saddr_p1_zext_vgpr(ptr inreg %sbase, i32 %voff ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -961,7 +961,7 @@ define amdgpu_ps void @flat_store_saddr_p1_zext_vgpr_offset_neg128(ptr inreg %sb ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -972,7 +972,7 @@ define amdgpu_ps void @flat_store_saddr_p1_zext_vgpr_offset_neg128(ptr inreg %sb ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -995,7 +995,7 @@ define amdgpu_ps void @flat_store_saddr_v3i32_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2 ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b96 v[0:1], v[2:4] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1007,7 +1007,7 @@ define amdgpu_ps void @flat_store_saddr_v3i32_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1029,7 +1029,7 @@ define amdgpu_ps void @flat_store_saddr_v3i32_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2 ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b96 v[0:1], v[2:4] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1041,7 +1041,7 @@ define amdgpu_ps void @flat_store_saddr_v3i32_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1064,7 +1064,7 @@ define amdgpu_ps void @flat_store_saddr_v3f32_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2 ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b96 v[0:1], v[2:4] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1076,7 +1076,7 @@ define amdgpu_ps void @flat_store_saddr_v3f32_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1098,7 +1098,7 @@ define amdgpu_ps void @flat_store_saddr_v3f32_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2 ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b96 v[0:1], v[2:4] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1110,7 +1110,7 @@ define amdgpu_ps void @flat_store_saddr_v3f32_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1133,7 +1133,7 @@ define amdgpu_ps void @flat_store_saddr_v6i16_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2 ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b96 v[0:1], v[2:4] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1145,7 +1145,7 @@ define amdgpu_ps void @flat_store_saddr_v6i16_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1167,7 +1167,7 @@ define amdgpu_ps void @flat_store_saddr_v6i16_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2 ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b96 v[0:1], v[2:4] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1179,7 +1179,7 @@ define amdgpu_ps void @flat_store_saddr_v6i16_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1202,7 +1202,7 @@ define amdgpu_ps void @flat_store_saddr_v6f16_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2 ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b96 v[0:1], v[2:4] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1214,7 +1214,7 @@ define amdgpu_ps void @flat_store_saddr_v6f16_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1236,7 +1236,7 @@ define amdgpu_ps void @flat_store_saddr_v6f16_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v4, v3 :: v_dual_mov_b32 v3, v2 ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b96 v[0:1], v[2:4] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1248,7 +1248,7 @@ define amdgpu_ps void @flat_store_saddr_v6f16_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 ; GFX1250-GISEL-NEXT: v_mov_b32_e32 v6, v3 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1272,7 +1272,7 @@ define amdgpu_ps void @flat_store_saddr_v4i32_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1284,7 +1284,7 @@ define amdgpu_ps void @flat_store_saddr_v4i32_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1307,7 +1307,7 @@ define amdgpu_ps void @flat_store_saddr_v4i32_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1319,7 +1319,7 @@ define amdgpu_ps void @flat_store_saddr_v4i32_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1343,7 +1343,7 @@ define amdgpu_ps void @flat_store_saddr_v4f32_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1355,7 +1355,7 @@ define amdgpu_ps void @flat_store_saddr_v4f32_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1378,7 +1378,7 @@ define amdgpu_ps void @flat_store_saddr_v4f32_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1390,7 +1390,7 @@ define amdgpu_ps void @flat_store_saddr_v4f32_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1414,7 +1414,7 @@ define amdgpu_ps void @flat_store_saddr_v2i64_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1426,7 +1426,7 @@ define amdgpu_ps void @flat_store_saddr_v2i64_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1449,7 +1449,7 @@ define amdgpu_ps void @flat_store_saddr_v2i64_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1461,7 +1461,7 @@ define amdgpu_ps void @flat_store_saddr_v2i64_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1485,7 +1485,7 @@ define amdgpu_ps void @flat_store_saddr_v2f64_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1497,7 +1497,7 @@ define amdgpu_ps void @flat_store_saddr_v2f64_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1520,7 +1520,7 @@ define amdgpu_ps void @flat_store_saddr_v2f64_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1532,7 +1532,7 @@ define amdgpu_ps void @flat_store_saddr_v2f64_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1556,7 +1556,7 @@ define amdgpu_ps void @flat_store_saddr_v8i16_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1568,7 +1568,7 @@ define amdgpu_ps void @flat_store_saddr_v8i16_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1591,7 +1591,7 @@ define amdgpu_ps void @flat_store_saddr_v8i16_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1603,7 +1603,7 @@ define amdgpu_ps void @flat_store_saddr_v8i16_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1627,7 +1627,7 @@ define amdgpu_ps void @flat_store_saddr_v8f16_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1639,7 +1639,7 @@ define amdgpu_ps void @flat_store_saddr_v8f16_zext_vgpr(ptr inreg %sbase, i32 %v ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1662,7 +1662,7 @@ define amdgpu_ps void @flat_store_saddr_v8f16_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1674,7 +1674,7 @@ define amdgpu_ps void @flat_store_saddr_v8f16_zext_vgpr_offset_neg128(ptr inreg ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1698,7 +1698,7 @@ define amdgpu_ps void @flat_store_saddr_v2p1_zext_vgpr(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1710,7 +1710,7 @@ define amdgpu_ps void @flat_store_saddr_v2p1_zext_vgpr(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1733,7 +1733,7 @@ define amdgpu_ps void @flat_store_saddr_v2p1_zext_vgpr_offset_neg128(ptr inreg % ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1745,7 +1745,7 @@ define amdgpu_ps void @flat_store_saddr_v2p1_zext_vgpr_offset_neg128(ptr inreg % ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1769,7 +1769,7 @@ define amdgpu_ps void @flat_store_saddr_v4p3_zext_vgpr(ptr inreg %sbase, i32 %vo ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1781,7 +1781,7 @@ define amdgpu_ps void @flat_store_saddr_v4p3_zext_vgpr(ptr inreg %sbase, i32 %vo ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1804,7 +1804,7 @@ define amdgpu_ps void @flat_store_saddr_v4p3_zext_vgpr_offset_neg128(ptr inreg % ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_b128 v[0:1], v[2:5] offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -1816,7 +1816,7 @@ define amdgpu_ps void @flat_store_saddr_v4p3_zext_vgpr_offset_neg128(ptr inreg % ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v6, v1 :: v_dual_mov_b32 v7, v2 ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v8, v3 :: v_dual_mov_b32 v9, v4 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1842,7 +1842,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i32_zext_vgpr(ptr inreg %sbase, i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_store_b32 v[0:1], v2 scope:SCOPE_SYS @@ -1854,7 +1854,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i32_zext_vgpr(ptr inreg %sbase, i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -1877,7 +1877,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i32_zext_vgpr_offset_neg128(ptr i ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_store_b32 v[0:1], v2 offset:-128 scope:SCOPE_SYS @@ -1889,7 +1889,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i32_zext_vgpr_offset_neg128(ptr i ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -1914,7 +1914,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i64_zext_vgpr(ptr inreg %sbase, i ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] scope:SCOPE_SYS @@ -1927,7 +1927,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i64_zext_vgpr(ptr inreg %sbase, i ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1951,7 +1951,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i64_zext_vgpr_offset_neg128(ptr i ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v3, v2 :: v_dual_mov_b32 v2, v1 ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_wb scope:SCOPE_SYS ; GFX1250-SDAG-NEXT: s_wait_storecnt 0x0 ; GFX1250-SDAG-NEXT: flat_store_b64 v[0:1], v[2:3] offset:-128 scope:SCOPE_SYS @@ -1964,7 +1964,7 @@ define amdgpu_ps void @atomic_flat_store_saddr_i64_zext_vgpr_offset_neg128(ptr i ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-GISEL-NEXT: v_dual_mov_b32 v4, v1 :: v_dual_mov_b32 v5, v2 -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v3, vcc_lo @@ -1992,7 +1992,7 @@ define amdgpu_ps void @flat_store_saddr_i16_d16hi_zext_vgpr(ptr inreg %sbase, i3 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_d16_hi_b16 v[0:1], v2 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -2002,7 +2002,7 @@ define amdgpu_ps void @flat_store_saddr_i16_d16hi_zext_vgpr(ptr inreg %sbase, i3 ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -2024,7 +2024,7 @@ define amdgpu_ps void @flat_store_saddr_i16_d16hi_zext_vgpr_offset_neg128(ptr in ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_d16_hi_b16 v[0:1], v2 offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -2034,7 +2034,7 @@ define amdgpu_ps void @flat_store_saddr_i16_d16hi_zext_vgpr_offset_neg128(ptr in ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -2057,7 +2057,7 @@ define amdgpu_ps void @flat_store_saddr_i16_d16hi_trunci8_zext_vgpr(ptr inreg %s ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_d16_hi_b8 v[0:1], v2 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -2067,7 +2067,7 @@ define amdgpu_ps void @flat_store_saddr_i16_d16hi_trunci8_zext_vgpr(ptr inreg %s ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo @@ -2090,7 +2090,7 @@ define amdgpu_ps void @flat_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg12 ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-SDAG-NEXT: v_dual_mov_b32 v2, v1 :: v_dual_mov_b32 v1, 0 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: flat_store_d16_hi_b8 v[0:1], v2 offset:-128 ; GFX1250-SDAG-NEXT: s_endpgm ; @@ -2100,7 +2100,7 @@ define amdgpu_ps void @flat_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg12 ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v2, vcc_lo, v2, v0 ; GFX1250-GISEL-NEXT: v_add_co_ci_u32_e64 v3, null, 0, v3, vcc_lo diff --git a/llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_ptr_s_buffer_loads.ll b/llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_ptr_s_buffer_loads.ll index 015e42200f4e29..8cd44ad6ff5e3c 100644 --- a/llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_ptr_s_buffer_loads.ll +++ b/llvm/test/CodeGen/AMDGPU/gfx12_scalar_subword_ptr_s_buffer_loads.ll @@ -3,29 +3,13 @@ ; RUN: llc -mtriple=amdgpu12.00-mesa-mesa3d -global-isel=1 < %s | FileCheck -check-prefixes=GCN,GISEL %s define amdgpu_ps void @ptr_s_buffer_load_byte_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out) { -; DAG-LABEL: ptr_s_buffer_load_byte_imm_offset: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s7, s5 -; DAG-NEXT: s_mov_b32 s6, s4 -; DAG-NEXT: s_mov_b32 s5, s3 -; DAG-NEXT: s_mov_b32 s4, s2 -; DAG-NEXT: s_buffer_load_i8 s0, s[4:7], 0x4 -; DAG-NEXT: s_wait_kmcnt 0x0 -; DAG-NEXT: v_mov_b32_e32 v2, s0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_byte_imm_offset: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: s_buffer_load_i8 s0, s[0:3], 0x4 -; GISEL-NEXT: s_wait_kmcnt 0x0 -; GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_byte_imm_offset: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: s_buffer_load_i8 s0, s[0:3], 0x4 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) %src, i32 4, i32 0), !invariant.load !0 %sext = sext i8 %ld to i32 @@ -34,29 +18,13 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_byte_sgpr(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %offset) { -; DAG-LABEL: ptr_s_buffer_load_byte_sgpr: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s11, s5 -; DAG-NEXT: s_mov_b32 s10, s4 -; DAG-NEXT: s_mov_b32 s9, s3 -; DAG-NEXT: s_mov_b32 s8, s2 -; DAG-NEXT: s_buffer_load_i8 s0, s[8:11], s6 offset:0x0 -; DAG-NEXT: s_wait_kmcnt 0x0 -; DAG-NEXT: v_mov_b32_e32 v2, s0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_byte_sgpr: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: s_buffer_load_i8 s0, s[0:3], s6 offset:0x0 -; GISEL-NEXT: s_wait_kmcnt 0x0 -; GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_byte_sgpr: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: s_buffer_load_i8 s0, s[0:3], s4 offset:0x0 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 %sext = sext i8 %ld to i32 @@ -65,29 +33,13 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_byte_sgpr_or_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %in) { -; DAG-LABEL: ptr_s_buffer_load_byte_sgpr_or_imm_offset: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s11, s5 -; DAG-NEXT: s_mov_b32 s10, s4 -; DAG-NEXT: s_mov_b32 s9, s3 -; DAG-NEXT: s_mov_b32 s8, s2 -; DAG-NEXT: s_buffer_load_i8 s0, s[8:11], s6 offset:0x64 -; DAG-NEXT: s_wait_kmcnt 0x0 -; DAG-NEXT: v_mov_b32_e32 v2, s0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_byte_sgpr_or_imm_offset: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: s_buffer_load_i8 s0, s[0:3], s6 offset:0x64 -; GISEL-NEXT: s_wait_kmcnt 0x0 -; GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_byte_sgpr_or_imm_offset: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: s_buffer_load_i8 s0, s[0:3], s4 offset:0x64 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %off = add nuw nsw i32 %in, 100 %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) %src, i32 %off, i32 0), !invariant.load !0 @@ -97,27 +49,12 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_byte_sgpr_or_imm_offset_divergent(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) { -; DAG-LABEL: ptr_s_buffer_load_byte_sgpr_or_imm_offset_divergent: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s7, s5 -; DAG-NEXT: s_mov_b32 s6, s4 -; DAG-NEXT: s_mov_b32 s5, s3 -; DAG-NEXT: s_mov_b32 s4, s2 -; DAG-NEXT: buffer_load_i8 v2, v2, s[4:7], null offen -; DAG-NEXT: s_wait_loadcnt 0x0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_byte_sgpr_or_imm_offset_divergent: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: buffer_load_i8 v2, v2, s[0:3], null offen -; GISEL-NEXT: s_wait_loadcnt 0x0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_byte_sgpr_or_imm_offset_divergent: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: buffer_load_i8 v2, v2, s[0:3], null offen +; GCN-NEXT: s_wait_loadcnt 0x0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.i8(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 %sext = sext i8 %ld to i32 @@ -126,33 +63,15 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_ubyte_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out) { -; DAG-LABEL: ptr_s_buffer_load_ubyte_imm_offset: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s7, s5 -; DAG-NEXT: s_mov_b32 s6, s4 -; DAG-NEXT: s_mov_b32 s5, s3 -; DAG-NEXT: s_mov_b32 s4, s2 -; DAG-NEXT: s_buffer_load_u8 s0, s[4:7], 0x4 -; DAG-NEXT: s_wait_kmcnt 0x0 -; DAG-NEXT: s_and_b32 s0, s0, 0xff -; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; DAG-NEXT: v_mov_b32_e32 v2, s0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_ubyte_imm_offset: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: s_buffer_load_u8 s0, s[0:3], 0x4 -; GISEL-NEXT: s_wait_kmcnt 0x0 -; GISEL-NEXT: s_and_b32 s0, s0, 0xff -; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_ubyte_imm_offset: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: s_buffer_load_u8 s0, s[0:3], 0x4 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: s_and_b32 s0, s0, 0xff +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.u8(ptr addrspace(8) %src, i32 4, i32 0), !invariant.load !0 %zext = zext i8 %ld to i32 @@ -161,33 +80,15 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_ubyte_sgpr(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %offset) { -; DAG-LABEL: ptr_s_buffer_load_ubyte_sgpr: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s11, s5 -; DAG-NEXT: s_mov_b32 s10, s4 -; DAG-NEXT: s_mov_b32 s9, s3 -; DAG-NEXT: s_mov_b32 s8, s2 -; DAG-NEXT: s_buffer_load_u8 s0, s[8:11], s6 offset:0x0 -; DAG-NEXT: s_wait_kmcnt 0x0 -; DAG-NEXT: s_and_b32 s0, s0, 0xff -; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; DAG-NEXT: v_mov_b32_e32 v2, s0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_ubyte_sgpr: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: s_buffer_load_u8 s0, s[0:3], s6 offset:0x0 -; GISEL-NEXT: s_wait_kmcnt 0x0 -; GISEL-NEXT: s_and_b32 s0, s0, 0xff -; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_ubyte_sgpr: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: s_buffer_load_u8 s0, s[0:3], s4 offset:0x0 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: s_and_b32 s0, s0, 0xff +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.u8(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 %zext = zext i8 %ld to i32 @@ -196,33 +97,15 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_ubyte_sgpr_or_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %in) { -; DAG-LABEL: ptr_s_buffer_load_ubyte_sgpr_or_imm_offset: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s11, s5 -; DAG-NEXT: s_mov_b32 s10, s4 -; DAG-NEXT: s_mov_b32 s9, s3 -; DAG-NEXT: s_mov_b32 s8, s2 -; DAG-NEXT: s_buffer_load_u8 s0, s[8:11], s6 offset:0x64 -; DAG-NEXT: s_wait_kmcnt 0x0 -; DAG-NEXT: s_and_b32 s0, s0, 0xff -; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; DAG-NEXT: v_mov_b32_e32 v2, s0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_ubyte_sgpr_or_imm_offset: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: s_buffer_load_u8 s0, s[0:3], s6 offset:0x64 -; GISEL-NEXT: s_wait_kmcnt 0x0 -; GISEL-NEXT: s_and_b32 s0, s0, 0xff -; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_ubyte_sgpr_or_imm_offset: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: s_buffer_load_u8 s0, s[0:3], s4 offset:0x64 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: s_and_b32 s0, s0, 0xff +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %off = add nuw nsw i32 %in, 100 %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.u8(ptr addrspace(8) %src, i32 %off, i32 0), !invariant.load !0 @@ -232,27 +115,12 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_ubyte_sgpr_or_imm_offset_divergent(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) { -; DAG-LABEL: ptr_s_buffer_load_ubyte_sgpr_or_imm_offset_divergent: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s7, s5 -; DAG-NEXT: s_mov_b32 s6, s4 -; DAG-NEXT: s_mov_b32 s5, s3 -; DAG-NEXT: s_mov_b32 s4, s2 -; DAG-NEXT: buffer_load_u8 v2, v2, s[4:7], null offen -; DAG-NEXT: s_wait_loadcnt 0x0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_ubyte_sgpr_or_imm_offset_divergent: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: buffer_load_u8 v2, v2, s[0:3], null offen -; GISEL-NEXT: s_wait_loadcnt 0x0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_ubyte_sgpr_or_imm_offset_divergent: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: buffer_load_u8 v2, v2, s[0:3], null offen +; GCN-NEXT: s_wait_loadcnt 0x0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %ld = call i8 @llvm.amdgcn.ptr.s.buffer.load.u8(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 %zext = zext i8 %ld to i32 @@ -261,29 +129,13 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_short_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out) { -; DAG-LABEL: ptr_s_buffer_load_short_imm_offset: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s7, s5 -; DAG-NEXT: s_mov_b32 s6, s4 -; DAG-NEXT: s_mov_b32 s5, s3 -; DAG-NEXT: s_mov_b32 s4, s2 -; DAG-NEXT: s_buffer_load_i16 s0, s[4:7], 0x4 -; DAG-NEXT: s_wait_kmcnt 0x0 -; DAG-NEXT: v_mov_b32_e32 v2, s0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_short_imm_offset: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: s_buffer_load_i16 s0, s[0:3], 0x4 -; GISEL-NEXT: s_wait_kmcnt 0x0 -; GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_short_imm_offset: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: s_buffer_load_i16 s0, s[0:3], 0x4 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) %src, i32 4, i32 0), !invariant.load !0 %sext = sext i16 %ld to i32 @@ -292,29 +144,13 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_short_sgpr(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %offset) { -; DAG-LABEL: ptr_s_buffer_load_short_sgpr: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s11, s5 -; DAG-NEXT: s_mov_b32 s10, s4 -; DAG-NEXT: s_mov_b32 s9, s3 -; DAG-NEXT: s_mov_b32 s8, s2 -; DAG-NEXT: s_buffer_load_i16 s0, s[8:11], s6 offset:0x0 -; DAG-NEXT: s_wait_kmcnt 0x0 -; DAG-NEXT: v_mov_b32_e32 v2, s0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_short_sgpr: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: s_buffer_load_i16 s0, s[0:3], s6 offset:0x0 -; GISEL-NEXT: s_wait_kmcnt 0x0 -; GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_short_sgpr: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: s_buffer_load_i16 s0, s[0:3], s4 offset:0x0 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 %sext = sext i16 %ld to i32 @@ -323,29 +159,13 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_short_sgpr_or_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %in) { -; DAG-LABEL: ptr_s_buffer_load_short_sgpr_or_imm_offset: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s11, s5 -; DAG-NEXT: s_mov_b32 s10, s4 -; DAG-NEXT: s_mov_b32 s9, s3 -; DAG-NEXT: s_mov_b32 s8, s2 -; DAG-NEXT: s_buffer_load_i16 s0, s[8:11], s6 offset:0x64 -; DAG-NEXT: s_wait_kmcnt 0x0 -; DAG-NEXT: v_mov_b32_e32 v2, s0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_short_sgpr_or_imm_offset: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: s_buffer_load_i16 s0, s[0:3], s6 offset:0x64 -; GISEL-NEXT: s_wait_kmcnt 0x0 -; GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_short_sgpr_or_imm_offset: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: s_buffer_load_i16 s0, s[0:3], s4 offset:0x64 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %off = add nuw nsw i32 %in, 100 %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) %src, i32 %off, i32 0), !invariant.load !0 @@ -355,27 +175,12 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_short_sgpr_or_imm_offset_divergent(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) { -; DAG-LABEL: ptr_s_buffer_load_short_sgpr_or_imm_offset_divergent: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s7, s5 -; DAG-NEXT: s_mov_b32 s6, s4 -; DAG-NEXT: s_mov_b32 s5, s3 -; DAG-NEXT: s_mov_b32 s4, s2 -; DAG-NEXT: buffer_load_i16 v2, v2, s[4:7], null offen -; DAG-NEXT: s_wait_loadcnt 0x0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_short_sgpr_or_imm_offset_divergent: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: buffer_load_i16 v2, v2, s[0:3], null offen -; GISEL-NEXT: s_wait_loadcnt 0x0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_short_sgpr_or_imm_offset_divergent: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: buffer_load_i16 v2, v2, s[0:3], null offen +; GCN-NEXT: s_wait_loadcnt 0x0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.i16(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 %sext = sext i16 %ld to i32 @@ -384,33 +189,15 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_ushort_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out) { -; DAG-LABEL: ptr_s_buffer_load_ushort_imm_offset: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s7, s5 -; DAG-NEXT: s_mov_b32 s6, s4 -; DAG-NEXT: s_mov_b32 s5, s3 -; DAG-NEXT: s_mov_b32 s4, s2 -; DAG-NEXT: s_buffer_load_u16 s0, s[4:7], 0x4 -; DAG-NEXT: s_wait_kmcnt 0x0 -; DAG-NEXT: s_and_b32 s0, s0, 0xffff -; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; DAG-NEXT: v_mov_b32_e32 v2, s0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_ushort_imm_offset: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: s_buffer_load_u16 s0, s[0:3], 0x4 -; GISEL-NEXT: s_wait_kmcnt 0x0 -; GISEL-NEXT: s_and_b32 s0, s0, 0xffff -; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_ushort_imm_offset: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: s_buffer_load_u16 s0, s[0:3], 0x4 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: s_and_b32 s0, s0, 0xffff +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.u16(ptr addrspace(8) %src, i32 4, i32 0), !invariant.load !0 %zext = zext i16 %ld to i32 @@ -419,33 +206,15 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_ushort_sgpr(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %offset) { -; DAG-LABEL: ptr_s_buffer_load_ushort_sgpr: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s11, s5 -; DAG-NEXT: s_mov_b32 s10, s4 -; DAG-NEXT: s_mov_b32 s9, s3 -; DAG-NEXT: s_mov_b32 s8, s2 -; DAG-NEXT: s_buffer_load_u16 s0, s[8:11], s6 offset:0x0 -; DAG-NEXT: s_wait_kmcnt 0x0 -; DAG-NEXT: s_and_b32 s0, s0, 0xffff -; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; DAG-NEXT: v_mov_b32_e32 v2, s0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_ushort_sgpr: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: s_buffer_load_u16 s0, s[0:3], s6 offset:0x0 -; GISEL-NEXT: s_wait_kmcnt 0x0 -; GISEL-NEXT: s_and_b32 s0, s0, 0xffff -; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_ushort_sgpr: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: s_buffer_load_u16 s0, s[0:3], s4 offset:0x0 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: s_and_b32 s0, s0, 0xffff +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.u16(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 %zext = zext i16 %ld to i32 @@ -454,33 +223,15 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_ushort_sgpr_or_imm_offset(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 inreg %in) { -; DAG-LABEL: ptr_s_buffer_load_ushort_sgpr_or_imm_offset: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s11, s5 -; DAG-NEXT: s_mov_b32 s10, s4 -; DAG-NEXT: s_mov_b32 s9, s3 -; DAG-NEXT: s_mov_b32 s8, s2 -; DAG-NEXT: s_buffer_load_u16 s0, s[8:11], s6 offset:0x64 -; DAG-NEXT: s_wait_kmcnt 0x0 -; DAG-NEXT: s_and_b32 s0, s0, 0xffff -; DAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; DAG-NEXT: v_mov_b32_e32 v2, s0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_ushort_sgpr_or_imm_offset: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: s_buffer_load_u16 s0, s[0:3], s6 offset:0x64 -; GISEL-NEXT: s_wait_kmcnt 0x0 -; GISEL-NEXT: s_and_b32 s0, s0, 0xffff -; GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GISEL-NEXT: v_mov_b32_e32 v2, s0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_ushort_sgpr_or_imm_offset: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: s_buffer_load_u16 s0, s[0:3], s4 offset:0x64 +; GCN-NEXT: s_wait_kmcnt 0x0 +; GCN-NEXT: s_and_b32 s0, s0, 0xffff +; GCN-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GCN-NEXT: v_mov_b32_e32 v2, s0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %off = add nuw nsw i32 %in, 100 %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.u16(ptr addrspace(8) %src, i32 %off, i32 0), !invariant.load !0 @@ -490,27 +241,12 @@ main_body: } define amdgpu_ps void @ptr_s_buffer_load_ushort_sgpr_or_imm_offset_divergent(ptr addrspace(8) inreg %src, ptr addrspace(1) nocapture %out, i32 %offset) { -; DAG-LABEL: ptr_s_buffer_load_ushort_sgpr_or_imm_offset_divergent: -; DAG: ; %bb.0: ; %main_body -; DAG-NEXT: s_mov_b32 s7, s5 -; DAG-NEXT: s_mov_b32 s6, s4 -; DAG-NEXT: s_mov_b32 s5, s3 -; DAG-NEXT: s_mov_b32 s4, s2 -; DAG-NEXT: buffer_load_u16 v2, v2, s[4:7], null offen -; DAG-NEXT: s_wait_loadcnt 0x0 -; DAG-NEXT: global_store_b32 v[0:1], v2, off -; DAG-NEXT: s_endpgm -; -; GISEL-LABEL: ptr_s_buffer_load_ushort_sgpr_or_imm_offset_divergent: -; GISEL: ; %bb.0: ; %main_body -; GISEL-NEXT: s_mov_b32 s0, s2 -; GISEL-NEXT: s_mov_b32 s1, s3 -; GISEL-NEXT: s_mov_b32 s2, s4 -; GISEL-NEXT: s_mov_b32 s3, s5 -; GISEL-NEXT: buffer_load_u16 v2, v2, s[0:3], null offen -; GISEL-NEXT: s_wait_loadcnt 0x0 -; GISEL-NEXT: global_store_b32 v[0:1], v2, off -; GISEL-NEXT: s_endpgm +; GCN-LABEL: ptr_s_buffer_load_ushort_sgpr_or_imm_offset_divergent: +; GCN: ; %bb.0: ; %main_body +; GCN-NEXT: buffer_load_u16 v2, v2, s[0:3], null offen +; GCN-NEXT: s_wait_loadcnt 0x0 +; GCN-NEXT: global_store_b32 v[0:1], v2, off +; GCN-NEXT: s_endpgm main_body: %ld = call i16 @llvm.amdgcn.ptr.s.buffer.load.u16(ptr addrspace(8) %src, i32 %offset, i32 0), !invariant.load !0 %zext = zext i16 %ld to i32 @@ -525,4 +261,5 @@ declare i16 @llvm.amdgcn.ptr.s.buffer.load.u16(ptr addrspace(8), i32, i32) !0 = !{} ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GCN: {{.*}} +; DAG: {{.*}} +; GISEL: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll index 7b7a8f0ed101e7..99ec84cc71a120 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics-min-max-system.ll @@ -62,12 +62,11 @@ define amdgpu_ps float @global_max_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; GFX11-LABEL: global_max_saddr_i32_rtn: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v2, v0 -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB0_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -90,10 +89,10 @@ define amdgpu_ps float @global_max_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; GFX12-LABEL: global_max_saddr_i32_rtn: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v2, v0 -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB0_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -174,12 +173,11 @@ define amdgpu_ps float @global_max_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; GFX11-LABEL: global_max_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v2, v0 -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB1_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -202,10 +200,10 @@ define amdgpu_ps float @global_max_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; GFX12-LABEL: global_max_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v2, v0 -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB1_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -282,12 +280,11 @@ define amdgpu_ps void @global_max_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_max_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v5, v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b32 v5, v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB2_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -307,10 +304,10 @@ define amdgpu_ps void @global_max_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_max_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v5, v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b32 v5, v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB2_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -383,12 +380,11 @@ define amdgpu_ps void @global_max_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_max_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v5, v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b32 v5, v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB3_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -408,10 +404,10 @@ define amdgpu_ps void @global_max_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_max_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v5, v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b32 v5, v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB3_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -497,12 +493,11 @@ define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_max_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[3:4], v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[3:4], v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB4_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -530,10 +525,10 @@ define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX12-LABEL: global_max_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[3:4], v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[3:4], v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB4_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -627,12 +622,11 @@ define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX11-LABEL: global_max_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[3:4], v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[3:4], v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB5_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -660,10 +654,10 @@ define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX12-LABEL: global_max_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[3:4], v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[3:4], v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB5_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -752,12 +746,11 @@ define amdgpu_ps void @global_max_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_max_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[5:6], v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[5:6], v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB6_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -781,10 +774,10 @@ define amdgpu_ps void @global_max_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_max_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[5:6], v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[5:6], v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB6_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -867,12 +860,11 @@ define amdgpu_ps void @global_max_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_max_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[5:6], v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[5:6], v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB7_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -896,10 +888,10 @@ define amdgpu_ps void @global_max_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_max_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[5:6], v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[5:6], v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB7_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -986,12 +978,11 @@ define amdgpu_ps float @global_min_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; GFX11-LABEL: global_min_saddr_i32_rtn: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v2, v0 -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB8_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1014,10 +1005,10 @@ define amdgpu_ps float @global_min_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; GFX12-LABEL: global_min_saddr_i32_rtn: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v2, v0 -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB8_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -1098,12 +1089,11 @@ define amdgpu_ps float @global_min_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; GFX11-LABEL: global_min_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v2, v0 -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB9_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1126,10 +1116,10 @@ define amdgpu_ps float @global_min_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; GFX12-LABEL: global_min_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v2, v0 -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB9_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -1206,12 +1196,11 @@ define amdgpu_ps void @global_min_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_min_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v5, v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b32 v5, v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB10_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1231,10 +1220,10 @@ define amdgpu_ps void @global_min_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_min_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v5, v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b32 v5, v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB10_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -1307,12 +1296,11 @@ define amdgpu_ps void @global_min_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_min_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v5, v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b32 v5, v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB11_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1332,10 +1320,10 @@ define amdgpu_ps void @global_min_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_min_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v5, v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b32 v5, v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB11_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -1421,12 +1409,11 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_min_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[3:4], v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[3:4], v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB12_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1454,10 +1441,10 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX12-LABEL: global_min_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[3:4], v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[3:4], v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB12_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -1551,12 +1538,11 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX11-LABEL: global_min_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[3:4], v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[3:4], v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB13_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1584,10 +1570,10 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX12-LABEL: global_min_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[3:4], v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[3:4], v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB13_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -1676,12 +1662,11 @@ define amdgpu_ps void @global_min_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_min_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[5:6], v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[5:6], v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB14_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1705,10 +1690,10 @@ define amdgpu_ps void @global_min_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_min_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[5:6], v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[5:6], v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB14_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -1791,12 +1776,11 @@ define amdgpu_ps void @global_min_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_min_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[5:6], v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[5:6], v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB15_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1820,10 +1804,10 @@ define amdgpu_ps void @global_min_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_min_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[5:6], v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[5:6], v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB15_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -1910,12 +1894,11 @@ define amdgpu_ps float @global_umax_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; GFX11-LABEL: global_umax_saddr_i32_rtn: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v2, v0 -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB16_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1938,10 +1921,10 @@ define amdgpu_ps float @global_umax_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; GFX12-LABEL: global_umax_saddr_i32_rtn: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v2, v0 -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB16_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -2022,12 +2005,11 @@ define amdgpu_ps float @global_umax_saddr_i32_rtn_neg128(ptr addrspace(1) inreg ; GFX11-LABEL: global_umax_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v2, v0 -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB17_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -2050,10 +2032,10 @@ define amdgpu_ps float @global_umax_saddr_i32_rtn_neg128(ptr addrspace(1) inreg ; GFX12-LABEL: global_umax_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v2, v0 -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB17_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -2130,12 +2112,11 @@ define amdgpu_ps void @global_umax_saddr_i32_nortn(ptr addrspace(1) inreg %sbase ; ; GFX11-LABEL: global_umax_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v5, v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b32 v5, v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB18_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -2155,10 +2136,10 @@ define amdgpu_ps void @global_umax_saddr_i32_nortn(ptr addrspace(1) inreg %sbase ; ; GFX12-LABEL: global_umax_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v5, v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b32 v5, v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB18_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -2231,12 +2212,11 @@ define amdgpu_ps void @global_umax_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_umax_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v5, v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b32 v5, v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB19_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -2256,10 +2236,10 @@ define amdgpu_ps void @global_umax_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_umax_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v5, v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b32 v5, v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB19_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -2345,12 +2325,11 @@ define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_umax_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[3:4], v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[3:4], v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB20_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -2378,10 +2357,10 @@ define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn(ptr addrspace(1) inreg % ; ; GFX12-LABEL: global_umax_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[3:4], v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[3:4], v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB20_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -2475,12 +2454,11 @@ define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn_neg128(ptr addrspace(1) ; ; GFX11-LABEL: global_umax_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[3:4], v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[3:4], v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB21_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -2508,10 +2486,10 @@ define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn_neg128(ptr addrspace(1) ; ; GFX12-LABEL: global_umax_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[3:4], v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[3:4], v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB21_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -2600,12 +2578,11 @@ define amdgpu_ps void @global_umax_saddr_i64_nortn(ptr addrspace(1) inreg %sbase ; ; GFX11-LABEL: global_umax_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[5:6], v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[5:6], v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB22_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -2629,10 +2606,10 @@ define amdgpu_ps void @global_umax_saddr_i64_nortn(ptr addrspace(1) inreg %sbase ; ; GFX12-LABEL: global_umax_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[5:6], v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[5:6], v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB22_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -2715,12 +2692,11 @@ define amdgpu_ps void @global_umax_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_umax_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[5:6], v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[5:6], v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB23_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -2744,10 +2720,10 @@ define amdgpu_ps void @global_umax_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_umax_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[5:6], v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[5:6], v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB23_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -2834,12 +2810,11 @@ define amdgpu_ps float @global_umin_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; GFX11-LABEL: global_umin_saddr_i32_rtn: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v2, v0 -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB24_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -2862,10 +2837,10 @@ define amdgpu_ps float @global_umin_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; GFX12-LABEL: global_umin_saddr_i32_rtn: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v2, v0 -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB24_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -2946,12 +2921,11 @@ define amdgpu_ps float @global_umin_saddr_i32_rtn_neg128(ptr addrspace(1) inreg ; GFX11-LABEL: global_umin_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v2, v0 -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB25_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -2974,10 +2948,10 @@ define amdgpu_ps float @global_umin_saddr_i32_rtn_neg128(ptr addrspace(1) inreg ; GFX12-LABEL: global_umin_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_mov_b32_e32 v2, v0 -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v2 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v2 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB25_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -3054,12 +3028,11 @@ define amdgpu_ps void @global_umin_saddr_i32_nortn(ptr addrspace(1) inreg %sbase ; ; GFX11-LABEL: global_umin_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v5, v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b32 v5, v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB26_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -3079,10 +3052,10 @@ define amdgpu_ps void @global_umin_saddr_i32_nortn(ptr addrspace(1) inreg %sbase ; ; GFX12-LABEL: global_umin_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v5, v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b32 v5, v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB26_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -3155,12 +3128,11 @@ define amdgpu_ps void @global_umin_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_umin_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v5, v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b32 v5, v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB27_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -3180,10 +3152,10 @@ define amdgpu_ps void @global_umin_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_umin_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v5, v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v2, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b32 v5, v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v2, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v3, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB27_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -3269,12 +3241,11 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_umin_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[3:4], v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[3:4], v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB28_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -3302,10 +3273,10 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn(ptr addrspace(1) inreg % ; ; GFX12-LABEL: global_umin_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[3:4], v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[3:4], v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB28_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -3399,12 +3370,11 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn_neg128(ptr addrspace(1) ; ; GFX11-LABEL: global_umin_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[3:4], v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[3:4], v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB29_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -3432,10 +3402,10 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn_neg128(ptr addrspace(1) ; ; GFX12-LABEL: global_umin_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[3:4], v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v5, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[3:4], v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v5, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v6, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB29_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -3524,12 +3494,11 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn(ptr addrspace(1) inreg %sbase ; ; GFX11-LABEL: global_umin_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[5:6], v0, s[2:3] -; GFX11-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[5:6], v0, s[0:1] +; GFX11-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB30_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -3553,10 +3522,10 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn(ptr addrspace(1) inreg %sbase ; ; GFX12-LABEL: global_umin_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[5:6], v0, s[2:3] -; GFX12-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[5:6], v0, s[0:1] +; GFX12-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB30_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -3639,12 +3608,11 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_umin_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[5:6], v0, s[2:3] offset:-128 -; GFX11-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX11-NEXT: global_load_b64 v[5:6], v0, s[0:1] offset:-128 +; GFX11-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX11-NEXT: s_mov_b64 s[0:1], 0 -; GFX11-NEXT: s_waitcnt_depctr depctr_sa_sdst(0) ; GFX11-NEXT: .LBB31_1: ; %atomicrmw.start ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -3668,10 +3636,10 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_umin_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[5:6], v0, s[2:3] offset:-128 -; GFX12-NEXT: v_add_co_u32 v7, s[0:1], s2, v0 +; GFX12-NEXT: global_load_b64 v[5:6], v0, s[0:1] offset:-128 +; GFX12-NEXT: v_add_co_u32 v7, s[2:3], s0, v0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s3, 0, s[0:1] +; GFX12-NEXT: v_add_co_ci_u32_e64 v8, null, s1, 0, s[2:3] ; GFX12-NEXT: s_mov_b64 s[0:1], 0 ; GFX12-NEXT: .LBB31_1: ; %atomicrmw.start ; GFX12-NEXT: ; =>This Inner Loop Header: Depth=1 diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll index c9ebcc15242580..4d24624b9dc2e8 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-atomics.ll @@ -24,7 +24,7 @@ define amdgpu_ps void @global_xchg_saddr_i32_nortn(ptr addrspace(1) inreg %sbase ; ; GFX11-LABEL: global_xchg_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_swap_b32 v0, v1, s[2:3] +; GFX11-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -32,7 +32,7 @@ define amdgpu_ps void @global_xchg_saddr_i32_nortn(ptr addrspace(1) inreg %sbase ; ; GFX12-LABEL: global_xchg_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_swap_b32 v0, v1, s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -61,7 +61,7 @@ define amdgpu_ps void @global_xchg_saddr_i32_nortn_offset_2047(ptr addrspace(1) ; ; GFX11-LABEL: global_xchg_saddr_i32_nortn_offset_2047: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_swap_b32 v0, v1, s[2:3] offset:2047 +; GFX11-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] offset:2047 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -69,7 +69,7 @@ define amdgpu_ps void @global_xchg_saddr_i32_nortn_offset_2047(ptr addrspace(1) ; ; GFX12-LABEL: global_xchg_saddr_i32_nortn_offset_2047: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_swap_b32 v0, v1, s[2:3] offset:2047 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] offset:2047 scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -99,7 +99,7 @@ define amdgpu_ps void @global_xchg_saddr_i32_nortn_offset_neg2048(ptr addrspace( ; ; GFX11-LABEL: global_xchg_saddr_i32_nortn_offset_neg2048: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_swap_b32 v0, v1, s[2:3] offset:-2048 +; GFX11-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] offset:-2048 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -107,7 +107,7 @@ define amdgpu_ps void @global_xchg_saddr_i32_nortn_offset_neg2048(ptr addrspace( ; ; GFX12-LABEL: global_xchg_saddr_i32_nortn_offset_neg2048: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_swap_b32 v0, v1, s[2:3] offset:-2048 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_swap_b32 v0, v1, s[0:1] offset:-2048 scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -136,7 +136,7 @@ define amdgpu_ps float @global_xchg_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_xchg_saddr_i32_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_swap_b32 v0, v0, v1, s[2:3] glc +; GFX11-NEXT: global_atomic_swap_b32 v0, v0, v1, s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -144,7 +144,7 @@ define amdgpu_ps float @global_xchg_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_xchg_saddr_i32_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_swap_b32 v0, v0, v1, s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_swap_b32 v0, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -177,7 +177,7 @@ define amdgpu_ps float @global_xchg_saddr_i32_rtn_2048(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_xchg_saddr_i32_rtn_2048: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_swap_b32 v0, v0, v1, s[2:3] offset:2048 glc +; GFX11-NEXT: global_atomic_swap_b32 v0, v0, v1, s[0:1] offset:2048 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -185,7 +185,7 @@ define amdgpu_ps float @global_xchg_saddr_i32_rtn_2048(ptr addrspace(1) inreg %s ; ; GFX12-LABEL: global_xchg_saddr_i32_rtn_2048: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_swap_b32 v0, v0, v1, s[2:3] offset:2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_swap_b32 v0, v0, v1, s[0:1] offset:2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -215,7 +215,7 @@ define amdgpu_ps float @global_xchg_saddr_i32_rtn_neg2048(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_xchg_saddr_i32_rtn_neg2048: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_swap_b32 v0, v0, v1, s[2:3] offset:-2048 glc +; GFX11-NEXT: global_atomic_swap_b32 v0, v0, v1, s[0:1] offset:-2048 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -223,7 +223,7 @@ define amdgpu_ps float @global_xchg_saddr_i32_rtn_neg2048(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_xchg_saddr_i32_rtn_neg2048: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_swap_b32 v0, v0, v1, s[2:3] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_swap_b32 v0, v0, v1, s[0:1] offset:-2048 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -507,7 +507,7 @@ define amdgpu_ps <2 x float> @global_xchg_saddr_i64_rtn(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_xchg_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_swap_b64 v[0:1], v0, v[1:2], s[2:3] glc +; GFX11-NEXT: global_atomic_swap_b64 v[0:1], v0, v[1:2], s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -515,7 +515,7 @@ define amdgpu_ps <2 x float> @global_xchg_saddr_i64_rtn(ptr addrspace(1) inreg % ; ; GFX12-LABEL: global_xchg_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_swap_b64 v[0:1], v0, v[1:2], s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_swap_b64 v[0:1], v0, v[1:2], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -544,7 +544,7 @@ define amdgpu_ps <2 x float> @global_xchg_saddr_i64_rtn_neg128(ptr addrspace(1) ; ; GFX11-LABEL: global_xchg_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_swap_b64 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_swap_b64 v[0:1], v0, v[1:2], s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -552,7 +552,7 @@ define amdgpu_ps <2 x float> @global_xchg_saddr_i64_rtn_neg128(ptr addrspace(1) ; ; GFX12-LABEL: global_xchg_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_swap_b64 v[0:1], v0, v[1:2], s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_swap_b64 v[0:1], v0, v[1:2], s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -582,7 +582,7 @@ define amdgpu_ps void @global_xchg_saddr_i64_nortn(ptr addrspace(1) inreg %sbase ; ; GFX11-LABEL: global_xchg_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_swap_b64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_atomic_swap_b64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -590,7 +590,7 @@ define amdgpu_ps void @global_xchg_saddr_i64_nortn(ptr addrspace(1) inreg %sbase ; ; GFX12-LABEL: global_xchg_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_swap_b64 v0, v[1:2], s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_swap_b64 v0, v[1:2], s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -618,7 +618,7 @@ define amdgpu_ps void @global_xchg_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_xchg_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_swap_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_swap_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -626,7 +626,7 @@ define amdgpu_ps void @global_xchg_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_xchg_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_swap_b64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_swap_b64 v0, v[1:2], s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -659,7 +659,7 @@ define amdgpu_ps float @global_add_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_add_saddr_i32_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_add_u32 v0, v0, v1, s[2:3] glc +; GFX11-NEXT: global_atomic_add_u32 v0, v0, v1, s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -667,7 +667,7 @@ define amdgpu_ps float @global_add_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_add_saddr_i32_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_add_u32 v0, v0, v1, s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_add_u32 v0, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -696,7 +696,7 @@ define amdgpu_ps float @global_add_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_add_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_add_u32 v0, v0, v1, s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_add_u32 v0, v0, v1, s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -704,7 +704,7 @@ define amdgpu_ps float @global_add_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; ; GFX12-LABEL: global_add_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_add_u32 v0, v0, v1, s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_add_u32 v0, v0, v1, s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -734,7 +734,7 @@ define amdgpu_ps void @global_add_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_add_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_add_u32 v0, v1, s[2:3] +; GFX11-NEXT: global_atomic_add_u32 v0, v1, s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -742,7 +742,7 @@ define amdgpu_ps void @global_add_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_add_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_add_u32 v0, v1, s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_add_u32 v0, v1, s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -770,7 +770,7 @@ define amdgpu_ps void @global_add_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_add_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_add_u32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_add_u32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -778,7 +778,7 @@ define amdgpu_ps void @global_add_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_add_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_add_u32 v0, v1, s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_add_u32 v0, v1, s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -807,7 +807,7 @@ define amdgpu_ps <2 x float> @global_add_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_add_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_add_u64 v[0:1], v0, v[1:2], s[2:3] glc +; GFX11-NEXT: global_atomic_add_u64 v[0:1], v0, v[1:2], s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -815,7 +815,7 @@ define amdgpu_ps <2 x float> @global_add_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX12-LABEL: global_add_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_add_u64 v[0:1], v0, v[1:2], s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_add_u64 v[0:1], v0, v[1:2], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -844,7 +844,7 @@ define amdgpu_ps <2 x float> @global_add_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX11-LABEL: global_add_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_add_u64 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_add_u64 v[0:1], v0, v[1:2], s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -852,7 +852,7 @@ define amdgpu_ps <2 x float> @global_add_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX12-LABEL: global_add_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_add_u64 v[0:1], v0, v[1:2], s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_add_u64 v[0:1], v0, v[1:2], s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -882,7 +882,7 @@ define amdgpu_ps void @global_add_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_add_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_add_u64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_atomic_add_u64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -890,7 +890,7 @@ define amdgpu_ps void @global_add_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_add_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_add_u64 v0, v[1:2], s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_add_u64 v0, v[1:2], s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -918,7 +918,7 @@ define amdgpu_ps void @global_add_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_add_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_add_u64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_add_u64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -926,7 +926,7 @@ define amdgpu_ps void @global_add_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_add_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_add_u64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_add_u64 v0, v[1:2], s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -959,7 +959,7 @@ define amdgpu_ps float @global_sub_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_sub_saddr_i32_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_sub_u32 v0, v0, v1, s[2:3] glc +; GFX11-NEXT: global_atomic_sub_u32 v0, v0, v1, s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -967,7 +967,7 @@ define amdgpu_ps float @global_sub_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_sub_saddr_i32_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_sub_u32 v0, v0, v1, s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_sub_u32 v0, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -996,7 +996,7 @@ define amdgpu_ps float @global_sub_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_sub_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_sub_u32 v0, v0, v1, s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_sub_u32 v0, v0, v1, s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1004,7 +1004,7 @@ define amdgpu_ps float @global_sub_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; ; GFX12-LABEL: global_sub_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_sub_u32 v0, v0, v1, s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_sub_u32 v0, v0, v1, s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1034,7 +1034,7 @@ define amdgpu_ps void @global_sub_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_sub_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_sub_u32 v0, v1, s[2:3] +; GFX11-NEXT: global_atomic_sub_u32 v0, v1, s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1042,7 +1042,7 @@ define amdgpu_ps void @global_sub_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_sub_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_sub_u32 v0, v1, s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_sub_u32 v0, v1, s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -1070,7 +1070,7 @@ define amdgpu_ps void @global_sub_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_sub_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_sub_u32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_sub_u32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1078,7 +1078,7 @@ define amdgpu_ps void @global_sub_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_sub_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_sub_u32 v0, v1, s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_sub_u32 v0, v1, s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -1107,7 +1107,7 @@ define amdgpu_ps <2 x float> @global_sub_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_sub_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_sub_u64 v[0:1], v0, v[1:2], s[2:3] glc +; GFX11-NEXT: global_atomic_sub_u64 v[0:1], v0, v[1:2], s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1115,7 +1115,7 @@ define amdgpu_ps <2 x float> @global_sub_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX12-LABEL: global_sub_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_sub_u64 v[0:1], v0, v[1:2], s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_sub_u64 v[0:1], v0, v[1:2], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1144,7 +1144,7 @@ define amdgpu_ps <2 x float> @global_sub_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX11-LABEL: global_sub_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_sub_u64 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_sub_u64 v[0:1], v0, v[1:2], s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1152,7 +1152,7 @@ define amdgpu_ps <2 x float> @global_sub_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX12-LABEL: global_sub_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_sub_u64 v[0:1], v0, v[1:2], s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_sub_u64 v[0:1], v0, v[1:2], s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1182,7 +1182,7 @@ define amdgpu_ps void @global_sub_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_sub_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_sub_u64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_atomic_sub_u64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1190,7 +1190,7 @@ define amdgpu_ps void @global_sub_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_sub_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_sub_u64 v0, v[1:2], s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_sub_u64 v0, v[1:2], s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -1218,7 +1218,7 @@ define amdgpu_ps void @global_sub_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_sub_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_sub_u64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_sub_u64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1226,7 +1226,7 @@ define amdgpu_ps void @global_sub_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_sub_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_sub_u64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_sub_u64 v0, v[1:2], s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -1259,7 +1259,7 @@ define amdgpu_ps float @global_and_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_and_saddr_i32_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_and_b32 v0, v0, v1, s[2:3] glc +; GFX11-NEXT: global_atomic_and_b32 v0, v0, v1, s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1267,7 +1267,7 @@ define amdgpu_ps float @global_and_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_and_saddr_i32_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_and_b32 v0, v0, v1, s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_and_b32 v0, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1296,7 +1296,7 @@ define amdgpu_ps float @global_and_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_and_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_and_b32 v0, v0, v1, s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_and_b32 v0, v0, v1, s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1304,7 +1304,7 @@ define amdgpu_ps float @global_and_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; ; GFX12-LABEL: global_and_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_and_b32 v0, v0, v1, s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_and_b32 v0, v0, v1, s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1334,7 +1334,7 @@ define amdgpu_ps void @global_and_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_and_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_and_b32 v0, v1, s[2:3] +; GFX11-NEXT: global_atomic_and_b32 v0, v1, s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1342,7 +1342,7 @@ define amdgpu_ps void @global_and_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_and_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_and_b32 v0, v1, s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_and_b32 v0, v1, s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -1370,7 +1370,7 @@ define amdgpu_ps void @global_and_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_and_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_and_b32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_and_b32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1378,7 +1378,7 @@ define amdgpu_ps void @global_and_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_and_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_and_b32 v0, v1, s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_and_b32 v0, v1, s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -1407,7 +1407,7 @@ define amdgpu_ps <2 x float> @global_and_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_and_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_and_b64 v[0:1], v0, v[1:2], s[2:3] glc +; GFX11-NEXT: global_atomic_and_b64 v[0:1], v0, v[1:2], s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1415,7 +1415,7 @@ define amdgpu_ps <2 x float> @global_and_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX12-LABEL: global_and_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_and_b64 v[0:1], v0, v[1:2], s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_and_b64 v[0:1], v0, v[1:2], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1444,7 +1444,7 @@ define amdgpu_ps <2 x float> @global_and_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX11-LABEL: global_and_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_and_b64 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_and_b64 v[0:1], v0, v[1:2], s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1452,7 +1452,7 @@ define amdgpu_ps <2 x float> @global_and_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX12-LABEL: global_and_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_and_b64 v[0:1], v0, v[1:2], s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_and_b64 v[0:1], v0, v[1:2], s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1482,7 +1482,7 @@ define amdgpu_ps void @global_and_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_and_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_and_b64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_atomic_and_b64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1490,7 +1490,7 @@ define amdgpu_ps void @global_and_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_and_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_and_b64 v0, v[1:2], s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_and_b64 v0, v[1:2], s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -1518,7 +1518,7 @@ define amdgpu_ps void @global_and_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_and_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_and_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_and_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1526,7 +1526,7 @@ define amdgpu_ps void @global_and_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_and_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_and_b64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_and_b64 v0, v[1:2], s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -1559,7 +1559,7 @@ define amdgpu_ps float @global_or_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, i ; ; GFX11-LABEL: global_or_saddr_i32_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_or_b32 v0, v0, v1, s[2:3] glc +; GFX11-NEXT: global_atomic_or_b32 v0, v0, v1, s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1567,7 +1567,7 @@ define amdgpu_ps float @global_or_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, i ; ; GFX12-LABEL: global_or_saddr_i32_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_or_b32 v0, v0, v1, s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_or_b32 v0, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1596,7 +1596,7 @@ define amdgpu_ps float @global_or_saddr_i32_rtn_neg128(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_or_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_or_b32 v0, v0, v1, s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_or_b32 v0, v0, v1, s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1604,7 +1604,7 @@ define amdgpu_ps float @global_or_saddr_i32_rtn_neg128(ptr addrspace(1) inreg %s ; ; GFX12-LABEL: global_or_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_or_b32 v0, v0, v1, s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_or_b32 v0, v0, v1, s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1634,7 +1634,7 @@ define amdgpu_ps void @global_or_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_or_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_or_b32 v0, v1, s[2:3] +; GFX11-NEXT: global_atomic_or_b32 v0, v1, s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1642,7 +1642,7 @@ define amdgpu_ps void @global_or_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_or_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_or_b32 v0, v1, s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_or_b32 v0, v1, s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -1670,7 +1670,7 @@ define amdgpu_ps void @global_or_saddr_i32_nortn_neg128(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_or_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_or_b32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_or_b32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1678,7 +1678,7 @@ define amdgpu_ps void @global_or_saddr_i32_nortn_neg128(ptr addrspace(1) inreg % ; ; GFX12-LABEL: global_or_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_or_b32 v0, v1, s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_or_b32 v0, v1, s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -1707,7 +1707,7 @@ define amdgpu_ps <2 x float> @global_or_saddr_i64_rtn(ptr addrspace(1) inreg %sb ; ; GFX11-LABEL: global_or_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_or_b64 v[0:1], v0, v[1:2], s[2:3] glc +; GFX11-NEXT: global_atomic_or_b64 v[0:1], v0, v[1:2], s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1715,7 +1715,7 @@ define amdgpu_ps <2 x float> @global_or_saddr_i64_rtn(ptr addrspace(1) inreg %sb ; ; GFX12-LABEL: global_or_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_or_b64 v[0:1], v0, v[1:2], s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_or_b64 v[0:1], v0, v[1:2], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1744,7 +1744,7 @@ define amdgpu_ps <2 x float> @global_or_saddr_i64_rtn_neg128(ptr addrspace(1) in ; ; GFX11-LABEL: global_or_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_or_b64 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_or_b64 v[0:1], v0, v[1:2], s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1752,7 +1752,7 @@ define amdgpu_ps <2 x float> @global_or_saddr_i64_rtn_neg128(ptr addrspace(1) in ; ; GFX12-LABEL: global_or_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_or_b64 v[0:1], v0, v[1:2], s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_or_b64 v[0:1], v0, v[1:2], s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1782,7 +1782,7 @@ define amdgpu_ps void @global_or_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_or_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_or_b64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_atomic_or_b64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1790,7 +1790,7 @@ define amdgpu_ps void @global_or_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_or_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_or_b64 v0, v[1:2], s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_or_b64 v0, v[1:2], s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -1818,7 +1818,7 @@ define amdgpu_ps void @global_or_saddr_i64_nortn_neg128(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_or_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_or_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_or_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1826,7 +1826,7 @@ define amdgpu_ps void @global_or_saddr_i64_nortn_neg128(ptr addrspace(1) inreg % ; ; GFX12-LABEL: global_or_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_or_b64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_or_b64 v0, v[1:2], s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -1859,7 +1859,7 @@ define amdgpu_ps float @global_xor_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_xor_saddr_i32_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_xor_b32 v0, v0, v1, s[2:3] glc +; GFX11-NEXT: global_atomic_xor_b32 v0, v0, v1, s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1867,7 +1867,7 @@ define amdgpu_ps float @global_xor_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_xor_saddr_i32_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_xor_b32 v0, v0, v1, s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_xor_b32 v0, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1896,7 +1896,7 @@ define amdgpu_ps float @global_xor_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_xor_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_xor_b32 v0, v0, v1, s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_xor_b32 v0, v0, v1, s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1904,7 +1904,7 @@ define amdgpu_ps float @global_xor_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; ; GFX12-LABEL: global_xor_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_xor_b32 v0, v0, v1, s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_xor_b32 v0, v0, v1, s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -1934,7 +1934,7 @@ define amdgpu_ps void @global_xor_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_xor_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_xor_b32 v0, v1, s[2:3] +; GFX11-NEXT: global_atomic_xor_b32 v0, v1, s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1942,7 +1942,7 @@ define amdgpu_ps void @global_xor_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_xor_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_xor_b32 v0, v1, s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_xor_b32 v0, v1, s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -1970,7 +1970,7 @@ define amdgpu_ps void @global_xor_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_xor_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_xor_b32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_xor_b32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -1978,7 +1978,7 @@ define amdgpu_ps void @global_xor_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_xor_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_xor_b32 v0, v1, s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_xor_b32 v0, v1, s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -2007,7 +2007,7 @@ define amdgpu_ps <2 x float> @global_xor_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_xor_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_xor_b64 v[0:1], v0, v[1:2], s[2:3] glc +; GFX11-NEXT: global_atomic_xor_b64 v[0:1], v0, v[1:2], s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -2015,7 +2015,7 @@ define amdgpu_ps <2 x float> @global_xor_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX12-LABEL: global_xor_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_xor_b64 v[0:1], v0, v[1:2], s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_xor_b64 v[0:1], v0, v[1:2], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -2044,7 +2044,7 @@ define amdgpu_ps <2 x float> @global_xor_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX11-LABEL: global_xor_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_xor_b64 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_xor_b64 v[0:1], v0, v[1:2], s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -2052,7 +2052,7 @@ define amdgpu_ps <2 x float> @global_xor_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX12-LABEL: global_xor_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_xor_b64 v[0:1], v0, v[1:2], s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_xor_b64 v[0:1], v0, v[1:2], s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: ; return to shader part epilog @@ -2082,7 +2082,7 @@ define amdgpu_ps void @global_xor_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_xor_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_xor_b64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_atomic_xor_b64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -2090,7 +2090,7 @@ define amdgpu_ps void @global_xor_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX12-LABEL: global_xor_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_xor_b64 v0, v[1:2], s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_xor_b64 v0, v[1:2], s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -2118,7 +2118,7 @@ define amdgpu_ps void @global_xor_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_xor_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_xor_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_xor_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -2126,7 +2126,7 @@ define amdgpu_ps void @global_xor_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX12-LABEL: global_xor_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_xor_b64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_xor_b64 v0, v[1:2], s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm @@ -2157,14 +2157,14 @@ define amdgpu_ps float @global_max_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_max_saddr_i32_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_i32 v0, v0, v1, s[2:3] glc +; GFX11-NEXT: global_atomic_max_i32 v0, v0, v1, s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_max_saddr_i32_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_i32 v0, v0, v1, s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_i32 v0, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -2191,14 +2191,14 @@ define amdgpu_ps float @global_max_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_max_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_i32 v0, v0, v1, s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_max_i32 v0, v0, v1, s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_max_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_i32 v0, v0, v1, s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_i32 v0, v0, v1, s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -2225,14 +2225,14 @@ define amdgpu_ps void @global_max_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_max_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_i32 v0, v1, s[2:3] +; GFX11-NEXT: global_atomic_max_i32 v0, v1, s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_max_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_i32 v0, v1, s[2:3] scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_i32 v0, v1, s[0:1] scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -2257,14 +2257,14 @@ define amdgpu_ps void @global_max_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_max_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_i32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_max_i32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_max_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_i32 v0, v1, s[2:3] offset:-128 scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_i32 v0, v1, s[0:1] offset:-128 scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -2291,14 +2291,14 @@ define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_max_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_i64 v[0:1], v0, v[1:2], s[2:3] glc +; GFX11-NEXT: global_atomic_max_i64 v[0:1], v0, v[1:2], s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_max_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_i64 v[0:1], v0, v[1:2], s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_i64 v[0:1], v0, v[1:2], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -2325,14 +2325,14 @@ define amdgpu_ps <2 x float> @global_max_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX11-LABEL: global_max_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_i64 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_max_i64 v[0:1], v0, v[1:2], s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_max_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_i64 v[0:1], v0, v[1:2], s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_i64 v[0:1], v0, v[1:2], s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -2359,14 +2359,14 @@ define amdgpu_ps void @global_max_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_max_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_i64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_atomic_max_i64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_max_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_i64 v0, v[1:2], s[2:3] scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_i64 v0, v[1:2], s[0:1] scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -2391,14 +2391,14 @@ define amdgpu_ps void @global_max_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_max_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_i64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_max_i64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_max_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_i64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_i64 v0, v[1:2], s[0:1] offset:-128 scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -2429,14 +2429,14 @@ define amdgpu_ps float @global_min_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_min_saddr_i32_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_i32 v0, v0, v1, s[2:3] glc +; GFX11-NEXT: global_atomic_min_i32 v0, v0, v1, s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_min_saddr_i32_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_i32 v0, v0, v1, s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_i32 v0, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -2463,14 +2463,14 @@ define amdgpu_ps float @global_min_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_min_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_i32 v0, v0, v1, s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_min_i32 v0, v0, v1, s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_min_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_i32 v0, v0, v1, s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_i32 v0, v0, v1, s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -2497,14 +2497,14 @@ define amdgpu_ps void @global_min_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_min_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_i32 v0, v1, s[2:3] +; GFX11-NEXT: global_atomic_min_i32 v0, v1, s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_min_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_i32 v0, v1, s[2:3] scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_i32 v0, v1, s[0:1] scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -2529,14 +2529,14 @@ define amdgpu_ps void @global_min_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_min_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_i32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_min_i32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_min_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_i32 v0, v1, s[2:3] offset:-128 scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_i32 v0, v1, s[0:1] offset:-128 scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -2563,14 +2563,14 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_min_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_i64 v[0:1], v0, v[1:2], s[2:3] glc +; GFX11-NEXT: global_atomic_min_i64 v[0:1], v0, v[1:2], s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_min_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_i64 v[0:1], v0, v[1:2], s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_i64 v[0:1], v0, v[1:2], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -2597,14 +2597,14 @@ define amdgpu_ps <2 x float> @global_min_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX11-LABEL: global_min_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_i64 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_min_i64 v[0:1], v0, v[1:2], s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_min_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_i64 v[0:1], v0, v[1:2], s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_i64 v[0:1], v0, v[1:2], s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -2631,14 +2631,14 @@ define amdgpu_ps void @global_min_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_min_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_i64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_atomic_min_i64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_min_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_i64 v0, v[1:2], s[2:3] scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_i64 v0, v[1:2], s[0:1] scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -2663,14 +2663,14 @@ define amdgpu_ps void @global_min_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_min_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_i64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_min_i64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_min_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_i64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_i64 v0, v[1:2], s[0:1] offset:-128 scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -2701,14 +2701,14 @@ define amdgpu_ps float @global_umax_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_umax_saddr_i32_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_u32 v0, v0, v1, s[2:3] glc +; GFX11-NEXT: global_atomic_max_u32 v0, v0, v1, s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_umax_saddr_i32_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_u32 v0, v0, v1, s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_u32 v0, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -2735,14 +2735,14 @@ define amdgpu_ps float @global_umax_saddr_i32_rtn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_umax_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_u32 v0, v0, v1, s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_max_u32 v0, v0, v1, s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_umax_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_u32 v0, v0, v1, s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_u32 v0, v0, v1, s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -2769,14 +2769,14 @@ define amdgpu_ps void @global_umax_saddr_i32_nortn(ptr addrspace(1) inreg %sbase ; ; GFX11-LABEL: global_umax_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_u32 v0, v1, s[2:3] +; GFX11-NEXT: global_atomic_max_u32 v0, v1, s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_umax_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_u32 v0, v1, s[2:3] scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_u32 v0, v1, s[0:1] scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -2801,14 +2801,14 @@ define amdgpu_ps void @global_umax_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_umax_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_u32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_max_u32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_umax_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_u32 v0, v1, s[2:3] offset:-128 scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_u32 v0, v1, s[0:1] offset:-128 scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -2835,14 +2835,14 @@ define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_umax_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_u64 v[0:1], v0, v[1:2], s[2:3] glc +; GFX11-NEXT: global_atomic_max_u64 v[0:1], v0, v[1:2], s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_umax_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_u64 v[0:1], v0, v[1:2], s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_u64 v[0:1], v0, v[1:2], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -2869,14 +2869,14 @@ define amdgpu_ps <2 x float> @global_umax_saddr_i64_rtn_neg128(ptr addrspace(1) ; ; GFX11-LABEL: global_umax_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_u64 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_max_u64 v[0:1], v0, v[1:2], s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_umax_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_u64 v[0:1], v0, v[1:2], s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_u64 v[0:1], v0, v[1:2], s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -2903,14 +2903,14 @@ define amdgpu_ps void @global_umax_saddr_i64_nortn(ptr addrspace(1) inreg %sbase ; ; GFX11-LABEL: global_umax_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_u64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_atomic_max_u64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_umax_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_u64 v0, v[1:2], s[2:3] scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_u64 v0, v[1:2], s[0:1] scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -2935,14 +2935,14 @@ define amdgpu_ps void @global_umax_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_umax_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_max_u64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_max_u64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_umax_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_max_u64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_SE +; GFX12-NEXT: global_atomic_max_u64 v0, v[1:2], s[0:1] offset:-128 scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -2973,14 +2973,14 @@ define amdgpu_ps float @global_umin_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_umin_saddr_i32_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_u32 v0, v0, v1, s[2:3] glc +; GFX11-NEXT: global_atomic_min_u32 v0, v0, v1, s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_umin_saddr_i32_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_u32 v0, v0, v1, s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_u32 v0, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -3007,14 +3007,14 @@ define amdgpu_ps float @global_umin_saddr_i32_rtn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_umin_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_u32 v0, v0, v1, s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_min_u32 v0, v0, v1, s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_umin_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_u32 v0, v0, v1, s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_u32 v0, v0, v1, s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -3041,14 +3041,14 @@ define amdgpu_ps void @global_umin_saddr_i32_nortn(ptr addrspace(1) inreg %sbase ; ; GFX11-LABEL: global_umin_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_u32 v0, v1, s[2:3] +; GFX11-NEXT: global_atomic_min_u32 v0, v1, s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_umin_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_u32 v0, v1, s[2:3] scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_u32 v0, v1, s[0:1] scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -3073,14 +3073,14 @@ define amdgpu_ps void @global_umin_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_umin_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_u32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_min_u32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_umin_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_u32 v0, v1, s[2:3] offset:-128 scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_u32 v0, v1, s[0:1] offset:-128 scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -3107,14 +3107,14 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_umin_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_u64 v[0:1], v0, v[1:2], s[2:3] glc +; GFX11-NEXT: global_atomic_min_u64 v[0:1], v0, v[1:2], s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_umin_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_u64 v[0:1], v0, v[1:2], s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_u64 v[0:1], v0, v[1:2], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -3141,14 +3141,14 @@ define amdgpu_ps <2 x float> @global_umin_saddr_i64_rtn_neg128(ptr addrspace(1) ; ; GFX11-LABEL: global_umin_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_u64 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_min_u64 v[0:1], v0, v[1:2], s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_umin_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_u64 v[0:1], v0, v[1:2], s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_u64 v[0:1], v0, v[1:2], s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SE ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: ; return to shader part epilog @@ -3175,14 +3175,14 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn(ptr addrspace(1) inreg %sbase ; ; GFX11-LABEL: global_umin_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_u64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_atomic_min_u64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_umin_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_u64 v0, v[1:2], s[2:3] scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_u64 v0, v[1:2], s[0:1] scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -3207,14 +3207,14 @@ define amdgpu_ps void @global_umin_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_umin_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_min_u64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_min_u64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl0_inv ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_umin_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_min_u64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_SE +; GFX12-NEXT: global_atomic_min_u64 v0, v[1:2], s[0:1] offset:-128 scope:SCOPE_SE ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SE ; GFX12-NEXT: s_endpgm @@ -3250,7 +3250,7 @@ define amdgpu_ps float @global_cmpxchg_saddr_i32_rtn(ptr addrspace(1) inreg %sba ; GFX11-LABEL: global_cmpxchg_saddr_i32_rtn: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v3, v1 -; GFX11-NEXT: global_atomic_cmpswap_b32 v0, v0, v[2:3], s[2:3] glc +; GFX11-NEXT: global_atomic_cmpswap_b32 v0, v0, v[2:3], s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -3261,7 +3261,7 @@ define amdgpu_ps float @global_cmpxchg_saddr_i32_rtn(ptr addrspace(1) inreg %sba ; GFX12-NEXT: v_mov_b32_e32 v3, v1 ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 -; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v0, v[2:3], s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS +; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v0, v[2:3], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SYS ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: ; return to shader part epilog @@ -3294,7 +3294,7 @@ define amdgpu_ps float @global_cmpxchg_saddr_i32_rtn_neg128(ptr addrspace(1) inr ; GFX11-LABEL: global_cmpxchg_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v3, v1 -; GFX11-NEXT: global_atomic_cmpswap_b32 v0, v0, v[2:3], s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_cmpswap_b32 v0, v0, v[2:3], s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -3305,7 +3305,7 @@ define amdgpu_ps float @global_cmpxchg_saddr_i32_rtn_neg128(ptr addrspace(1) inr ; GFX12-NEXT: v_mov_b32_e32 v3, v1 ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 -; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v0, v[2:3], s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SYS +; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v0, v[2:3], s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SYS ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: ; return to shader part epilog @@ -3339,7 +3339,7 @@ define amdgpu_ps void @global_cmpxchg_saddr_i32_nortn(ptr addrspace(1) inreg %sb ; GFX11-LABEL: global_cmpxchg_saddr_i32_nortn: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v3, v1 -; GFX11-NEXT: global_atomic_cmpswap_b32 v0, v[2:3], s[2:3] +; GFX11-NEXT: global_atomic_cmpswap_b32 v0, v[2:3], s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -3350,7 +3350,7 @@ define amdgpu_ps void @global_cmpxchg_saddr_i32_nortn(ptr addrspace(1) inreg %sb ; GFX12-NEXT: v_mov_b32_e32 v3, v1 ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 -; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[2:3], s[2:3] scope:SCOPE_SYS +; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[2:3], s[0:1] scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: s_endpgm @@ -3381,7 +3381,7 @@ define amdgpu_ps void @global_cmpxchg_saddr_i32_nortn_neg128(ptr addrspace(1) in ; GFX11-LABEL: global_cmpxchg_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v3, v1 -; GFX11-NEXT: global_atomic_cmpswap_b32 v0, v[2:3], s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_cmpswap_b32 v0, v[2:3], s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -3392,7 +3392,7 @@ define amdgpu_ps void @global_cmpxchg_saddr_i32_nortn_neg128(ptr addrspace(1) in ; GFX12-NEXT: v_mov_b32_e32 v3, v1 ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 -; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[2:3], s[2:3] offset:-128 scope:SCOPE_SYS +; GFX12-NEXT: global_atomic_cmpswap_b32 v0, v[2:3], s[0:1] offset:-128 scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: s_endpgm @@ -3427,7 +3427,7 @@ define amdgpu_ps <2 x float> @global_cmpxchg_saddr_i64_rtn(ptr addrspace(1) inre ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v6, v2 ; GFX11-NEXT: v_mov_b32_e32 v5, v1 -; GFX11-NEXT: global_atomic_cmpswap_b64 v[0:1], v0, v[3:6], s[2:3] glc +; GFX11-NEXT: global_atomic_cmpswap_b64 v[0:1], v0, v[3:6], s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -3439,7 +3439,7 @@ define amdgpu_ps <2 x float> @global_cmpxchg_saddr_i64_rtn(ptr addrspace(1) inre ; GFX12-NEXT: v_mov_b32_e32 v5, v1 ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 -; GFX12-NEXT: global_atomic_cmpswap_b64 v[0:1], v0, v[3:6], s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_SYS +; GFX12-NEXT: global_atomic_cmpswap_b64 v[0:1], v0, v[3:6], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_SYS ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: ; return to shader part epilog @@ -3475,7 +3475,7 @@ define amdgpu_ps <2 x float> @global_cmpxchg_saddr_i64_rtn_neg128(ptr addrspace( ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v6, v2 ; GFX11-NEXT: v_mov_b32_e32 v5, v1 -; GFX11-NEXT: global_atomic_cmpswap_b64 v[0:1], v0, v[3:6], s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_cmpswap_b64 v[0:1], v0, v[3:6], s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -3487,7 +3487,7 @@ define amdgpu_ps <2 x float> @global_cmpxchg_saddr_i64_rtn_neg128(ptr addrspace( ; GFX12-NEXT: v_mov_b32_e32 v5, v1 ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 -; GFX12-NEXT: global_atomic_cmpswap_b64 v[0:1], v0, v[3:6], s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SYS +; GFX12-NEXT: global_atomic_cmpswap_b64 v[0:1], v0, v[3:6], s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_SYS ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: ; return to shader part epilog @@ -3524,7 +3524,7 @@ define amdgpu_ps void @global_cmpxchg_saddr_i64_nortn(ptr addrspace(1) inreg %sb ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v6, v2 ; GFX11-NEXT: v_mov_b32_e32 v5, v1 -; GFX11-NEXT: global_atomic_cmpswap_b64 v0, v[3:6], s[2:3] +; GFX11-NEXT: global_atomic_cmpswap_b64 v0, v[3:6], s[0:1] ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -3536,7 +3536,7 @@ define amdgpu_ps void @global_cmpxchg_saddr_i64_nortn(ptr addrspace(1) inreg %sb ; GFX12-NEXT: v_mov_b32_e32 v5, v1 ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 -; GFX12-NEXT: global_atomic_cmpswap_b64 v0, v[3:6], s[2:3] scope:SCOPE_SYS +; GFX12-NEXT: global_atomic_cmpswap_b64 v0, v[3:6], s[0:1] scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: s_endpgm @@ -3570,7 +3570,7 @@ define amdgpu_ps void @global_cmpxchg_saddr_i64_nortn_neg128(ptr addrspace(1) in ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v6, v2 ; GFX11-NEXT: v_mov_b32_e32 v5, v1 -; GFX11-NEXT: global_atomic_cmpswap_b64 v0, v[3:6], s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_cmpswap_b64 v0, v[3:6], s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -3582,7 +3582,7 @@ define amdgpu_ps void @global_cmpxchg_saddr_i64_nortn_neg128(ptr addrspace(1) in ; GFX12-NEXT: v_mov_b32_e32 v5, v1 ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 -; GFX12-NEXT: global_atomic_cmpswap_b64 v0, v[3:6], s[2:3] offset:-128 scope:SCOPE_SYS +; GFX12-NEXT: global_atomic_cmpswap_b64 v0, v[3:6], s[0:1] offset:-128 scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: s_endpgm @@ -3606,13 +3606,13 @@ define amdgpu_ps float @global_inc_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_inc_saddr_i32_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_inc_u32 v0, v0, v1, s[2:3] glc +; GFX11-NEXT: global_atomic_inc_u32 v0, v0, v1, s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_inc_saddr_i32_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_inc_u32 v0, v0, v1, s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_inc_u32 v0, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3631,13 +3631,13 @@ define amdgpu_ps float @global_inc_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_inc_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_inc_u32 v0, v0, v1, s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_inc_u32 v0, v0, v1, s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_inc_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_inc_u32 v0, v0, v1, s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_inc_u32 v0, v0, v1, s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3656,12 +3656,12 @@ define amdgpu_ps void @global_inc_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_inc_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_inc_u32 v0, v1, s[2:3] +; GFX11-NEXT: global_atomic_inc_u32 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_inc_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_inc_u32 v0, v1, s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_inc_u32 v0, v1, s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -3677,12 +3677,12 @@ define amdgpu_ps void @global_inc_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_inc_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_inc_u32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_inc_u32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_inc_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_inc_u32 v0, v1, s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_inc_u32 v0, v1, s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -3700,13 +3700,13 @@ define amdgpu_ps <2 x float> @global_inc_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_inc_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_inc_u64 v[0:1], v0, v[1:2], s[2:3] glc +; GFX11-NEXT: global_atomic_inc_u64 v[0:1], v0, v[1:2], s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_inc_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_inc_u64 v[0:1], v0, v[1:2], s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_inc_u64 v[0:1], v0, v[1:2], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3725,13 +3725,13 @@ define amdgpu_ps <2 x float> @global_inc_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX11-LABEL: global_inc_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_inc_u64 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_inc_u64 v[0:1], v0, v[1:2], s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_inc_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_inc_u64 v[0:1], v0, v[1:2], s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_inc_u64 v[0:1], v0, v[1:2], s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3750,12 +3750,12 @@ define amdgpu_ps void @global_inc_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_inc_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_inc_u64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_atomic_inc_u64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_inc_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_inc_u64 v0, v[1:2], s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_inc_u64 v0, v[1:2], s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -3771,12 +3771,12 @@ define amdgpu_ps void @global_inc_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_inc_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_inc_u64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_inc_u64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_inc_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_inc_u64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_inc_u64 v0, v[1:2], s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -3799,13 +3799,13 @@ define amdgpu_ps float @global_dec_saddr_i32_rtn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_dec_saddr_i32_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_dec_u32 v0, v0, v1, s[2:3] glc +; GFX11-NEXT: global_atomic_dec_u32 v0, v0, v1, s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_dec_saddr_i32_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_dec_u32 v0, v0, v1, s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_dec_u32 v0, v0, v1, s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3824,13 +3824,13 @@ define amdgpu_ps float @global_dec_saddr_i32_rtn_neg128(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_dec_saddr_i32_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_dec_u32 v0, v0, v1, s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_dec_u32 v0, v0, v1, s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_dec_saddr_i32_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_dec_u32 v0, v0, v1, s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_dec_u32 v0, v0, v1, s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3849,12 +3849,12 @@ define amdgpu_ps void @global_dec_saddr_i32_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_dec_saddr_i32_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_dec_u32 v0, v1, s[2:3] +; GFX11-NEXT: global_atomic_dec_u32 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_dec_saddr_i32_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_dec_u32 v0, v1, s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_dec_u32 v0, v1, s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -3870,12 +3870,12 @@ define amdgpu_ps void @global_dec_saddr_i32_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_dec_saddr_i32_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_dec_u32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_dec_u32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_dec_saddr_i32_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_dec_u32 v0, v1, s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_dec_u32 v0, v1, s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -3893,13 +3893,13 @@ define amdgpu_ps <2 x float> @global_dec_saddr_i64_rtn(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_dec_saddr_i64_rtn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_dec_u64 v[0:1], v0, v[1:2], s[2:3] glc +; GFX11-NEXT: global_atomic_dec_u64 v[0:1], v0, v[1:2], s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_dec_saddr_i64_rtn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_dec_u64 v[0:1], v0, v[1:2], s[2:3] th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_dec_u64 v[0:1], v0, v[1:2], s[0:1] th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3918,13 +3918,13 @@ define amdgpu_ps <2 x float> @global_dec_saddr_i64_rtn_neg128(ptr addrspace(1) i ; ; GFX11-LABEL: global_dec_saddr_i64_rtn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_dec_u64 v[0:1], v0, v[1:2], s[2:3] offset:-128 glc +; GFX11-NEXT: global_atomic_dec_u64 v[0:1], v0, v[1:2], s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_dec_saddr_i64_rtn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_dec_u64 v[0:1], v0, v[1:2], s[2:3] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_dec_u64 v[0:1], v0, v[1:2], s[0:1] offset:-128 th:TH_ATOMIC_RETURN scope:SCOPE_DEV ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3943,12 +3943,12 @@ define amdgpu_ps void @global_dec_saddr_i64_nortn(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_dec_saddr_i64_nortn: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_dec_u64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_atomic_dec_u64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_dec_saddr_i64_nortn: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_dec_u64 v0, v[1:2], s[2:3] scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_dec_u64 v0, v[1:2], s[0:1] scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -3964,12 +3964,12 @@ define amdgpu_ps void @global_dec_saddr_i64_nortn_neg128(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_dec_saddr_i64_nortn_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_atomic_dec_u64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_atomic_dec_u64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_dec_saddr_i64_nortn_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_atomic_dec_u64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_DEV +; GFX12-NEXT: global_atomic_dec_u64 v0, v[1:2], s[0:1] offset:-128 scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll index a1130abf89a7a5..bbd31ce8d19be5 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-load.ll @@ -26,13 +26,13 @@ define amdgpu_ps float @global_load_saddr_i8_offset_0(ptr addrspace(1) inreg %sb ; GFX11-LABEL: global_load_saddr_i8_offset_0: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_offset_0: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_load_u8 s0, s[2:3], 0x0 +; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -61,13 +61,13 @@ define amdgpu_ps float @global_load_saddr_i8_offset_4095(ptr addrspace(1) inreg ; GFX11-LABEL: global_load_saddr_i8_offset_4095: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:4095 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:4095 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_offset_4095: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_load_u8 s0, s[2:3], 0xfff +; GFX12-NEXT: s_load_u8 s0, s[0:1], 0xfff ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -90,13 +90,13 @@ define amdgpu_ps float @global_load_saddr_i8_offset_4096(ptr addrspace(1) inreg ; GFX11-LABEL: global_load_saddr_i8_offset_4096: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0x1000 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_offset_4096: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_load_u8 s0, s[2:3], 0x1000 +; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x1000 ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -119,13 +119,13 @@ define amdgpu_ps float @global_load_saddr_i8_offset_4097(ptr addrspace(1) inreg ; GFX11-LABEL: global_load_saddr_i8_offset_4097: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0x1000 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:1 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_offset_4097: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_load_u8 s0, s[2:3], 0x1001 +; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x1001 ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -156,16 +156,16 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg4096(ptr addrspace(1) inr ; GFX11-LABEL: global_load_saddr_i8_offset_neg4096: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:-4096 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:-4096 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_neg4096: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_movk_i32 s0, 0xf000 -; GFX12-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX12-SDAG-NEXT: s_movk_i32 s2, 0xf000 +; GFX12-SDAG-NEXT: s_mov_b32 s3, -1 ; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 @@ -173,8 +173,8 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg4096(ptr addrspace(1) inr ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_neg4096: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, 0xfffff000 -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, -1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 0xfffff000 +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -207,19 +207,19 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg4097(ptr addrspace(1) inr ; ; GFX11-LABEL: global_load_saddr_i8_offset_neg4097: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], 0xfffff000, s2 +; GFX11-NEXT: v_add_co_u32 v0, s[2:3], 0xfffff000, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s3, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s[2:3] ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:-1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_neg4097: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_movk_i32 s0, 0xefff -; GFX12-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX12-SDAG-NEXT: s_movk_i32 s2, 0xefff +; GFX12-SDAG-NEXT: s_mov_b32 s3, -1 ; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 @@ -227,8 +227,8 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg4097(ptr addrspace(1) inr ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_neg4097: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, 0xffffefff -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, -1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 0xffffefff +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -261,19 +261,19 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg4098(ptr addrspace(1) inr ; ; GFX11-LABEL: global_load_saddr_i8_offset_neg4098: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], 0xfffff000, s2 +; GFX11-NEXT: v_add_co_u32 v0, s[2:3], 0xfffff000, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s3, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s[2:3] ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:-2 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_neg4098: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_movk_i32 s0, 0xeffe -; GFX12-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX12-SDAG-NEXT: s_movk_i32 s2, 0xeffe +; GFX12-SDAG-NEXT: s_mov_b32 s3, -1 ; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 @@ -281,8 +281,8 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg4098(ptr addrspace(1) inr ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_neg4098: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, 0xffffeffe -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, -1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 0xffffeffe +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -313,13 +313,13 @@ define amdgpu_ps float @global_load_saddr_i8_offset_2048(ptr addrspace(1) inreg ; GFX11-LABEL: global_load_saddr_i8_offset_2048: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:2048 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:2048 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_offset_2048: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_load_u8 s0, s[2:3], 0x800 +; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x800 ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -349,13 +349,13 @@ define amdgpu_ps float @global_load_saddr_i8_offset_2049(ptr addrspace(1) inreg ; GFX11-LABEL: global_load_saddr_i8_offset_2049: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:2049 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:2049 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_offset_2049: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_load_u8 s0, s[2:3], 0x801 +; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x801 ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -385,13 +385,13 @@ define amdgpu_ps float @global_load_saddr_i8_offset_2050(ptr addrspace(1) inreg ; GFX11-LABEL: global_load_saddr_i8_offset_2050: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:2050 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:2050 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_offset_2050: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_load_u8 s0, s[2:3], 0x802 +; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x802 ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -414,16 +414,16 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg2048(ptr addrspace(1) inr ; GFX11-LABEL: global_load_saddr_i8_offset_neg2048: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:-2048 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:-2048 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_neg2048: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_movk_i32 s0, 0xf800 -; GFX12-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX12-SDAG-NEXT: s_movk_i32 s2, 0xf800 +; GFX12-SDAG-NEXT: s_mov_b32 s3, -1 ; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 @@ -431,8 +431,8 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg2048(ptr addrspace(1) inr ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_neg2048: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, 0xfffff800 -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, -1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 0xfffff800 +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -464,16 +464,16 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg2049(ptr addrspace(1) inr ; GFX11-LABEL: global_load_saddr_i8_offset_neg2049: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:-2049 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:-2049 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_neg2049: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_movk_i32 s0, 0xf7ff -; GFX12-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX12-SDAG-NEXT: s_movk_i32 s2, 0xf7ff +; GFX12-SDAG-NEXT: s_mov_b32 s3, -1 ; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 @@ -481,8 +481,8 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg2049(ptr addrspace(1) inr ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_neg2049: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, 0xfffff7ff -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, -1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 0xfffff7ff +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -514,16 +514,16 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg2050(ptr addrspace(1) inr ; GFX11-LABEL: global_load_saddr_i8_offset_neg2050: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:-2050 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:-2050 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_neg2050: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_movk_i32 s0, 0xf7fe -; GFX12-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX12-SDAG-NEXT: s_movk_i32 s2, 0xf7fe +; GFX12-SDAG-NEXT: s_mov_b32 s3, -1 ; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 @@ -531,8 +531,8 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg2050(ptr addrspace(1) inr ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_neg2050: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, 0xfffff7fe -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, -1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 0xfffff7fe +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -562,13 +562,13 @@ define amdgpu_ps float @global_load_saddr_i8_offset_0x7FFFFF(ptr addrspace(1) in ; GFX11-LABEL: global_load_saddr_i8_offset_0x7FFFFF: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0x7ff000 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:4095 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:4095 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_offset_0x7FFFFF: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_load_u8 s0, s[2:3], 0x7fffff +; GFX12-NEXT: s_load_u8 s0, s[0:1], 0x7fffff ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -599,19 +599,19 @@ define amdgpu_ps float @global_load_saddr_i8_offset_0xFFFFFF(ptr addrspace(1) in ; ; GFX11-LABEL: global_load_saddr_i8_offset_0xFFFFFF: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], 0xff800000, s2 +; GFX11-NEXT: v_add_co_u32 v0, s[2:3], 0xff800000, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s3, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s[2:3] ; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_0xFFFFFF: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_mov_b32 s0, 0xff800000 -; GFX12-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX12-SDAG-NEXT: s_mov_b32 s2, 0xff800000 +; GFX12-SDAG-NEXT: s_mov_b32 s3, -1 ; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 @@ -619,8 +619,8 @@ define amdgpu_ps float @global_load_saddr_i8_offset_0xFFFFFF(ptr addrspace(1) in ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_0xFFFFFF: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, 0xff800000 -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, -1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 0xff800000 +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -650,14 +650,14 @@ define amdgpu_ps float @global_load_saddr_i8_offset_0xFFFFFFFF(ptr addrspace(1) ; GFX11-LABEL: global_load_saddr_i8_offset_0xFFFFFFFF: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0xfffff000 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:4095 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:4095 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_offset_0xFFFFFFFF: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mov_b32 s0, -1 -; GFX12-NEXT: s_load_u8 s0, s[2:3], s0 offset:0x0 +; GFX12-NEXT: s_mov_b32 s2, -1 +; GFX12-NEXT: s_load_u8 s0, s[0:1], s2 offset:0x0 ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -688,23 +688,23 @@ define amdgpu_ps float @global_load_saddr_i8_offset_0x100000000(ptr addrspace(1) ; GFX11-LABEL: global_load_saddr_i8_offset_0x100000000: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: s_add_i32 s3, s3, 1 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX11-NEXT: s_add_i32 s1, s1, 1 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_0x100000000: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_add_co_i32 s3, s3, 1 -; GFX12-SDAG-NEXT: s_load_u8 s0, s[2:3], 0x0 +; GFX12-SDAG-NEXT: s_add_co_i32 s1, s1, 1 +; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-SDAG-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_0x100000000: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, 0 -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, 1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 0 +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 1 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -736,19 +736,19 @@ define amdgpu_ps float @global_load_saddr_i8_offset_0x100000001(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_i8_offset_0x100000001: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 +; GFX11-NEXT: v_add_co_u32 v0, s[2:3], 0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s3, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s1, s[2:3] ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_0x100000001: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_mov_b32 s0, 1 +; GFX12-SDAG-NEXT: s_mov_b32 s2, 1 ; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_mov_b32 s1, s0 -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] +; GFX12-SDAG-NEXT: s_mov_b32 s3, s2 +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 @@ -756,8 +756,8 @@ define amdgpu_ps float @global_load_saddr_i8_offset_0x100000001(ptr addrspace(1) ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_0x100000001: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, 1 -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, 1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 1 +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 1 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -789,19 +789,19 @@ define amdgpu_ps float @global_load_saddr_i8_offset_0x100000FFF(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_i8_offset_0x100000FFF: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 +; GFX11-NEXT: v_add_co_u32 v0, s[2:3], 0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s3, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s1, s[2:3] ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4095 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_0x100000FFF: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_movk_i32 s0, 0xfff -; GFX12-SDAG-NEXT: s_mov_b32 s1, 1 +; GFX12-SDAG-NEXT: s_movk_i32 s2, 0xfff +; GFX12-SDAG-NEXT: s_mov_b32 s3, 1 ; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 @@ -809,8 +809,8 @@ define amdgpu_ps float @global_load_saddr_i8_offset_0x100000FFF(ptr addrspace(1) ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_0x100000FFF: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, 0xfff -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, 1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 0xfff +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 1 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -842,19 +842,19 @@ define amdgpu_ps float @global_load_saddr_i8_offset_0x100001000(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_i8_offset_0x100001000: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], 0x1000, s2 +; GFX11-NEXT: v_add_co_u32 v0, s[2:3], 0x1000, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s3, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 1, s1, s[2:3] ; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_0x100001000: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_movk_i32 s0, 0x1000 -; GFX12-SDAG-NEXT: s_mov_b32 s1, 1 +; GFX12-SDAG-NEXT: s_movk_i32 s2, 0x1000 +; GFX12-SDAG-NEXT: s_mov_b32 s3, 1 ; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 @@ -862,8 +862,8 @@ define amdgpu_ps float @global_load_saddr_i8_offset_0x100001000(ptr addrspace(1) ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_0x100001000: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, 0x1000 -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, 1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 0x1000 +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 1 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -896,19 +896,19 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg0xFFFFFFFF(ptr addrspace( ; ; GFX11-LABEL: global_load_saddr_i8_offset_neg0xFFFFFFFF: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], 0x1000, s2 +; GFX11-NEXT: v_add_co_u32 v0, s[2:3], 0x1000, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s3, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s[2:3] ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:-4095 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_neg0xFFFFFFFF: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_mov_b32 s0, 1 -; GFX12-SDAG-NEXT: s_mov_b32 s1, -1 +; GFX12-SDAG-NEXT: s_mov_b32 s2, 1 +; GFX12-SDAG-NEXT: s_mov_b32 s3, -1 ; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 @@ -916,8 +916,8 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg0xFFFFFFFF(ptr addrspace( ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_neg0xFFFFFFFF: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, 1 -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, -1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 1 +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -949,23 +949,23 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg0x100000000(ptr addrspace ; GFX11-LABEL: global_load_saddr_i8_offset_neg0x100000000: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: s_add_i32 s3, s3, -1 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX11-NEXT: s_add_i32 s1, s1, -1 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_neg0x100000000: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_add_co_i32 s3, s3, -1 -; GFX12-SDAG-NEXT: s_load_u8 s0, s[2:3], 0x0 +; GFX12-SDAG-NEXT: s_add_co_i32 s1, s1, -1 +; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-SDAG-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_neg0x100000000: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, 0 -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, -1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 0 +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -997,19 +997,19 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg0x100000001(ptr addrspace ; ; GFX11-LABEL: global_load_saddr_i8_offset_neg0x100000001: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], 0, s2 +; GFX11-NEXT: v_add_co_u32 v0, s[2:3], 0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s3, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, s1, s[2:3] ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:-1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_offset_neg0x100000001: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_mov_b32 s0, -1 -; GFX12-SDAG-NEXT: s_mov_b32 s1, -2 +; GFX12-SDAG-NEXT: s_mov_b32 s2, -1 +; GFX12-SDAG-NEXT: s_mov_b32 s3, -2 ; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[0:1] +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-SDAG-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 @@ -1017,8 +1017,8 @@ define amdgpu_ps float @global_load_saddr_i8_offset_neg0x100000001(ptr addrspace ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_offset_neg0x100000001: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, -1 -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, -2 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, -1 +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -2 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 ; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0 ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0 @@ -1044,13 +1044,13 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -1081,13 +1081,13 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_4095(ptr addrspace ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_4095: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:4095 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:4095 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_offset_4095: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] offset:4095 +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] offset:4095 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -1124,10 +1124,10 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_4096(ptr addrspace ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_4096: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 +; GFX11-NEXT: v_add_co_u32 v0, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_u32 v0, vcc, 0x1000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s[2:3] ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc ; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1135,7 +1135,7 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_4096(ptr addrspace ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_offset_4096: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] offset:4096 +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] offset:4096 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -1167,13 +1167,13 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_neg4096(ptr addrsp ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4096: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:-4096 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:-4096 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4096: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] offset:-4096 +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] offset:-4096 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -1210,10 +1210,10 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_neg4097(ptr addrsp ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4097: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 +; GFX11-NEXT: v_add_co_u32 v0, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_u32 v0, vcc, 0xfffff000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s[2:3] ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:-1 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1221,7 +1221,7 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_neg4097(ptr addrsp ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg4097: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] offset:-4097 +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] offset:-4097 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -1243,13 +1243,13 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_2047(ptr addrspace ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_2047: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:2047 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:2047 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_offset_2047: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] offset:2047 +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] offset:2047 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -1281,13 +1281,13 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_2048(ptr addrspace ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_2048: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:2048 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:2048 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_offset_2048: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] offset:2048 +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] offset:2048 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -1309,13 +1309,13 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_neg2048(ptr addrsp ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg2048: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:-2048 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:-2048 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg2048: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] offset:-2048 +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] offset:-2048 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -1347,13 +1347,13 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_neg2049(ptr addrsp ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg2049: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:-2049 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:-2049 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_offset_neg2049: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] offset:-2049 +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] offset:-2049 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -1390,10 +1390,10 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_0x7FFFFF(ptr addrs ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_0x7FFFFF: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 +; GFX11-NEXT: v_add_co_u32 v0, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_u32 v0, vcc, 0x7ff000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s[2:3] ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4095 ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1401,7 +1401,7 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_0x7FFFFF(ptr addrs ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_offset_0x7FFFFF: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] offset:8388607 +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] offset:8388607 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1437,10 +1437,10 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_0xFFFFFF(ptr addrs ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_0xFFFFFF: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, s[0:1], s2, v0 +; GFX11-NEXT: v_add_co_u32 v0, s[2:3], s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_add_co_u32 v0, vcc, 0xff800000, v0 -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, 0, s[0:1] +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s1, 0, s[2:3] ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, -1, v1, vcc ; GFX11-NEXT: global_load_u8 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) @@ -1448,7 +1448,7 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_0xFFFFFF(ptr addrs ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_offset_0xFFFFFF: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] offset:-8388608 +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] offset:-8388608 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1480,13 +1480,13 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_offset_4095_gep_order(ptr ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_offset_4095_gep_order: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:4095 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:4095 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_offset_4095_gep_order: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] offset:4095 +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] offset:4095 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -1508,13 +1508,13 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_ptrtoint(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -1537,13 +1537,13 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add(ptr ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -1566,13 +1566,13 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_ ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset0: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:128 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset0: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] offset:128 +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] offset:128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -1596,13 +1596,13 @@ define amdgpu_ps float @global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_ ; ; GFX11-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset1: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:128 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_vgpr_ptrtoint_commute_add_imm_offset1: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] offset:128 +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] offset:128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -1768,14 +1768,14 @@ define amdgpu_ps float @global_load_saddr_i8_zext_uniform_offset(ptr addrspace(1 ; ; GFX11-LABEL: global_load_saddr_i8_zext_uniform_offset: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_mov_b32_e32 v0, s4 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_uniform_offset: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_load_u8 s0, s[2:3], s4 offset:0x0 +; GFX12-NEXT: s_load_u8 s0, s[0:1], s2 offset:0x0 ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -1798,16 +1798,16 @@ define amdgpu_ps float @global_load_saddr_i8_zext_uniform_offset_immoffset(ptr a ; ; GFX11-LABEL: global_load_saddr_i8_zext_uniform_offset_immoffset: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_mov_b32_e32 v0, s4 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:-24 +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:-24 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i8_zext_uniform_offset_immoffset: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_mov_b32 s5, 0 +; GFX12-SDAG-NEXT: s_mov_b32 s3, 0 ; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1) -; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[2:3], s[4:5] +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] ; GFX12-SDAG-NEXT: s_movk_i32 s2, 0xffe8 ; GFX12-SDAG-NEXT: s_mov_b32 s3, -1 ; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], s[2:3] @@ -1818,8 +1818,8 @@ define amdgpu_ps float @global_load_saddr_i8_zext_uniform_offset_immoffset(ptr a ; ; GFX12-GISEL-LABEL: global_load_saddr_i8_zext_uniform_offset_immoffset: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_add_co_u32 s0, s2, s4 -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s3, 0 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, s2 +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0 ; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 0xffffffe8 ; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, -1 ; GFX12-GISEL-NEXT: s_load_u8 s0, s[0:1], 0x0 @@ -1846,14 +1846,14 @@ define amdgpu_ps float @global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add(ptr ; ; GFX11-LABEL: global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_mov_b32_e32 v0, s4 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_load_u8 s0, s[2:3], s4 offset:0x0 +; GFX12-NEXT: s_load_u8 s0, s[0:1], s2 offset:0x0 ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -1878,14 +1878,14 @@ define amdgpu_ps float @global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_ ; ; GFX11-LABEL: global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_offset0: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_mov_b32_e32 v0, s4 -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:128 +; GFX11-NEXT: v_mov_b32_e32 v0, s2 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i8_zext_sgpr_ptrtoint_commute_add_imm_offset0: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_load_u8 s0, s[2:3], s4 offset:0x80 +; GFX12-NEXT: s_load_u8 s0, s[0:1], s2 offset:0x80 ; GFX12-NEXT: s_wait_kmcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -1920,7 +1920,7 @@ define amdgpu_ps float @global_load_i8_vgpr64_sgpr32(ptr addrspace(1) %vbase, i3 ; ; GFX11-LABEL: global_load_i8_vgpr64_sgpr32: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, vcc, v0, s2 +; GFX11-NEXT: v_add_co_u32 v0, vcc, v0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc ; GFX11-NEXT: global_load_u8 v0, v[0:1], off @@ -1929,7 +1929,7 @@ define amdgpu_ps float @global_load_i8_vgpr64_sgpr32(ptr addrspace(1) %vbase, i3 ; ; GFX12-SDAG-LABEL: global_load_i8_vgpr64_sgpr32: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc, v0, s2 +; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc, v0, s0 ; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc ; GFX12-SDAG-NEXT: global_load_u8 v0, v[0:1], off @@ -1938,9 +1938,9 @@ define amdgpu_ps float @global_load_i8_vgpr64_sgpr32(ptr addrspace(1) %vbase, i3 ; ; GFX12-GISEL-LABEL: global_load_i8_vgpr64_sgpr32: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_mov_b32 s3, 0 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; GFX12-GISEL-NEXT: s_mov_b32 s1, 0 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v3, s1 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc, v0, v2 ; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc @@ -1977,7 +1977,7 @@ define amdgpu_ps float @global_load_i8_vgpr64_sgpr32_offset_4095(ptr addrspace(1 ; ; GFX11-LABEL: global_load_i8_vgpr64_sgpr32_offset_4095: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_add_co_u32 v0, vcc, v0, s2 +; GFX11-NEXT: v_add_co_u32 v0, vcc, v0, s0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc ; GFX11-NEXT: global_load_u8 v0, v[0:1], off offset:4095 @@ -1986,7 +1986,7 @@ define amdgpu_ps float @global_load_i8_vgpr64_sgpr32_offset_4095(ptr addrspace(1 ; ; GFX12-SDAG-LABEL: global_load_i8_vgpr64_sgpr32_offset_4095: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc, v0, s2 +; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc, v0, s0 ; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, 0, v1, vcc ; GFX12-SDAG-NEXT: global_load_u8 v0, v[0:1], off offset:4095 @@ -1995,9 +1995,9 @@ define amdgpu_ps float @global_load_i8_vgpr64_sgpr32_offset_4095(ptr addrspace(1 ; ; GFX12-GISEL-LABEL: global_load_i8_vgpr64_sgpr32_offset_4095: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: s_mov_b32 s3, 0 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; GFX12-GISEL-NEXT: s_mov_b32 s1, 0 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v3, s1 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-GISEL-NEXT: v_add_co_u32 v0, vcc, v0, v2 ; GFX12-GISEL-NEXT: v_add_co_ci_u32_e64 v1, null, v1, v3, vcc @@ -2051,9 +2051,9 @@ define amdgpu_ps float @global_load_saddr_f32_natural_addressing(ptr addrspace(1 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] -; GFX11-NEXT: v_add_co_u32 v0, vcc, s2, v0 +; GFX11-NEXT: v_add_co_u32 v0, vcc, s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, v1, vcc +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc ; GFX11-NEXT: global_load_b32 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog @@ -2065,9 +2065,9 @@ define amdgpu_ps float @global_load_saddr_f32_natural_addressing(ptr addrspace(1 ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-SDAG-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1] -; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc, s2, v0 +; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc, s0, v0 ; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, s3, v1, vcc +; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc ; GFX12-SDAG-NEXT: global_load_b32 v0, v[0:1], off ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-NEXT: ; return to shader part epilog @@ -2076,8 +2076,8 @@ define amdgpu_ps float @global_load_saddr_f32_natural_addressing(ptr addrspace(1 ; GFX12-GISEL: ; %bb.0: ; GFX12-GISEL-NEXT: global_load_b32 v0, v[0:1], off ; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v3, s1 ; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-GISEL-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1] @@ -2108,7 +2108,7 @@ define amdgpu_ps float @global_load_saddr_f32_natural_addressing_immoffset(ptr a ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b32 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] offset:128 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] offset:128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; @@ -2116,7 +2116,7 @@ define amdgpu_ps float @global_load_saddr_f32_natural_addressing_immoffset(ptr a ; GFX12: ; %bb.0: ; GFX12-NEXT: global_load_b32 v0, v[0:1], off ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:128 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] offset:128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %voffset = load i32, ptr addrspace(1) %voffset.ptr @@ -2143,7 +2143,7 @@ define amdgpu_ps float @global_load_f32_saddr_zext_vgpr_range(ptr addrspace(1) i ; GFX11-NEXT: global_load_b32 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; @@ -2152,7 +2152,7 @@ define amdgpu_ps float @global_load_f32_saddr_zext_vgpr_range(ptr addrspace(1) i ; GFX12-NEXT: global_load_b32 v0, v[0:1], off ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %voffset = load i32, ptr addrspace(1) %voffset.ptr, !range !0, !noundef !{} @@ -2178,7 +2178,7 @@ define amdgpu_ps float @global_load_f32_saddr_zext_vgpr_range_imm_offset(ptr add ; GFX11-NEXT: global_load_b32 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] offset:400 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] offset:400 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; @@ -2187,7 +2187,7 @@ define amdgpu_ps float @global_load_f32_saddr_zext_vgpr_range_imm_offset(ptr add ; GFX12-NEXT: global_load_b32 v0, v[0:1], off ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0 -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:400 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] offset:400 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %voffset = load i32, ptr addrspace(1) %voffset.ptr, !range !0, !noundef !{} @@ -2232,9 +2232,9 @@ define amdgpu_ps float @global_load_f32_saddr_zext_vgpr_range_too_large(ptr addr ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX11-NEXT: v_lshlrev_b64 v[0:1], 2, v[0:1] -; GFX11-NEXT: v_add_co_u32 v0, vcc, s2, v0 +; GFX11-NEXT: v_add_co_u32 v0, vcc, s0, v0 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s3, v1, vcc +; GFX11-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc ; GFX11-NEXT: global_load_b32 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog @@ -2246,9 +2246,9 @@ define amdgpu_ps float @global_load_f32_saddr_zext_vgpr_range_too_large(ptr addr ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-SDAG-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1] -; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc, s2, v0 +; GFX12-SDAG-NEXT: v_add_co_u32 v0, vcc, s0, v0 ; GFX12-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, s3, v1, vcc +; GFX12-SDAG-NEXT: v_add_co_ci_u32_e64 v1, null, s1, v1, vcc ; GFX12-SDAG-NEXT: global_load_b32 v0, v[0:1], off ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-NEXT: ; return to shader part epilog @@ -2257,8 +2257,8 @@ define amdgpu_ps float @global_load_f32_saddr_zext_vgpr_range_too_large(ptr addr ; GFX12-GISEL: ; %bb.0: ; GFX12-GISEL-NEXT: global_load_b32 v0, v[0:1], off ; GFX12-GISEL-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s2 -; GFX12-GISEL-NEXT: v_mov_b32_e32 v3, s3 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v2, s0 +; GFX12-GISEL-NEXT: v_mov_b32_e32 v3, s1 ; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX12-GISEL-NEXT: v_lshlrev_b64_e32 v[0:1], 2, v[0:1] @@ -2288,37 +2288,37 @@ define amdgpu_ps half @global_load_saddr_i16(ptr addrspace(1) inreg %sbase, i32 ; ; GFX11-TRUE16-LABEL: global_load_saddr_i16: ; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] +; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: global_load_saddr_i16: ; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX11-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_i16: ; GFX12-SDAG-TRUE16: ; %bb.0: -; GFX12-SDAG-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] +; GFX12-SDAG-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] ; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_i16: ; GFX12-SDAG-FAKE16: ; %bb.0: -; GFX12-SDAG-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX12-SDAG-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16: ; GFX12-GISEL-TRUE16: ; %bb.0: -; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] +; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] ; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16: ; GFX12-GISEL-FAKE16: ; %bb.0: -; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-FAKE16-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2337,37 +2337,37 @@ define amdgpu_ps half @global_load_saddr_i16_immneg128(ptr addrspace(1) inreg %s ; ; GFX11-TRUE16-LABEL: global_load_saddr_i16_immneg128: ; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] offset:-128 +; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] offset:-128 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: global_load_saddr_i16_immneg128: ; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] offset:-128 +; GFX11-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] offset:-128 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_i16_immneg128: ; GFX12-SDAG-TRUE16: ; %bb.0: -; GFX12-SDAG-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] offset:-128 +; GFX12-SDAG-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] offset:-128 ; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_i16_immneg128: ; GFX12-SDAG-FAKE16: ; %bb.0: -; GFX12-SDAG-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] offset:-128 +; GFX12-SDAG-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] offset:-128 ; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_immneg128: ; GFX12-GISEL-TRUE16: ; %bb.0: -; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] offset:-128 +; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] offset:-128 ; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_immneg128: ; GFX12-GISEL-FAKE16: ; %bb.0: -; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] offset:-128 +; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] offset:-128 ; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-FAKE16-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2387,31 +2387,31 @@ define amdgpu_ps half @global_load_saddr_f16(ptr addrspace(1) inreg %sbase, i32 ; ; GFX11-TRUE16-LABEL: global_load_saddr_f16: ; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] +; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: global_load_saddr_f16: ; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX11-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_f16: ; GFX12-SDAG-TRUE16: ; %bb.0: -; GFX12-SDAG-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] +; GFX12-SDAG-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] ; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_f16: ; GFX12-SDAG-FAKE16: ; %bb.0: -; GFX12-SDAG-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX12-SDAG-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-LABEL: global_load_saddr_f16: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX12-GISEL-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2429,31 +2429,31 @@ define amdgpu_ps half @global_load_saddr_f16_immneg128(ptr addrspace(1) inreg %s ; ; GFX11-TRUE16-LABEL: global_load_saddr_f16_immneg128: ; GFX11-TRUE16: ; %bb.0: -; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] offset:-128 +; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] offset:-128 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-FAKE16-LABEL: global_load_saddr_f16_immneg128: ; GFX11-FAKE16: ; %bb.0: -; GFX11-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] offset:-128 +; GFX11-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] offset:-128 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_f16_immneg128: ; GFX12-SDAG-TRUE16: ; %bb.0: -; GFX12-SDAG-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] offset:-128 +; GFX12-SDAG-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] offset:-128 ; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_f16_immneg128: ; GFX12-SDAG-FAKE16: ; %bb.0: -; GFX12-SDAG-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] offset:-128 +; GFX12-SDAG-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] offset:-128 ; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-LABEL: global_load_saddr_f16_immneg128: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: global_load_u16 v0, v0, s[2:3] offset:-128 +; GFX12-GISEL-NEXT: global_load_u16 v0, v0, s[0:1] offset:-128 ; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2472,13 +2472,13 @@ define amdgpu_ps float @global_load_saddr_i32(ptr addrspace(1) inreg %sbase, i32 ; ; GFX11-LABEL: global_load_saddr_i32: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i32: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2497,13 +2497,13 @@ define amdgpu_ps float @global_load_saddr_i32_immneg128(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_load_saddr_i32_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i32_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2523,13 +2523,13 @@ define amdgpu_ps float @global_load_saddr_f32(ptr addrspace(1) inreg %sbase, i32 ; ; GFX11-LABEL: global_load_saddr_f32: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_f32: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2547,13 +2547,13 @@ define amdgpu_ps float @global_load_saddr_f32_immneg128(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_load_saddr_f32_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_f32_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2572,13 +2572,13 @@ define amdgpu_ps <2 x half> @global_load_saddr_v2i16(ptr addrspace(1) inreg %sba ; ; GFX11-LABEL: global_load_saddr_v2i16: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v2i16: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2597,13 +2597,13 @@ define amdgpu_ps <2 x half> @global_load_saddr_v2i16_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_v2i16_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v2i16_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2623,13 +2623,13 @@ define amdgpu_ps <2 x half> @global_load_saddr_v2f16(ptr addrspace(1) inreg %sba ; ; GFX11-LABEL: global_load_saddr_v2f16: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v2f16: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2647,13 +2647,13 @@ define amdgpu_ps <2 x half> @global_load_saddr_v2f16_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_v2f16_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v2f16_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2672,13 +2672,13 @@ define amdgpu_ps <2 x half> @global_load_saddr_p3(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_load_saddr_p3: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_p3: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2698,13 +2698,13 @@ define amdgpu_ps <2 x half> @global_load_saddr_p3_immneg128(ptr addrspace(1) inr ; ; GFX11-LABEL: global_load_saddr_p3_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_p3_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2725,13 +2725,13 @@ define amdgpu_ps <2 x float> @global_load_saddr_f64(ptr addrspace(1) inreg %sbas ; ; GFX11-LABEL: global_load_saddr_f64: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_f64: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2750,13 +2750,13 @@ define amdgpu_ps <2 x float> @global_load_saddr_f64_immneg128(ptr addrspace(1) i ; ; GFX11-LABEL: global_load_saddr_f64_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_f64_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2776,13 +2776,13 @@ define amdgpu_ps <2 x float> @global_load_saddr_i64(ptr addrspace(1) inreg %sbas ; ; GFX11-LABEL: global_load_saddr_i64: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i64: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2801,13 +2801,13 @@ define amdgpu_ps <2 x float> @global_load_saddr_i64_immneg128(ptr addrspace(1) i ; ; GFX11-LABEL: global_load_saddr_i64_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i64_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2827,13 +2827,13 @@ define amdgpu_ps <2 x float> @global_load_saddr_v2f32(ptr addrspace(1) inreg %sb ; ; GFX11-LABEL: global_load_saddr_v2f32: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v2f32: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2851,13 +2851,13 @@ define amdgpu_ps <2 x float> @global_load_saddr_v2f32_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_v2f32_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v2f32_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2876,13 +2876,13 @@ define amdgpu_ps <2 x float> @global_load_saddr_v2i32(ptr addrspace(1) inreg %sb ; ; GFX11-LABEL: global_load_saddr_v2i32: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v2i32: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2901,13 +2901,13 @@ define amdgpu_ps <2 x float> @global_load_saddr_v2i32_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_v2i32_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v2i32_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2927,13 +2927,13 @@ define amdgpu_ps <2 x float> @global_load_saddr_v4i16(ptr addrspace(1) inreg %sb ; ; GFX11-LABEL: global_load_saddr_v4i16: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v4i16: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2952,13 +2952,13 @@ define amdgpu_ps <2 x float> @global_load_saddr_v4i16_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_v4i16_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v4i16_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -2978,13 +2978,13 @@ define amdgpu_ps <2 x float> @global_load_saddr_v4f16(ptr addrspace(1) inreg %sb ; ; GFX11-LABEL: global_load_saddr_v4f16: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v4f16: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3003,13 +3003,13 @@ define amdgpu_ps <2 x float> @global_load_saddr_v4f16_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_v4f16_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v4f16_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3029,13 +3029,13 @@ define amdgpu_ps <2 x float> @global_load_saddr_p1(ptr addrspace(1) inreg %sbase ; ; GFX11-LABEL: global_load_saddr_p1: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_p1: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3055,13 +3055,13 @@ define amdgpu_ps <2 x float> @global_load_saddr_p1_immneg128(ptr addrspace(1) in ; ; GFX11-LABEL: global_load_saddr_p1_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_p1_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3082,13 +3082,13 @@ define amdgpu_ps <3 x float> @global_load_saddr_v3f32(ptr addrspace(1) inreg %sb ; ; GFX11-LABEL: global_load_saddr_v3f32: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b96 v[0:2], v0, s[2:3] +; GFX11-NEXT: global_load_b96 v[0:2], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v3f32: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b96 v[0:2], v0, s[2:3] +; GFX12-NEXT: global_load_b96 v[0:2], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3106,13 +3106,13 @@ define amdgpu_ps <3 x float> @global_load_saddr_v3f32_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_v3f32_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b96 v[0:2], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b96 v[0:2], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v3f32_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b96 v[0:2], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b96 v[0:2], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3131,13 +3131,13 @@ define amdgpu_ps <3 x float> @global_load_saddr_v3i32(ptr addrspace(1) inreg %sb ; ; GFX11-LABEL: global_load_saddr_v3i32: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b96 v[0:2], v0, s[2:3] +; GFX11-NEXT: global_load_b96 v[0:2], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v3i32: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b96 v[0:2], v0, s[2:3] +; GFX12-NEXT: global_load_b96 v[0:2], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3156,13 +3156,13 @@ define amdgpu_ps <3 x float> @global_load_saddr_v3i32_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_v3i32_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b96 v[0:2], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b96 v[0:2], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v3i32_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b96 v[0:2], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b96 v[0:2], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3182,13 +3182,13 @@ define amdgpu_ps <6 x half> @global_load_saddr_v6f16(ptr addrspace(1) inreg %sba ; ; GFX11-LABEL: global_load_saddr_v6f16: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b96 v[0:2], v0, s[2:3] +; GFX11-NEXT: global_load_b96 v[0:2], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v6f16: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b96 v[0:2], v0, s[2:3] +; GFX12-NEXT: global_load_b96 v[0:2], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3206,13 +3206,13 @@ define amdgpu_ps <6 x half> @global_load_saddr_v6f16_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_v6f16_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b96 v[0:2], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b96 v[0:2], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v6f16_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b96 v[0:2], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b96 v[0:2], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3231,13 +3231,13 @@ define amdgpu_ps <4 x float> @global_load_saddr_v4f32(ptr addrspace(1) inreg %sb ; ; GFX11-LABEL: global_load_saddr_v4f32: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v4f32: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX12-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3255,13 +3255,13 @@ define amdgpu_ps <4 x float> @global_load_saddr_v4f32_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_v4f32_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v4f32_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3280,13 +3280,13 @@ define amdgpu_ps <4 x float> @global_load_saddr_v4i32(ptr addrspace(1) inreg %sb ; ; GFX11-LABEL: global_load_saddr_v4i32: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v4i32: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX12-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3305,13 +3305,13 @@ define amdgpu_ps <4 x float> @global_load_saddr_v4i32_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_v4i32_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v4i32_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3331,13 +3331,13 @@ define amdgpu_ps <4 x float> @global_load_saddr_v2i64(ptr addrspace(1) inreg %sb ; ; GFX11-LABEL: global_load_saddr_v2i64: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v2i64: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX12-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3356,13 +3356,13 @@ define amdgpu_ps <4 x float> @global_load_saddr_v2i64_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_v2i64_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v2i64_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3382,13 +3382,13 @@ define amdgpu_ps <4 x float> @global_load_saddr_i128(ptr addrspace(1) inreg %sba ; ; GFX11-LABEL: global_load_saddr_i128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX12-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3407,13 +3407,13 @@ define amdgpu_ps <4 x float> @global_load_saddr_i128_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_i128_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i128_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3433,13 +3433,13 @@ define amdgpu_ps <4 x float> @global_load_saddr_v2p1(ptr addrspace(1) inreg %sba ; ; GFX11-LABEL: global_load_saddr_v2p1: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v2p1: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX12-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3459,13 +3459,13 @@ define amdgpu_ps <4 x float> @global_load_saddr_v2p1_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_v2p1_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v2p1_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3486,13 +3486,13 @@ define amdgpu_ps <4 x float> @global_load_saddr_v4p3(ptr addrspace(1) inreg %sba ; ; GFX11-LABEL: global_load_saddr_v4p3: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v4p3: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b128 v[0:3], v0, s[2:3] +; GFX12-NEXT: global_load_b128 v[0:3], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3512,13 +3512,13 @@ define amdgpu_ps <4 x float> @global_load_saddr_v4p3_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_v4p3_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_v4p3_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b128 v[0:3], v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_b128 v[0:3], v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3543,13 +3543,13 @@ define amdgpu_ps float @global_sextload_saddr_i8(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_sextload_saddr_i8: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_i8 v0, v0, s[2:3] +; GFX11-NEXT: global_load_i8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_sextload_saddr_i8: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_i8 v0, v0, s[2:3] +; GFX12-NEXT: global_load_i8 v0, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3569,13 +3569,13 @@ define amdgpu_ps float @global_sextload_saddr_i8_immneg128(ptr addrspace(1) inre ; ; GFX11-LABEL: global_sextload_saddr_i8_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_i8 v0, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_i8 v0, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_sextload_saddr_i8_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_i8 v0, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_i8 v0, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3596,13 +3596,13 @@ define amdgpu_ps float @global_sextload_saddr_i16(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_sextload_saddr_i16: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_i16 v0, v0, s[2:3] +; GFX11-NEXT: global_load_i16 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_sextload_saddr_i16: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_i16 v0, v0, s[2:3] +; GFX12-NEXT: global_load_i16 v0, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3622,13 +3622,13 @@ define amdgpu_ps float @global_sextload_saddr_i16_immneg128(ptr addrspace(1) inr ; ; GFX11-LABEL: global_sextload_saddr_i16_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_i16 v0, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_i16 v0, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_sextload_saddr_i16_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_i16 v0, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_i16 v0, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3649,13 +3649,13 @@ define amdgpu_ps float @global_zextload_saddr_i8(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_zextload_saddr_i8: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_zextload_saddr_i8: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3675,13 +3675,13 @@ define amdgpu_ps float @global_zextload_saddr_i8_immneg128(ptr addrspace(1) inre ; ; GFX11-LABEL: global_zextload_saddr_i8_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u8 v0, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_u8 v0, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_zextload_saddr_i8_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u8 v0, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_u8 v0, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3702,13 +3702,13 @@ define amdgpu_ps float @global_zextload_saddr_i16(ptr addrspace(1) inreg %sbase, ; ; GFX11-LABEL: global_zextload_saddr_i16: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_zextload_saddr_i16: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX12-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3728,13 +3728,13 @@ define amdgpu_ps float @global_zextload_saddr_i16_immneg128(ptr addrspace(1) inr ; ; GFX11-LABEL: global_zextload_saddr_i16_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_u16 v0, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_u16 v0, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_zextload_saddr_i16_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_u16 v0, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_u16 v0, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog %zext.offset = zext i32 %voffset to i64 @@ -3768,7 +3768,7 @@ define amdgpu_ps float @atomic_global_load_saddr_i32(ptr addrspace(1) inreg %sba ; ; GFX11-LABEL: atomic_global_load_saddr_i32: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] glc +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -3776,7 +3776,7 @@ define amdgpu_ps float @atomic_global_load_saddr_i32(ptr addrspace(1) inreg %sba ; ; GFX12-LABEL: atomic_global_load_saddr_i32: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] scope:SCOPE_SYS +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] scope:SCOPE_SYS ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: ; return to shader part epilog @@ -3805,7 +3805,7 @@ define amdgpu_ps float @atomic_global_load_saddr_i32_immneg128(ptr addrspace(1) ; ; GFX11-LABEL: atomic_global_load_saddr_i32_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 glc +; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -3813,7 +3813,7 @@ define amdgpu_ps float @atomic_global_load_saddr_i32_immneg128(ptr addrspace(1) ; ; GFX12-LABEL: atomic_global_load_saddr_i32_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b32 v0, v0, s[2:3] offset:-128 scope:SCOPE_SYS +; GFX12-NEXT: global_load_b32 v0, v0, s[0:1] offset:-128 scope:SCOPE_SYS ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: ; return to shader part epilog @@ -3843,7 +3843,7 @@ define amdgpu_ps <2 x float> @atomic_global_load_saddr_i64(ptr addrspace(1) inre ; ; GFX11-LABEL: atomic_global_load_saddr_i64: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] glc +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -3851,7 +3851,7 @@ define amdgpu_ps <2 x float> @atomic_global_load_saddr_i64(ptr addrspace(1) inre ; ; GFX12-LABEL: atomic_global_load_saddr_i64: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] scope:SCOPE_SYS +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] scope:SCOPE_SYS ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: ; return to shader part epilog @@ -3880,7 +3880,7 @@ define amdgpu_ps <2 x float> @atomic_global_load_saddr_i64_immneg128(ptr addrspa ; ; GFX11-LABEL: atomic_global_load_saddr_i64_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 glc +; GFX11-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 glc ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: buffer_gl1_inv ; GFX11-NEXT: buffer_gl0_inv @@ -3888,7 +3888,7 @@ define amdgpu_ps <2 x float> @atomic_global_load_saddr_i64_immneg128(ptr addrspa ; ; GFX12-LABEL: atomic_global_load_saddr_i64_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:-128 scope:SCOPE_SYS +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:-128 scope:SCOPE_SYS ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: global_inv scope:SCOPE_SYS ; GFX12-NEXT: ; return to shader part epilog @@ -3913,25 +3913,25 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_undef_hi(ptr addrspace( ; ; GFX11-LABEL: global_load_saddr_i16_d16lo_undef_hi: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_b16 v0, v0, s[2:3] +; GFX11-NEXT: global_load_d16_b16 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i16_d16lo_undef_hi: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: global_load_d16_b16 v0, v0, s[2:3] +; GFX12-SDAG-NEXT: global_load_d16_b16 v0, v0, s[0:1] ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16lo_undef_hi: ; GFX12-GISEL-TRUE16: ; %bb.0: -; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] +; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] ; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16lo_undef_hi: ; GFX12-GISEL-FAKE16: ; %bb.0: -; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -3954,25 +3954,25 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_undef_hi_immneg128(ptr ; ; GFX11-LABEL: global_load_saddr_i16_d16lo_undef_hi_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_b16 v0, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_d16_b16 v0, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i16_d16lo_undef_hi_immneg128: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: global_load_d16_b16 v0, v0, s[2:3] offset:-128 +; GFX12-SDAG-NEXT: global_load_d16_b16 v0, v0, s[0:1] offset:-128 ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16lo_undef_hi_immneg128: ; GFX12-GISEL-TRUE16: ; %bb.0: -; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] offset:-128 +; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] offset:-128 ; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16lo_undef_hi_immneg128: ; GFX12-GISEL-FAKE16: ; %bb.0: -; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] offset:-128 +; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] offset:-128 ; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -3999,7 +3999,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_zero_hi(ptr addrspace(1 ; GFX11-LABEL: global_load_saddr_i16_d16lo_zero_hi: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: global_load_d16_b16 v1, v0, s[2:3] +; GFX11-NEXT: global_load_d16_b16 v1, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: ; return to shader part epilog @@ -4007,21 +4007,21 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_zero_hi(ptr addrspace(1 ; GFX12-SDAG-LABEL: global_load_saddr_i16_d16lo_zero_hi: ; GFX12-SDAG: ; %bb.0: ; GFX12-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-SDAG-NEXT: global_load_d16_b16 v1, v0, s[2:3] +; GFX12-SDAG-NEXT: global_load_d16_b16 v1, v0, s[0:1] ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-SDAG-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16lo_zero_hi: ; GFX12-GISEL-TRUE16: ; %bb.0: -; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] +; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] ; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l ; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16lo_zero_hi: ; GFX12-GISEL-FAKE16: ; %bb.0: -; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-GISEL-FAKE16-NEXT: ; return to shader part epilog @@ -4045,7 +4045,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_zero_hi_immneg128(ptr a ; GFX11-LABEL: global_load_saddr_i16_d16lo_zero_hi_immneg128: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: global_load_d16_b16 v1, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_d16_b16 v1, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: ; return to shader part epilog @@ -4053,21 +4053,21 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_zero_hi_immneg128(ptr a ; GFX12-SDAG-LABEL: global_load_saddr_i16_d16lo_zero_hi_immneg128: ; GFX12-SDAG: ; %bb.0: ; GFX12-SDAG-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-SDAG-NEXT: global_load_d16_b16 v1, v0, s[2:3] offset:-128 +; GFX12-SDAG-NEXT: global_load_d16_b16 v1, v0, s[0:1] offset:-128 ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-SDAG-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16lo_zero_hi_immneg128: ; GFX12-GISEL-TRUE16: ; %bb.0: -; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] offset:-128 +; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] offset:-128 ; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-TRUE16-NEXT: v_cvt_u32_u16_e32 v0, v0.l ; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16lo_zero_hi_immneg128: ; GFX12-GISEL-FAKE16: ; %bb.0: -; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] offset:-128 +; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] offset:-128 ; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX12-GISEL-FAKE16-NEXT: ; return to shader part epilog @@ -4090,14 +4090,14 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_reg_hi(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_i16_d16lo_reg_hi: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_b16 v1, v0, s[2:3] +; GFX11-NEXT: global_load_d16_b16 v1, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i16_d16lo_reg_hi: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_d16_b16 v1, v0, s[2:3] +; GFX12-NEXT: global_load_d16_b16 v1, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-NEXT: ; return to shader part epilog @@ -4119,14 +4119,14 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_reg_hi_immneg128(ptr ad ; ; GFX11-LABEL: global_load_saddr_i16_d16lo_reg_hi_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_b16 v1, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_d16_b16 v1, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i16_d16lo_reg_hi_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_d16_b16 v1, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_d16_b16 v1, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-NEXT: ; return to shader part epilog @@ -4149,14 +4149,14 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_zexti8_reg_hi(ptr addrs ; ; GFX11-LABEL: global_load_saddr_i16_d16lo_zexti8_reg_hi: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_u8 v1, v0, s[2:3] +; GFX11-NEXT: global_load_d16_u8 v1, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i16_d16lo_zexti8_reg_hi: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_d16_u8 v1, v0, s[2:3] +; GFX12-NEXT: global_load_d16_u8 v1, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-NEXT: ; return to shader part epilog @@ -4179,14 +4179,14 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128 ; ; GFX11-LABEL: global_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_u8 v1, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_d16_u8 v1, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i16_d16lo_zexti8_reg_hi_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_d16_u8 v1, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_d16_u8 v1, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-NEXT: ; return to shader part epilog @@ -4210,14 +4210,14 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_sexti8_reg_hi(ptr addrs ; ; GFX11-LABEL: global_load_saddr_i16_d16lo_sexti8_reg_hi: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_i8 v1, v0, s[2:3] +; GFX11-NEXT: global_load_d16_i8 v1, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i16_d16lo_sexti8_reg_hi: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_d16_i8 v1, v0, s[2:3] +; GFX12-NEXT: global_load_d16_i8 v1, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-NEXT: ; return to shader part epilog @@ -4240,14 +4240,14 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128 ; ; GFX11-LABEL: global_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_i8 v1, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_d16_i8 v1, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i16_d16lo_sexti8_reg_hi_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_d16_i8 v1, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_d16_i8 v1, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-NEXT: ; return to shader part epilog @@ -4274,25 +4274,25 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_undef_hi(ptr addrspace( ; ; GFX11-LABEL: global_load_saddr_i16_d16hi_undef_hi: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_hi_b16 v0, v0, s[2:3] +; GFX11-NEXT: global_load_d16_hi_b16 v0, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i16_d16hi_undef_hi: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: global_load_d16_hi_b16 v0, v0, s[2:3] +; GFX12-SDAG-NEXT: global_load_d16_hi_b16 v0, v0, s[0:1] ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16hi_undef_hi: ; GFX12-GISEL-TRUE16: ; %bb.0: -; GFX12-GISEL-TRUE16-NEXT: global_load_d16_hi_b16 v0, v0, s[2:3] +; GFX12-GISEL-TRUE16-NEXT: global_load_d16_hi_b16 v0, v0, s[0:1] ; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16hi_undef_hi: ; GFX12-GISEL-FAKE16: ; %bb.0: -; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX12-GISEL-FAKE16-NEXT: v_and_b32_e64 v1, 0xffff, s0 ; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -4315,25 +4315,25 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_undef_hi_immneg128(ptr ; ; GFX11-LABEL: global_load_saddr_i16_d16hi_undef_hi_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_hi_b16 v0, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_d16_hi_b16 v0, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: global_load_saddr_i16_d16hi_undef_hi_immneg128: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: global_load_d16_hi_b16 v0, v0, s[2:3] offset:-128 +; GFX12-SDAG-NEXT: global_load_d16_hi_b16 v0, v0, s[0:1] offset:-128 ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16hi_undef_hi_immneg128: ; GFX12-GISEL-TRUE16: ; %bb.0: -; GFX12-GISEL-TRUE16-NEXT: global_load_d16_hi_b16 v0, v0, s[2:3] offset:-128 +; GFX12-GISEL-TRUE16-NEXT: global_load_d16_hi_b16 v0, v0, s[0:1] offset:-128 ; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16hi_undef_hi_immneg128: ; GFX12-GISEL-FAKE16: ; %bb.0: -; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] offset:-128 +; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] offset:-128 ; GFX12-GISEL-FAKE16-NEXT: v_and_b32_e64 v1, 0xffff, s0 ; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1) @@ -4360,7 +4360,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi(ptr addrspace(1 ; GFX11-TRUE16-LABEL: global_load_saddr_i16_d16hi_zero_hi: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 -; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] +; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[0:1] ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -4368,7 +4368,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi(ptr addrspace(1 ; GFX11-FAKE16-LABEL: global_load_saddr_i16_d16hi_zero_hi: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-FAKE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] +; GFX11-FAKE16-NEXT: global_load_d16_hi_b16 v1, v0, s[0:1] ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -4376,7 +4376,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi(ptr addrspace(1 ; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_i16_d16hi_zero_hi: ; GFX12-SDAG-TRUE16: ; %bb.0: ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 -; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] +; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[0:1] ; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-SDAG-TRUE16-NEXT: ; return to shader part epilog @@ -4384,21 +4384,21 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi(ptr addrspace(1 ; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_i16_d16hi_zero_hi: ; GFX12-SDAG-FAKE16: ; %bb.0: ; GFX12-SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-SDAG-FAKE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] +; GFX12-SDAG-FAKE16-NEXT: global_load_d16_hi_b16 v1, v0, s[0:1] ; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-SDAG-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16hi_zero_hi: ; GFX12-GISEL-TRUE16: ; %bb.0: -; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] +; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] ; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16hi_zero_hi: ; GFX12-GISEL-FAKE16: ; %bb.0: -; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] +; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] ; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX12-GISEL-FAKE16-NEXT: ; return to shader part epilog @@ -4422,7 +4422,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi_immneg128(ptr a ; GFX11-TRUE16-LABEL: global_load_saddr_i16_d16hi_zero_hi_immneg128: ; GFX11-TRUE16: ; %bb.0: ; GFX11-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 -; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128 +; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[0:1] offset:-128 ; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-TRUE16-NEXT: ; return to shader part epilog @@ -4430,7 +4430,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi_immneg128(ptr a ; GFX11-FAKE16-LABEL: global_load_saddr_i16_d16hi_zero_hi_immneg128: ; GFX11-FAKE16: ; %bb.0: ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-FAKE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128 +; GFX11-FAKE16-NEXT: global_load_d16_hi_b16 v1, v0, s[0:1] offset:-128 ; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) ; GFX11-FAKE16-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-FAKE16-NEXT: ; return to shader part epilog @@ -4438,7 +4438,7 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi_immneg128(ptr a ; GFX12-SDAG-TRUE16-LABEL: global_load_saddr_i16_d16hi_zero_hi_immneg128: ; GFX12-SDAG-TRUE16: ; %bb.0: ; GFX12-SDAG-TRUE16-NEXT: v_mov_b16_e32 v1.l, 0 -; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128 +; GFX12-SDAG-TRUE16-NEXT: global_load_d16_hi_b16 v1, v0, s[0:1] offset:-128 ; GFX12-SDAG-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-TRUE16-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-SDAG-TRUE16-NEXT: ; return to shader part epilog @@ -4446,21 +4446,21 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zero_hi_immneg128(ptr a ; GFX12-SDAG-FAKE16-LABEL: global_load_saddr_i16_d16hi_zero_hi_immneg128: ; GFX12-SDAG-FAKE16: ; %bb.0: ; GFX12-SDAG-FAKE16-NEXT: v_mov_b32_e32 v1, 0 -; GFX12-SDAG-FAKE16-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128 +; GFX12-SDAG-FAKE16-NEXT: global_load_d16_hi_b16 v1, v0, s[0:1] offset:-128 ; GFX12-SDAG-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-SDAG-FAKE16-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-SDAG-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-TRUE16-LABEL: global_load_saddr_i16_d16hi_zero_hi_immneg128: ; GFX12-GISEL-TRUE16: ; %bb.0: -; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[2:3] offset:-128 +; GFX12-GISEL-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[0:1] offset:-128 ; GFX12-GISEL-TRUE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-TRUE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX12-GISEL-TRUE16-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-FAKE16-LABEL: global_load_saddr_i16_d16hi_zero_hi_immneg128: ; GFX12-GISEL-FAKE16: ; %bb.0: -; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[2:3] offset:-128 +; GFX12-GISEL-FAKE16-NEXT: global_load_u16 v0, v0, s[0:1] offset:-128 ; GFX12-GISEL-FAKE16-NEXT: s_wait_loadcnt 0x0 ; GFX12-GISEL-FAKE16-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GFX12-GISEL-FAKE16-NEXT: ; return to shader part epilog @@ -4483,14 +4483,14 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_reg_hi(ptr addrspace(1) ; ; GFX11-LABEL: global_load_saddr_i16_d16hi_reg_hi: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] +; GFX11-NEXT: global_load_d16_hi_b16 v1, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i16_d16hi_reg_hi: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] +; GFX12-NEXT: global_load_d16_hi_b16 v1, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-NEXT: ; return to shader part epilog @@ -4512,14 +4512,14 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_reg_hi_immneg128(ptr ad ; ; GFX11-LABEL: global_load_saddr_i16_d16hi_reg_hi_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_d16_hi_b16 v1, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i16_d16hi_reg_hi_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_d16_hi_b16 v1, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_d16_hi_b16 v1, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-NEXT: ; return to shader part epilog @@ -4542,14 +4542,14 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zexti8_reg_hi(ptr addrs ; ; GFX11-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3] +; GFX11-NEXT: global_load_d16_hi_u8 v1, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3] +; GFX12-NEXT: global_load_d16_hi_u8 v1, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-NEXT: ; return to shader part epilog @@ -4572,14 +4572,14 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128 ; ; GFX11-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_d16_hi_u8 v1, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i16_d16hi_zexti8_reg_hi_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_d16_hi_u8 v1, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_d16_hi_u8 v1, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-NEXT: ; return to shader part epilog @@ -4603,14 +4603,14 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_sexti8_reg_hi(ptr addrs ; ; GFX11-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3] +; GFX11-NEXT: global_load_d16_hi_i8 v1, v0, s[0:1] ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3] +; GFX12-NEXT: global_load_d16_hi_i8 v1, v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-NEXT: ; return to shader part epilog @@ -4633,14 +4633,14 @@ define amdgpu_ps <2 x half> @global_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128 ; ; GFX11-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3] offset:-128 +; GFX11-NEXT: global_load_d16_hi_i8 v1, v0, s[0:1] offset:-128 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: v_mov_b32_e32 v0, v1 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: global_load_saddr_i16_d16hi_sexti8_reg_hi_immneg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_load_d16_hi_i8 v1, v0, s[2:3] offset:-128 +; GFX12-NEXT: global_load_d16_hi_i8 v1, v0, s[0:1] offset:-128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: v_mov_b32_e32 v0, v1 ; GFX12-NEXT: ; return to shader part epilog @@ -4766,15 +4766,15 @@ define amdgpu_ps void @global_addr_64bit_lsr_iv(ptr addrspace(1) inreg %arg) { ; GFX11-LABEL: global_addr_64bit_lsr_iv: ; GFX11: ; %bb.0: ; %bb ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: s_movk_i32 s0, 0x100 +; GFX11-NEXT: s_movk_i32 s2, 0x100 ; GFX11-NEXT: .LBB132_1: ; %bb3 ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc +; GFX11-NEXT: global_load_b32 v1, v0, s[0:1] glc dlc ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_add_i32 s0, s0, -1 -; GFX11-NEXT: s_add_u32 s2, s2, 4 -; GFX11-NEXT: s_addc_u32 s3, s3, 0 -; GFX11-NEXT: s_cmp_eq_u32 s0, 0 +; GFX11-NEXT: s_add_i32 s2, s2, -1 +; GFX11-NEXT: s_add_u32 s0, s0, 4 +; GFX11-NEXT: s_addc_u32 s1, s1, 0 +; GFX11-NEXT: s_cmp_eq_u32 s2, 0 ; GFX11-NEXT: s_cbranch_scc0 .LBB132_1 ; GFX11-NEXT: ; %bb.2: ; %bb2 ; GFX11-NEXT: s_endpgm @@ -4782,14 +4782,14 @@ define amdgpu_ps void @global_addr_64bit_lsr_iv(ptr addrspace(1) inreg %arg) { ; GFX12-SDAG-LABEL: global_addr_64bit_lsr_iv: ; GFX12-SDAG: ; %bb.0: ; %bb ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-SDAG-NEXT: s_movk_i32 s0, 0x100 +; GFX12-SDAG-NEXT: s_movk_i32 s2, 0x100 ; GFX12-SDAG-NEXT: .LBB132_1: ; %bb3 ; GFX12-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX12-SDAG-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS +; GFX12-SDAG-NEXT: global_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 -; GFX12-SDAG-NEXT: s_add_co_i32 s0, s0, -1 -; GFX12-SDAG-NEXT: s_add_nc_u64 s[2:3], s[2:3], 4 -; GFX12-SDAG-NEXT: s_cmp_eq_u32 s0, 0 +; GFX12-SDAG-NEXT: s_add_co_i32 s2, s2, -1 +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], 4 +; GFX12-SDAG-NEXT: s_cmp_eq_u32 s2, 0 ; GFX12-SDAG-NEXT: s_cbranch_scc0 .LBB132_1 ; GFX12-SDAG-NEXT: ; %bb.2: ; %bb2 ; GFX12-SDAG-NEXT: s_endpgm @@ -4797,15 +4797,15 @@ define amdgpu_ps void @global_addr_64bit_lsr_iv(ptr addrspace(1) inreg %arg) { ; GFX12-GISEL-LABEL: global_addr_64bit_lsr_iv: ; GFX12-GISEL: ; %bb.0: ; %bb ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-GISEL-NEXT: s_movk_i32 s0, 0x100 +; GFX12-GISEL-NEXT: s_movk_i32 s2, 0x100 ; GFX12-GISEL-NEXT: .LBB132_1: ; %bb3 ; GFX12-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX12-GISEL-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS +; GFX12-GISEL-NEXT: global_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS ; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 -; GFX12-GISEL-NEXT: s_add_co_i32 s0, s0, -1 -; GFX12-GISEL-NEXT: s_add_co_u32 s2, s2, 4 -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s3, s3, 0 -; GFX12-GISEL-NEXT: s_cmp_eq_u32 s0, 0 +; GFX12-GISEL-NEXT: s_add_co_i32 s2, s2, -1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 4 +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0 +; GFX12-GISEL-NEXT: s_cmp_eq_u32 s2, 0 ; GFX12-GISEL-NEXT: s_cbranch_scc0 .LBB132_1 ; GFX12-GISEL-NEXT: ; %bb.2: ; %bb2 ; GFX12-GISEL-NEXT: s_endpgm @@ -4868,17 +4868,17 @@ define amdgpu_ps void @global_addr_64bit_lsr_iv_multiload(ptr addrspace(1) inreg ; GFX11-LABEL: global_addr_64bit_lsr_iv_multiload: ; GFX11: ; %bb.0: ; %bb ; GFX11-NEXT: v_mov_b32_e32 v0, 0 -; GFX11-NEXT: s_movk_i32 s0, 0x100 +; GFX11-NEXT: s_movk_i32 s2, 0x100 ; GFX11-NEXT: .LBB133_1: ; %bb3 ; GFX11-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc +; GFX11-NEXT: global_load_b32 v1, v0, s[0:1] glc dlc ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] glc dlc +; GFX11-NEXT: global_load_b32 v1, v0, s[0:1] glc dlc ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: s_add_i32 s0, s0, -1 -; GFX11-NEXT: s_add_u32 s2, s2, 4 -; GFX11-NEXT: s_addc_u32 s3, s3, 0 -; GFX11-NEXT: s_cmp_eq_u32 s0, 0 +; GFX11-NEXT: s_add_i32 s2, s2, -1 +; GFX11-NEXT: s_add_u32 s0, s0, 4 +; GFX11-NEXT: s_addc_u32 s1, s1, 0 +; GFX11-NEXT: s_cmp_eq_u32 s2, 0 ; GFX11-NEXT: s_cbranch_scc0 .LBB133_1 ; GFX11-NEXT: ; %bb.2: ; %bb2 ; GFX11-NEXT: s_endpgm @@ -4886,16 +4886,16 @@ define amdgpu_ps void @global_addr_64bit_lsr_iv_multiload(ptr addrspace(1) inreg ; GFX12-SDAG-LABEL: global_addr_64bit_lsr_iv_multiload: ; GFX12-SDAG: ; %bb.0: ; %bb ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-SDAG-NEXT: s_movk_i32 s0, 0x100 +; GFX12-SDAG-NEXT: s_movk_i32 s2, 0x100 ; GFX12-SDAG-NEXT: .LBB133_1: ; %bb3 ; GFX12-SDAG-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX12-SDAG-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS +; GFX12-SDAG-NEXT: global_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 -; GFX12-SDAG-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS +; GFX12-SDAG-NEXT: global_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS ; GFX12-SDAG-NEXT: s_wait_loadcnt 0x0 -; GFX12-SDAG-NEXT: s_add_co_i32 s0, s0, -1 -; GFX12-SDAG-NEXT: s_add_nc_u64 s[2:3], s[2:3], 4 -; GFX12-SDAG-NEXT: s_cmp_eq_u32 s0, 0 +; GFX12-SDAG-NEXT: s_add_co_i32 s2, s2, -1 +; GFX12-SDAG-NEXT: s_add_nc_u64 s[0:1], s[0:1], 4 +; GFX12-SDAG-NEXT: s_cmp_eq_u32 s2, 0 ; GFX12-SDAG-NEXT: s_cbranch_scc0 .LBB133_1 ; GFX12-SDAG-NEXT: ; %bb.2: ; %bb2 ; GFX12-SDAG-NEXT: s_endpgm @@ -4903,17 +4903,17 @@ define amdgpu_ps void @global_addr_64bit_lsr_iv_multiload(ptr addrspace(1) inreg ; GFX12-GISEL-LABEL: global_addr_64bit_lsr_iv_multiload: ; GFX12-GISEL: ; %bb.0: ; %bb ; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, 0 -; GFX12-GISEL-NEXT: s_movk_i32 s0, 0x100 +; GFX12-GISEL-NEXT: s_movk_i32 s2, 0x100 ; GFX12-GISEL-NEXT: .LBB133_1: ; %bb3 ; GFX12-GISEL-NEXT: ; =>This Inner Loop Header: Depth=1 -; GFX12-GISEL-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS +; GFX12-GISEL-NEXT: global_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS ; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 -; GFX12-GISEL-NEXT: global_load_b32 v1, v0, s[2:3] scope:SCOPE_SYS +; GFX12-GISEL-NEXT: global_load_b32 v1, v0, s[0:1] scope:SCOPE_SYS ; GFX12-GISEL-NEXT: s_wait_loadcnt 0x0 -; GFX12-GISEL-NEXT: s_add_co_i32 s0, s0, -1 -; GFX12-GISEL-NEXT: s_add_co_u32 s2, s2, 4 -; GFX12-GISEL-NEXT: s_add_co_ci_u32 s3, s3, 0 -; GFX12-GISEL-NEXT: s_cmp_eq_u32 s0, 0 +; GFX12-GISEL-NEXT: s_add_co_i32 s2, s2, -1 +; GFX12-GISEL-NEXT: s_add_co_u32 s0, s0, 4 +; GFX12-GISEL-NEXT: s_add_co_ci_u32 s1, s1, 0 +; GFX12-GISEL-NEXT: s_cmp_eq_u32 s2, 0 ; GFX12-GISEL-NEXT: s_cbranch_scc0 .LBB133_1 ; GFX12-GISEL-NEXT: ; %bb.2: ; %bb2 ; GFX12-GISEL-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/global-saddr-store.ll b/llvm/test/CodeGen/AMDGPU/global-saddr-store.ll index b2e6b3831136c8..29dc8e6ea32b51 100644 --- a/llvm/test/CodeGen/AMDGPU/global-saddr-store.ll +++ b/llvm/test/CodeGen/AMDGPU/global-saddr-store.ll @@ -18,14 +18,14 @@ define amdgpu_ps void @global_store_saddr_i8_zext_vgpr(ptr addrspace(1) inreg %s ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b32 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b8 v0, v2, s[2:3] +; GFX11-NEXT: global_store_b8 v0, v2, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i8_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_load_b32 v0, v[0:1], off ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b8 v0, v2, s[2:3] +; GFX12-NEXT: global_store_b8 v0, v2, s[0:1] ; GFX12-NEXT: s_endpgm %voffset = load i32, ptr addrspace(1) %voffset.ptr %zext.offset = zext i32 %voffset to i64 @@ -47,14 +47,14 @@ define amdgpu_ps void @global_store_saddr_i8_zext_vgpr_offset_2047(ptr addrspace ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b32 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b8 v0, v2, s[2:3] offset:2047 +; GFX11-NEXT: global_store_b8 v0, v2, s[0:1] offset:2047 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i8_zext_vgpr_offset_2047: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_load_b32 v0, v[0:1], off ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b8 v0, v2, s[2:3] offset:2047 +; GFX12-NEXT: global_store_b8 v0, v2, s[0:1] offset:2047 ; GFX12-NEXT: s_endpgm %voffset = load i32, ptr addrspace(1) %voffset.ptr %zext.offset = zext i32 %voffset to i64 @@ -77,14 +77,14 @@ define amdgpu_ps void @global_store_saddr_i8_zext_vgpr_offset_neg2048(ptr addrsp ; GFX11: ; %bb.0: ; GFX11-NEXT: global_load_b32 v0, v[0:1], off ; GFX11-NEXT: s_waitcnt vmcnt(0) -; GFX11-NEXT: global_store_b8 v0, v2, s[2:3] offset:-2048 +; GFX11-NEXT: global_store_b8 v0, v2, s[0:1] offset:-2048 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i8_zext_vgpr_offset_neg2048: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_load_b32 v0, v[0:1], off ; GFX12-NEXT: s_wait_loadcnt 0x0 -; GFX12-NEXT: global_store_b8 v0, v2, s[2:3] offset:-2048 +; GFX12-NEXT: global_store_b8 v0, v2, s[0:1] offset:-2048 ; GFX12-NEXT: s_endpgm %voffset = load i32, ptr addrspace(1) %voffset.ptr %zext.offset = zext i32 %voffset to i64 @@ -211,12 +211,12 @@ define amdgpu_ps void @global_store_saddr_i16_zext_vgpr(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_store_saddr_i16_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b16 v0, v1, s[2:3] +; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i16_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b16 v0, v1, s[2:3] +; GFX12-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -232,12 +232,12 @@ define amdgpu_ps void @global_store_saddr_i16_zext_vgpr_offset_neg128(ptr addrsp ; ; GFX11-LABEL: global_store_saddr_i16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b16 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b16 v0, v1, s[2:3] offset:-128 +; GFX12-NEXT: global_store_b16 v0, v1, s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -254,12 +254,12 @@ define amdgpu_ps void @global_store_saddr_f16_zext_vgpr(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_store_saddr_f16_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b16 v0, v1, s[2:3] +; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_f16_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b16 v0, v1, s[2:3] +; GFX12-NEXT: global_store_b16 v0, v1, s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -275,12 +275,12 @@ define amdgpu_ps void @global_store_saddr_f16_zext_vgpr_offset_neg128(ptr addrsp ; ; GFX11-LABEL: global_store_saddr_f16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b16 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_f16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b16 v0, v1, s[2:3] offset:-128 +; GFX12-NEXT: global_store_b16 v0, v1, s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -297,12 +297,12 @@ define amdgpu_ps void @global_store_saddr_i32_zext_vgpr(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_store_saddr_i32_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i32_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -318,12 +318,12 @@ define amdgpu_ps void @global_store_saddr_i32_zext_vgpr_offset_neg128(ptr addrsp ; ; GFX11-LABEL: global_store_saddr_i32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -340,12 +340,12 @@ define amdgpu_ps void @global_store_saddr_f32_zext_vgpr(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_store_saddr_f32_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_f32_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -361,12 +361,12 @@ define amdgpu_ps void @global_store_saddr_f32_zext_vgpr_offset_neg128(ptr addrsp ; ; GFX11-LABEL: global_store_saddr_f32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_f32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -383,12 +383,12 @@ define amdgpu_ps void @global_store_saddr_p3_zext_vgpr(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_store_saddr_p3_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_p3_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -404,12 +404,12 @@ define amdgpu_ps void @global_store_saddr_p3_zext_vgpr_offset_neg128(ptr addrspa ; ; GFX11-LABEL: global_store_saddr_p3_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_p3_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -426,12 +426,12 @@ define amdgpu_ps void @global_store_saddr_i64_zext_vgpr(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_store_saddr_i64_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i64_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -447,12 +447,12 @@ define amdgpu_ps void @global_store_saddr_i64_zext_vgpr_offset_neg128(ptr addrsp ; ; GFX11-LABEL: global_store_saddr_i64_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i64_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -469,12 +469,12 @@ define amdgpu_ps void @global_store_saddr_f64_zext_vgpr(ptr addrspace(1) inreg % ; ; GFX11-LABEL: global_store_saddr_f64_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_f64_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -490,12 +490,12 @@ define amdgpu_ps void @global_store_saddr_f64_zext_vgpr_offset_neg128(ptr addrsp ; ; GFX11-LABEL: global_store_saddr_f64_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_f64_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -512,12 +512,12 @@ define amdgpu_ps void @global_store_saddr_v2i32_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v2i32_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2i32_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -533,12 +533,12 @@ define amdgpu_ps void @global_store_saddr_v2i32_zext_vgpr_offset_neg128(ptr addr ; ; GFX11-LABEL: global_store_saddr_v2i32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2i32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -555,12 +555,12 @@ define amdgpu_ps void @global_store_saddr_v2f32_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v2f32_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2f32_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -576,12 +576,12 @@ define amdgpu_ps void @global_store_saddr_v2f32_zext_vgpr_offset_neg128(ptr addr ; ; GFX11-LABEL: global_store_saddr_v2f32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2f32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -598,12 +598,12 @@ define amdgpu_ps void @global_store_saddr_v4i16_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v4i16_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4i16_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -619,12 +619,12 @@ define amdgpu_ps void @global_store_saddr_v4i16_zext_vgpr_offset_neg128(ptr addr ; ; GFX11-LABEL: global_store_saddr_v4i16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4i16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -641,12 +641,12 @@ define amdgpu_ps void @global_store_saddr_v4f16_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v4f16_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4f16_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -662,12 +662,12 @@ define amdgpu_ps void @global_store_saddr_v4f16_zext_vgpr_offset_neg128(ptr addr ; ; GFX11-LABEL: global_store_saddr_v4f16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4f16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -684,12 +684,12 @@ define amdgpu_ps void @global_store_saddr_p1_zext_vgpr(ptr addrspace(1) inreg %s ; ; GFX11-LABEL: global_store_saddr_p1_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_p1_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -705,12 +705,12 @@ define amdgpu_ps void @global_store_saddr_p1_zext_vgpr_offset_neg128(ptr addrspa ; ; GFX11-LABEL: global_store_saddr_p1_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_p1_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -727,12 +727,12 @@ define amdgpu_ps void @global_store_saddr_v3i32_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v3i32_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] +; GFX11-NEXT: global_store_b96 v0, v[1:3], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v3i32_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] +; GFX12-NEXT: global_store_b96 v0, v[1:3], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -748,12 +748,12 @@ define amdgpu_ps void @global_store_saddr_v3i32_zext_vgpr_offset_neg128(ptr addr ; ; GFX11-LABEL: global_store_saddr_v3i32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b96 v0, v[1:3], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v3i32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b96 v0, v[1:3], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -770,12 +770,12 @@ define amdgpu_ps void @global_store_saddr_v3f32_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v3f32_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] +; GFX11-NEXT: global_store_b96 v0, v[1:3], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v3f32_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] +; GFX12-NEXT: global_store_b96 v0, v[1:3], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -791,12 +791,12 @@ define amdgpu_ps void @global_store_saddr_v3f32_zext_vgpr_offset_neg128(ptr addr ; ; GFX11-LABEL: global_store_saddr_v3f32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b96 v0, v[1:3], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v3f32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b96 v0, v[1:3], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -813,12 +813,12 @@ define amdgpu_ps void @global_store_saddr_v6i16_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v6i16_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] +; GFX11-NEXT: global_store_b96 v0, v[1:3], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v6i16_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] +; GFX12-NEXT: global_store_b96 v0, v[1:3], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -834,12 +834,12 @@ define amdgpu_ps void @global_store_saddr_v6i16_zext_vgpr_offset_neg128(ptr addr ; ; GFX11-LABEL: global_store_saddr_v6i16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b96 v0, v[1:3], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v6i16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b96 v0, v[1:3], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -856,12 +856,12 @@ define amdgpu_ps void @global_store_saddr_v6f16_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v6f16_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] +; GFX11-NEXT: global_store_b96 v0, v[1:3], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v6f16_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] +; GFX12-NEXT: global_store_b96 v0, v[1:3], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -877,12 +877,12 @@ define amdgpu_ps void @global_store_saddr_v6f16_zext_vgpr_offset_neg128(ptr addr ; ; GFX11-LABEL: global_store_saddr_v6f16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b96 v0, v[1:3], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v6f16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b96 v0, v[1:3], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b96 v0, v[1:3], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -899,12 +899,12 @@ define amdgpu_ps void @global_store_saddr_v4i32_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v4i32_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4i32_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -920,12 +920,12 @@ define amdgpu_ps void @global_store_saddr_v4i32_zext_vgpr_offset_neg128(ptr addr ; ; GFX11-LABEL: global_store_saddr_v4i32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4i32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -942,12 +942,12 @@ define amdgpu_ps void @global_store_saddr_v4f32_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v4f32_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4f32_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -963,12 +963,12 @@ define amdgpu_ps void @global_store_saddr_v4f32_zext_vgpr_offset_neg128(ptr addr ; ; GFX11-LABEL: global_store_saddr_v4f32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4f32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -985,12 +985,12 @@ define amdgpu_ps void @global_store_saddr_v2i64_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v2i64_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2i64_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1006,12 +1006,12 @@ define amdgpu_ps void @global_store_saddr_v2i64_zext_vgpr_offset_neg128(ptr addr ; ; GFX11-LABEL: global_store_saddr_v2i64_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2i64_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1028,12 +1028,12 @@ define amdgpu_ps void @global_store_saddr_v2f64_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v2f64_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2f64_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1049,12 +1049,12 @@ define amdgpu_ps void @global_store_saddr_v2f64_zext_vgpr_offset_neg128(ptr addr ; ; GFX11-LABEL: global_store_saddr_v2f64_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2f64_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1071,12 +1071,12 @@ define amdgpu_ps void @global_store_saddr_v8i16_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v8i16_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v8i16_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1092,12 +1092,12 @@ define amdgpu_ps void @global_store_saddr_v8i16_zext_vgpr_offset_neg128(ptr addr ; ; GFX11-LABEL: global_store_saddr_v8i16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v8i16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1114,12 +1114,12 @@ define amdgpu_ps void @global_store_saddr_v8f16_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v8f16_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v8f16_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1135,12 +1135,12 @@ define amdgpu_ps void @global_store_saddr_v8f16_zext_vgpr_offset_neg128(ptr addr ; ; GFX11-LABEL: global_store_saddr_v8f16_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v8f16_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1157,12 +1157,12 @@ define amdgpu_ps void @global_store_saddr_v2p1_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v2p1_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2p1_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1178,12 +1178,12 @@ define amdgpu_ps void @global_store_saddr_v2p1_zext_vgpr_offset_neg128(ptr addrs ; ; GFX11-LABEL: global_store_saddr_v2p1_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v2p1_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1200,12 +1200,12 @@ define amdgpu_ps void @global_store_saddr_v4p3_zext_vgpr(ptr addrspace(1) inreg ; ; GFX11-LABEL: global_store_saddr_v4p3_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4p3_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1221,12 +1221,12 @@ define amdgpu_ps void @global_store_saddr_v4p3_zext_vgpr_offset_neg128(ptr addrs ; ; GFX11-LABEL: global_store_saddr_v4p3_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_v4p3_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_b128 v0, v[1:4], s[2:3] offset:-128 +; GFX12-NEXT: global_store_b128 v0, v[1:4], s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1247,14 +1247,14 @@ define amdgpu_ps void @atomic_global_store_saddr_i32_zext_vgpr(ptr addrspace(1) ; ; GFX11-LABEL: atomic_global_store_saddr_i32_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: atomic_global_store_saddr_i32_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 -; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] scope:SCOPE_SYS ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1270,14 +1270,14 @@ define amdgpu_ps void @atomic_global_store_saddr_i32_zext_vgpr_offset_neg128(ptr ; ; GFX11-LABEL: atomic_global_store_saddr_i32_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: atomic_global_store_saddr_i32_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 -; GFX12-NEXT: global_store_b32 v0, v1, s[2:3] offset:-128 scope:SCOPE_SYS +; GFX12-NEXT: global_store_b32 v0, v1, s[0:1] offset:-128 scope:SCOPE_SYS ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1294,14 +1294,14 @@ define amdgpu_ps void @atomic_global_store_saddr_i64_zext_vgpr(ptr addrspace(1) ; ; GFX11-LABEL: atomic_global_store_saddr_i64_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: atomic_global_store_saddr_i64_zext_vgpr: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] scope:SCOPE_SYS +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] scope:SCOPE_SYS ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1317,14 +1317,14 @@ define amdgpu_ps void @atomic_global_store_saddr_i64_zext_vgpr_offset_neg128(ptr ; ; GFX11-LABEL: atomic_global_store_saddr_i64_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 +; GFX11-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: atomic_global_store_saddr_i64_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: ; GFX12-NEXT: global_wb scope:SCOPE_SYS ; GFX12-NEXT: s_wait_storecnt 0x0 -; GFX12-NEXT: global_store_b64 v0, v[1:2], s[2:3] offset:-128 scope:SCOPE_SYS +; GFX12-NEXT: global_store_b64 v0, v[1:2], s[0:1] offset:-128 scope:SCOPE_SYS ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1345,12 +1345,12 @@ define amdgpu_ps void @global_store_saddr_i16_d16hi_zext_vgpr(ptr addrspace(1) i ; ; GFX11-LABEL: global_store_saddr_i16_d16hi_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_d16_hi_b16 v0, v1, s[2:3] +; GFX11-NEXT: global_store_d16_hi_b16 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i16_d16hi_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_d16_hi_b16 v0, v1, s[2:3] +; GFX12-NEXT: global_store_d16_hi_b16 v0, v1, s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1367,12 +1367,12 @@ define amdgpu_ps void @global_store_saddr_i16_d16hi_zext_vgpr_offset_neg128(ptr ; ; GFX11-LABEL: global_store_saddr_i16_d16hi_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_d16_hi_b16 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_store_d16_hi_b16 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i16_d16hi_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_d16_hi_b16 v0, v1, s[2:3] offset:-128 +; GFX12-NEXT: global_store_d16_hi_b16 v0, v1, s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1390,12 +1390,12 @@ define amdgpu_ps void @global_store_saddr_i16_d16hi_trunci8_zext_vgpr(ptr addrsp ; ; GFX11-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3] +; GFX11-NEXT: global_store_d16_hi_b8 v0, v1, s[0:1] ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3] +; GFX12-NEXT: global_store_d16_hi_b8 v0, v1, s[0:1] ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset @@ -1413,12 +1413,12 @@ define amdgpu_ps void @global_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg ; ; GFX11-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128: ; GFX11: ; %bb.0: -; GFX11-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3] offset:-128 +; GFX11-NEXT: global_store_d16_hi_b8 v0, v1, s[0:1] offset:-128 ; GFX11-NEXT: s_endpgm ; ; GFX12-LABEL: global_store_saddr_i16_d16hi_trunci8_zext_vgpr_offset_neg128: ; GFX12: ; %bb.0: -; GFX12-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3] offset:-128 +; GFX12-NEXT: global_store_d16_hi_b8 v0, v1, s[0:1] offset:-128 ; GFX12-NEXT: s_endpgm %zext.offset = zext i32 %voffset to i64 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset diff --git a/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll b/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll index 3b2d08eb26695e..00d33c54f95774 100644 --- a/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll +++ b/llvm/test/CodeGen/AMDGPU/image-load-d16-tfe.ll @@ -48,16 +48,9 @@ define amdgpu_ps void @load_1d_f16_tfe_dmask0(<8 x i32> inreg %rsrc, i32 %s) { ; GFX11-LABEL: load_1d_f16_tfe_dmask0: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s11, s9 -; GFX11-NEXT: s_mov_b32 s10, s8 -; GFX11-NEXT: s_mov_b32 s9, s7 -; GFX11-NEXT: s_mov_b32 s8, s6 -; GFX11-NEXT: s_mov_b32 s7, s5 -; GFX11-NEXT: s_mov_b32 s6, s4 -; GFX11-NEXT: s_mov_b32 s5, s3 -; GFX11-NEXT: s_mov_b32 s4, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 -; GFX11-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 +; GFX11-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: global_store_b16 v[0:1], v1, off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 @@ -136,16 +129,9 @@ define amdgpu_ps void @load_1d_f16_tfe_dmask1(<8 x i32> inreg %rsrc, i32 %s) { ; GFX11-LABEL: load_1d_f16_tfe_dmask1: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s11, s9 -; GFX11-NEXT: s_mov_b32 s10, s8 -; GFX11-NEXT: s_mov_b32 s9, s7 -; GFX11-NEXT: s_mov_b32 s8, s6 -; GFX11-NEXT: s_mov_b32 s7, s5 -; GFX11-NEXT: s_mov_b32 s6, s4 -; GFX11-NEXT: s_mov_b32 s5, s3 -; GFX11-NEXT: s_mov_b32 s4, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 -; GFX11-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 +; GFX11-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: global_store_b16 v[0:1], v1, off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 @@ -224,16 +210,9 @@ define amdgpu_ps void @load_1d_v2f16_tfe_dmask0(<8 x i32> inreg %rsrc, i32 %s) { ; GFX11-LABEL: load_1d_v2f16_tfe_dmask0: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s11, s9 -; GFX11-NEXT: s_mov_b32 s10, s8 -; GFX11-NEXT: s_mov_b32 s9, s7 -; GFX11-NEXT: s_mov_b32 s8, s6 -; GFX11-NEXT: s_mov_b32 s7, s5 -; GFX11-NEXT: s_mov_b32 s6, s4 -; GFX11-NEXT: s_mov_b32 s5, s3 -; GFX11-NEXT: s_mov_b32 s4, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 -; GFX11-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 +; GFX11-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: global_store_b32 v[0:1], v1, off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 @@ -312,16 +291,9 @@ define amdgpu_ps void @load_1d_v2f16_tfe_dmask1(<8 x i32> inreg %rsrc, i32 %s) { ; GFX11-LABEL: load_1d_v2f16_tfe_dmask1: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s11, s9 -; GFX11-NEXT: s_mov_b32 s10, s8 -; GFX11-NEXT: s_mov_b32 s9, s7 -; GFX11-NEXT: s_mov_b32 s8, s6 -; GFX11-NEXT: s_mov_b32 s7, s5 -; GFX11-NEXT: s_mov_b32 s6, s4 -; GFX11-NEXT: s_mov_b32 s5, s3 -; GFX11-NEXT: s_mov_b32 s4, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 -; GFX11-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 +; GFX11-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x1 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: global_store_b32 v[0:1], v1, off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 @@ -400,16 +372,9 @@ define amdgpu_ps void @load_1d_v2f16_tfe_dmask3(<8 x i32> inreg %rsrc, i32 %s) { ; GFX11-LABEL: load_1d_v2f16_tfe_dmask3: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s11, s9 -; GFX11-NEXT: s_mov_b32 s10, s8 -; GFX11-NEXT: s_mov_b32 s9, s7 -; GFX11-NEXT: s_mov_b32 s8, s6 -; GFX11-NEXT: s_mov_b32 s7, s5 -; GFX11-NEXT: s_mov_b32 s6, s4 -; GFX11-NEXT: s_mov_b32 s5, s3 -; GFX11-NEXT: s_mov_b32 s4, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 -; GFX11-NEXT: image_load v[1:2], v0, s[4:11] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm tfe d16 +; GFX11-NEXT: image_load v[1:2], v0, s[0:7] dmask:0x3 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: global_store_b32 v[0:1], v1, off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 @@ -497,17 +462,10 @@ define amdgpu_ps void @load_1d_v3f16_tfe_dmask7(<8 x i32> inreg %rsrc, i32 %s) { ; GFX11-LABEL: load_1d_v3f16_tfe_dmask7: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s11, s9 -; GFX11-NEXT: s_mov_b32 s10, s8 -; GFX11-NEXT: s_mov_b32 s9, s7 -; GFX11-NEXT: s_mov_b32 s8, s6 -; GFX11-NEXT: s_mov_b32 s7, s5 -; GFX11-NEXT: s_mov_b32 s6, s4 -; GFX11-NEXT: s_mov_b32 s5, s3 -; GFX11-NEXT: s_mov_b32 s4, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 ; GFX11-NEXT: v_mov_b32_e32 v3, v1 -; GFX11-NEXT: image_load v[1:3], v0, s[4:11] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm tfe d16 +; GFX11-NEXT: image_load v[1:3], v0, s[0:7] dmask:0x7 dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: global_store_b16 v[0:1], v2, off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 @@ -596,17 +554,10 @@ define amdgpu_ps void @load_1d_v4f16_tfe_dmask15(<8 x i32> inreg %rsrc, i32 %s) ; GFX11-LABEL: load_1d_v4f16_tfe_dmask15: ; GFX11: ; %bb.0: ; GFX11-NEXT: v_mov_b32_e32 v1, 0 -; GFX11-NEXT: s_mov_b32 s11, s9 -; GFX11-NEXT: s_mov_b32 s10, s8 -; GFX11-NEXT: s_mov_b32 s9, s7 -; GFX11-NEXT: s_mov_b32 s8, s6 -; GFX11-NEXT: s_mov_b32 s7, s5 -; GFX11-NEXT: s_mov_b32 s6, s4 -; GFX11-NEXT: s_mov_b32 s5, s3 -; GFX11-NEXT: s_mov_b32 s4, s2 +; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX11-NEXT: v_mov_b32_e32 v2, v1 ; GFX11-NEXT: v_mov_b32_e32 v3, v1 -; GFX11-NEXT: image_load v[1:3], v0, s[4:11] dmask:0xf dim:SQ_RSRC_IMG_1D unorm tfe d16 +; GFX11-NEXT: image_load v[1:3], v0, s[0:7] dmask:0xf dim:SQ_RSRC_IMG_1D unorm tfe d16 ; GFX11-NEXT: s_waitcnt vmcnt(0) ; GFX11-NEXT: global_store_b64 v[0:1], v[1:2], off dlc ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll index 5d76eb61b04a55..8b874d1cc41359 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.fma.legacy.ll @@ -236,16 +236,16 @@ define amdgpu_ps float @v_fma_sss(float inreg %a, float inreg %b, float inreg %c ; ; GFX11-LABEL: v_fma_sss: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_mov_b32_e32 v0, s4 +; GFX11-NEXT: v_mov_b32_e32 v0, s2 ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX11-NEXT: v_fma_dx9_zero_f32 v0, s3, s2, v0 +; GFX11-NEXT: v_fma_dx9_zero_f32 v0, s1, s0, v0 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: v_fma_sss: ; GFX12: ; %bb.0: -; GFX12-NEXT: v_mov_b32_e32 v0, s4 +; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_fma_dx9_zero_f32 v0, s2, s3, v0 +; GFX12-NEXT: v_fma_dx9_zero_f32 v0, s0, s1, v0 ; GFX12-NEXT: ; return to shader part epilog %fma = call float @llvm.amdgcn.fma.legacy(float %a, float %b, float %c) ret float %fma diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll deleted file mode 100644 index 3ef45aefd8910d..00000000000000 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.hsa.ll +++ /dev/null @@ -1,22 +0,0 @@ -; RUN: not llc -mtriple=amdgpu7.00-amd-amdhsa < %s 2>&1 | FileCheck -check-prefix=ERROR %s - -; ERROR: in function test_kernel{{.*}}: non-hsa intrinsic with hsa target -define amdgpu_kernel void @test_kernel(ptr addrspace(1) %out) #1 { - %implicit_buffer_ptr = call ptr addrspace(4) @llvm.amdgcn.implicit.buffer.ptr() - %value = load i32, ptr addrspace(4) %implicit_buffer_ptr - store i32 %value, ptr addrspace(1) %out - ret void -} - -; ERROR: in function test_func{{.*}}: non-hsa intrinsic with hsa target -define void @test_func(ptr addrspace(1) %out) #1 { - %implicit_buffer_ptr = call ptr addrspace(4) @llvm.amdgcn.implicit.buffer.ptr() - %value = load i32, ptr addrspace(4) %implicit_buffer_ptr - store i32 %value, ptr addrspace(1) %out - ret void -} - -declare ptr addrspace(4) @llvm.amdgcn.implicit.buffer.ptr() #0 - -attributes #0 = { nounwind readnone speculatable } -attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.unsupported.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.unsupported.ll new file mode 100644 index 00000000000000..f6bd59dc9b4f87 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.implicit.ptr.buffer.unsupported.ll @@ -0,0 +1,61 @@ +; Mesa shaders on targets with architected flat scratch don't have an implicit +; buffer pointer. +; RUN: not llc -global-isel=0 -mtriple=amdgpu11.00-mesa-mesa3d -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error --check-prefix=SUBTARGET %s +; RUN: not llc -global-isel -mtriple=amdgpu11.00-mesa-mesa3d -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error --check-prefix=SUBTARGET %s + +; Only Mesa shaders have an implicit buffer pointer. +; RUN: not llc -global-isel=0 -mtriple=amdgpu10.30-mesa-mesa3d -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error --check-prefix=CC %s +; RUN: not llc -global-isel -mtriple=amdgpu10.30-mesa-mesa3d -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error --check-prefix=CC %s +; RUN: not llc -global-isel=0 -mtriple=amdgpu10.30-- -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error --check-prefix=OS %s +; RUN: not llc -global-isel -mtriple=amdgpu10.30-- -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error --check-prefix=OS %s +; RUN: not llc -global-isel=0 -mtriple=amdgpu10.30-amd-amdpal -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error --check-prefix=OS %s +; RUN: not llc -global-isel -mtriple=amdgpu10.30-amd-amdpal -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error --check-prefix=OS %s +; RUN: not llc -global-isel=0 -mtriple=amdgpu7.00-amd-amdhsa -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error --check-prefixes=OS,HSA-SDAG %s +; RUN: not llc -global-isel -mtriple=amdgpu7.00-amd-amdhsa -filetype=null < %s 2>&1 | FileCheck --implicit-check-not=error --check-prefix=OS %s + +; HSA-SDAG: error: {{.*}}in function test_ps{{.*}}: unsupported non-compute shaders with HSA +; SUBTARGET: error: {{.*}}in function test_ps{{.*}}: intrinsic not supported on subtarget +; OS: error: {{.*}}in function test_ps{{.*}}: intrinsic not supported for OS +define amdgpu_ps i32 @test_ps() { + %implicit_buffer_ptr = call ptr addrspace(4) @llvm.amdgcn.implicit.buffer.ptr() + %value = load volatile i32, ptr addrspace(4) %implicit_buffer_ptr + ret i32 %value +} + +; HSA-SDAG: error: {{.*}}in function test_cs{{.*}}: unsupported non-compute shaders with HSA +; SUBTARGET: error: {{.*}}in function test_cs{{.*}}: intrinsic not supported on subtarget +; OS: error: {{.*}}in function test_cs{{.*}}: intrinsic not supported for OS +define amdgpu_cs i32 @test_cs() { + %implicit_buffer_ptr = call ptr addrspace(4) @llvm.amdgcn.implicit.buffer.ptr() + %value = load volatile i32, ptr addrspace(4) %implicit_buffer_ptr + ret i32 %value +} + +; SUBTARGET: error: {{.*}}in function test_kernel{{.*}}: intrinsic not supported on subtarget +; OS: error: {{.*}}in function test_kernel{{.*}}: intrinsic not supported for OS +; CC: error: {{.*}}in function test_kernel{{.*}}: intrinsic not supported for calling convention +define amdgpu_kernel void @test_kernel(ptr addrspace(1) %out) { + %implicit_buffer_ptr = call ptr addrspace(4) @llvm.amdgcn.implicit.buffer.ptr() + %value = load volatile i32, ptr addrspace(4) %implicit_buffer_ptr + store i32 %value, ptr addrspace(1) %out + ret void +} + +; HSA-SDAG: error: {{.*}}in function test_gfx_func{{.*}}: unsupported non-compute shaders with HSA +; SUBTARGET: error: {{.*}}in function test_gfx_func{{.*}}: intrinsic not supported on subtarget +; OS: error: {{.*}}in function test_gfx_func{{.*}}: intrinsic not supported for OS +; CC: error: {{.*}}in function test_gfx_func{{.*}}: intrinsic not supported for calling convention +define amdgpu_gfx i32 @test_gfx_func() { + %implicit_buffer_ptr = call ptr addrspace(4) @llvm.amdgcn.implicit.buffer.ptr() + %value = load volatile i32, ptr addrspace(4) %implicit_buffer_ptr + ret i32 %value +} + +; SUBTARGET: error: {{.*}}in function test_func{{.*}}: intrinsic not supported on subtarget +; OS: error: {{.*}}in function test_func{{.*}}: intrinsic not supported for OS +; CC: error: {{.*}}in function test_func{{.*}}: intrinsic not supported for calling convention +define i32 @test_func() { + %implicit_buffer_ptr = call ptr addrspace(4) @llvm.amdgcn.implicit.buffer.ptr() + %value = load volatile i32, ptr addrspace(4) %implicit_buffer_ptr + ret i32 %value +} diff --git a/llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll b/llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll index c9c1894fe9e1d4..186facccf2b12c 100644 --- a/llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll +++ b/llvm/test/CodeGen/AMDGPU/load-saddr-offset-imm.ll @@ -12,7 +12,7 @@ define amdgpu_ps <2 x float> @global_load_scale_add_foldable_knownbits(ptr addrs ; GFX12-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:128 +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog ; @@ -23,7 +23,7 @@ define amdgpu_ps <2 x float> @global_load_scale_add_foldable_knownbits(ptr addrs ; GFX1250-NEXT: v_nop ; GFX1250-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE ; GFX1250-NEXT: v_mbcnt_lo_u32_b32 v0, -1, 0 -; GFX1250-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:128 scale_offset +; GFX1250-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:128 scale_offset ; GFX1250-NEXT: s_wait_loadcnt 0x0 ; GFX1250-NEXT: ; return to shader part epilog %v = tail call i32 @llvm.amdgcn.mbcnt.lo(i32 -1, i32 0) @@ -40,7 +40,7 @@ define amdgpu_ps <2 x float> @global_load_scale_add_foldable_nowrap(ptr addrspac ; GFX12-LABEL: global_load_scale_add_foldable_nowrap: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_lshlrev_b32_e32 v0, 3, v0 -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:128 +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:128 ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog ; @@ -50,7 +50,7 @@ define amdgpu_ps <2 x float> @global_load_scale_add_foldable_nowrap(ptr addrspac ; GFX1250-SDAG-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-SDAG-NEXT: v_nop ; GFX1250-SDAG-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-SDAG-NEXT: global_load_b64 v[0:1], v0, s[2:3] offset:128 scale_offset +; GFX1250-SDAG-NEXT: global_load_b64 v[0:1], v0, s[0:1] offset:128 scale_offset ; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog ; @@ -60,7 +60,7 @@ define amdgpu_ps <2 x float> @global_load_scale_add_foldable_nowrap(ptr addrspac ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 @@ -81,7 +81,7 @@ define amdgpu_ps <2 x float> @global_load_scale_add_unfoldable(ptr addrspace(1) ; GFX12-LABEL: global_load_scale_add_unfoldable: ; GFX12: ; %bb.0: ; GFX12-NEXT: v_lshl_add_u32 v0, v0, 3, 0x80 -; GFX12-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX12-NEXT: global_load_b64 v[0:1], v0, s[0:1] ; GFX12-NEXT: s_wait_loadcnt 0x0 ; GFX12-NEXT: ; return to shader part epilog ; @@ -94,7 +94,7 @@ define amdgpu_ps <2 x float> @global_load_scale_add_unfoldable(ptr addrspace(1) ; GFX1250-SDAG-NEXT: v_mov_b32_e32 v1, 0 ; GFX1250-SDAG-NEXT: v_lshl_add_u32 v0, v0, 3, 0x80 ; GFX1250-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[2:3], v[0:1] +; GFX1250-SDAG-NEXT: v_add_nc_u64_e32 v[0:1], s[0:1], v[0:1] ; GFX1250-SDAG-NEXT: global_load_b64 v[0:1], v[0:1], off ; GFX1250-SDAG-NEXT: s_wait_loadcnt 0x0 ; GFX1250-SDAG-NEXT: ; return to shader part epilog @@ -105,7 +105,7 @@ define amdgpu_ps <2 x float> @global_load_scale_add_unfoldable(ptr addrspace(1) ; GFX1250-GISEL-NEXT: s_mov_b64 s[64:65], 0 ; GFX1250-GISEL-NEXT: v_nop ; GFX1250-GISEL-NEXT: global_prefetch_b8 v0, s[64:65] scope:SCOPE_SE -; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[2:3] +; GFX1250-GISEL-NEXT: v_mov_b64_e32 v[2:3], s[0:1] ; GFX1250-GISEL-NEXT: v_lshl_add_u32 v0, v0, 3, 0x80 ; GFX1250-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1) ; GFX1250-GISEL-NEXT: v_add_co_u32 v0, vcc_lo, v2, v0 diff --git a/llvm/test/CodeGen/AMDGPU/mesa-architected-flat-scratch-user-sgprs.ll b/llvm/test/CodeGen/AMDGPU/mesa-architected-flat-scratch-user-sgprs.ll new file mode 100644 index 00000000000000..8b49e8c56900d5 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/mesa-architected-flat-scratch-user-sgprs.ll @@ -0,0 +1,132 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=amdgpu10.30-mesa-mesa3d < %s | FileCheck -check-prefix=GFX10 %s +; RUN: llc -mtriple=amdgpu11.00-mesa-mesa3d < %s | FileCheck -check-prefix=GFX11 %s + +; Without architected flat scratch, s[0:1] is reserved for the implicit buffer +; pointer of Mesa shaders, which is used to set up scratch. With architected +; flat scratch, it isn't needed and the user SGPRs start at s0. + +define amdgpu_cs void @cs_user_sgprs(i32 inreg %a, ptr addrspace(1) inreg %out) { +; GFX10-LABEL: cs_user_sgprs: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: v_mov_b32_e32 v1, s2 +; GFX10-NEXT: s_mov_b32 s1, s4 +; GFX10-NEXT: s_mov_b32 s0, s3 +; GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: cs_user_sgprs: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: s_mov_b32 s3, s2 +; GFX11-NEXT: s_mov_b32 s2, s1 +; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] +; GFX11-NEXT: s_endpgm + store i32 %a, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ps_user_sgprs(i32 inreg %a, ptr addrspace(1) inreg %out) { +; GFX10-LABEL: ps_user_sgprs: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-NEXT: v_mov_b32_e32 v1, s2 +; GFX10-NEXT: s_mov_b32 s1, s4 +; GFX10-NEXT: s_mov_b32 s0, s3 +; GFX10-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: ps_user_sgprs: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0 +; GFX11-NEXT: s_mov_b32 s3, s2 +; GFX11-NEXT: s_mov_b32 s2, s1 +; GFX11-NEXT: global_store_b32 v0, v1, s[2:3] +; GFX11-NEXT: s_endpgm + store i32 %a, ptr addrspace(1) %out + ret void +} + +define amdgpu_cs void @cs_scratch(i32 inreg %a, ptr addrspace(1) inreg %out, i32 %idx) { +; GFX10-LABEL: cs_scratch: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b64 s[8:9], s[0:1] +; GFX10-NEXT: s_mov_b32 s10, -1 +; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, 0 +; GFX10-NEXT: v_mov_b32_e32 v1, s2 +; GFX10-NEXT: s_mov_b32 s11, 0x31c16000 +; GFX10-NEXT: s_add_u32 s8, s8, s5 +; GFX10-NEXT: s_addc_u32 s9, s9, 0 +; GFX10-NEXT: s_mov_b32 s1, s4 +; GFX10-NEXT: buffer_store_dword v1, v0, s[8:11], 0 offen +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: buffer_load_dword v0, off, s[8:11], 0 glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GFX10-NEXT: s_mov_b32 s0, s3 +; GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: cs_scratch: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_lshl_add_u32 v0, v0, 2, 0 +; GFX11-NEXT: v_mov_b32_e32 v1, s0 +; GFX11-NEXT: s_mov_b32 s3, s2 +; GFX11-NEXT: s_mov_b32 s2, s1 +; GFX11-NEXT: scratch_store_b32 v0, v1, off dlc +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: scratch_load_b32 v0, off, off glc dlc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-NEXT: global_store_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_endpgm + %alloca = alloca [8 x i32], align 4, addrspace(5) + %gep = getelementptr [8 x i32], ptr addrspace(5) %alloca, i32 0, i32 %idx + store volatile i32 %a, ptr addrspace(5) %gep + %load = load volatile i32, ptr addrspace(5) %alloca + store i32 %load, ptr addrspace(1) %out + ret void +} + +define amdgpu_ps void @ps_scratch(i32 inreg %a, ptr addrspace(1) inreg %out, i32 %idx) { +; GFX10-LABEL: ps_scratch: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x0 +; GFX10-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-NEXT: s_mov_b32 s10, -1 +; GFX10-NEXT: v_lshl_add_u32 v0, v0, 2, 0 +; GFX10-NEXT: v_mov_b32_e32 v1, s2 +; GFX10-NEXT: s_mov_b32 s11, 0x31c16000 +; GFX10-NEXT: s_add_u32 s8, s8, s5 +; GFX10-NEXT: s_addc_u32 s9, s9, 0 +; GFX10-NEXT: s_mov_b32 s1, s4 +; GFX10-NEXT: buffer_store_dword v1, v0, s[8:11], 0 offen +; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX10-NEXT: buffer_load_dword v0, off, s[8:11], 0 glc dlc +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_mov_b32_e32 v1, 0 +; GFX10-NEXT: s_mov_b32 s0, s3 +; GFX10-NEXT: global_store_dword v1, v0, s[0:1] +; GFX10-NEXT: s_endpgm +; +; GFX11-LABEL: ps_scratch: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_lshl_add_u32 v0, v0, 2, 0 +; GFX11-NEXT: v_mov_b32_e32 v1, s0 +; GFX11-NEXT: s_mov_b32 s3, s2 +; GFX11-NEXT: s_mov_b32 s2, s1 +; GFX11-NEXT: scratch_store_b32 v0, v1, off dlc +; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 +; GFX11-NEXT: scratch_load_b32 v0, off, off glc dlc +; GFX11-NEXT: s_waitcnt vmcnt(0) +; GFX11-NEXT: v_mov_b32_e32 v1, 0 +; GFX11-NEXT: global_store_b32 v1, v0, s[2:3] +; GFX11-NEXT: s_endpgm + %alloca = alloca [8 x i32], align 4, addrspace(5) + %gep = getelementptr [8 x i32], ptr addrspace(5) %alloca, i32 0, i32 %idx + store volatile i32 %a, ptr addrspace(5) %gep + %load = load volatile i32, ptr addrspace(5) %alloca + store i32 %load, ptr addrspace(1) %out + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/or3.ll b/llvm/test/CodeGen/AMDGPU/or3.ll index 81d13aa432c6ea..db2bef6b90cc7d 100644 --- a/llvm/test/CodeGen/AMDGPU/or3.ll +++ b/llvm/test/CodeGen/AMDGPU/or3.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgpu8.03-amd-mesa3d | FileCheck -check-prefix=VI %s ; RUN: llc < %s -mtriple=amdgpu9.00-amd-mesa3d | FileCheck -check-prefix=GFX9 %s -; RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefix=GFX10 %s -; RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s +; RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefixes=GFX10P,GFX10 %s +; RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX10P,GFX11 %s ; =================================================================================== ; V_OR3_B32 @@ -20,10 +20,10 @@ define amdgpu_ps float @or3(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: or3: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_or3_b32 v0, v0, v1, v2 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: or3: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_or3_b32 v0, v0, v1, v2 +; GFX10P-NEXT: ; return to shader part epilog %x = or i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -49,6 +49,11 @@ define amdgpu_ps float @or3_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_or3_b32 v0, v0, s2, s3 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: or3_vgpr_a: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_or3_b32 v0, v0, s0, s1 +; GFX11-NEXT: ; return to shader part epilog %x = or i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -67,10 +72,10 @@ define amdgpu_ps float @or3_vgpr_all2(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_or3_b32 v0, v1, v2, v0 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: or3_vgpr_all2: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_or3_b32 v0, v1, v2, v0 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: or3_vgpr_all2: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_or3_b32 v0, v1, v2, v0 +; GFX10P-NEXT: ; return to shader part epilog %x = or i32 %b, %c %result = or i32 %a, %x %bc = bitcast i32 %result to float @@ -93,6 +98,11 @@ define amdgpu_ps float @or3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_or3_b32 v0, s2, v0, v1 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: or3_vgpr_bc: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_or3_b32 v0, s0, v0, v1 +; GFX11-NEXT: ; return to shader part epilog %x = or i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -111,10 +121,10 @@ define amdgpu_ps float @or3_vgpr_const(i32 %a, i32 %b) { ; GFX9-NEXT: v_or3_b32 v0, v1, v0, 64 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: or3_vgpr_const: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_or3_b32 v0, v1, v0, 64 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: or3_vgpr_const: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_or3_b32 v0, v1, v0, 64 +; GFX10P-NEXT: ; return to shader part epilog %x = or i32 64, %b %result = or i32 %x, %a %bc = bitcast i32 %result to float @@ -138,12 +148,12 @@ define <2 x i32> @v_or3_v2i32(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c) { ; GFX9-NEXT: v_or3_b32 v0, v0, v2, v4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: v_or3_v2i32: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_or3_b32 v0, v0, v2, v4 -; GFX10-NEXT: v_or3_b32 v1, v1, v3, v5 -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10P-LABEL: v_or3_v2i32: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10P-NEXT: v_or3_b32 v0, v0, v2, v4 +; GFX10P-NEXT: v_or3_b32 v1, v1, v3, v5 +; GFX10P-NEXT: s_setpc_b64 s[30:31] %x = or <2 x i32> %a, %b %result = or <2 x i32> %x, %c ret <2 x i32> %result @@ -172,8 +182,16 @@ define <2 x i32> @v_or3_v2i32_b(<2 x i32> inreg %a, <2 x i32> %b, <2 x i32> inre ; GFX10-LABEL: v_or3_v2i32_b: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-DAG: v_or3_b32 v0, s{{[0-9]+}}, v0, s{{[0-9]+}} -; GFX10-DAG: v_or3_b32 v1, s{{[0-9]+}}, v1, s{{[0-9]+}} +; GFX10-NEXT: v_or3_b32 v0, s16, v0, s18 +; GFX10-NEXT: v_or3_b32 v1, s17, v1, s19 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_or3_v2i32_b: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_or3_b32 v0, s0, v0, s2 +; GFX11-NEXT: v_or3_b32 v1, s1, v1, s3 +; GFX11-NEXT: s_setpc_b64 s[30:31] %x = or <2 x i32> %a, %b %result = or <2 x i32> %x, %c ret <2 x i32> %result @@ -199,8 +217,16 @@ define <2 x i32> @v_or3_v2i32_ab(<2 x i32> %a, <2 x i32> %b, <2 x i32> inreg %c) ; GFX10-LABEL: v_or3_v2i32_ab: ; GFX10: ; %bb.0: ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-DAG: v_or3_b32 v0, v0, v2, s{{[0-9]+}} -; GFX10-DAG: v_or3_b32 v1, v1, v3, s{{[0-9]+}} +; GFX10-NEXT: v_or3_b32 v0, v0, v2, s16 +; GFX10-NEXT: v_or3_b32 v1, v1, v3, s17 +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX11-LABEL: v_or3_v2i32_ab: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX11-NEXT: v_or3_b32 v0, v0, v2, s0 +; GFX11-NEXT: v_or3_b32 v1, v1, v3, s1 +; GFX11-NEXT: s_setpc_b64 s[30:31] %x = or <2 x i32> %a, %b %result = or <2 x i32> %x, %c ret <2 x i32> %result @@ -223,12 +249,12 @@ define <2 x i32> @v_or3_v2i32_const(<2 x i32> %a, <2 x i32> %b) { ; GFX9-NEXT: v_or3_b32 v0, v0, v2, 4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: v_or3_v2i32_const: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_or3_b32 v0, v0, v2, 4 -; GFX10-NEXT: v_or3_b32 v1, v1, v3, 16 -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10P-LABEL: v_or3_v2i32_const: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10P-NEXT: v_or3_b32 v0, v0, v2, 4 +; GFX10P-NEXT: v_or3_b32 v1, v1, v3, 16 +; GFX10P-NEXT: s_setpc_b64 s[30:31] %x = or <2 x i32> %a, %result = or <2 x i32> %x, %b ret <2 x i32> %result @@ -253,12 +279,12 @@ define <2 x i32> @v_or3_v2i32_inline_const(<2 x i32> %a, <2 x i32> %b) { ; GFX9-NEXT: v_or3_b32 v0, v0, v2, s4 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: v_or3_v2i32_inline_const: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_or3_b32 v0, v0, v2, 0x808 -; GFX10-NEXT: v_or3_b32 v1, v1, v3, 0x809 -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10P-LABEL: v_or3_v2i32_inline_const: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10P-NEXT: v_or3_b32 v0, v0, v2, 0x808 +; GFX10P-NEXT: v_or3_b32 v1, v1, v3, 0x809 +; GFX10P-NEXT: s_setpc_b64 s[30:31] %x = or <2 x i32> %a, %result = or <2 x i32> %x, %b ret <2 x i32> %result @@ -287,16 +313,16 @@ define <2 x i32> @v_or3_v2i32_multi_use(<2 x i32> %a, <2 x i32> %b, <2 x i32> %c ; GFX9-NEXT: v_add_u32_e32 v1, v1, v2 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: v_or3_v2i32_multi_use: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_or_b32_e32 v0, v0, v2 -; GFX10-NEXT: v_or_b32_e32 v1, v1, v3 -; GFX10-NEXT: v_or_b32_e32 v2, v0, v4 -; GFX10-NEXT: v_or_b32_e32 v3, v1, v5 -; GFX10-NEXT: v_add_nc_u32_e32 v0, v0, v2 -; GFX10-NEXT: v_add_nc_u32_e32 v1, v1, v3 -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10P-LABEL: v_or3_v2i32_multi_use: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10P-NEXT: v_or_b32_e32 v0, v0, v2 +; GFX10P-NEXT: v_or_b32_e32 v1, v1, v3 +; GFX10P-NEXT: v_or_b32_e32 v2, v0, v4 +; GFX10P-NEXT: v_or_b32_e32 v3, v1, v5 +; GFX10P-NEXT: v_add_nc_u32_e32 v0, v0, v2 +; GFX10P-NEXT: v_add_nc_u32_e32 v1, v1, v3 +; GFX10P-NEXT: s_setpc_b64 s[30:31] %x = or <2 x i32> %a, %b %y = or <2 x i32> %x, %c %result = add <2 x i32> %x, %y @@ -321,6 +347,12 @@ define amdgpu_ps <2 x i32> @s_or3_v2i32(<2 x i32> inreg %a, <2 x i32> inreg %b, ; GFX10-NEXT: s_or_b64 s[0:1], s[2:3], s[4:5] ; GFX10-NEXT: s_or_b64 s[0:1], s[0:1], s[6:7] ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_or3_v2i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3] +; GFX11-NEXT: s_or_b64 s[0:1], s[0:1], s[4:5] +; GFX11-NEXT: ; return to shader part epilog %x = or <2 x i32> %a, %b %result = or <2 x i32> %x, %c ret <2 x i32> %result diff --git a/llvm/test/CodeGen/AMDGPU/ptr-s-buffer-load-mmo-offsets.ll b/llvm/test/CodeGen/AMDGPU/ptr-s-buffer-load-mmo-offsets.ll index 3adec802d5fe36..1368708e3d8add 100644 --- a/llvm/test/CodeGen/AMDGPU/ptr-s-buffer-load-mmo-offsets.ll +++ b/llvm/test/CodeGen/AMDGPU/ptr-s-buffer-load-mmo-offsets.ll @@ -10,13 +10,13 @@ define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %offset) { ; CHECK-LABEL: name: ptr_s_buffer_load_v8f32_vgpr_offset ; CHECK: bb.0 (%ir-block.0): - ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr5 - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr4 - ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr3 - ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr1 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr0 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0 @@ -52,13 +52,13 @@ define amdgpu_ps <8 x float> @ptr_s_buffer_load_v8f32_vgpr_offset(ptr addrspace( define amdgpu_ps <16 x float> @ptr_s_buffer_load_v16f32_vgpr_offset(ptr addrspace(8) inreg %rsrc, i32 %offset) { ; CHECK-LABEL: name: ptr_s_buffer_load_v16f32_vgpr_offset ; CHECK: bb.0 (%ir-block.0): - ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr5 - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr4 - ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr3 - ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr1 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr0 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY1]], %subreg.sub1 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub1 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[REG_SEQUENCE]].sub0 diff --git a/llvm/test/CodeGen/AMDGPU/ptrmask.ll b/llvm/test/CodeGen/AMDGPU/ptrmask.ll index c720ebe74303de..01101a3564f267 100644 --- a/llvm/test/CodeGen/AMDGPU/ptrmask.ll +++ b/llvm/test/CodeGen/AMDGPU/ptrmask.ll @@ -43,10 +43,15 @@ define amdgpu_ps ptr addrspace(1) @s_ptrmask_global_variable_i64(ptr addrspace(1 ; GCN-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5] ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_ptrmask_global_variable_i64: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5] -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_ptrmask_global_variable_i64: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_and_b64 s[0:1], s[2:3], s[4:5] +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_ptrmask_global_variable_i64: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3] +; GFX11-NEXT: ; return to shader part epilog %masked = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) %ptr, i64 %mask) ret ptr addrspace(1) %masked } @@ -57,10 +62,15 @@ define amdgpu_ps ptr addrspace(3) @s_ptrmask_local_variable_i32(ptr addrspace(3) ; GCN-NEXT: s_and_b32 s0, s2, s3 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_ptrmask_local_variable_i32: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_and_b32 s0, s2, s3 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_ptrmask_local_variable_i32: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_and_b32 s0, s2, s3 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_ptrmask_local_variable_i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_and_b32 s0, s0, s1 +; GFX11-NEXT: ; return to shader part epilog %masked = call ptr addrspace(3) @llvm.ptrmask.p3.i32(ptr addrspace(3) %ptr, i32 %mask) ret ptr addrspace(3) %masked } @@ -108,15 +118,20 @@ define amdgpu_ps ptr addrspace(7) @s_ptrmask_buffer_fat_ptr_variable_i32(ptr add ; GCN-NEXT: s_mov_b32 s3, s5 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_ptrmask_buffer_fat_ptr_variable_i32: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_mov_b32 s8, s4 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_and_b32 s4, s6, s7 -; GFX10PLUS-NEXT: s_mov_b32 s2, s8 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_ptrmask_buffer_fat_ptr_variable_i32: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s8, s4 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_and_b32 s4, s6, s7 +; GFX10-NEXT: s_mov_b32 s2, s8 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_ptrmask_buffer_fat_ptr_variable_i32: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_and_b32 s4, s4, s5 +; GFX11-NEXT: ; return to shader part epilog %masked = call ptr addrspace(7) @llvm.ptrmask.p7.i32(ptr addrspace(7) %ptr, i32 %mask) ret ptr addrspace(7) %masked } @@ -132,15 +147,20 @@ define amdgpu_ps ptr addrspace(7) @s_ptrmask_buffer_fat_ptr_i32_neg8(ptr addrspa ; GCN-NEXT: s_mov_b32 s3, s5 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_ptrmask_buffer_fat_ptr_i32_neg8: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_mov_b32 s7, s4 -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_mov_b32 s0, s2 -; GFX10PLUS-NEXT: s_and_b32 s4, s6, -8 -; GFX10PLUS-NEXT: s_mov_b32 s2, s7 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_ptrmask_buffer_fat_ptr_i32_neg8: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s7, s4 +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_mov_b32 s0, s2 +; GFX10-NEXT: s_and_b32 s4, s6, -8 +; GFX10-NEXT: s_mov_b32 s2, s7 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_ptrmask_buffer_fat_ptr_i32_neg8: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_and_b32 s4, s4, -8 +; GFX11-NEXT: ; return to shader part epilog %masked = call ptr addrspace(7) @llvm.ptrmask.p7.i32(ptr addrspace(7) %ptr, i32 -8) ret ptr addrspace(7) %masked } @@ -190,13 +210,19 @@ define amdgpu_ps ptr addrspace(8) @s_ptrmask_buffer_resource_variable_i48(ptr ad ; GCN-NEXT: s_mov_b32 s3, s5 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_ptrmask_buffer_resource_variable_i48: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_or_b32 s7, s7, 0xffff0000 -; GFX10PLUS-NEXT: s_and_b64 s[0:1], s[2:3], s[6:7] -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_ptrmask_buffer_resource_variable_i48: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_or_b32 s7, s7, 0xffff0000 +; GFX10-NEXT: s_and_b64 s[0:1], s[2:3], s[6:7] +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_ptrmask_buffer_resource_variable_i48: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_or_b32 s5, s5, 0xffff0000 +; GFX11-NEXT: s_and_b64 s[0:1], s[0:1], s[4:5] +; GFX11-NEXT: ; return to shader part epilog %masked = call ptr addrspace(8) @llvm.ptrmask.p8.i48(ptr addrspace(8) %ptr, i48 %mask) ret ptr addrspace(8) %masked } @@ -210,13 +236,18 @@ define amdgpu_ps ptr addrspace(8) @s_ptrmask_buffer_resource_variable_i48_neg8(p ; GCN-NEXT: s_mov_b32 s3, s5 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_ptrmask_buffer_resource_variable_i48_neg8: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: s_mov_b32 s1, s3 -; GFX10PLUS-NEXT: s_and_b32 s0, s2, -8 -; GFX10PLUS-NEXT: s_mov_b32 s2, s4 -; GFX10PLUS-NEXT: s_mov_b32 s3, s5 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_ptrmask_buffer_resource_variable_i48_neg8: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_mov_b32 s1, s3 +; GFX10-NEXT: s_and_b32 s0, s2, -8 +; GFX10-NEXT: s_mov_b32 s2, s4 +; GFX10-NEXT: s_mov_b32 s3, s5 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_ptrmask_buffer_resource_variable_i48_neg8: +; GFX11: ; %bb.0: +; GFX11-NEXT: s_and_b32 s0, s0, -8 +; GFX11-NEXT: ; return to shader part epilog %masked = call ptr addrspace(8) @llvm.ptrmask.p8.i48(ptr addrspace(8) %ptr, i48 -8) ret ptr addrspace(8) %masked } @@ -225,6 +256,3 @@ declare ptr addrspace(3) @llvm.ptrmask.p3.i32(ptr addrspace(3), i32) #0 declare ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1), i64) #0 attributes #0 = { nounwind readnone speculatable willreturn } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GFX10: {{.*}} -; GFX11: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/s-buffer-load-mmo-offsets.ll b/llvm/test/CodeGen/AMDGPU/s-buffer-load-mmo-offsets.ll index cf6802220645ee..2e605ce6d4778f 100644 --- a/llvm/test/CodeGen/AMDGPU/s-buffer-load-mmo-offsets.ll +++ b/llvm/test/CodeGen/AMDGPU/s-buffer-load-mmo-offsets.ll @@ -10,13 +10,13 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %offset) { ; CHECK-LABEL: name: s_buffer_load_v8f32_vgpr_offset ; CHECK: bb.0 (%ir-block.0): - ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr5 - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr4 - ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr3 - ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr1 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr0 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY1]], %subreg.sub3 ; CHECK-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128), align 32) ; CHECK-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from unknown-address + 16) @@ -46,13 +46,13 @@ define amdgpu_ps <8 x float> @s_buffer_load_v8f32_vgpr_offset(<4 x i32> inreg %r define amdgpu_ps <16 x float> @s_buffer_load_v16f32_vgpr_offset(<4 x i32> inreg %rsrc, i32 %offset) { ; CHECK-LABEL: name: s_buffer_load_v16f32_vgpr_offset ; CHECK: bb.0 (%ir-block.0): - ; CHECK-NEXT: liveins: $sgpr2, $sgpr3, $sgpr4, $sgpr5, $vgpr0 + ; CHECK-NEXT: liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3, $vgpr0 ; CHECK-NEXT: {{ $}} ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 - ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr5 - ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr4 - ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr3 - ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sgpr_32 = COPY $sgpr3 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sgpr_32 = COPY $sgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sgpr_32 = COPY $sgpr1 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sgpr_32 = COPY $sgpr0 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY4]], %subreg.sub0, [[COPY3]], %subreg.sub1, [[COPY2]], %subreg.sub2, [[COPY1]], %subreg.sub3 ; CHECK-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY]], [[REG_SEQUENCE]], $sgpr_null, 0, 0, 0, implicit $exec :: (dereferenceable invariant load (s128), align 64) ; CHECK-NEXT: [[BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN1:%[0-9]+]]:vreg_128 = BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN [[COPY]], [[REG_SEQUENCE]], $sgpr_null, 16, 0, 0, implicit $exec :: (dereferenceable invariant load (s128) from unknown-address + 16) diff --git a/llvm/test/CodeGen/AMDGPU/shl_add.ll b/llvm/test/CodeGen/AMDGPU/shl_add.ll index d0aed371966f71..2cd0c716cd9188 100644 --- a/llvm/test/CodeGen/AMDGPU/shl_add.ll +++ b/llvm/test/CodeGen/AMDGPU/shl_add.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgpu8.03-amd-mesa3d | FileCheck -check-prefix=VI %s ; RUN: llc < %s -mtriple=amdgpu9.00-amd-mesa3d | FileCheck -check-prefix=GFX9 %s -; RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefix=GFX10 %s -; RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s +; RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefixes=GFX10P,GFX10 %s +; RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX10P,GFX11 %s ; RUN: llc -O0 < %s -mtriple=amdgpu9.00-amd-mesa3d | FileCheck -check-prefix=GFX9-O0 %s ; =================================================================================== @@ -21,10 +21,10 @@ define amdgpu_ps float @shl_add(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: shl_add: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: shl_add: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_lshl_add_u32 v0, v0, v1, v2 +; GFX10P-NEXT: ; return to shader part epilog ; ; GFX9-O0-LABEL: shl_add: ; GFX9-O0: ; %bb.0: @@ -55,6 +55,11 @@ define amdgpu_ps float @shl_add_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) { ; GFX10-NEXT: v_lshl_add_u32 v0, v0, s2, s3 ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: shl_add_vgpr_a: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_lshl_add_u32 v0, v0, s0, s1 +; GFX11-NEXT: ; return to shader part epilog +; ; GFX9-O0-LABEL: shl_add_vgpr_a: ; GFX9-O0: ; %bb.0: ; GFX9-O0-NEXT: v_lshlrev_b32_e64 v0, s2, v0 @@ -78,10 +83,10 @@ define amdgpu_ps float @shl_add_vgpr_all(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_lshl_add_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: shl_add_vgpr_all: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, v2 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: shl_add_vgpr_all: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_lshl_add_u32 v0, v0, v1, v2 +; GFX10P-NEXT: ; return to shader part epilog ; ; GFX9-O0-LABEL: shl_add_vgpr_all: ; GFX9-O0: ; %bb.0: @@ -110,6 +115,11 @@ define amdgpu_ps float @shl_add_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) { ; GFX10-NEXT: v_lshl_add_u32 v0, v0, v1, s2 ; GFX10-NEXT: ; return to shader part epilog ; +; GFX11-LABEL: shl_add_vgpr_ab: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_lshl_add_u32 v0, v0, v1, s0 +; GFX11-NEXT: ; return to shader part epilog +; ; GFX9-O0-LABEL: shl_add_vgpr_ab: ; GFX9-O0: ; %bb.0: ; GFX9-O0-NEXT: v_lshl_add_u32 v0, v0, v1, s2 @@ -132,10 +142,10 @@ define amdgpu_ps float @shl_add_vgpr_const(i32 %a, i32 %b) { ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 3, v1 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: shl_add_vgpr_const: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_lshl_add_u32 v0, v0, 3, v1 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: shl_add_vgpr_const: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_lshl_add_u32 v0, v0, 3, v1 +; GFX10P-NEXT: ; return to shader part epilog ; ; GFX9-O0-LABEL: shl_add_vgpr_const: ; GFX9-O0: ; %bb.0: @@ -168,11 +178,11 @@ define i32 @v_shl1_add_chain(i32 %src) { ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 5, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: v_shl1_add_chain: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_lshl_add_u32 v0, v0, 5, 0x9b3e1f00 -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10P-LABEL: v_shl1_add_chain: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10P-NEXT: v_lshl_add_u32 v0, v0, 5, 0x9b3e1f00 +; GFX10P-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-O0-LABEL: v_shl1_add_chain: ; GFX9-O0: ; %bb.0: @@ -218,11 +228,11 @@ define i32 @v_shl2_add_chain(i32 %src) { ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 10, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: v_shl2_add_chain: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_lshl_add_u32 v0, v0, 10, 0xabab5500 -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10P-LABEL: v_shl2_add_chain: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10P-NEXT: v_lshl_add_u32 v0, v0, 10, 0xabab5500 +; GFX10P-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-O0-LABEL: v_shl2_add_chain: ; GFX9-O0: ; %bb.0: @@ -268,11 +278,11 @@ define i32 @v_shl3_add_chain(i32 %src) { ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 15, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: v_shl3_add_chain: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_lshl_add_u32 v0, v0, 15, 0x91a44900 -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10P-LABEL: v_shl3_add_chain: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10P-NEXT: v_lshl_add_u32 v0, v0, 15, 0x91a44900 +; GFX10P-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-O0-LABEL: v_shl3_add_chain: ; GFX9-O0: ; %bb.0: @@ -318,11 +328,11 @@ define i32 @v_shl4_add_chain(i32 %src) { ; GFX9-NEXT: v_lshl_add_u32 v0, v0, 20, v1 ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX10-LABEL: v_shl4_add_chain: -; GFX10: ; %bb.0: -; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX10-NEXT: v_lshl_add_u32 v0, v0, 20, 0x78331100 -; GFX10-NEXT: s_setpc_b64 s[30:31] +; GFX10P-LABEL: v_shl4_add_chain: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10P-NEXT: v_lshl_add_u32 v0, v0, 20, 0x78331100 +; GFX10P-NEXT: s_setpc_b64 s[30:31] ; ; GFX9-O0-LABEL: v_shl4_add_chain: ; GFX9-O0: ; %bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/shl_or.ll b/llvm/test/CodeGen/AMDGPU/shl_or.ll index 9843be3490c148..ebbb0b84534b4b 100644 --- a/llvm/test/CodeGen/AMDGPU/shl_or.ll +++ b/llvm/test/CodeGen/AMDGPU/shl_or.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgpu8.03-amd-mesa3d | FileCheck -check-prefix=VI %s ; RUN: llc < %s -mtriple=amdgpu9.00-amd-mesa3d | FileCheck -check-prefix=GFX9 %s -; RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefix=GFX10 %s -; RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s +; RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefixes=GFX10P,GFX10 %s +; RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX10P,GFX11 %s ; =================================================================================== ; V_LSHL_OR_B32 @@ -20,10 +20,10 @@ define amdgpu_ps float @shl_or(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_lshl_or_b32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: shl_or: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_lshl_or_b32 v0, v0, v1, v2 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: shl_or: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_lshl_or_b32 v0, v0, v1, v2 +; GFX10P-NEXT: ; return to shader part epilog %x = shl i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -47,6 +47,11 @@ define amdgpu_ps float @shl_or_vgpr_c(i32 inreg %a, i32 inreg %b, i32 %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_lshl_or_b32 v0, s2, s3, v0 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: shl_or_vgpr_c: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_lshl_or_b32 v0, s0, s1, v0 +; GFX11-NEXT: ; return to shader part epilog %x = shl i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -65,10 +70,10 @@ define amdgpu_ps float @shl_or_vgpr_all2(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_lshl_or_b32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: shl_or_vgpr_all2: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_lshl_or_b32 v0, v0, v1, v2 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: shl_or_vgpr_all2: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_lshl_or_b32 v0, v0, v1, v2 +; GFX10P-NEXT: ; return to shader part epilog %x = shl i32 %a, %b %result = or i32 %c, %x %bc = bitcast i32 %result to float @@ -91,6 +96,11 @@ define amdgpu_ps float @shl_or_vgpr_ac(i32 %a, i32 inreg %b, i32 %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_lshl_or_b32 v0, v0, s2, v1 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: shl_or_vgpr_ac: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_lshl_or_b32 v0, v0, s0, v1 +; GFX11-NEXT: ; return to shader part epilog %x = shl i32 %a, %b %result = or i32 %x, %c %bc = bitcast i32 %result to float @@ -109,10 +119,10 @@ define amdgpu_ps float @shl_or_vgpr_const(i32 %a, i32 %b) { ; GFX9-NEXT: v_lshl_or_b32 v0, v0, v1, 6 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: shl_or_vgpr_const: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_lshl_or_b32 v0, v0, v1, 6 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: shl_or_vgpr_const: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_lshl_or_b32 v0, v0, v1, 6 +; GFX10P-NEXT: ; return to shader part epilog %x = shl i32 %a, %b %result = or i32 %x, 6 %bc = bitcast i32 %result to float @@ -131,10 +141,10 @@ define amdgpu_ps float @shl_or_vgpr_const2(i32 %a, i32 %b) { ; GFX9-NEXT: v_lshl_or_b32 v0, v0, 6, v1 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: shl_or_vgpr_const2: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_lshl_or_b32 v0, v0, 6, v1 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: shl_or_vgpr_const2: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_lshl_or_b32 v0, v0, 6, v1 +; GFX10P-NEXT: ; return to shader part epilog %x = shl i32 %a, 6 %result = or i32 %x, %b %bc = bitcast i32 %result to float @@ -157,6 +167,11 @@ define amdgpu_ps float @shl_or_vgpr_const_scalar1(i32 inreg %a, i32 %b) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_lshl_or_b32 v0, s2, 6, v0 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: shl_or_vgpr_const_scalar1: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_lshl_or_b32 v0, s0, 6, v0 +; GFX11-NEXT: ; return to shader part epilog %x = shl i32 %a, 6 %result = or i32 %x, %b %bc = bitcast i32 %result to float @@ -179,6 +194,11 @@ define amdgpu_ps float @shl_or_vgpr_const_scalar2(i32 %a, i32 inreg %b) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_lshl_or_b32 v0, v0, 6, s2 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: shl_or_vgpr_const_scalar2: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_lshl_or_b32 v0, v0, 6, s0 +; GFX11-NEXT: ; return to shader part epilog %x = shl i32 %a, 6 %result = or i32 %x, %b %bc = bitcast i32 %result to float diff --git a/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll index 080ff3b16ee612..5dfd6eeb054469 100644 --- a/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/strict_fadd.f16.ll @@ -502,27 +502,27 @@ define amdgpu_ps half @s_constained_fadd_f16_fpexcept_strict(half inreg %x, half ; ; GFX11-SDAG-TRUE16-LABEL: s_constained_fadd_f16_fpexcept_strict: ; GFX11-SDAG-TRUE16: ; %bb.0: -; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e64 v0.l, s2, s3 +; GFX11-SDAG-TRUE16-NEXT: v_add_f16_e64 v0.l, s0, s1 ; GFX11-SDAG-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-SDAG-FAKE16-LABEL: s_constained_fadd_f16_fpexcept_strict: ; GFX11-SDAG-FAKE16: ; %bb.0: -; GFX11-SDAG-FAKE16-NEXT: v_add_f16_e64 v0, s2, s3 +; GFX11-SDAG-FAKE16-NEXT: v_add_f16_e64 v0, s0, s1 ; GFX11-SDAG-FAKE16-NEXT: ; return to shader part epilog ; ; GFX11-GISEL-TRUE16-LABEL: s_constained_fadd_f16_fpexcept_strict: ; GFX11-GISEL-TRUE16: ; %bb.0: -; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e64 v0.l, s2, s3 +; GFX11-GISEL-TRUE16-NEXT: v_add_f16_e64 v0.l, s0, s1 ; GFX11-GISEL-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-GISEL-FAKE16-LABEL: s_constained_fadd_f16_fpexcept_strict: ; GFX11-GISEL-FAKE16: ; %bb.0: -; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e64 v0, s2, s3 +; GFX11-GISEL-FAKE16-NEXT: v_add_f16_e64 v0, s0, s1 ; GFX11-GISEL-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: s_constained_fadd_f16_fpexcept_strict: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_add_f16 s0, s2, s3 +; GFX12-NEXT: s_add_f16 s0, s0, s1 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -573,12 +573,12 @@ define amdgpu_ps <2 x half> @s_constained_fadd_v2f16_fpexcept_strict(<2 x half> ; ; GFX11-LABEL: s_constained_fadd_v2f16_fpexcept_strict: ; GFX11: ; %bb.0: -; GFX11-NEXT: v_pk_add_f16 v0, s2, s3 +; GFX11-NEXT: v_pk_add_f16 v0, s0, s1 ; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: s_constained_fadd_v2f16_fpexcept_strict: ; GFX12: ; %bb.0: -; GFX12-NEXT: v_pk_add_f16 v0, s2, s3 +; GFX12-NEXT: v_pk_add_f16 v0, s0, s1 ; GFX12-NEXT: ; return to shader part epilog %val = call <2 x half> @llvm.experimental.constrained.fadd.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict") ret <2 x half> %val diff --git a/llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll b/llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll index 5c07338d3108c1..86ef47a045dbb2 100644 --- a/llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/strict_fadd.f32.ll @@ -416,14 +416,29 @@ define amdgpu_ps float @s_constained_fadd_f32_fpexcept_strict(float inreg %x, fl ; GFX9-NEXT: v_add_f32_e32 v0, s2, v0 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_constained_fadd_f32_fpexcept_strict: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_add_f32_e64 v0, s2, s3 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-SDAG-LABEL: s_constained_fadd_f32_fpexcept_strict: +; GFX10-SDAG: ; %bb.0: +; GFX10-SDAG-NEXT: v_add_f32_e64 v0, s2, s3 +; GFX10-SDAG-NEXT: ; return to shader part epilog +; +; GFX10-GISEL-LABEL: s_constained_fadd_f32_fpexcept_strict: +; GFX10-GISEL: ; %bb.0: +; GFX10-GISEL-NEXT: v_add_f32_e64 v0, s2, s3 +; GFX10-GISEL-NEXT: ; return to shader part epilog +; +; GFX11-SDAG-LABEL: s_constained_fadd_f32_fpexcept_strict: +; GFX11-SDAG: ; %bb.0: +; GFX11-SDAG-NEXT: v_add_f32_e64 v0, s0, s1 +; GFX11-SDAG-NEXT: ; return to shader part epilog +; +; GFX11-GISEL-LABEL: s_constained_fadd_f32_fpexcept_strict: +; GFX11-GISEL: ; %bb.0: +; GFX11-GISEL-NEXT: v_add_f32_e64 v0, s0, s1 +; GFX11-GISEL-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: s_constained_fadd_f32_fpexcept_strict: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_add_f32 s0, s2, s3 +; GFX12-NEXT: s_add_f32 s0, s0, s1 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog diff --git a/llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll b/llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll index b96a53f3786282..f2b320bf3333d3 100644 --- a/llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/strict_fadd.f64.ll @@ -118,12 +118,12 @@ define amdgpu_ps <2 x float> @s_constained_fadd_f64_fpexcept_strict(double inreg ; ; GFX11-SDAG-LABEL: s_constained_fadd_f64_fpexcept_strict: ; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: v_add_f64 v[0:1], s[2:3], s[4:5] +; GFX11-SDAG-NEXT: v_add_f64 v[0:1], s[0:1], s[2:3] ; GFX11-SDAG-NEXT: ; return to shader part epilog ; ; GFX11-GISEL-LABEL: s_constained_fadd_f64_fpexcept_strict: ; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: v_add_f64 v[0:1], s[2:3], s[4:5] +; GFX11-GISEL-NEXT: v_add_f64 v[0:1], s[0:1], s[2:3] ; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 diff --git a/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll index ad4d9224e25b40..4df4de7b265243 100644 --- a/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/strict_fmul.f16.ll @@ -574,27 +574,27 @@ define amdgpu_ps half @s_constained_fmul_f16_fpexcept_strict(half inreg %x, half ; ; GFX11-SDAG-TRUE16-LABEL: s_constained_fmul_f16_fpexcept_strict: ; GFX11-SDAG-TRUE16: ; %bb.0: -; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e64 v0.l, s2, s3 +; GFX11-SDAG-TRUE16-NEXT: v_mul_f16_e64 v0.l, s0, s1 ; GFX11-SDAG-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-SDAG-FAKE16-LABEL: s_constained_fmul_f16_fpexcept_strict: ; GFX11-SDAG-FAKE16: ; %bb.0: -; GFX11-SDAG-FAKE16-NEXT: v_mul_f16_e64 v0, s2, s3 +; GFX11-SDAG-FAKE16-NEXT: v_mul_f16_e64 v0, s0, s1 ; GFX11-SDAG-FAKE16-NEXT: ; return to shader part epilog ; ; GFX11-GISEL-TRUE16-LABEL: s_constained_fmul_f16_fpexcept_strict: ; GFX11-GISEL-TRUE16: ; %bb.0: -; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e64 v0.l, s2, s3 +; GFX11-GISEL-TRUE16-NEXT: v_mul_f16_e64 v0.l, s0, s1 ; GFX11-GISEL-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-GISEL-FAKE16-LABEL: s_constained_fmul_f16_fpexcept_strict: ; GFX11-GISEL-FAKE16: ; %bb.0: -; GFX11-GISEL-FAKE16-NEXT: v_mul_f16_e64 v0, s2, s3 +; GFX11-GISEL-FAKE16-NEXT: v_mul_f16_e64 v0, s0, s1 ; GFX11-GISEL-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: s_constained_fmul_f16_fpexcept_strict: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mul_f16 s0, s2, s3 +; GFX12-NEXT: s_mul_f16 s0, s0, s1 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -646,14 +646,19 @@ define amdgpu_ps <2 x half> @s_constained_fmul_v2f16_fpexcept_strict(<2 x half> ; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, s0 ; GFX8-GISEL-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_constained_fmul_v2f16_fpexcept_strict: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_pk_mul_f16 v0, s2, s3 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_constained_fmul_v2f16_fpexcept_strict: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_pk_mul_f16 v0, s2, s3 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_constained_fmul_v2f16_fpexcept_strict: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_pk_mul_f16 v0, s0, s1 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: s_constained_fmul_v2f16_fpexcept_strict: ; GFX12: ; %bb.0: -; GFX12-NEXT: v_pk_mul_f16 v0, s2, s3 +; GFX12-NEXT: v_pk_mul_f16 v0, s0, s1 ; GFX12-NEXT: ; return to shader part epilog %val = call <2 x half> @llvm.experimental.constrained.fmul.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict") ret <2 x half> %val @@ -667,6 +672,5 @@ declare <4 x half> @llvm.experimental.constrained.fmul.v4f16(<4 x half>, <4 x ha attributes #0 = { strictfp } attributes #1 = { inaccessiblememonly nounwind willreturn } ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GFX11: {{.*}} ; GFX11-SDAG: {{.*}} ; GFX8: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll b/llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll index ee7d27b8317d23..bc771ed58dbe84 100644 --- a/llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/strict_fmul.f32.ll @@ -236,14 +236,19 @@ define amdgpu_ps float @s_constained_fmul_f32_fpexcept_strict(float inreg %x, fl ; GCN-NEXT: v_mul_f32_e32 v0, s2, v0 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_constained_fmul_f32_fpexcept_strict: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_mul_f32_e64 v0, s2, s3 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_constained_fmul_f32_fpexcept_strict: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_mul_f32_e64 v0, s2, s3 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_constained_fmul_f32_fpexcept_strict: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_mul_f32_e64 v0, s0, s1 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: s_constained_fmul_f32_fpexcept_strict: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_mul_f32 s0, s2, s3 +; GFX12-NEXT: s_mul_f32 s0, s0, s1 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog diff --git a/llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll b/llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll index e0644fc95a06c6..2f6b836ac7f1b7 100644 --- a/llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/strict_fmul.f64.ll @@ -290,12 +290,12 @@ define amdgpu_ps <2 x float> @s_constained_fmul_f64_fpexcept_strict(double inreg ; ; GFX11-SDAG-LABEL: s_constained_fmul_f64_fpexcept_strict: ; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: v_mul_f64 v[0:1], s[2:3], s[4:5] +; GFX11-SDAG-NEXT: v_mul_f64 v[0:1], s[0:1], s[2:3] ; GFX11-SDAG-NEXT: ; return to shader part epilog ; ; GFX11-GISEL-LABEL: s_constained_fmul_f64_fpexcept_strict: ; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], s[2:3], s[4:5] +; GFX11-GISEL-NEXT: v_mul_f64 v[0:1], s[0:1], s[2:3] ; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 @@ -303,14 +303,15 @@ define amdgpu_ps <2 x float> @s_constained_fmul_f64_fpexcept_strict(double inreg ; ; GFX12-SDAG-LABEL: s_constained_fmul_f64_fpexcept_strict: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: v_mul_f64_e64 v[0:1], s[2:3], s[4:5] +; GFX12-SDAG-NEXT: v_mul_f64_e64 v[0:1], s[0:1], s[2:3] ; GFX12-SDAG-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-LABEL: s_constained_fmul_f64_fpexcept_strict: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: v_mul_f64_e64 v[0:1], s[2:3], s[4:5] +; GFX12-GISEL-NEXT: v_mul_f64_e64 v[0:1], s[0:1], s[2:3] ; GFX12-GISEL-NEXT: v_readfirstlane_b32 s0, v0 ; GFX12-GISEL-NEXT: v_readfirstlane_b32 s1, v1 +; GFX12-GISEL-NEXT: s_wait_alu depctr_va_sdst(0) ; GFX12-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 ; GFX12-GISEL-NEXT: ; return to shader part epilog %val = call double @llvm.experimental.constrained.fmul.f64(double %x, double %y, metadata !"round.tonearest", metadata !"fpexcept.strict") diff --git a/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll b/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll index 1b010f7e0d9b47..e5cb91ebbff9ec 100644 --- a/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll @@ -714,27 +714,27 @@ define amdgpu_ps half @s_constained_fsub_f16_fpexcept_strict(half inreg %x, half ; ; GFX11-SDAG-TRUE16-LABEL: s_constained_fsub_f16_fpexcept_strict: ; GFX11-SDAG-TRUE16: ; %bb.0: -; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e64 v0.l, s2, s3 +; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e64 v0.l, s0, s1 ; GFX11-SDAG-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-SDAG-FAKE16-LABEL: s_constained_fsub_f16_fpexcept_strict: ; GFX11-SDAG-FAKE16: ; %bb.0: -; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e64 v0, s2, s3 +; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e64 v0, s0, s1 ; GFX11-SDAG-FAKE16-NEXT: ; return to shader part epilog ; ; GFX11-GISEL-TRUE16-LABEL: s_constained_fsub_f16_fpexcept_strict: ; GFX11-GISEL-TRUE16: ; %bb.0: -; GFX11-GISEL-TRUE16-NEXT: v_sub_f16_e64 v0.l, s2, s3 +; GFX11-GISEL-TRUE16-NEXT: v_sub_f16_e64 v0.l, s0, s1 ; GFX11-GISEL-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-GISEL-FAKE16-LABEL: s_constained_fsub_f16_fpexcept_strict: ; GFX11-GISEL-FAKE16: ; %bb.0: -; GFX11-GISEL-FAKE16-NEXT: v_sub_f16_e64 v0, s2, s3 +; GFX11-GISEL-FAKE16-NEXT: v_sub_f16_e64 v0, s0, s1 ; GFX11-GISEL-FAKE16-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: s_constained_fsub_f16_fpexcept_strict: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_sub_f16 s0, s2, s3 +; GFX12-NEXT: s_sub_f16 s0, s0, s1 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -807,42 +807,41 @@ define amdgpu_ps <2 x half> @s_constained_fsub_v2f16_fpexcept_strict(<2 x half> ; ; GFX11-SDAG-TRUE16-LABEL: s_constained_fsub_v2f16_fpexcept_strict: ; GFX11-SDAG-TRUE16: ; %bb.0: -; GFX11-SDAG-TRUE16-NEXT: s_lshr_b32 s0, s3, 16 -; GFX11-SDAG-TRUE16-NEXT: s_lshr_b32 s1, s2, 16 -; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e64 v0.l, s2, s3 -; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e64 v0.h, s1, s0 +; GFX11-SDAG-TRUE16-NEXT: s_lshr_b32 s2, s1, 16 +; GFX11-SDAG-TRUE16-NEXT: s_lshr_b32 s3, s0, 16 +; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e64 v0.l, s0, s1 +; GFX11-SDAG-TRUE16-NEXT: v_sub_f16_e64 v0.h, s3, s2 ; GFX11-SDAG-TRUE16-NEXT: ; return to shader part epilog ; ; GFX11-SDAG-FAKE16-LABEL: s_constained_fsub_v2f16_fpexcept_strict: ; GFX11-SDAG-FAKE16: ; %bb.0: -; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e64 v0, s2, s3 -; GFX11-SDAG-FAKE16-NEXT: s_lshr_b32 s0, s3, 16 -; GFX11-SDAG-FAKE16-NEXT: s_lshr_b32 s1, s2, 16 -; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e64 v1, s1, s0 +; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e64 v0, s0, s1 +; GFX11-SDAG-FAKE16-NEXT: s_lshr_b32 s1, s1, 16 +; GFX11-SDAG-FAKE16-NEXT: s_lshr_b32 s0, s0, 16 +; GFX11-SDAG-FAKE16-NEXT: v_sub_f16_e64 v1, s0, s1 ; GFX11-SDAG-FAKE16-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX11-SDAG-FAKE16-NEXT: v_lshl_or_b32 v0, v1, 16, v0 ; GFX11-SDAG-FAKE16-NEXT: ; return to shader part epilog ; ; GFX11-GISEL-LABEL: s_constained_fsub_v2f16_fpexcept_strict: ; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: v_pk_add_f16 v0, s2, s3 neg_lo:[0,1] neg_hi:[0,1] +; GFX11-GISEL-NEXT: v_pk_add_f16 v0, s0, s1 neg_lo:[0,1] neg_hi:[0,1] ; GFX11-GISEL-NEXT: ; return to shader part epilog ; ; GFX12-SDAG-LABEL: s_constained_fsub_v2f16_fpexcept_strict: ; GFX12-SDAG: ; %bb.0: -; GFX12-SDAG-NEXT: s_lshr_b32 s0, s3, 16 -; GFX12-SDAG-NEXT: s_lshr_b32 s1, s2, 16 -; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_3) -; GFX12-SDAG-NEXT: s_sub_f16 s0, s1, s0 -; GFX12-SDAG-NEXT: s_sub_f16 s1, s2, s3 -; GFX12-SDAG-NEXT: s_pack_ll_b32_b16 s0, s1, s0 -; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_1) +; GFX12-SDAG-NEXT: s_lshr_b32 s2, s1, 16 +; GFX12-SDAG-NEXT: s_lshr_b32 s3, s0, 16 +; GFX12-SDAG-NEXT: s_sub_f16 s0, s0, s1 +; GFX12-SDAG-NEXT: s_sub_f16 s2, s3, s2 +; GFX12-SDAG-NEXT: s_delay_alu instid0(SALU_CYCLE_3) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; GFX12-SDAG-NEXT: s_pack_ll_b32_b16 s0, s0, s2 ; GFX12-SDAG-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-SDAG-NEXT: ; return to shader part epilog ; ; GFX12-GISEL-LABEL: s_constained_fsub_v2f16_fpexcept_strict: ; GFX12-GISEL: ; %bb.0: -; GFX12-GISEL-NEXT: v_pk_add_f16 v0, s2, s3 neg_lo:[0,1] neg_hi:[0,1] +; GFX12-GISEL-NEXT: v_pk_add_f16 v0, s0, s1 neg_lo:[0,1] neg_hi:[0,1] ; GFX12-GISEL-NEXT: ; return to shader part epilog %val = call <2 x half> @llvm.experimental.constrained.fsub.v2f16(<2 x half> %x, <2 x half> %y, metadata !"round.tonearest", metadata !"fpexcept.strict") ret <2 x half> %val diff --git a/llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll b/llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll index 099c1b56ee8408..453939fb813d9d 100644 --- a/llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll +++ b/llvm/test/CodeGen/AMDGPU/strict_fsub.f32.ll @@ -236,14 +236,19 @@ define amdgpu_ps float @s_constained_fsub_f32_fpexcept_strict(float inreg %x, fl ; GCN-NEXT: v_sub_f32_e32 v0, s2, v0 ; GCN-NEXT: ; return to shader part epilog ; -; GFX10PLUS-LABEL: s_constained_fsub_f32_fpexcept_strict: -; GFX10PLUS: ; %bb.0: -; GFX10PLUS-NEXT: v_sub_f32_e64 v0, s2, s3 -; GFX10PLUS-NEXT: ; return to shader part epilog +; GFX10-LABEL: s_constained_fsub_f32_fpexcept_strict: +; GFX10: ; %bb.0: +; GFX10-NEXT: v_sub_f32_e64 v0, s2, s3 +; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: s_constained_fsub_f32_fpexcept_strict: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_sub_f32_e64 v0, s0, s1 +; GFX11-NEXT: ; return to shader part epilog ; ; GFX12-LABEL: s_constained_fsub_f32_fpexcept_strict: ; GFX12: ; %bb.0: -; GFX12-NEXT: s_sub_f32 s0, s2, s3 +; GFX12-NEXT: s_sub_f32 s0, s0, s1 ; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_3) ; GFX12-NEXT: v_mov_b32_e32 v0, s0 ; GFX12-NEXT: ; return to shader part epilog @@ -339,6 +344,3 @@ declare <2 x float> @llvm.experimental.constrained.fsub.v2f32(<2 x float>, <2 x declare <3 x float> @llvm.experimental.constrained.fsub.v3f32(<3 x float>, <3 x float>, metadata, metadata) attributes #0 = { strictfp } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GFX12-GISEL: {{.*}} -; GFX12-SDAG: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll b/llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll index 7d636a3dee3679..ec85080c872f61 100644 --- a/llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll +++ b/llvm/test/CodeGen/AMDGPU/strict_fsub.f64.ll @@ -212,12 +212,12 @@ define amdgpu_ps <2 x float> @s_constained_fsub_f64_fpexcept_strict(double inreg ; ; GFX11-SDAG-LABEL: s_constained_fsub_f64_fpexcept_strict: ; GFX11-SDAG: ; %bb.0: -; GFX11-SDAG-NEXT: v_add_f64 v[0:1], s[2:3], -s[4:5] +; GFX11-SDAG-NEXT: v_add_f64 v[0:1], s[0:1], -s[2:3] ; GFX11-SDAG-NEXT: ; return to shader part epilog ; ; GFX11-GISEL-LABEL: s_constained_fsub_f64_fpexcept_strict: ; GFX11-GISEL: ; %bb.0: -; GFX11-GISEL-NEXT: v_add_f64 v[0:1], s[2:3], -s[4:5] +; GFX11-GISEL-NEXT: v_add_f64 v[0:1], s[0:1], -s[2:3] ; GFX11-GISEL-NEXT: v_readfirstlane_b32 s0, v0 ; GFX11-GISEL-NEXT: v_readfirstlane_b32 s1, v1 ; GFX11-GISEL-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v1, s1 diff --git a/llvm/test/CodeGen/AMDGPU/xor3.ll b/llvm/test/CodeGen/AMDGPU/xor3.ll index 3051bffa13cd2a..e2978cb4af5db8 100644 --- a/llvm/test/CodeGen/AMDGPU/xor3.ll +++ b/llvm/test/CodeGen/AMDGPU/xor3.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgpu9.00-amd-mesa3d | FileCheck -check-prefix=GFX9 %s -; RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefix=GFX10 %s -; RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s +; RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefixes=GFX10P,GFX10 %s +; RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX10P,GFX11 %s ; =================================================================================== ; V_XOR3_B32 @@ -14,10 +14,10 @@ define amdgpu_ps float @xor3(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_xor_b32_e32 v0, v0, v2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: xor3: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_xor3_b32 v0, v0, v1, v2 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: xor3: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_xor3_b32 v0, v0, v1, v2 +; GFX10P-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = xor i32 %x, %c %bc = bitcast i32 %result to float @@ -35,6 +35,11 @@ define amdgpu_ps float @xor3_vgpr_b(i32 inreg %a, i32 %b, i32 inreg %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_xor3_b32 v0, s3, s2, v0 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: xor3_vgpr_b: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_xor3_b32 v0, s1, s0, v0 +; GFX11-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = xor i32 %x, %c %bc = bitcast i32 %result to float @@ -48,10 +53,10 @@ define amdgpu_ps float @xor3_vgpr_all2(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_xor_b32_e32 v0, v0, v1 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: xor3_vgpr_all2: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_xor3_b32 v0, v1, v2, v0 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: xor3_vgpr_all2: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_xor3_b32 v0, v1, v2, v0 +; GFX10P-NEXT: ; return to shader part epilog %x = xor i32 %b, %c %result = xor i32 %a, %x %bc = bitcast i32 %result to float @@ -69,6 +74,11 @@ define amdgpu_ps float @xor3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_xor3_b32 v0, s2, v0, v1 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: xor3_vgpr_bc: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_xor3_b32 v0, s0, v0, v1 +; GFX11-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = xor i32 %x, %c %bc = bitcast i32 %result to float @@ -82,10 +92,10 @@ define amdgpu_ps float @xor3_vgpr_const(i32 %a, i32 %b) { ; GFX9-NEXT: v_xor_b32_e32 v0, 16, v0 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: xor3_vgpr_const: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_xor3_b32 v0, v0, v1, 16 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: xor3_vgpr_const: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_xor3_b32 v0, v0, v1, 16 +; GFX10P-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = xor i32 %x, 16 %bc = bitcast i32 %result to float @@ -100,11 +110,11 @@ define amdgpu_ps <2 x float> @xor3_multiuse_outer(i32 %a, i32 %b, i32 %c, i32 %x ; GFX9-NEXT: v_mul_lo_u32 v1, v0, v3 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: xor3_multiuse_outer: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_xor3_b32 v0, v0, v1, v2 -; GFX10-NEXT: v_mul_lo_u32 v1, v0, v3 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: xor3_multiuse_outer: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_xor3_b32 v0, v0, v1, v2 +; GFX10P-NEXT: v_mul_lo_u32 v1, v0, v3 +; GFX10P-NEXT: ; return to shader part epilog %inner = xor i32 %a, %b %outer = xor i32 %inner, %c %x1 = mul i32 %outer, %x @@ -121,11 +131,11 @@ define amdgpu_ps <2 x float> @xor3_multiuse_inner(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_xor_b32_e32 v1, v0, v2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: xor3_multiuse_inner: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1 -; GFX10-NEXT: v_xor_b32_e32 v1, v0, v2 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: xor3_multiuse_inner: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_xor_b32_e32 v0, v0, v1 +; GFX10P-NEXT: v_xor_b32_e32 v1, v0, v2 +; GFX10P-NEXT: ; return to shader part epilog %inner = xor i32 %a, %b %outer = xor i32 %inner, %c %r1 = insertelement <2 x i32> poison, i32 %inner, i32 0 @@ -155,6 +165,15 @@ define amdgpu_ps float @xor3_uniform_vgpr(float inreg %a, float inreg %b, float ; GFX10-NEXT: v_xor_b32_e32 v0, v0, v1 ; GFX10-NEXT: v_xor_b32_e32 v0, v0, v2 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: xor3_uniform_vgpr: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_add_f32_e64 v0, s0, 1.0 +; GFX11-NEXT: v_add_f32_e64 v1, s1, 2.0 +; GFX11-NEXT: v_add_f32_e64 v2, s2, 0x40400000 +; GFX11-NEXT: v_xor_b32_e32 v0, v0, v1 +; GFX11-NEXT: v_xor_b32_e32 v0, v0, v2 +; GFX11-NEXT: ; return to shader part epilog %a1 = fadd float %a, 1.0 %b2 = fadd float %b, 2.0 %c3 = fadd float %c, 3.0 diff --git a/llvm/test/CodeGen/AMDGPU/xor_add.ll b/llvm/test/CodeGen/AMDGPU/xor_add.ll index 7a643091b7d6de..eb436c6bbcbd62 100644 --- a/llvm/test/CodeGen/AMDGPU/xor_add.ll +++ b/llvm/test/CodeGen/AMDGPU/xor_add.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=amdgpu8.03-amd-mesa3d | FileCheck -check-prefix=VI %s ; RUN: llc < %s -mtriple=amdgpu9.00-amd-mesa3d | FileCheck -check-prefix=GFX9 %s -; RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefix=GFX10 %s -; RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s +; RUN: llc < %s -mtriple=amdgpu10.10-amd-mesa3d | FileCheck -check-prefixes=GFX10P,GFX10 %s +; RUN: llc < %s -mtriple=amdgpu11.00-amd-mesa3d -amdgpu-enable-delay-alu=0 | FileCheck -check-prefixes=GFX10P,GFX11 %s ; =================================================================================== ; V_XAD_U32 @@ -20,10 +20,10 @@ define amdgpu_ps float @xor_add(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_xad_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: xor_add: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_xad_u32 v0, v0, v1, v2 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: xor_add: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_xad_u32 v0, v0, v1, v2 +; GFX10P-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -48,6 +48,11 @@ define amdgpu_ps float @xor_add_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_xad_u32 v0, v0, s2, s3 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: xor_add_vgpr_a: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_xad_u32 v0, v0, s0, s1 +; GFX11-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -66,10 +71,10 @@ define amdgpu_ps float @xor_add_vgpr_all(i32 %a, i32 %b, i32 %c) { ; GFX9-NEXT: v_xad_u32 v0, v0, v1, v2 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: xor_add_vgpr_all: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_xad_u32 v0, v0, v1, v2 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: xor_add_vgpr_all: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_xad_u32 v0, v0, v1, v2 +; GFX10P-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -92,6 +97,11 @@ define amdgpu_ps float @xor_add_vgpr_ab(i32 %a, i32 %b, i32 inreg %c) { ; GFX10: ; %bb.0: ; GFX10-NEXT: v_xad_u32 v0, v0, v1, s2 ; GFX10-NEXT: ; return to shader part epilog +; +; GFX11-LABEL: xor_add_vgpr_ab: +; GFX11: ; %bb.0: +; GFX11-NEXT: v_xad_u32 v0, v0, v1, s0 +; GFX11-NEXT: ; return to shader part epilog %x = xor i32 %a, %b %result = add i32 %x, %c %bc = bitcast i32 %result to float @@ -110,10 +120,10 @@ define amdgpu_ps float @xor_add_vgpr_const(i32 %a, i32 %b) { ; GFX9-NEXT: v_xad_u32 v0, v0, 3, v1 ; GFX9-NEXT: ; return to shader part epilog ; -; GFX10-LABEL: xor_add_vgpr_const: -; GFX10: ; %bb.0: -; GFX10-NEXT: v_xad_u32 v0, v0, 3, v1 -; GFX10-NEXT: ; return to shader part epilog +; GFX10P-LABEL: xor_add_vgpr_const: +; GFX10P: ; %bb.0: +; GFX10P-NEXT: v_xad_u32 v0, v0, 3, v1 +; GFX10P-NEXT: ; return to shader part epilog %x = xor i32 %a, 3 %result = add i32 %x, %b %bc = bitcast i32 %result to float From 60c2f3eb1591d43d9dd4e585e46dc039f35b461d Mon Sep 17 00:00:00 2001 From: Michael Kruse Date: Sat, 24 Oct 2026 19:19:27 +0200 Subject: [PATCH 12/31] [runtimes][Fortran] No introspection in bootstrapping build (#234424) In a bootstrapping build, flang is only built for the runtime's build step, but not the configure step. That means the the result of Fortran compiler introspection is unreliable. Don't attempt `check_fortran_builtins_available()` in a bootstrapping configure. One may think that any compiler introspection will just fail as intended if flang is not even available, but https://github.com/llvm/llvm-project/pull/209482#issuecomment-6202154199 describes how it may pass: `fakeflang` just runs the preprocessor (which is sufficient for CMake to detect LLVMFlang), but `check_fortran_builtins_available`'s check is intended to fail during symbol resolution. --- runtimes/cmake/config-Fortran.cmake | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/runtimes/cmake/config-Fortran.cmake b/runtimes/cmake/config-Fortran.cmake index 869e03515e09ca..97433fd8c4c228 100644 --- a/runtimes/cmake/config-Fortran.cmake +++ b/runtimes/cmake/config-Fortran.cmake @@ -190,6 +190,12 @@ if (CMAKE_Fortran_COMPILER) target_link_libraries(fortran-compile-depends INTERFACE flang-rt-mod flang-rt-mod.barrier) set(RUNTIMES_ENABLE_FORTRAN ON) message(STATUS "Fortran support enabled using just-built Flang-RT builtin modules") + elseif (LLVM_TREE_AVAILABLE) + # Bootstrapping build without flang-rt: CMAKE_Fortran_COMPILER is + # necessarily Flang, but must avoid compiler introspection such as + # check_fortran_builtins_available() below. Because flang-rt is needed for + # building other Fortran code, disable Fortran. + message(STATUS "Fortran support disabled: bootstrapping build without LLVM_ENABLE_RUNTIMES=flang-rt") else () # Check whether building modules works, avoid causing the entire build to # fail because of Fortran. The primary situation we want to support here From 625d950b175fe99404e93b5396a3bfe03cf02581 Mon Sep 17 00:00:00 2001 From: Vasileios Porpodas Date: Sat, 24 Oct 2026 10:48:23 -0700 Subject: [PATCH 13/31] [SandboxVec] Remove empty test directory (NFC) (#235015) This removes `Passes/BundleVec/AMDGPU/` as there are no tests left in this directory after https://github.com/llvm/llvm-project/pull/234432 --- .../SandboxVectorizer/Passes/BundleVec/AMDGPU/lit.local.cfg | 2 -- 1 file changed, 2 deletions(-) delete mode 100644 llvm/test/Transforms/SandboxVectorizer/Passes/BundleVec/AMDGPU/lit.local.cfg diff --git a/llvm/test/Transforms/SandboxVectorizer/Passes/BundleVec/AMDGPU/lit.local.cfg b/llvm/test/Transforms/SandboxVectorizer/Passes/BundleVec/AMDGPU/lit.local.cfg deleted file mode 100644 index 7c492428aec761..00000000000000 --- a/llvm/test/Transforms/SandboxVectorizer/Passes/BundleVec/AMDGPU/lit.local.cfg +++ /dev/null @@ -1,2 +0,0 @@ -if not "AMDGPU" in config.root.targets: - config.unsupported = True From 9cf173d541d9d9d5a1f0646e3100962955570b06 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 24 Oct 2026 11:07:59 -0700 Subject: [PATCH 14/31] CodeGen: Consolidate MachinePipeliner controls (#235311) This pass followed the anti-pattern of having a cl::opt in the pass which early returned instead of not adding the pass to the pipeline in the first place. Additionally several targets had their own cl::opts used from the subtarget enablement hook. Consolidate this into one generic control with a subtarget hook to enable the pipeliner, following the example of enable-misched / enableMachineScheduler. Adding the nop pass still had the side effect of running the required analyses which exposed issues. In particular this hides failures in PPC with the defaults. The LiveIntervals dependency would assert if there were unreachable blocks which was possible with the point PPC inserted the pass. Hexagon's hardware loop passes move to the end of addMachineSSAOptimization so they still run before the pipeliner. This preserves the existing target specific opt level checks in the subtarget hook, though that means opt level disablement doesn't get the same benefit. I'm assuming these choices are arbitrary and we can just pick one opt level for all targets in the future. Co-authored-by: Claude Opus 5.5 --- llvm/include/llvm/CodeGen/TargetPassConfig.h | 4 +++ llvm/include/llvm/Passes/CodeGenPassBuilder.h | 4 +++ .../include/llvm/Target/CGPassBuilderOption.h | 1 + llvm/lib/CodeGen/CodeGenOptions.td | 2 ++ llvm/lib/CodeGen/MachinePipeliner.cpp | 7 ----- llvm/lib/CodeGen/TargetPassConfig.cpp | 5 +++ llvm/lib/Passes/CodeGenPassBuilder.cpp | 8 +++++ llvm/lib/Target/AArch64/AArch64Options.td | 2 -- .../Target/AArch64/AArch64TargetMachine.cpp | 2 -- .../lib/Target/AMDGPU/AMDGPUTargetMachine.cpp | 9 ------ llvm/lib/Target/ARM/ARMTargetMachine.cpp | 6 ++-- .../Target/Hexagon/HexagonTargetMachine.cpp | 31 ++++++++++++------- llvm/lib/Target/PowerPC/PPCSubtarget.cpp | 7 +---- llvm/lib/Target/PowerPC/PPCTargetMachine.cpp | 3 -- llvm/lib/Target/RISCV/RISCVOptions.td | 2 -- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 4 --- .../CodeGen/AArch64/sms-acceptable-loop1.mir | 2 +- .../CodeGen/AArch64/sms-acceptable-loop2.mir | 2 +- .../CodeGen/AArch64/sms-acceptable-loop3.mir | 2 +- .../CodeGen/AArch64/sms-acceptable-loop4.mir | 2 +- .../sms-loop-carried-fp-exceptions1.mir | 2 +- .../sms-loop-carried-fp-exceptions2.mir | 2 +- llvm/test/CodeGen/AArch64/sms-mve1.mir | 2 +- llvm/test/CodeGen/AArch64/sms-mve10.mir | 2 +- llvm/test/CodeGen/AArch64/sms-mve11.mir | 2 +- llvm/test/CodeGen/AArch64/sms-mve12.mir | 2 +- llvm/test/CodeGen/AArch64/sms-mve2.mir | 2 +- llvm/test/CodeGen/AArch64/sms-mve3.mir | 2 +- llvm/test/CodeGen/AArch64/sms-mve4.mir | 2 +- llvm/test/CodeGen/AArch64/sms-mve5.mir | 2 +- llvm/test/CodeGen/AArch64/sms-mve6.mir | 2 +- llvm/test/CodeGen/AArch64/sms-mve7.mir | 2 +- llvm/test/CodeGen/AArch64/sms-mve8.mir | 2 +- llvm/test/CodeGen/AArch64/sms-mve9.mir | 2 +- .../AArch64/sms-order-physreg-deps.mir | 2 +- llvm/test/CodeGen/AArch64/sms-regpress.mir | 2 +- .../AArch64/sms-unacceptable-loop1.mir | 2 +- .../AArch64/sms-unacceptable-loop2.mir | 2 +- .../AArch64/sms-unacceptable-loop3.mir | 2 +- .../CodeGen/AArch64/sms-unpipeline-insts1.mir | 2 +- .../CodeGen/AArch64/sms-unpipeline-insts2.mir | 2 +- .../CodeGen/AArch64/sms-unpipeline-insts3.mir | 2 +- .../AMDGPU/swp-amdgpu-pipeline-max-mii.ll | 4 +-- .../AMDGPU/swp-amdgpu-pipeline-minimal.ll | 4 +-- .../swp-amdgpu-pipeline-neg-multi-bb.ll | 2 +- .../swp-amdgpu-pipeline-resmii-issue-bound.ll | 2 +- .../AMDGPU/swp-amdgpu-pipeline-resmii-mfma.ll | 2 +- .../swp-amdgpu-pipeline-scalar-accumulate.ll | 2 +- .../swp-amdgpu-pipeline-vector-accumulate.ll | 2 +- llvm/test/CodeGen/PowerPC/O3-pipeline.ll | 7 ----- llvm/test/CodeGen/PowerPC/sms-cpy-1.ll | 2 +- llvm/test/CodeGen/PowerPC/sms-grp-order.ll | 2 +- llvm/test/CodeGen/PowerPC/sms-iterator.ll | 2 +- .../test/CodeGen/PowerPC/sms-large-stages.mir | 2 +- llvm/test/CodeGen/PowerPC/sms-phi-1.ll | 2 +- llvm/test/CodeGen/PowerPC/sms-phi-2.ll | 2 +- llvm/test/CodeGen/PowerPC/sms-phi-3.ll | 2 +- llvm/test/CodeGen/PowerPC/sms-phi-5.ll | 2 +- llvm/test/CodeGen/PowerPC/sms-phi.ll | 2 +- llvm/test/CodeGen/PowerPC/sms-recmii.ll | 2 +- llvm/test/CodeGen/PowerPC/sms-regpress.mir | 2 +- llvm/test/CodeGen/PowerPC/sms-remark.ll | 6 ++-- llvm/test/CodeGen/PowerPC/sms-simple.ll | 2 +- .../CodeGen/PowerPC/sms-store-dependence.ll | 2 +- llvm/test/CodeGen/RISCV/machine-pipeliner.ll | 4 +-- 65 files changed, 100 insertions(+), 110 deletions(-) diff --git a/llvm/include/llvm/CodeGen/TargetPassConfig.h b/llvm/include/llvm/CodeGen/TargetPassConfig.h index fe252045070cad..f19ba86241601a 100644 --- a/llvm/include/llvm/CodeGen/TargetPassConfig.h +++ b/llvm/include/llvm/CodeGen/TargetPassConfig.h @@ -400,6 +400,10 @@ class LLVM_ABI TargetPassConfig : public ImmutablePass { /// immediately before register allocation. virtual void addPreRegAlloc() { } + /// Return true if the MachinePipeliner should run before addPreRegAlloc by + /// default. -enable-pipeliner overrides this. + virtual bool isMachinePipelinerEnabled() const { return false; } + /// createTargetRegisterAllocator - Create the register allocator pass for /// this target at the current optimization level. virtual FunctionPass *createTargetRegisterAllocator(bool Optimized); diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 363d7769b00621..84a4048db0b5d1 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -210,6 +210,10 @@ class LLVM_ABI CodeGenPassBuilder { /// immediately before register allocation. virtual void addPreRegAlloc(PassManagerWrapper &PMW) {} + /// Return true if the MachinePipeliner should run before addPreRegAlloc by + /// default. -enable-pipeliner overrides this. + virtual bool isMachinePipelinerEnabled() const { return false; } + /// addPreRewrite - Add passes to the optimized register allocation pipeline /// after register allocation is complete, but before virtual registers are /// rewritten to physical registers. diff --git a/llvm/include/llvm/Target/CGPassBuilderOption.h b/llvm/include/llvm/Target/CGPassBuilderOption.h index 5458449e32d82f..69c94c772d2adb 100644 --- a/llvm/include/llvm/Target/CGPassBuilderOption.h +++ b/llvm/include/llvm/Target/CGPassBuilderOption.h @@ -91,6 +91,7 @@ struct CGPassBuilderOption { cl::boolOrDefault EnableFastISelOption = cl::boolOrDefault::BOU_UNSET; cl::boolOrDefault EnableRegAllocFastTied = cl::boolOrDefault::BOU_UNSET; + cl::boolOrDefault EnableMachinePipeliner = cl::boolOrDefault::BOU_UNSET; cl::boolOrDefault EnableGlobalISelOption = cl::boolOrDefault::BOU_UNSET; cl::boolOrDefault DebugifyAndStripAll = cl::boolOrDefault::BOU_UNSET; cl::boolOrDefault DebugifyCheckAndStripAll = cl::boolOrDefault::BOU_UNSET; diff --git a/llvm/lib/CodeGen/CodeGenOptions.td b/llvm/lib/CodeGen/CodeGenOptions.td index 21ba8450ca3947..46f33fa137c2d5 100644 --- a/llvm/lib/CodeGen/CodeGenOptions.td +++ b/llvm/lib/CodeGen/CodeGenOptions.td @@ -153,6 +153,8 @@ defm : BoolField<"enable-implicit-null-checks", "false", "Fold null checks into faulting memory operations">; defm : OptionalBoolField<"enable-ipra", "Enable interprocedural register allocation to reduce load/store at procedure calls">; +defm : OptionalBoolField<"enable-pipeliner", + "Enable the MachinePipeliner (overrides the target's default)">; defm : EnumField<"function-splitting", "std::optional", "std::nullopt", "none,bbsections,all", ["FunctionSplittingMode::None", "FunctionSplittingMode::BBSectionsOnly", diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index 9b9392fb8c3255..dd0dd264785511 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -113,10 +113,6 @@ STATISTIC(NumFailZeroStage, "Pipeliner abort due to zero stage"); STATISTIC(NumFailLargeMaxStage, "Pipeliner abort due to too many stages"); STATISTIC(NumFailTooManyStores, "Pipeliner abort due to too many stores"); -/// A command line option to turn software pipelining on or off. -static cl::opt EnableSWP("enable-pipeliner", cl::Hidden, cl::init(true), - cl::desc("Enable Software Pipelining")); - /// A command line option to enable SWP at -Os. static cl::opt EnableSWPOptSize("enable-pipeliner-opt-size", cl::desc("Enable SWP at Os."), cl::Hidden, @@ -433,9 +429,6 @@ static bool runMachinePipeliner( function_ref GetLIS, function_ref GetAA, function_ref GetORE, function_ref GetRCI) { - if (!EnableSWP) - return false; - if (MF.getFunction().getAttributes().hasFnAttr(Attribute::OptimizeForSize) && !EnableSWPOptSize.getPosition()) return false; diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index 30b6615eedeb8c..536dcd5159115c 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -335,6 +335,7 @@ CGPassBuilderOption llvm::getCGPassBuilderOption(const TargetMachine &TM) { Opt.EnableIPRA = Opts.enable_ipra == BoolOrDefault::True; Opt.EnableFastISelOption = toBoolOrDefault(Opts.fast_isel); Opt.EnableRegAllocFastTied = toBoolOrDefault(Opts.regalloc_fast_tied); + Opt.EnableMachinePipeliner = toBoolOrDefault(Opts.enable_pipeliner); Opt.EnableGlobalISelOption = toBoolOrDefault(Opts.global_isel); Opt.VerifyMachineCode = computeMachineVerifierMode( Opts, valueOr(Opts.verify_machineinstrs, false)); @@ -997,6 +998,10 @@ void TargetPassConfig::addMachinePasses() { if (TM->Options.EnableIPRA) addPass(createRegUsageInfoPropPass()); + if (getOptLevel() != CodeGenOptLevel::None && + valueOr(getOpts(*TM).enable_pipeliner, isMachinePipelinerEnabled())) + addPass(&MachinePipelinerID); + // Run pre-ra passes. addPreRegAlloc(); diff --git a/llvm/lib/Passes/CodeGenPassBuilder.cpp b/llvm/lib/Passes/CodeGenPassBuilder.cpp index 7f03546944fc16..bbfef2e341633f 100644 --- a/llvm/lib/Passes/CodeGenPassBuilder.cpp +++ b/llvm/lib/Passes/CodeGenPassBuilder.cpp @@ -55,6 +55,7 @@ #include "llvm/CodeGen/MachineLateInstrsCleanup.h" #include "llvm/CodeGen/MachineModuleInfo.h" #include "llvm/CodeGen/MachinePassManager.h" +#include "llvm/CodeGen/MachinePipeliner.h" #include "llvm/CodeGen/MachineScheduler.h" #include "llvm/CodeGen/MachineSink.h" #include "llvm/CodeGen/MachineVerifier.h" @@ -632,6 +633,13 @@ Error CodeGenPassBuilder::addMachinePasses(PassManagerWrapper &PMW) { PMW, /*Force=*/true); addMachineFunctionPass(RegUsageInfoPropagationPass(), PMW); } + + if (getOptLevel() != CodeGenOptLevel::None && + (Opt.EnableMachinePipeliner == cl::boolOrDefault::BOU_UNSET + ? isMachinePipelinerEnabled() + : Opt.EnableMachinePipeliner == cl::boolOrDefault::BOU_TRUE)) + addMachineFunctionPass(MachinePipelinerPass(), PMW); + // Run pre-ra passes. addPreRegAlloc(PMW); diff --git a/llvm/lib/Target/AArch64/AArch64Options.td b/llvm/lib/Target/AArch64/AArch64Options.td index 681c751d4dc60f..3cfea0ad209fc4 100644 --- a/llvm/lib/Target/AArch64/AArch64Options.td +++ b/llvm/lib/Target/AArch64/AArch64Options.td @@ -279,8 +279,6 @@ defm : BoolField<"aarch64-enable-loop-data-prefetch", "true", "Enable the loop data prefetch pass">; defm : BoolField<"aarch64-enable-mcr", "true", "Enable the machine combiner pass">; -defm : BoolField<"aarch64-enable-pipeliner", "false", - "Enable Machine Pipeliner for AArch64">; defm : BoolField<"aarch64-enable-predicate-as-counter-loop-rewrites", "true", "Enable rewriting loops with wide loop-carried masks to use predicate-as-counter">; defm : BoolField<"aarch64-enable-promote-const", "true", diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp index 75285be28e71d0..e7f4c740ad3189 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -705,8 +705,6 @@ void AArch64PassConfig::addPreRegAlloc() { // be register coalescer friendly. addPass(&PeepholeOptimizerLegacyID); } - if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_pipeliner) - addPass(&MachinePipelinerID); } void AArch64PassConfig::addPostRewrite() { diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index 53130fae3c9980..117b5c52a2b5e3 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -665,11 +665,6 @@ static cl::opt EnableUniformIntrinsicCombine( cl::desc("Enable/Disable the Uniform Intrinsic Combine Pass"), cl::init(true), cl::Hidden); -static cl::opt - EnableMachinePipeliner("amdgpu-enable-pipeliner", - cl::desc("Enable Machine Pipeliner for AMDGCN"), - cl::init(false), cl::Hidden); - static cl::opt UseSSAMachineScheduler("amdgpu-use-ssa-machine-scheduler", cl::desc("Use the machine scheduler in SSA mode."), @@ -1848,8 +1843,6 @@ void GCNPassConfig::addFastRegAlloc() { void GCNPassConfig::addPreRegAlloc() { if (getOptLevel() != CodeGenOptLevel::None) addPass(&AMDGPUPrepareAGPRAllocLegacyID); - if (getOptLevel() >= CodeGenOptLevel::Default && EnableMachinePipeliner) - addPass(&MachinePipelinerID); } void GCNPassConfig::addOptimizedRegAlloc() { @@ -2710,8 +2703,6 @@ Error AMDGPUCodeGenPassBuilder::addOptimizedRegAlloc(PassManagerWrapper &PMW) { void AMDGPUCodeGenPassBuilder::addPreRegAlloc(PassManagerWrapper &PMW) { if (getOptLevel() != CodeGenOptLevel::None) addMachineFunctionPass(AMDGPUPrepareAGPRAllocPass(), PMW); - if (getOptLevel() >= CodeGenOptLevel::Default && EnableMachinePipeliner) - addMachineFunctionPass(MachinePipelinerPass(), PMW); } Expected AMDGPUCodeGenPassBuilder::addRegAssignAndRewriteOptimized( diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp index f2ff41c634cd24..337fd447d7f5e7 100644 --- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp +++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp @@ -345,6 +345,9 @@ class ARMPassConfig : public TargetPassConfig { bool addRegBankSelect() override; bool addGlobalInstructionSelect() override; void addPreRegAlloc() override; + bool isMachinePipelinerEnabled() const override { + return getOptLevel() == CodeGenOptLevel::Aggressive; + } void addPreSched2() override; void addPreEmitPass() override; void addPreEmitPass2() override; @@ -492,9 +495,6 @@ bool ARMPassConfig::addGlobalInstructionSelect() { void ARMPassConfig::addPreRegAlloc() { if (getOptLevel() != CodeGenOptLevel::None) { - if (getOptLevel() == CodeGenOptLevel::Aggressive) - addPass(&MachinePipelinerID); - addPass(createMVETPAndVPTOptimisationsPass()); addPass(createMLxExpansionPass()); diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index 42418227e7c13c..e37f62fc72a1e5 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -371,7 +371,11 @@ class HexagonPassConfig : public TargetPassConfig { void addIRPasses() override; bool addInstSelector() override; bool addILPOpts() override; + void addMachineSSAOptimization() override; void addPreRegAlloc() override; + bool isMachinePipelinerEnabled() const override { + return getOptLevel() >= CodeGenOptLevel::Default; + } void addPostRegAlloc() override; void addPreSched2() override; void addPreEmitPass() override; @@ -475,27 +479,30 @@ bool HexagonPassConfig::addILPOpts() { return true; } +void HexagonPassConfig::addMachineSSAOptimization() { + TargetPassConfig::addMachineSSAOptimization(); + + if (EnableCExtOpt) + addPass(createHexagonConstExtenders()); + if (!DisableStoreWidening) + addPass(createHexagonStoreWidening()); + if (!DisableLoadWidening) + addPass(createHexagonLoadWidening()); + if (EnableGenMemAbs) + addPass(createHexagonGenMemAbsolute()); + if (!DisableHardwareLoops) + addPass(createHexagonHardwareLoops()); +} + void HexagonPassConfig::addPreRegAlloc() { if (getOptLevel() != CodeGenOptLevel::None) { - if (EnableCExtOpt) - addPass(createHexagonConstExtenders()); if (EnableExpandCondsets) insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID); if (EnableCopyHoist) insertPass(&RegisterCoalescerID, &HexagonCopyHoistingID); if (EnableTfrCleanup) insertPass(&VirtRegRewriterID, &HexagonTfrCleanupID); - if (!DisableStoreWidening) - addPass(createHexagonStoreWidening()); - if (!DisableLoadWidening) - addPass(createHexagonLoadWidening()); - if (EnableGenMemAbs) - addPass(createHexagonGenMemAbsolute()); - if (!DisableHardwareLoops) - addPass(createHexagonHardwareLoops()); } - if (TM->getOptLevel() >= CodeGenOptLevel::Default) - addPass(&MachinePipelinerID); addPass(createHexagonHVXSaveRemark()); } diff --git a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp index 2dfb67ff4c33db..f53f9e99a0927f 100644 --- a/llvm/lib/Target/PowerPC/PPCSubtarget.cpp +++ b/llvm/lib/Target/PowerPC/PPCSubtarget.cpp @@ -38,11 +38,6 @@ using namespace llvm; #define GET_SUBTARGETINFO_CTOR #include "PPCGenSubtargetInfo.inc" -static cl::opt - EnableMachinePipeliner("ppc-enable-pipeliner", - cl::desc("Enable Machine Pipeliner for PPC"), - cl::init(false), cl::Hidden); - PPCSubtarget &PPCSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef TuneCPU, StringRef FS) { @@ -154,7 +149,7 @@ void PPCSubtarget::initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, bool PPCSubtarget::enableMachineScheduler() const { return true; } bool PPCSubtarget::enableMachinePipeliner() const { - return getSchedModel().hasInstrSchedModel() && EnableMachinePipeliner; + return getSchedModel().hasInstrSchedModel(); } bool PPCSubtarget::useDFAforSMS() const { return false; } diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp index 8184d67fbecad8..b79f82134886ed 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp +++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.cpp @@ -528,9 +528,6 @@ void PPCPassConfig::addPreRegAlloc() { } if (EnableExtraTOCRegDeps) addPass(createPPCTOCRegDepsPass()); - - if (getOptLevel() != CodeGenOptLevel::None) - addPass(&MachinePipelinerID); } void PPCPassConfig::addPreSched2() { diff --git a/llvm/lib/Target/RISCV/RISCVOptions.td b/llvm/lib/Target/RISCV/RISCVOptions.td index 410c84e9fc2ac6..f8503a6cc37af2 100644 --- a/llvm/lib/Target/RISCV/RISCVOptions.td +++ b/llvm/lib/Target/RISCV/RISCVOptions.td @@ -103,8 +103,6 @@ defm : BoolField<"riscv-enable-loop-data-prefetch", "true", "Enable the loop data prefetch pass">; defm : BoolField<"riscv-enable-machine-combiner", "true", "Enable the machine combiner pass">; -defm : BoolField<"riscv-enable-pipeliner", "false", - "Enable Machine Pipeliner for RISC-V">; defm : BoolField<"riscv-enable-sink-fold", "true", "Enable sinking and folding of instruction copies">; defm : BoolField<"riscv-select-opt", "true", diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 1100e6ebfa304c..ea0721703c8900 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -576,10 +576,6 @@ void RISCVPassConfig::addPreRegAlloc() { addPass(createRISCVInsertReadWriteCSRPass()); addPass(createRISCVInsertWriteVXRMPass()); addPass(createRISCVLandingPadSetupPass()); - - if (TM->getOptLevel() != CodeGenOptLevel::None && CLOpts.enable_pipeliner) - addPass(&MachinePipelinerID); - addPass(createRISCVVMV0EliminationPass()); } diff --git a/llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir b/llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir index 7f28610a312c5d..ea1a9d5638912a 100644 --- a/llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir +++ b/llvm/test/CodeGen/AArch64/sms-acceptable-loop1.mir @@ -1,4 +1,4 @@ -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -debug-only=pipeliner 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -debug-only=pipeliner 2>&1 | FileCheck %s # REQUIRES: asserts # An acceptable loop by pipeliner: TBB == ExitBB, FBB == LoopBB, Branch with NZCV flags diff --git a/llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir b/llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir index 84fe0f6b032dc2..3760b7cbbe0c3e 100644 --- a/llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir +++ b/llvm/test/CodeGen/AArch64/sms-acceptable-loop2.mir @@ -1,4 +1,4 @@ -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -debug-only=pipeliner 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -debug-only=pipeliner 2>&1 | FileCheck %s # REQUIRES: asserts # An acceptable loop by pipeliner: TBB == LoopBB, FBB == ExitBB, Branch with NZCV flags diff --git a/llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir b/llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir index 7a88bb1363d464..fbcf76dbf44e5c 100644 --- a/llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir +++ b/llvm/test/CodeGen/AArch64/sms-acceptable-loop3.mir @@ -1,4 +1,4 @@ -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-enable-copytophi=0 -debug-only=pipeliner 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-enable-copytophi=0 -debug-only=pipeliner 2>&1 | FileCheck %s # REQUIRES: asserts # Compare and branch instructions are not supported now. diff --git a/llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir b/llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir index 1c0e1cc5aa41f6..bae136986be363 100644 --- a/llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir +++ b/llvm/test/CodeGen/AArch64/sms-acceptable-loop4.mir @@ -1,4 +1,4 @@ -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-enable-copytophi=0 -debug-only=pipeliner 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-enable-copytophi=0 -debug-only=pipeliner 2>&1 | FileCheck %s # REQUIRES: asserts # Compare and branch instructions are not supported now. diff --git a/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir b/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir index 4d3552a056df5a..7244a5395c3df3 100644 --- a/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir +++ b/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions1.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64 -run-pass=pipeliner -debug-only=pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg %s -o /dev/null 2>&1 | FileCheck %s +# RUN: llc -mtriple=aarch64 -run-pass=pipeliner -debug-only=pipeliner -enable-pipeliner -pipeliner-mve-cg %s -o /dev/null 2>&1 | FileCheck %s # REQUIRES: asserts # Test a case where fenv is enabled, there are instructions that may raise a diff --git a/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions2.mir b/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions2.mir index b7bda43a75aa19..b326aad5f4c335 100644 --- a/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions2.mir +++ b/llvm/test/CodeGen/AArch64/sms-loop-carried-fp-exceptions2.mir @@ -1,4 +1,4 @@ -# RUN: llc -mtriple=aarch64 -run-pass=pipeliner -debug-only=pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg %s -o /dev/null 2>&1 | FileCheck %s +# RUN: llc -mtriple=aarch64 -run-pass=pipeliner -debug-only=pipeliner -enable-pipeliner -pipeliner-mve-cg %s -o /dev/null 2>&1 | FileCheck %s # REQUIRES: asserts # Test a case where fenv is enabled, there are instructions that may raise a diff --git a/llvm/test/CodeGen/AArch64/sms-mve1.mir b/llvm/test/CodeGen/AArch64/sms-mve1.mir index c7f187c807eadb..2beca99f3dcdd8 100644 --- a/llvm/test/CodeGen/AArch64/sms-mve1.mir +++ b/llvm/test/CodeGen/AArch64/sms-mve1.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s # test pipeliner code genearation by MVE algorithm # #stages: 2, unroll count: 3 diff --git a/llvm/test/CodeGen/AArch64/sms-mve10.mir b/llvm/test/CodeGen/AArch64/sms-mve10.mir index f94ad7c95bc142..c15231bfab09a2 100644 --- a/llvm/test/CodeGen/AArch64/sms-mve10.mir +++ b/llvm/test/CodeGen/AArch64/sms-mve10.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s # test pipeliner code genearation by MVE algorithm # same as sms-mve1.mir except for the order of the operands diff --git a/llvm/test/CodeGen/AArch64/sms-mve11.mir b/llvm/test/CodeGen/AArch64/sms-mve11.mir index ab8cff858c2e6e..a5599a63bc92e2 100644 --- a/llvm/test/CodeGen/AArch64/sms-mve11.mir +++ b/llvm/test/CodeGen/AArch64/sms-mve11.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s # test pipeliner code genearation by MVE algorithm # counter increment/compare instruction with immediate operand diff --git a/llvm/test/CodeGen/AArch64/sms-mve12.mir b/llvm/test/CodeGen/AArch64/sms-mve12.mir index 6fce7b5fb9a8ec..143b703165dabc 100644 --- a/llvm/test/CodeGen/AArch64/sms-mve12.mir +++ b/llvm/test/CodeGen/AArch64/sms-mve12.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-v1 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-v1 2>&1 | FileCheck %s # test pipeliner code genearation by MVE algorithm # the compare instruction is whilexx diff --git a/llvm/test/CodeGen/AArch64/sms-mve2.mir b/llvm/test/CodeGen/AArch64/sms-mve2.mir index 103f3741969776..283c3f57381fbe 100644 --- a/llvm/test/CodeGen/AArch64/sms-mve2.mir +++ b/llvm/test/CodeGen/AArch64/sms-mve2.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=4 -mcpu=neoverse-n1 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=4 -mcpu=neoverse-n1 2>&1 | FileCheck %s # test pipeliner code genearation by MVE algorithm # #stages: 2, unroll count: 2 diff --git a/llvm/test/CodeGen/AArch64/sms-mve3.mir b/llvm/test/CodeGen/AArch64/sms-mve3.mir index 017383b46be0cc..321c5d2e15cfaf 100644 --- a/llvm/test/CodeGen/AArch64/sms-mve3.mir +++ b/llvm/test/CodeGen/AArch64/sms-mve3.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s # test pipeliner code genearation by MVE algorithm # #stages: 2, unroll count: 1 diff --git a/llvm/test/CodeGen/AArch64/sms-mve4.mir b/llvm/test/CodeGen/AArch64/sms-mve4.mir index 203ce6ddfd2ecb..f06a7384fb5efc 100644 --- a/llvm/test/CodeGen/AArch64/sms-mve4.mir +++ b/llvm/test/CodeGen/AArch64/sms-mve4.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s # test pipeliner code genearation by MVE algorithm # no dedicated exit diff --git a/llvm/test/CodeGen/AArch64/sms-mve5.mir b/llvm/test/CodeGen/AArch64/sms-mve5.mir index 4795df70c07a48..a0109de9fc8b8e 100644 --- a/llvm/test/CodeGen/AArch64/sms-mve5.mir +++ b/llvm/test/CodeGen/AArch64/sms-mve5.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s # test pipeliner code genearation by MVE algorithm # exit loop when condition holds diff --git a/llvm/test/CodeGen/AArch64/sms-mve6.mir b/llvm/test/CodeGen/AArch64/sms-mve6.mir index 527e9e9d09dfc9..41b82fad029f76 100644 --- a/llvm/test/CodeGen/AArch64/sms-mve6.mir +++ b/llvm/test/CodeGen/AArch64/sms-mve6.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s # test pipeliner code genearation by MVE algorithm # #stages: 2, unroll count: 3 diff --git a/llvm/test/CodeGen/AArch64/sms-mve7.mir b/llvm/test/CodeGen/AArch64/sms-mve7.mir index 3b3d0ea09eaf06..c626aaa5636b86 100644 --- a/llvm/test/CodeGen/AArch64/sms-mve7.mir +++ b/llvm/test/CodeGen/AArch64/sms-mve7.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s # test pipeliner code genearation by MVE algorithm # compare instruction also updates the counter diff --git a/llvm/test/CodeGen/AArch64/sms-mve8.mir b/llvm/test/CodeGen/AArch64/sms-mve8.mir index c1ea6defac1fba..6e84bfde385e99 100644 --- a/llvm/test/CodeGen/AArch64/sms-mve8.mir +++ b/llvm/test/CodeGen/AArch64/sms-mve8.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s # test pipeliner code genearation by MVE algorithm # compare instruction also updates the counter diff --git a/llvm/test/CodeGen/AArch64/sms-mve9.mir b/llvm/test/CodeGen/AArch64/sms-mve9.mir index 469a9ecfff8ee1..15ad2e61649742 100644 --- a/llvm/test/CodeGen/AArch64/sms-mve9.mir +++ b/llvm/test/CodeGen/AArch64/sms-mve9.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-mve-cg -pipeliner-force-ii=3 -mcpu=neoverse-n1 2>&1 | FileCheck %s # test pipeliner code genearation by MVE algorithm # COPY instructions exist diff --git a/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir b/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir index 5eb174c433b8a8..7d7d4c56aa1b8c 100644 --- a/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir +++ b/llvm/test/CodeGen/AArch64/sms-order-physreg-deps.mir @@ -1,4 +1,4 @@ -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -mcpu=a64fx -aarch64-enable-pipeliner -pipeliner-max-mii=100 -pipeliner-enable-copytophi=0 -debug-only=pipeliner -run-pass=pipeliner 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -mcpu=a64fx -enable-pipeliner -pipeliner-max-mii=100 -pipeliner-enable-copytophi=0 -debug-only=pipeliner -run-pass=pipeliner 2>&1 | FileCheck %s # REQUIRES: asserts diff --git a/llvm/test/CodeGen/AArch64/sms-regpress.mir b/llvm/test/CodeGen/AArch64/sms-regpress.mir index 0e126ccf87cbeb..ac540e1c30e1fe 100644 --- a/llvm/test/CodeGen/AArch64/sms-regpress.mir +++ b/llvm/test/CodeGen/AArch64/sms-regpress.mir @@ -1,4 +1,4 @@ -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-max-mii=40 -pipeliner-register-pressure -pipeliner-ii-search-range=30 -debug-only=pipeliner 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-max-mii=40 -pipeliner-register-pressure -pipeliner-ii-search-range=30 -debug-only=pipeliner 2>&1 | FileCheck %s # REQUIRES: asserts diff --git a/llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir b/llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir index 8a9ccee3565afe..bfbc5843a5b21c 100644 --- a/llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir +++ b/llvm/test/CodeGen/AArch64/sms-unacceptable-loop1.mir @@ -1,4 +1,4 @@ -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -debug-only=pipeliner 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -debug-only=pipeliner 2>&1 | FileCheck %s # REQUIRES: asserts # An unacceptable loop by pipeliner: No exits diff --git a/llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir b/llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir index 2b7d78b1d3daf9..66edfb1894dbe7 100644 --- a/llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir +++ b/llvm/test/CodeGen/AArch64/sms-unacceptable-loop2.mir @@ -1,4 +1,4 @@ -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-enable-copytophi=0 -debug-only=pipeliner 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-enable-copytophi=0 -debug-only=pipeliner 2>&1 | FileCheck %s # REQUIRES: asserts # An unacceptable loop by pipeliner: The operand of the compare and branch is not defined in the loop diff --git a/llvm/test/CodeGen/AArch64/sms-unacceptable-loop3.mir b/llvm/test/CodeGen/AArch64/sms-unacceptable-loop3.mir index e6d86859a41b95..2c728fb5800fed 100644 --- a/llvm/test/CodeGen/AArch64/sms-unacceptable-loop3.mir +++ b/llvm/test/CodeGen/AArch64/sms-unacceptable-loop3.mir @@ -1,4 +1,4 @@ -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -debug-only=pipeliner 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -debug-only=pipeliner 2>&1 | FileCheck %s # REQUIRES: asserts # unacceptable loops by pipeliner diff --git a/llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir b/llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir index 769fc21266b09e..905ee8bf4a7978 100644 --- a/llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir +++ b/llvm/test/CodeGen/AArch64/sms-unpipeline-insts1.mir @@ -1,4 +1,4 @@ -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -mcpu=neoverse-n1 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -debug-only=pipeliner 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -mcpu=neoverse-n1 -o - %s -run-pass pipeliner -enable-pipeliner -debug-only=pipeliner 2>&1 | FileCheck %s # REQUIRES: asserts # Check that instructions referencing NZCV are not pipelined diff --git a/llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir b/llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir index d40d28e0e47e6d..5564a9942384fa 100644 --- a/llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir +++ b/llvm/test/CodeGen/AArch64/sms-unpipeline-insts2.mir @@ -1,4 +1,4 @@ -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -aarch64-enable-pipeliner -pipeliner-enable-copytophi=0 -debug-only=pipeliner 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -o - %s -run-pass pipeliner -enable-pipeliner -pipeliner-enable-copytophi=0 -debug-only=pipeliner 2>&1 | FileCheck %s # REQUIRES: asserts # Compare and branch instructions are not supported now. diff --git a/llvm/test/CodeGen/AArch64/sms-unpipeline-insts3.mir b/llvm/test/CodeGen/AArch64/sms-unpipeline-insts3.mir index 0b1dcecba03c44..1aa5ca47ec5d7d 100644 --- a/llvm/test/CodeGen/AArch64/sms-unpipeline-insts3.mir +++ b/llvm/test/CodeGen/AArch64/sms-unpipeline-insts3.mir @@ -1,4 +1,4 @@ -# RUN: llc --verify-machineinstrs -mtriple=aarch64 -run-pass=pipeliner -o - %s -aarch64-enable-pipeliner -pipeliner-enable-copytophi=1 +# RUN: llc --verify-machineinstrs -mtriple=aarch64 -run-pass=pipeliner -o - %s -enable-pipeliner -pipeliner-enable-copytophi=1 --- | target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32" diff --git a/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-max-mii.ll b/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-max-mii.ll index f00a50d1d429eb..7aa54985cb6052 100644 --- a/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-max-mii.ll +++ b/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-max-mii.ll @@ -1,5 +1,5 @@ -; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -amdgpu-enable-pipeliner -pass-remarks-analysis=pipeliner %s -filetype=null 2>&1 | FileCheck %s --check-prefix=DEFAULT -; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -amdgpu-enable-pipeliner -pipeliner-max-mii=64 -pass-remarks-analysis=pipeliner %s -filetype=null 2>&1 | FileCheck %s --check-prefix=RAISED +; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -enable-pipeliner -pass-remarks-analysis=pipeliner %s -filetype=null 2>&1 | FileCheck %s --check-prefix=DEFAULT +; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -enable-pipeliner -pipeliner-max-mii=64 -pass-remarks-analysis=pipeliner %s -filetype=null 2>&1 | FileCheck %s --check-prefix=RAISED ; This loop's MII is 32: two independent accumulators each issue one MFMA per ; iteration, and each MFMA holds the XDL pipe for 16 cycles (res=32). That diff --git a/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-minimal.ll b/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-minimal.ll index 3ce8d528b34b15..9763bc82181350 100644 --- a/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-minimal.ll +++ b/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-minimal.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 ; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-UNPIPELINED -; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -amdgpu-enable-pipeliner %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-PIPELINED -; Minimal loop: software-pipelined only under -amdgpu-enable-pipeliner. +; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -enable-pipeliner %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-PIPELINED +; Minimal loop: software-pipelined only under -enable-pipeliner. define amdgpu_kernel void @swp_amdgpu_pipeline_minimal(i1 %arg) { ; CHECK-UNPIPELINED-LABEL: swp_amdgpu_pipeline_minimal: diff --git a/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-neg-multi-bb.ll b/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-neg-multi-bb.ll index da8cb965b49a00..be939216685f11 100644 --- a/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-neg-multi-bb.ll +++ b/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-neg-multi-bb.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -amdgpu-enable-pipeliner -pass-remarks-analysis=pipeliner %s -filetype=null 2>&1 | FileCheck %s +; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -enable-pipeliner -pass-remarks-analysis=pipeliner %s -filetype=null 2>&1 | FileCheck %s ; Reject a loop whose body lowers to more than one basic block: the runtime-masked ; load is scalarized into cond.load blocks, so the pipeliner bails (single-block only). ; CHECK: Not a single basic block diff --git a/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-resmii-issue-bound.ll b/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-resmii-issue-bound.ll index 1fe846e7dc63cc..d8e5a8f839ba6f 100644 --- a/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-resmii-issue-bound.ll +++ b/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-resmii-issue-bound.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -amdgpu-enable-pipeliner -debug-only=pipeliner %s -filetype=null 2>&1 | FileCheck %s +; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -enable-pipeliner -debug-only=pipeliner %s -filetype=null 2>&1 | FileCheck %s ; REQUIRES: asserts ; Resource-bound II set by the aggregate micro-op issue width, not by any single diff --git a/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-resmii-mfma.ll b/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-resmii-mfma.ll index 8b7c9b053728f4..6b1814c4b2210b 100644 --- a/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-resmii-mfma.ll +++ b/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-resmii-mfma.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -amdgpu-enable-pipeliner -debug-only=pipeliner %s -filetype=null 2>&1 | FileCheck %s +; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -enable-pipeliner -debug-only=pipeliner %s -filetype=null 2>&1 | FileCheck %s ; REQUIRES: asserts ; Resource-bound II set by a single functional unit, the MFMA (XDL) matrix pipe. diff --git a/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-scalar-accumulate.ll b/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-scalar-accumulate.ll index d1b790b784c9c4..1987205c12fb05 100644 --- a/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-scalar-accumulate.ll +++ b/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-scalar-accumulate.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -amdgpu-enable-pipeliner -pass-remarks-analysis=pipeliner %s -filetype=null 2>&1 | FileCheck %s +; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -enable-pipeliner -pass-remarks-analysis=pipeliner %s -filetype=null 2>&1 | FileCheck %s ; Reduced from Composable Kernels. Scalar fp reduction: an i16 buffer ; load feeding a transcendental exp() with a NaN-guarded accumulate. Verifies ; such a loop software-pipelines. diff --git a/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-vector-accumulate.ll b/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-vector-accumulate.ll index be758d4638aa3a..dcd1c082878309 100644 --- a/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-vector-accumulate.ll +++ b/llvm/test/CodeGen/AMDGPU/swp-amdgpu-pipeline-vector-accumulate.ll @@ -1,4 +1,4 @@ -; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -amdgpu-enable-pipeliner -pass-remarks-analysis=pipeliner %s -filetype=null 2>&1 | FileCheck %s +; RUN: llc -mtriple=amdgpu9.50-amd-amdhsa -enable-pipeliner -pass-remarks-analysis=pipeliner %s -filetype=null 2>&1 | FileCheck %s ; Reduced from Composable Kernels. Vector <2 x float> reduction with ; two accumulators fed by two buffer loads and vector-predicated selects. ; Verifies such a loop software-pipelines. diff --git a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll index 6cf362f7e654da..4e596d2e1dbde1 100644 --- a/llvm/test/CodeGen/PowerPC/O3-pipeline.ll +++ b/llvm/test/CodeGen/PowerPC/O3-pipeline.ll @@ -145,13 +145,6 @@ ; CHECK-NEXT: Live Interval Analysis ; CHECK-NEXT: PowerPC TLS Dynamic Call Fixup ; CHECK-NEXT: PowerPC TOC Register Dependencies -; CHECK-NEXT: MachineDominator Tree Construction -; CHECK-NEXT: Machine Natural Loop Construction -; CHECK-NEXT: Slot index numbering -; CHECK-NEXT: Live Interval Analysis -; CHECK-NEXT: Lazy Machine Block Frequency Analysis -; CHECK-NEXT: Machine Optimization Remark Emitter -; CHECK-NEXT: Modulo Software Pipelining ; CHECK-NEXT: Detect Dead Lanes ; CHECK-NEXT: Init Undef Pass ; CHECK-NEXT: Process Implicit Definitions diff --git a/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll b/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll index 9bf619983ee781..6bb63d5d1ac751 100644 --- a/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll +++ b/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ -; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s +; RUN: -mcpu=pwr9 --enable-pipeliner 2>&1 | FileCheck %s @.str.28 = external unnamed_addr constant [69 x i8], align 1 diff --git a/llvm/test/CodeGen/PowerPC/sms-grp-order.ll b/llvm/test/CodeGen/PowerPC/sms-grp-order.ll index eaea47608eb23e..9760e3d83d77e6 100644 --- a/llvm/test/CodeGen/PowerPC/sms-grp-order.ll +++ b/llvm/test/CodeGen/PowerPC/sms-grp-order.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ -; RUN: -mcpu=pwr9 --ppc-enable-pipeliner | FileCheck %s +; RUN: -mcpu=pwr9 --enable-pipeliner | FileCheck %s define void @lame_encode_buffer_interleaved(ptr %arg0) local_unnamed_addr { ; CHECK-LABEL: lame_encode_buffer_interleaved: diff --git a/llvm/test/CodeGen/PowerPC/sms-iterator.ll b/llvm/test/CodeGen/PowerPC/sms-iterator.ll index 7e70d5e8d3dadf..9f16af8e17bc94 100644 --- a/llvm/test/CodeGen/PowerPC/sms-iterator.ll +++ b/llvm/test/CodeGen/PowerPC/sms-iterator.ll @@ -1,6 +1,6 @@ ; REQUIRES: asserts ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ -; RUN: -mcpu=pwr9 --ppc-enable-pipeliner -debug-only=pipeliner -cgp-delete-phis=0 2>&1 \ +; RUN: -mcpu=pwr9 --enable-pipeliner -debug-only=pipeliner -cgp-delete-phis=0 2>&1 \ ; RUN: >/dev/null | FileCheck %s %0 = type { i32, [16 x double] } diff --git a/llvm/test/CodeGen/PowerPC/sms-large-stages.mir b/llvm/test/CodeGen/PowerPC/sms-large-stages.mir index 0ba5ca2bde2e8c..dfa14cfd269199 100644 --- a/llvm/test/CodeGen/PowerPC/sms-large-stages.mir +++ b/llvm/test/CodeGen/PowerPC/sms-large-stages.mir @@ -1,5 +1,5 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py -# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 --ppc-enable-pipeliner -pipeliner-max-stages=10 -run-pass=pipeliner -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 --enable-pipeliner -pipeliner-max-stages=10 -run-pass=pipeliner -verify-machineinstrs -o - %s | FileCheck %s --check-prefix=CHECK --- | define dso_local void @f(ptr noalias nocapture noundef writeonly %a, ptr nocapture noundef readonly %b, i32 noundef signext %n) local_unnamed_addr #0 { diff --git a/llvm/test/CodeGen/PowerPC/sms-phi-1.ll b/llvm/test/CodeGen/PowerPC/sms-phi-1.ll index 516d54ba2fdbef..628da2fe3521b1 100644 --- a/llvm/test/CodeGen/PowerPC/sms-phi-1.ll +++ b/llvm/test/CodeGen/PowerPC/sms-phi-1.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ -; RUN: -mcpu=pwr9 --ppc-enable-pipeliner --pipeliner-force-ii=4 2>&1 | FileCheck %s +; RUN: -mcpu=pwr9 --enable-pipeliner --pipeliner-force-ii=4 2>&1 | FileCheck %s define void @main() nounwind #0 { ; CHECK-LABEL: main: diff --git a/llvm/test/CodeGen/PowerPC/sms-phi-2.ll b/llvm/test/CodeGen/PowerPC/sms-phi-2.ll index 8b4b50239a1a0e..458757be2c3da0 100644 --- a/llvm/test/CodeGen/PowerPC/sms-phi-2.ll +++ b/llvm/test/CodeGen/PowerPC/sms-phi-2.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ -; RUN: -mcpu=pwr9 --ppc-enable-pipeliner --pipeliner-force-ii=15 2>&1 | FileCheck %s +; RUN: -mcpu=pwr9 --enable-pipeliner --pipeliner-force-ii=15 2>&1 | FileCheck %s define void @phi2(i32, i32, ptr) local_unnamed_addr { ; CHECK-LABEL: phi2: diff --git a/llvm/test/CodeGen/PowerPC/sms-phi-3.ll b/llvm/test/CodeGen/PowerPC/sms-phi-3.ll index 628822edabf392..e96a8186b6ce1b 100644 --- a/llvm/test/CodeGen/PowerPC/sms-phi-3.ll +++ b/llvm/test/CodeGen/PowerPC/sms-phi-3.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ -; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s +; RUN: -mcpu=pwr9 --enable-pipeliner 2>&1 | FileCheck %s %0 = type { double, double, double, i32, i32 } declare ptr @malloc() local_unnamed_addr diff --git a/llvm/test/CodeGen/PowerPC/sms-phi-5.ll b/llvm/test/CodeGen/PowerPC/sms-phi-5.ll index 5dcfdf5cc81248..7171a6f662dab6 100644 --- a/llvm/test/CodeGen/PowerPC/sms-phi-5.ll +++ b/llvm/test/CodeGen/PowerPC/sms-phi-5.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ -; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s +; RUN: -mcpu=pwr9 --enable-pipeliner 2>&1 | FileCheck %s define void @phi5() unnamed_addr { ; CHECK-LABEL: phi5: diff --git a/llvm/test/CodeGen/PowerPC/sms-phi.ll b/llvm/test/CodeGen/PowerPC/sms-phi.ll index 5d71423dc781ef..59baee4707e582 100644 --- a/llvm/test/CodeGen/PowerPC/sms-phi.ll +++ b/llvm/test/CodeGen/PowerPC/sms-phi.ll @@ -1,6 +1,6 @@ ; REQUIRES: asserts ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ -; RUN: -mcpu=pwr9 --ppc-enable-pipeliner -debug-only=pipeliner 2>&1 \ +; RUN: -mcpu=pwr9 --enable-pipeliner -debug-only=pipeliner 2>&1 \ ; RUN: >/dev/null | FileCheck %s define dso_local void @sha512(ptr %p) #0 { ;CHECK: prolog: diff --git a/llvm/test/CodeGen/PowerPC/sms-recmii.ll b/llvm/test/CodeGen/PowerPC/sms-recmii.ll index 45747f787b2362..90dd1d40d11e24 100644 --- a/llvm/test/CodeGen/PowerPC/sms-recmii.ll +++ b/llvm/test/CodeGen/PowerPC/sms-recmii.ll @@ -1,6 +1,6 @@ ; REQUIRES: asserts ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ -; RUN: -mcpu=pwr9 --ppc-enable-pipeliner --debug-only=pipeliner 2>&1 | FileCheck %s +; RUN: -mcpu=pwr9 --enable-pipeliner --debug-only=pipeliner 2>&1 | FileCheck %s ; Test that the pipeliner doesn't overestimate the recurrence MII when evaluating circuits. ; CHECK: MII = 16 MAX_II = 26 (rec=16, res=5) diff --git a/llvm/test/CodeGen/PowerPC/sms-regpress.mir b/llvm/test/CodeGen/PowerPC/sms-regpress.mir index 5e81b9d0b8ee50..13180a5eba7501 100644 --- a/llvm/test/CodeGen/PowerPC/sms-regpress.mir +++ b/llvm/test/CodeGen/PowerPC/sms-regpress.mir @@ -1,4 +1,4 @@ -# RUN: llc --verify-machineinstrs -mcpu=pwr9 -o - %s -run-pass=pipeliner -ppc-enable-pipeliner -pipeliner-register-pressure -pipeliner-max-mii=50 -pipeliner-ii-search-range=30 -pipeliner-max-stages=10 -debug-only=pipeliner 2>&1 | FileCheck %s +# RUN: llc --verify-machineinstrs -mcpu=pwr9 -o - %s -run-pass=pipeliner -enable-pipeliner -pipeliner-register-pressure -pipeliner-max-mii=50 -pipeliner-ii-search-range=30 -pipeliner-max-stages=10 -debug-only=pipeliner 2>&1 | FileCheck %s # REQUIRES: asserts diff --git a/llvm/test/CodeGen/PowerPC/sms-remark.ll b/llvm/test/CodeGen/PowerPC/sms-remark.ll index adecf488c9b1e2..a02f53be466043 100644 --- a/llvm/test/CodeGen/PowerPC/sms-remark.ll +++ b/llvm/test/CodeGen/PowerPC/sms-remark.ll @@ -1,13 +1,13 @@ ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \ -; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr9 --ppc-enable-pipeliner \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr9 --enable-pipeliner \ ; RUN: -pass-remarks-analysis=pipeliner -pass-remarks=pipeliner -o /dev/null 2>&1 \ ; RUN: | FileCheck %s --check-prefix=ENABLED ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \ -; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 --ppc-enable-pipeliner \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr8 --enable-pipeliner \ ; RUN: -pass-remarks-analysis=pipeliner -pass-remarks=pipeliner -o /dev/null 2>&1 \ ; RUN: | FileCheck %s --check-prefix=ENABLED ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \ -; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr7 --ppc-enable-pipeliner \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr7 --enable-pipeliner \ ; RUN: -pass-remarks-analysis=pipeliner -pass-remarks=pipeliner -o /dev/null 2>&1 \ ; RUN: | FileCheck %s --allow-empty --check-prefix=ENABLED diff --git a/llvm/test/CodeGen/PowerPC/sms-simple.ll b/llvm/test/CodeGen/PowerPC/sms-simple.ll index 689b5054797070..d39b9a253ec65c 100644 --- a/llvm/test/CodeGen/PowerPC/sms-simple.ll +++ b/llvm/test/CodeGen/PowerPC/sms-simple.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -ppc-vsr-nums-as-vr -mtriple=powerpc64-unknown-linux-gnu \ -; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr9 --ppc-enable-pipeliner \ +; RUN: -verify-machineinstrs -ppc-asm-full-reg-names -mcpu=pwr9 --enable-pipeliner \ ; RUN: | FileCheck %s @x = dso_local local_unnamed_addr global <{ i32, i32, i32, i32, [1020 x i32] }> <{ i32 1, i32 2, i32 3, i32 4, [1020 x i32] zeroinitializer }>, align 4 diff --git a/llvm/test/CodeGen/PowerPC/sms-store-dependence.ll b/llvm/test/CodeGen/PowerPC/sms-store-dependence.ll index d1ec320d55680f..934012a5c31e09 100644 --- a/llvm/test/CodeGen/PowerPC/sms-store-dependence.ll +++ b/llvm/test/CodeGen/PowerPC/sms-store-dependence.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\ -; RUN: -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s +; RUN: -mcpu=pwr9 --enable-pipeliner 2>&1 | FileCheck %s ; Test that the pipeliner schedules the store instructions correctly. Since ; there is a dependence between the store, they cannot be scheduled further than diff --git a/llvm/test/CodeGen/RISCV/machine-pipeliner.ll b/llvm/test/CodeGen/RISCV/machine-pipeliner.ll index 35bf14bb0c8f1d..b35d0c9c208989 100644 --- a/llvm/test/CodeGen/RISCV/machine-pipeliner.ll +++ b/llvm/test/CodeGen/RISCV/machine-pipeliner.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 -; RUN: llc -mtriple=riscv64 -mcpu=sifive-p670 -O3 -verify-machineinstrs -riscv-enable-pipeliner=false < %s \ +; RUN: llc -mtriple=riscv64 -mcpu=sifive-p670 -O3 -verify-machineinstrs -enable-pipeliner=false < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-NOT-PIPELINED -; RUN: llc -mtriple=riscv64 -mcpu=sifive-p670 -O3 -verify-machineinstrs -riscv-enable-pipeliner=true < %s \ +; RUN: llc -mtriple=riscv64 -mcpu=sifive-p670 -O3 -verify-machineinstrs -enable-pipeliner=true < %s \ ; RUN: | FileCheck %s --check-prefixes=CHECK,CHECK-PIPELINED ; We shouldn't pipeline this loop as one operand of branch is a PHI. From f99a0182125b8c67436fc66dcdda91c90be9cb5e Mon Sep 17 00:00:00 2001 From: Rahman Lavaee Date: Sat, 24 Oct 2026 11:11:17 -0700 Subject: [PATCH 15/31] [CodeGen] Move BasicBlockMatchingAndInference options to CodeGenOptions.td (#235180) Move -propeller-match-bbid and -propeller-infer-threshold from cl::opt in BasicBlockMatchingAndInference.cpp to CodeGenOptions.td. This avoids exposing PropellerMatchBBID in BasicBlockMatchingAndInference.h and including that header in TargetPassConfig.cpp. --- .../CodeGen/BasicBlockMatchingAndInference.h | 4 ---- .../CodeGen/BasicBlockMatchingAndInference.cpp | 18 ++++-------------- llvm/lib/CodeGen/CodeGenOptions.td | 6 ++++++ llvm/lib/CodeGen/TargetPassConfig.cpp | 3 +-- 4 files changed, 11 insertions(+), 20 deletions(-) diff --git a/llvm/include/llvm/CodeGen/BasicBlockMatchingAndInference.h b/llvm/include/llvm/CodeGen/BasicBlockMatchingAndInference.h index e444de88d1db11..cf6d901723a7b6 100644 --- a/llvm/include/llvm/CodeGen/BasicBlockMatchingAndInference.h +++ b/llvm/include/llvm/CodeGen/BasicBlockMatchingAndInference.h @@ -19,10 +19,6 @@ namespace llvm { -/// Whether to match basic blocks using BBIDs instead of hashes for Propeller -/// inference. -LLVM_ABI extern cl::opt PropellerMatchBBID; - class LLVM_ABI BasicBlockMatchingAndInference : public MachineFunctionPass { private: using Edge = std::pair; diff --git a/llvm/lib/CodeGen/BasicBlockMatchingAndInference.cpp b/llvm/lib/CodeGen/BasicBlockMatchingAndInference.cpp index 7f6b5791d87c17..b49280b753200f 100644 --- a/llvm/lib/CodeGen/BasicBlockMatchingAndInference.cpp +++ b/llvm/lib/CodeGen/BasicBlockMatchingAndInference.cpp @@ -19,6 +19,7 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/BasicBlockMatchingAndInference.h" +#include "CodeGenOptions.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DenseSet.h" #include "llvm/CodeGen/BasicBlockSectionsProfileReader.h" @@ -26,23 +27,11 @@ #include "llvm/CodeGen/Passes.h" #include "llvm/InitializePasses.h" #include "llvm/Support/Debug.h" -#include using namespace llvm; #define DEBUG_TYPE "machine-block-match-infer" -static cl::opt - PropellerInferThreshold("propeller-infer-threshold", - cl::desc("Threshold for infer stale profile"), - cl::init(0.6)); - -cl::opt llvm::PropellerMatchBBID( - "propeller-match-bbid", - cl::desc("Match basic blocks using BBIDs instead of " - "hashes for Propeller inference"), - cl::init(false)); - /// The object is used to identify and match basic blocks given their hashes. class StaleMatcher { public: @@ -258,8 +247,9 @@ bool BasicBlockMatchingAndInference::runOnMachineFunction(MachineFunction &MF) { if (CFG == nullptr || (CFG->NodeCounts.empty() && CFG->EdgeCounts.empty())) return false; + const CodeGenOptions &Opts = getCodeGenOptions(MF); BasicBlockMatchingAndInference::WeightInfo MatchWeight; - if (PropellerMatchBBID) { + if (Opts.propeller_match_bbid) { MatchWeight = initWeightInfoByBBID(MF, *CFG); } else { MatchWeight = initWeightInfoByMatching(MF); @@ -267,7 +257,7 @@ bool BasicBlockMatchingAndInference::runOnMachineFunction(MachineFunction &MF) { // MBBs in the function is less than the threshold value, the processing // should be abandoned. if (static_cast(MatchWeight.BlockWeights.size()) / MF.size() < - PropellerInferThreshold) { + Opts.propeller_infer_threshold) { return false; } } diff --git a/llvm/lib/CodeGen/CodeGenOptions.td b/llvm/lib/CodeGen/CodeGenOptions.td index 46f33fa137c2d5..2aeb09be04dd67 100644 --- a/llvm/lib/CodeGen/CodeGenOptions.td +++ b/llvm/lib/CodeGen/CodeGenOptions.td @@ -10,6 +10,12 @@ include "llvm/Option/LibraryOptions.td" def CodeGenOptions : OptionsStruct; +// BasicBlockMatchingAndInference.cpp +defm : ValueField<"propeller-infer-threshold", "float", "0.6", + "Threshold for infer stale profile">; +defm : BoolField<"propeller-match-bbid", "false", + "Match basic blocks using BBIDs instead of hashes for Propeller inference">; + // CodeGenPrepare.cpp defm : BoolField<"bbsections-guided-section-prefix", "true", "Use the basic-block-sections profile to determine the text section prefix for hot functions. " diff --git a/llvm/lib/CodeGen/TargetPassConfig.cpp b/llvm/lib/CodeGen/TargetPassConfig.cpp index 536dcd5159115c..ed43dc6d5d3f73 100644 --- a/llvm/lib/CodeGen/TargetPassConfig.cpp +++ b/llvm/lib/CodeGen/TargetPassConfig.cpp @@ -21,7 +21,6 @@ #include "llvm/Analysis/ScopedNoAliasAA.h" #include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/TypeBasedAliasAnalysis.h" -#include "llvm/CodeGen/BasicBlockMatchingAndInference.h" #include "llvm/CodeGen/BasicBlockSectionsProfileReader.h" #include "llvm/CodeGen/CSEConfigBase.h" #include "llvm/CodeGen/CodeGenTargetMachineImpl.h" @@ -1155,7 +1154,7 @@ void TargetPassConfig::addMachinePasses() { if (TM->getBBSectionsType() == llvm::BasicBlockSection::List) { addPass(llvm::createBasicBlockSectionsProfileReaderWrapperPass( TM->getBBSectionsFuncListBuf())); - if (!Opts.basic_block_section_match_infer || PropellerMatchBBID) + if (!Opts.basic_block_section_match_infer || Opts.propeller_match_bbid) addPass(llvm::createBasicBlockPathCloningPass()); if (Opts.basic_block_section_match_infer) addPass(llvm::createBasicBlockMatchingAndInferencePass()); From 34379c8a88246f340a20a76df24714c41f0a163e Mon Sep 17 00:00:00 2001 From: Arseniy Obolenskiy Date: Sat, 24 Oct 2026 20:24:43 +0200 Subject: [PATCH 16/31] [mlir] Skip uniquer locks when a context starts without threading (#235294) --- mlir/lib/IR/MLIRContext.cpp | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/mlir/lib/IR/MLIRContext.cpp b/mlir/lib/IR/MLIRContext.cpp index c5d66c27557c50..350680692a6e0f 100644 --- a/mlir/lib/IR/MLIRContext.cpp +++ b/mlir/lib/IR/MLIRContext.cpp @@ -286,8 +286,16 @@ class MLIRContextImpl { if (threadingIsEnabled) { ownedThreadPool = std::make_unique(); threadPool = ownedThreadPool.get(); + } else { + disableUniquerMultithreading(true); } } + /// Update the threading mode for each of the uniquers. + void disableUniquerMultithreading(bool disable) { + affineUniquer.disableMultithreading(disable); + attributeUniquer.disableMultithreading(disable); + typeUniquer.disableMultithreading(disable); + } ~MLIRContextImpl() { for (auto typeMapping : registeredTypes) typeMapping.second->~AbstractType(); @@ -624,10 +632,7 @@ void MLIRContext::disableMultithreading(bool disable) { impl->threadingIsEnabled = !disable; - // Update the threading mode for each of the uniquers. - impl->affineUniquer.disableMultithreading(disable); - impl->attributeUniquer.disableMultithreading(disable); - impl->typeUniquer.disableMultithreading(disable); + impl->disableUniquerMultithreading(disable); // Destroy thread pool (stop all threads) if it is no longer needed, or create // a new one if multithreading was re-enabled. From 4f2421fb77137dd7cbd72e530670fda96f742f90 Mon Sep 17 00:00:00 2001 From: Snehasish Kumar Date: Sat, 24 Oct 2026 11:27:23 -0700 Subject: [PATCH 17/31] [TLI][SimplifyLibCalls] Accept [2 x iN] return type for __size_returing_new (#234856) On AArch64 (AAPCS64), Clang lowers `struct __sized_ptr_t { void *p; size_t n; }` as `[2 x i64]` (`llvm::ArrayType`), whereas on x86_64 it is lowered as `{ ptr, i64 }` (`llvm::StructType`). Additionally, `emitHotColdSizeReturningNew` and `emitHotColdSizeReturningNewAligned` in `BuildLibCalls.cpp` previously hardcoded `StructType::get(B.getContext(), {B.getPtrTy(), SizeTTy})` as the return type of the newly emitted `_hot_cold` call, which would fail `replaceAllUsesWith` when replacing a call returning `[2 x i64]`. Assisted-by: Gemini Argon --- clang/test/CodeGen/alloc-token-lower.c | 10 +++-- .../llvm/Transforms/Utils/BuildLibCalls.h | 10 ++--- llvm/lib/Analysis/TargetLibraryInfo.cpp | 10 +++-- llvm/lib/Transforms/Utils/BuildLibCalls.cpp | 24 ++++++------ .../lib/Transforms/Utils/SimplifyLibCalls.cpp | 12 +++--- .../AllocToken/extralibfuncs.ll | 9 ++++- .../InstCombine/simplify-libcalls-new.ll | 12 ++++++ .../memprof_match_hot_cold_new_calls.ll | 6 +++ .../Analysis/TargetLibraryInfoTest.cpp | 37 +++++++++++++++++++ 9 files changed, 99 insertions(+), 31 deletions(-) diff --git a/clang/test/CodeGen/alloc-token-lower.c b/clang/test/CodeGen/alloc-token-lower.c index 9ab50ca7cd9383..cef9b99a07f852 100644 --- a/clang/test/CodeGen/alloc-token-lower.c +++ b/clang/test/CodeGen/alloc-token-lower.c @@ -1,12 +1,13 @@ // Test optimization pipelines do not interfere with AllocToken lowering, and we // pass on function attributes correctly. // -// RUN: %clang_cc1 -fsanitize=alloc-token -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,DEFAULT -// RUN: %clang_cc1 -O1 -fsanitize=alloc-token -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,DEFAULT -// RUN: %clang_cc1 -O2 -fsanitize=alloc-token -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,DEFAULT +// RUN: %clang_cc1 -fsanitize=alloc-token -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,DEFAULT,X86 +// RUN: %clang_cc1 -O1 -fsanitize=alloc-token -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,DEFAULT,X86 +// RUN: %clang_cc1 -O2 -fsanitize=alloc-token -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,DEFAULT,X86 // RUN: %clang_cc1 -fsanitize=alloc-token -fsanitize-alloc-token-fast-abi -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,FASTABI // RUN: %clang_cc1 -O1 -fsanitize=alloc-token -fsanitize-alloc-token-fast-abi -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,FASTABI // RUN: %clang_cc1 -O2 -fsanitize=alloc-token -fsanitize-alloc-token-fast-abi -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,FASTABI +// RUN: %clang_cc1 -O1 -fsanitize=alloc-token -triple aarch64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefixes=CHECK,DEFAULT,ARM typedef __typeof(sizeof(int)) size_t; @@ -45,7 +46,8 @@ typedef struct { __sized_ptr_t __size_returning_new(size_t size) __attribute__((malloc_span)); // CHECK-LABEL: @test_size_returning_new -// DEFAULT: call{{.*}} { ptr, i64 } @__alloc_token___size_returning_new(i64 noundef 4, i64 2689373973731826898){{.*}} !alloc_token [[META_INT]] +// X86: call{{.*}} { ptr, i64 } @__alloc_token___size_returning_new(i64 noundef 4, i64 2689373973731826898){{.*}} !alloc_token [[META_INT]] +// ARM: call{{.*}} [2 x i64] @__alloc_token___size_returning_new(i64 noundef 4, i64 2689373973731826898){{.*}} !alloc_token [[META_INT]] // FASTABI: call{{.*}} { ptr, i64 } @__alloc_token_2689373973731826898___size_returning_new(i64 noundef 4){{.*}} !alloc_token [[META_INT]] void *test_size_returning_new() { __sized_ptr_t ret = __size_returning_new(sizeof(int)); diff --git a/llvm/include/llvm/Transforms/Utils/BuildLibCalls.h b/llvm/include/llvm/Transforms/Utils/BuildLibCalls.h index 67b4ff985db636..c2a407dd43a8ce 100644 --- a/llvm/include/llvm/Transforms/Utils/BuildLibCalls.h +++ b/llvm/include/llvm/Transforms/Utils/BuildLibCalls.h @@ -299,11 +299,11 @@ namespace llvm { LibFunc NewFunc, Value *HotCold); LLVM_ABI Value *emitHotColdSizeReturningNew(Value *Num, IRBuilderBase &B, const TargetLibraryInfo *TLI, - LibFunc NewFunc, Value *HotCold); - LLVM_ABI Value * - emitHotColdSizeReturningNewAligned(Value *Num, Value *Align, IRBuilderBase &B, - const TargetLibraryInfo *TLI, - LibFunc NewFunc, Value *HotCold); + LibFunc NewFunc, Value *HotCold, + Type *RetTy); + LLVM_ABI Value *emitHotColdSizeReturningNewAligned( + Value *Num, Value *Align, IRBuilderBase &B, const TargetLibraryInfo *TLI, + LibFunc NewFunc, Value *HotCold, Type *RetTy); } #endif diff --git a/llvm/lib/Analysis/TargetLibraryInfo.cpp b/llvm/lib/Analysis/TargetLibraryInfo.cpp index c3469979d72047..4612e1fb5dbf6a 100644 --- a/llvm/lib/Analysis/TargetLibraryInfo.cpp +++ b/llvm/lib/Analysis/TargetLibraryInfo.cpp @@ -1085,9 +1085,13 @@ static bool isValidProtoForSizeReturningNew(const FunctionType &FTy, LibFunc F, auto &Context = M.getContext(); PointerType *PtrTy = PointerType::get(Context, 0); - StructType *SizedPtrTy = StructType::get( - Context, {PtrTy, Type::getIntNTy(Context, SizeTSizeBits)}); - return FTy.getReturnType() == SizedPtrTy; + Type *SizeTTy = Type::getIntNTy(Context, SizeTSizeBits); + Type *RetTy = FTy.getReturnType(); + // Return type struct __sized_ptr_t { void*, size_t } is lowered to + // { ptr, iN } on some targets (e.g. x86_64) and [2 x iN] on others (e.g. + // AArch64). + return RetTy == StructType::get(Context, {PtrTy, SizeTTy}) || + RetTy == ArrayType::get(SizeTTy, 2); } bool TargetLibraryInfoImpl::isValidProtoForLibFunc(const FunctionType &FTy, diff --git a/llvm/lib/Transforms/Utils/BuildLibCalls.cpp b/llvm/lib/Transforms/Utils/BuildLibCalls.cpp index 497927684a8d33..8e3f0249ff3548 100644 --- a/llvm/lib/Transforms/Utils/BuildLibCalls.cpp +++ b/llvm/lib/Transforms/Utils/BuildLibCalls.cpp @@ -2100,18 +2100,18 @@ Value *llvm::emitCalloc(Value *Num, Value *Size, IRBuilderBase &B, Value *llvm::emitHotColdSizeReturningNew(Value *Num, IRBuilderBase &B, const TargetLibraryInfo *TLI, LibFunc SizeFeedbackNewFunc, - Value *HotCold) { + Value *HotCold, Type *RetTy) { Module *M = B.getModule(); if (!isLibFuncEmittable(M, TLI, SizeFeedbackNewFunc)) return nullptr; StringRef Name = TLI->getName(SizeFeedbackNewFunc); + if (const Function *F = M->getFunction(Name); + F && F->getReturnType() != RetTy) + return nullptr; - // __sized_ptr_t struct return type { void*, size_t } - StructType *SizedPtrT = - StructType::get(M->getContext(), {B.getPtrTy(), Num->getType()}); - FunctionCallee Func = getOrInsertLibFunc( - M, *TLI, SizeFeedbackNewFunc, SizedPtrT, Num->getType(), B.getInt8Ty()); + FunctionCallee Func = getOrInsertLibFunc(M, *TLI, SizeFeedbackNewFunc, RetTy, + Num->getType(), B.getInt8Ty()); inferNonMandatoryLibFuncAttrs(M, Name, *TLI); CallInst *CI = B.CreateCall(Func, {Num, HotCold}, "sized_ptr"); @@ -2125,19 +2125,19 @@ Value *llvm::emitHotColdSizeReturningNewAligned(Value *Num, Value *Align, IRBuilderBase &B, const TargetLibraryInfo *TLI, LibFunc SizeFeedbackNewFunc, - Value *HotCold) { + Value *HotCold, Type *RetTy) { Module *M = B.getModule(); if (!isLibFuncEmittable(M, TLI, SizeFeedbackNewFunc)) return nullptr; StringRef Name = TLI->getName(SizeFeedbackNewFunc); + if (const Function *F = M->getFunction(Name); + F && F->getReturnType() != RetTy) + return nullptr; - // __sized_ptr_t struct return type { void*, size_t } - StructType *SizedPtrT = - StructType::get(M->getContext(), {B.getPtrTy(), Num->getType()}); FunctionCallee Func = - getOrInsertLibFunc(M, *TLI, SizeFeedbackNewFunc, SizedPtrT, - Num->getType(), Align->getType(), B.getInt8Ty()); + getOrInsertLibFunc(M, *TLI, SizeFeedbackNewFunc, RetTy, Num->getType(), + Align->getType(), B.getInt8Ty()); inferNonMandatoryLibFuncAttrs(M, Name, *TLI); CallInst *CI = B.CreateCall(Func, {Num, Align, HotCold}, "sized_ptr"); diff --git a/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp b/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp index 60bfda6efaa4cb..4b21e3a02b1d77 100644 --- a/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp @@ -1995,25 +1995,25 @@ Value *LibCallSimplifier::optimizeNew(CallInst *CI, IRBuilderBase &B, case LibFunc_size_returning_new: NewCall = emitHotColdSizeReturningNew(CI->getArgOperand(0), B, TLI, LibFunc_size_returning_new_hot_cold, - HotColdVal); + HotColdVal, CI->getType()); break; case LibFunc_size_returning_new_hot_cold: if (ShouldOptimizeExistingHotColdNew) - NewCall = emitHotColdSizeReturningNew(CI->getArgOperand(0), B, TLI, - LibFunc_size_returning_new_hot_cold, - getHotColdHintForExisting(HotCold)); + NewCall = emitHotColdSizeReturningNew( + CI->getArgOperand(0), B, TLI, LibFunc_size_returning_new_hot_cold, + getHotColdHintForExisting(HotCold), CI->getType()); break; case LibFunc_size_returning_new_aligned: NewCall = emitHotColdSizeReturningNewAligned( CI->getArgOperand(0), CI->getArgOperand(1), B, TLI, - LibFunc_size_returning_new_aligned_hot_cold, HotColdVal); + LibFunc_size_returning_new_aligned_hot_cold, HotColdVal, CI->getType()); break; case LibFunc_size_returning_new_aligned_hot_cold: if (ShouldOptimizeExistingHotColdNew) NewCall = emitHotColdSizeReturningNewAligned( CI->getArgOperand(0), CI->getArgOperand(1), B, TLI, LibFunc_size_returning_new_aligned_hot_cold, - getHotColdHintForExisting(HotCold)); + getHotColdHintForExisting(HotCold), CI->getType()); break; default: return nullptr; diff --git a/llvm/test/Instrumentation/AllocToken/extralibfuncs.ll b/llvm/test/Instrumentation/AllocToken/extralibfuncs.ll index 0e382b2cebed69..4529f09b7c087d 100644 --- a/llvm/test/Instrumentation/AllocToken/extralibfuncs.ll +++ b/llvm/test/Instrumentation/AllocToken/extralibfuncs.ll @@ -6,6 +6,7 @@ target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" declare {ptr, i64} @__size_returning_new(i64) +declare [2 x i64] @__size_returning_new_aligned(i64, i64) define ptr @test_extra_libfuncs() sanitize_alloc_token { ; CHECK-LABEL: define ptr @test_extra_libfuncs( @@ -13,11 +14,17 @@ define ptr @test_extra_libfuncs() sanitize_alloc_token { ; CHECK-NEXT: [[ENTRY:.*:]] ; CHECK-NEXT: [[TMP0:%.*]] = call { ptr, i64 } @__alloc_token___size_returning_new(i64 10, i64 2689373973731826898), !alloc_token [[META0:![0-9]+]] ; CHECK-NEXT: [[PTR1:%.*]] = extractvalue { ptr, i64 } [[TMP0]], 0 +; CHECK-NEXT: [[TMP1:%.*]] = call [2 x i64] @__alloc_token___size_returning_new_aligned(i64 10, i64 8, i64 2689373973731826898), !alloc_token [[META0]] +; CHECK-NEXT: [[PTR2_INT:%.*]] = extractvalue [2 x i64] [[TMP1]], 0 +; CHECK-NEXT: [[PTR2:%.*]] = inttoptr i64 [[PTR2_INT]] to ptr ; CHECK-NEXT: ret ptr [[PTR1]] ; entry: %srn = call {ptr, i64} @__size_returning_new(i64 10), !alloc_token !0 - %ptr1 = extractvalue {ptr, i64} %srn, 0 + %ptr1 = extractvalue {ptr, i64} %srn, 0 + %srna = call [2 x i64] @__size_returning_new_aligned(i64 10, i64 8), !alloc_token !0 + %ptr2_int = extractvalue [2 x i64] %srna, 0 + %ptr2 = inttoptr i64 %ptr2_int to ptr ret ptr %ptr1 } diff --git a/llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll b/llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll index 545df33a389ff9..a5fe051a7a654d 100644 --- a/llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll +++ b/llvm/test/Transforms/InstCombine/simplify-libcalls-new.ll @@ -25,6 +25,10 @@ ; RUN: opt < %s -passes=instcombine -optimize-hot-cold-new -cold-new-hint-value=5 -notcold-new-hint-value=100 -hot-new-hint-value=200 -ambiguous-new-hint-value=44 -optimize-existing-hot-cold-new -min-existing-hot-cold-new-hint -S | FileCheck %s --check-prefixes=HOTCOLD,NOBUILTIN-OFF,MIN-ALWAYS -DCOLD=5 -DHOT=-56 -DNOTCOLD=100 -DAMBIG=44 -DPREVHINTCOLD=5 -DPREVHINTNOTCOLD=7 -DPREVHINTHOT=7 -DPREVHINTAMBIG=7 -DMINCOLD1=2 -DMINCOLD2=5 -DMINHOT1=-56 -DMINHOT2=50 ; RUN: opt < %s -passes=instcombine -optimize-hot-cold-new -cold-new-hint-value=5 -notcold-new-hint-value=100 -hot-new-hint-value=200 -ambiguous-new-hint-value=44 -optimize-existing-hot-cold-new=cold -min-existing-hot-cold-new-hint -S | FileCheck %s --check-prefixes=HOTCOLD,NOBUILTIN-OFF,MIN-COLD -DCOLD=5 -DHOT=-56 -DNOTCOLD=100 -DAMBIG=44 -DPREVHINTCOLD=5 -DPREVHINTNOTCOLD=7 -DPREVHINTHOT=7 -DPREVHINTAMBIG=7 -DMINCOLD1=2 -DMINCOLD2=5 -DMINHOT1=-6 -DMINHOT2=50 +;; Check that [2 x i64] return type (e.g. on AArch64) is also recognized and +;; preserved for __size_returning_new variants. +; RUN: sed -e 's/{ptr, i64}/[2 x i64]/g' -e 's/call void @dummy(ptr %%p/; /g' %s | opt -passes=instcombine -optimize-hot-cold-new -optimize-existing-hot-cold-new -S | FileCheck %s --check-prefix=ARRAY-RET + ;; Make sure that values not in 0..255 are flagged with an error ; RUN: not opt < %s -passes=instcombine -optimize-hot-cold-new -cold-new-hint-value=256 -S 2>&1 | FileCheck %s --check-prefix=ERROR ; RUN: not opt < %s -passes=instcombine -optimize-hot-cold-new -hot-new-hint-value=5000 -S 2>&1 | FileCheck %s --check-prefix=ERROR @@ -489,9 +493,11 @@ define void @array_new_align_nothrow_hot_cold() { ;; Check that operator __size_returning_new(unsigned long) converted to ;; __size_returning_new(unsigned long, __hot_cold_t) with a hot or cold attribute. ; HOTCOLD-LABEL: @size_returning_test() +; ARRAY-RET-LABEL: @size_returning_test() define void @size_returning_test() { ;; Attribute cold converted to __hot_cold_t cold value. ; HOTCOLD: @__size_returning_new_hot_cold(i64 10, i8 [[COLD]]) + ; ARRAY-RET: call [2 x i64] @__size_returning_new_hot_cold(i64 10, i8 1) %call = call {ptr, i64} @__size_returning_new(i64 10) #3 %p = extractvalue {ptr, i64} %call, 0 call void @dummy(ptr %p) @@ -522,9 +528,11 @@ define void @size_returning_test() { ;; Check that operator __size_returning_new_aligned(unsigned long, std::align_val_t) converted to ;; __size_returning_new_aligned(unsigned long, std::align_val_t, __hot_cold_t) with a hot or cold attribute. ; HOTCOLD-LABEL: @size_returning_aligned_test() +; ARRAY-RET-LABEL: @size_returning_aligned_test() define void @size_returning_aligned_test() { ;; Attribute cold converted to __hot_cold_t cold value. ; HOTCOLD: @__size_returning_new_aligned_hot_cold(i64 10, i64 8, i8 [[COLD]]) + ; ARRAY-RET: call [2 x i64] @__size_returning_new_aligned_hot_cold(i64 10, i64 8, i8 1) %call = call {ptr, i64} @__size_returning_new_aligned(i64 10, i64 8) #3 %p = extractvalue {ptr, i64} %call, 0 call void @dummy(ptr %p) @@ -555,9 +563,11 @@ define void @size_returning_aligned_test() { ;; Check that __size_returning_new_hot_cold(unsigned long, __hot_cold_t) ;; optionally has its hint updated. ; HOTCOLD-LABEL: @size_returning_update_test() +; ARRAY-RET-LABEL: @size_returning_update_test() define void @size_returning_update_test() { ;; Attribute cold converted to __hot_cold_t cold value. ; HOTCOLD: @__size_returning_new_hot_cold(i64 10, i8 [[PREVHINTCOLD]]) + ; ARRAY-RET: call [2 x i64] @__size_returning_new_hot_cold(i64 10, i8 1) %call = call {ptr, i64} @__size_returning_new_hot_cold(i64 10, i8 7) #3 %p = extractvalue {ptr, i64} %call, 0 call void @dummy(ptr %p) @@ -587,9 +597,11 @@ define void @size_returning_update_test() { ;; Check that __size_returning_new_aligned_hot_cold(unsigned long, __hot_cold_t) ;; optionally has its hint updated. ; HOTCOLD-LABEL: @size_returning_aligned_update_test() +; ARRAY-RET-LABEL: @size_returning_aligned_update_test() define void @size_returning_aligned_update_test() { ;; Attribute cold converted to __hot_cold_t cold value. ; HOTCOLD: @__size_returning_new_aligned_hot_cold(i64 10, i64 8, i8 [[PREVHINTCOLD]]) + ; ARRAY-RET: call [2 x i64] @__size_returning_new_aligned_hot_cold(i64 10, i64 8, i8 1) %call = call {ptr, i64} @__size_returning_new_aligned_hot_cold(i64 10, i64 8, i8 7) #3 %p = extractvalue {ptr, i64} %call, 0 call void @dummy(ptr %p) diff --git a/llvm/test/Transforms/PGOProfile/memprof_match_hot_cold_new_calls.ll b/llvm/test/Transforms/PGOProfile/memprof_match_hot_cold_new_calls.ll index 4aa05116226623..b71e478cb36cd7 100644 --- a/llvm/test/Transforms/PGOProfile/memprof_match_hot_cold_new_calls.ll +++ b/llvm/test/Transforms/PGOProfile/memprof_match_hot_cold_new_calls.ll @@ -100,10 +100,16 @@ define dso_local noundef ptr @_Z3foov() !dbg !10 { entry: ; MEMPROF: call {{.*}} @_Znwm{{.*}} !memprof ![[M1:[0-9]+]], !callsite ![[C1:[0-9]+]] %call = call noalias noundef align 32 ptr @_ZnwmSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64 noundef 32, i64 noundef 32, ptr noundef nonnull align 1 dereferenceable(1) @_ZSt7nothrow, i8 noundef zeroext 0), !dbg !13 + ; MEMPROF: call {{.*}} @__size_returning_new_hot_cold{{.*}} !memprof ![[M1]], !callsite ![[C1]] + %srn = call [2 x i64] @__size_returning_new_hot_cold(i64 noundef 32, i8 noundef zeroext 0), !dbg !13 + ; MEMPROF: call {{.*}} @__size_returning_new_aligned_hot_cold{{.*}} !memprof ![[M1]], !callsite ![[C1]] + %srna = call [2 x i64] @__size_returning_new_aligned_hot_cold(i64 noundef 32, i64 noundef 32, i8 noundef zeroext 0), !dbg !13 ret ptr %call } declare noundef ptr @_ZnwmSt11align_val_tRKSt9nothrow_t12__hot_cold_t(i64 noundef, i64 noundef, ptr noundef nonnull align 1 dereferenceable(1), i8 noundef zeroext) +declare [2 x i64] @__size_returning_new_hot_cold(i64 noundef, i8 noundef zeroext) +declare [2 x i64] @__size_returning_new_aligned_hot_cold(i64 noundef, i64 noundef, i8 noundef zeroext) ; MEMPROF: ![[M1]] = !{![[MIB1:[0-9]+]], ![[MIB2:[0-9]+]], ![[MIB3:[0-9]+]], ![[MIB4:[0-9]+]]} ; MEMPROF: ![[MIB1]] = !{![[STACK1:[0-9]+]], !"cold"} diff --git a/llvm/unittests/Analysis/TargetLibraryInfoTest.cpp b/llvm/unittests/Analysis/TargetLibraryInfoTest.cpp index c68f5051b8ced9..fed7fa85fc7bf0 100644 --- a/llvm/unittests/Analysis/TargetLibraryInfoTest.cpp +++ b/llvm/unittests/Analysis/TargetLibraryInfoTest.cpp @@ -107,6 +107,43 @@ TEST_F(TargetLibraryInfoTest, SizeReturningNewInvalidProto) { } } +TEST_F(TargetLibraryInfoTest, SizeReturningNewArrayProto) { + parseAssembly("target datalayout = \"p:64:64:64\"\n" + "declare [2 x i64] @__size_returning_new(i64)\n" + "declare [2 x i64] @__size_returning_new_hot_cold(i64, i8)\n" + "declare [2 x i64] @__size_returning_new_aligned(i64, i64)\n" + "declare [2 x i64] @__size_returning_new_aligned_hot_cold(i64, " + "i64, i8)\n"); + + for (const LibFunc LF : + {LibFunc_size_returning_new, LibFunc_size_returning_new_aligned, + LibFunc_size_returning_new_hot_cold, + LibFunc_size_returning_new_aligned_hot_cold}) { + TLII.setAvailable(LF); + Function *F = M->getFunction(TLI.getName(LF)); + ASSERT_NE(F, nullptr); + EXPECT_TRUE(isLibFunc(F, LF)); + } + + // Invalid array element count or element type. + parseAssembly("target datalayout = \"p:64:64:64\"\n" + "declare [3 x i64] @__size_returning_new(i64)\n" + "declare [1 x i64] @__size_returning_new_hot_cold(i64, i8)\n" + "declare [2 x i32] @__size_returning_new_aligned(i64, i64)\n" + "declare [2 x ptr] @__size_returning_new_aligned_hot_cold(i64, " + "i64, i8)\n"); + + for (const LibFunc LF : + {LibFunc_size_returning_new, LibFunc_size_returning_new_aligned, + LibFunc_size_returning_new_hot_cold, + LibFunc_size_returning_new_aligned_hot_cold}) { + TLII.setAvailable(LF); + Function *F = M->getFunction(TLI.getName(LF)); + ASSERT_NE(F, nullptr); + EXPECT_FALSE(isLibFunc(F, LF)); + } +} + // Check that we do accept know-correct prototypes. TEST_F(TargetLibraryInfoTest, ValidProto) { parseAssembly( From f45474e16eb99c07e6b34cee08d26b44c8ce4148 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Sat, 24 Oct 2026 11:34:25 -0700 Subject: [PATCH 18/31] Revert "[SelectionDAG] Implement SDTCisSameAs in verifyNode." (#235329) M68k is failing on the bots. I'll need to fix it or waive the broken node, but I need time to investigate. Reverts #235157 --- llvm/lib/CodeGen/SelectionDAG/SDNodeInfo.cpp | 11 +---------- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/SDNodeInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/SDNodeInfo.cpp index 029dd583c2736f..f5042aef054838 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SDNodeInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SDNodeInfo.cpp @@ -277,17 +277,8 @@ void SDNodeInfo::verifyNode(const SelectionDAG &DAG, const SDNode *N) const { reportNodeError(DAG, N, SS.str()); } break; - case SDTCisSameAs: { - SDNodeValue OtherVal = GetConstraintValue(C.ConstrainingValIdx); - EVT OtherVT = OtherVal.getValueType(); - - if (VT != OtherVT) { - SS << Val << " must have the same type as " << OtherVal << " (" - << OtherVT << "), but has type " << VT; - reportNodeError(DAG, N, SS.str()); - } + case SDTCisSameAs: break; - } case SDTCisVTSmallerThanOp: { const auto *VTNode = dyn_cast(Val.getValue().getNode()); if (!VTNode) { From ee824d2baaf7f864520141c0b5d3f704ed518985 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sat, 24 Oct 2026 11:49:23 -0700 Subject: [PATCH 19/31] [clang] Replace PointerUnion::dyn_cast with llvm::dyn_cast (NFC) (#235232) PointerUnion::dyn_cast has been soft-deprecated in favor of llvm::dyn_cast and llvm::dyn_cast_if_present. This patch replaces PointerUnion::dyn_cast with llvm::dyn_cast at 17 call sites across 11 files under clang/. All tests in check-clang pass with these changes, and LLM-based static analysis of the surrounding data structures and call sites confirms that the PointerUnion operand at each site is nonnull either by construction or because callers ensure it is nonnull before reaching llvm::dyn_cast. Assisted-by: Antigravity --- clang/include/clang/AST/DeclCXX.h | 2 +- clang/include/clang/AST/DeclFriend.h | 2 +- clang/include/clang/AST/DeclTemplate.h | 10 +++++----- clang/include/clang/AST/ExprCXX.h | 4 ++-- clang/include/clang/AST/ExternalASTSource.h | 6 +++--- clang/include/clang/Lex/PreprocessingRecord.h | 2 +- .../StaticAnalyzer/Core/PathSensitive/CallEvent.h | 6 ++---- clang/lib/AST/Decl.cpp | 2 +- clang/lib/Sema/SemaTemplateInstantiate.cpp | 2 +- clang/lib/Serialization/ASTWriter.cpp | 2 +- clang/lib/Serialization/MultiOnDiskHashTable.h | 5 +++-- 11 files changed, 21 insertions(+), 22 deletions(-) diff --git a/clang/include/clang/AST/DeclCXX.h b/clang/include/clang/AST/DeclCXX.h index 1ebc8a7191bde9..cf61653728cb65 100644 --- a/clang/include/clang/AST/DeclCXX.h +++ b/clang/include/clang/AST/DeclCXX.h @@ -2539,7 +2539,7 @@ class CXXCtorInitializer final { /// Returns the declarator information for a base class or delegating /// initializer. TypeSourceInfo *getTypeSourceInfo() const { - return Initializee.dyn_cast(); + return dyn_cast(Initializee); } /// If this is a member initializer, returns the declaration of the diff --git a/clang/include/clang/AST/DeclFriend.h b/clang/include/clang/AST/DeclFriend.h index 607930a35b32bf..2b96d4a34999a1 100644 --- a/clang/include/clang/AST/DeclFriend.h +++ b/clang/include/clang/AST/DeclFriend.h @@ -100,7 +100,7 @@ class FriendDecl : public Decl { /// If this friend declaration doesn't name a type, return the inner /// declaration. virtual NamedDecl *getFriendDecl() const { - return Friend.dyn_cast(); + return dyn_cast(Friend); } /// Retrieves the location of the '...', if present. diff --git a/clang/include/clang/AST/DeclTemplate.h b/clang/include/clang/AST/DeclTemplate.h index 5724645602d9b3..b9f70ea4c872e3 100644 --- a/clang/include/clang/AST/DeclTemplate.h +++ b/clang/include/clang/AST/DeclTemplate.h @@ -316,7 +316,7 @@ class DefaultArgStorage { static ParmDecl *getParmOwningDefaultArg(ParmDecl *Parm) { const DefaultArgStorage &Storage = Parm->getDefaultArgStorage(); - if (auto *Prev = Storage.ValueOrInherited.template dyn_cast()) + if (auto *Prev = dyn_cast(Storage.ValueOrInherited)) Parm = Prev; assert(!isa(Parm->getDefaultArgStorage().ValueOrInherited) && "should only be one level of indirection"); @@ -337,9 +337,9 @@ class DefaultArgStorage { /// default argument is visible. ArgType get() const { const DefaultArgStorage *Storage = this; - if (const auto *Prev = ValueOrInherited.template dyn_cast()) + if (const auto *Prev = dyn_cast(ValueOrInherited)) Storage = &Prev->getDefaultArgStorage(); - if (const auto *C = Storage->ValueOrInherited.template dyn_cast()) + if (const auto *C = dyn_cast(Storage->ValueOrInherited)) return C->Value; return cast(Storage->ValueOrInherited); } @@ -347,9 +347,9 @@ class DefaultArgStorage { /// Get the parameter from which we inherit the default argument, if any. /// This is the parameter on which the default argument was actually written. const ParmDecl *getInheritedFrom() const { - if (const auto *D = ValueOrInherited.template dyn_cast()) + if (const auto *D = dyn_cast(ValueOrInherited)) return D; - if (const auto *C = ValueOrInherited.template dyn_cast()) + if (const auto *C = dyn_cast(ValueOrInherited)) return C->PrevDeclWithDefaultArg; return nullptr; } diff --git a/clang/include/clang/AST/ExprCXX.h b/clang/include/clang/AST/ExprCXX.h index 5187655386d9b7..af1d3be39004e6 100644 --- a/clang/include/clang/AST/ExprCXX.h +++ b/clang/include/clang/AST/ExprCXX.h @@ -2713,11 +2713,11 @@ class PseudoDestructorTypeStorage { PseudoDestructorTypeStorage(TypeSourceInfo *Info); TypeSourceInfo *getTypeSourceInfo() const { - return Type.dyn_cast(); + return dyn_cast(Type); } const IdentifierInfo *getIdentifier() const { - return Type.dyn_cast(); + return dyn_cast(Type); } SourceLocation getLocation() const { return Location; } diff --git a/clang/include/clang/AST/ExternalASTSource.h b/clang/include/clang/AST/ExternalASTSource.h index 8696cd3334ee2d..95b81139dc95ff 100644 --- a/clang/include/clang/AST/ExternalASTSource.h +++ b/clang/include/clang/AST/ExternalASTSource.h @@ -471,7 +471,7 @@ struct LazyGenerationalDeclPtr { /// Set the value of this pointer, in the current generation. void set(Decl *NewValue) { - if (auto *LazyVal = Value.template dyn_cast()) { + if (auto *LazyVal = dyn_cast(Value)) { LazyVal->LastValue = NewValue; return; } @@ -480,7 +480,7 @@ struct LazyGenerationalDeclPtr { /// Get the value of this pointer, updating its owner if necessary. Decl *get(const Decl *O) { - if (auto *LazyVal = Value.template dyn_cast()) { + if (auto *LazyVal = dyn_cast(Value)) { if (LazyVal->LastGeneration != LazyVal->ExternalSource->getGeneration()) { LazyVal->LastGeneration = LazyVal->ExternalSource->getGeneration(); LazyVal->ExternalSource->CompleteRedeclChain(O); @@ -492,7 +492,7 @@ struct LazyGenerationalDeclPtr { /// Get the most recently computed value of this pointer without updating it. Decl *getNotUpdated() const { - if (auto *LazyVal = Value.template dyn_cast()) + if (auto *LazyVal = dyn_cast(Value)) return LazyVal->LastValue; return cast(Value); } diff --git a/clang/include/clang/Lex/PreprocessingRecord.h b/clang/include/clang/Lex/PreprocessingRecord.h index 7886aef7f0c7f3..1c45f02902b363 100644 --- a/clang/include/clang/Lex/PreprocessingRecord.h +++ b/clang/include/clang/Lex/PreprocessingRecord.h @@ -192,7 +192,7 @@ class Token; /// The definition of the macro being expanded. May return null if /// this is a builtin macro. MacroDefinitionRecord *getDefinition() const { - return NameOrDef.dyn_cast(); + return dyn_cast(NameOrDef); } // Implement isa/cast/dyncast/etc. diff --git a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallEvent.h b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallEvent.h index 2010e4b0da84b0..f854c25ede8521 100644 --- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallEvent.h +++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/CallEvent.h @@ -230,9 +230,7 @@ class CallEvent { /// Returns the declaration of the function or method that will be /// called. May be null. - virtual const Decl *getDecl() const { - return Origin.dyn_cast(); - } + virtual const Decl *getDecl() const { return dyn_cast(Origin); } bool isForeign() const { assert(Foreign && "Foreign must be set before querying"); @@ -260,7 +258,7 @@ class CallEvent { /// Returns the expression whose value will be the result of this call. /// Null if and only if 'this' is a CXXDestructorCall. virtual const Expr *getOriginExpr() const { - return Origin.dyn_cast(); + return dyn_cast(Origin); } /// Returns the number of arguments (explicit and implicit). diff --git a/clang/lib/AST/Decl.cpp b/clang/lib/AST/Decl.cpp index d334d1066987aa..f920a1e9b8fd85 100644 --- a/clang/lib/AST/Decl.cpp +++ b/clang/lib/AST/Decl.cpp @@ -2406,7 +2406,7 @@ Expr *VarDecl::getInit() { } Stmt **VarDecl::getInitAddress() { - if (auto *ES = Init.dyn_cast()) + if (auto *ES = dyn_cast(Init)) return ES->Value.getAddressOfPointer(getASTContext().getExternalSource()); return Init.getAddrOfPtr1(); diff --git a/clang/lib/Sema/SemaTemplateInstantiate.cpp b/clang/lib/Sema/SemaTemplateInstantiate.cpp index 036642f22bd8cb..ecd3f4a1096c1e 100644 --- a/clang/lib/Sema/SemaTemplateInstantiate.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiate.cpp @@ -2819,7 +2819,7 @@ TemplateInstantiator::TransformExprRequirement(concepts::ExprRequirement *Req) { } } assert(TransRetReq && "All code paths leading here must set TransRetReq"); - if (Expr *E = TransExpr.dyn_cast()) + if (Expr *E = dyn_cast(TransExpr)) return RebuildExprRequirement(E, Req->isSimple(), Req->getNoexceptLoc(), std::move(*TransRetReq)); return RebuildExprRequirement( diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp index cb89eaffc4bf00..0d9ec7a460dfbf 100644 --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -6694,7 +6694,7 @@ void ASTWriter::WriteDeclUpdatesBlocks(ASTContext &Context, // specialization. If so, record which one. auto From = Spec->getInstantiatedFrom(); if (auto PartialSpec = - From.dyn_cast()) { + dyn_cast(From)) { Record.push_back(true); Record.AddDeclRef(PartialSpec); Record.AddTemplateArgumentList( diff --git a/clang/lib/Serialization/MultiOnDiskHashTable.h b/clang/lib/Serialization/MultiOnDiskHashTable.h index a179016d474194..93193bb9224611 100644 --- a/clang/lib/Serialization/MultiOnDiskHashTable.h +++ b/clang/lib/Serialization/MultiOnDiskHashTable.h @@ -110,8 +110,9 @@ template class MultiOnDiskHashTable { MergedTable *getMergedTable() const { // If we already have a merged table, it's the first one. - return Tables.empty() ? nullptr : Table::getFromOpaqueValue(*Tables.begin()) - .template dyn_cast(); + return Tables.empty() ? nullptr + : llvm::dyn_cast( + Table::getFromOpaqueValue(*Tables.begin())); } /// Delete all our current on-disk tables. From de39e758b91f4e2fface739251f1c0b651318749 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sat, 24 Oct 2026 11:49:32 -0700 Subject: [PATCH 20/31] [IR] Remove unused GEPOperator::countNonConstantIndices (NFC) (#235233) The last callers of GEPOperator::countNonConstantIndices were removed on April 26, 2024 in commit cbe1760f02882328c91e5764648f97fe644f44c9. Assisted-by: Antigravity --- llvm/include/llvm/IR/Operator.h | 6 ------ 1 file changed, 6 deletions(-) diff --git a/llvm/include/llvm/IR/Operator.h b/llvm/include/llvm/IR/Operator.h index c44cddca930094..9bee3845cb4a7d 100644 --- a/llvm/include/llvm/IR/Operator.h +++ b/llvm/include/llvm/IR/Operator.h @@ -469,12 +469,6 @@ class GEPOperator return true; } - unsigned countNonConstantIndices() const { - return count_if(indices(), [](const Use& use) { - return !isa(*use); - }); - } - /// Compute the maximum alignment that this GEP is garranteed to preserve. LLVM_ABI Align getMaxPreservedAlignment(const DataLayout &DL) const; From c0815b9b22d449906d89ca7d0a4e66157243f968 Mon Sep 17 00:00:00 2001 From: David Green Date: Sat, 24 Oct 2026 20:09:31 +0100 Subject: [PATCH 21/31] [ARM] Replace reg in preheader when reverting WhileLoopStartLR (#229754) As we revert a wls loop to a dls loop, we remove the t2WhileLoopStartLR to a t2DoLoopStart at the start of the preheader. In finding the t2WhileLoopStartLR we might have looked through a copy that is still using the t2WhileLoopStartLR def. Make sure we replace the use with the Src to remain valid. Fixes #229400 --- .../ARM/MVETPAndVPTOptimisationsPass.cpp | 9 + .../revert-after-call-preheader.mir | 220 ++++++++++++++++++ 2 files changed, 229 insertions(+) create mode 100644 llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call-preheader.mir diff --git a/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp b/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp index 7c340ed71457d8..b1ff6aacb70ddd 100644 --- a/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp +++ b/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp @@ -289,6 +289,8 @@ MachineInstr *MVETPAndVPTOptimisations::CheckForLRUseInPredecessors( continue; LLVM_DEBUG(dbgs() << "Found LR use in predecessors, reverting: " << MI); + Register DefReg = LoopStart->getOperand(0).getReg(); + Register SrcReg = LoopStart->getOperand(1).getReg(); // Create a t2DoLoopStart at the end of the preheader. MachineInstrBuilder MIB = @@ -302,6 +304,13 @@ MachineInstr *MVETPAndVPTOptimisations::CheckForLRUseInPredecessors( // Revert the t2WhileLoopStartLR to a CMP and Br. RevertWhileLoopStartLR(LoopStart, TII, ARM::t2Bcc, true); + // If we looked through a COPY to find the WhileLoopStart, replace it's + // use with SrcReg. + for (MachineOperand &MO : + make_early_inc_range(MRI->use_operands(DefReg))) { + if (MO.getParent()->getOpcode() == TargetOpcode::COPY) + MO.setReg(SrcReg); + } return MIB; } diff --git a/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call-preheader.mir b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call-preheader.mir new file mode 100644 index 00000000000000..7e31d5b00f7da1 --- /dev/null +++ b/llvm/test/CodeGen/Thumb2/LowOverheadLoops/revert-after-call-preheader.mir @@ -0,0 +1,220 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6 +# RUN: llc -mtriple=thumbv8.1m.main %s -run-pass=arm-mve-vpt-opts -o - | FileCheck %s + +--- | + target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" + target triple = "thumbv8.1m.main-unknown-none-eabihf" + + define i1 @_Z9reproducePKfPvj4Typex(ptr %output, i32 %size, i8 %type, i64 %zero) #0 { + entry: + %0 = zext i8 %type to i32 + switch i32 %0, label %common.ret1 [ + i32 4, label %for.cond52.preheader + i32 3, label %for.cond37.preheader + ] + + for.cond52.preheader: ; preds = %entry + %cmp5399.not = icmp eq i32 %size, 0 + %1 = call { i32, i1 } @llvm.test.start.loop.iterations.i32(i32 %size) + %2 = extractvalue { i32, i1 } %1, 1 + %3 = extractvalue { i32, i1 } %1, 0 + br i1 %2, label %for.body55.lr.ph, label %common.ret1 + + for.body55.lr.ph: ; preds = %for.cond52.preheader + %conv56 = sitofp i64 %zero to float + br label %for.body55 + + common.ret1: ; preds = %for.body55, %for.cond37.preheader, %for.cond52.preheader, %entry + %common.ret1.op = phi i1 [ true, %for.cond37.preheader ], [ false, %entry ], [ false, %for.cond52.preheader ], [ false, %for.body55 ] + ret i1 %common.ret1.op + + for.cond37.preheader: ; preds = %entry + br label %common.ret1 + + for.body55: ; preds = %for.body55, %for.body55.lr.ph + %4 = phi i32 [ %3, %for.body55.lr.ph ], [ %5, %for.body55 ] + %conv59 = fptosi float %conv56 to i64 + store i64 %conv59, ptr %output, align 8 + %5 = call i32 @llvm.loop.decrement.reg.i32(i32 %4, i32 1) + %6 = icmp ne i32 %5, 0 + br i1 %6, label %for.body55, label %common.ret1 + } + + attributes #0 = { "target-cpu"="cortex-m55" } + attributes #1 = { nocallback noduplicate nofree nosync nounwind willreturn } +... +--- +name: _Z9reproducePKfPvj4Typex +tracksRegLiveness: true +fixedStack: + - { id: 0, type: default, offset: 4, size: 4, alignment: 4, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } + - { id: 1, type: default, offset: 0, size: 4, alignment: 8, stack-id: default, + isImmutable: true, isAliased: false, callee-saved-register: '', callee-saved-restored: true, + debug-info-variable: '', debug-info-expression: '', debug-info-location: '' } +machineFunctionInfo: + isLRSpilled: false +body: | + ; CHECK-LABEL: name: _Z9reproducePKfPvj4Typex + ; CHECK: bb.0.entry: + ; CHECK-NEXT: successors: %bb.6(0x2aaaaaab), %bb.1(0x55555555) + ; CHECK-NEXT: liveins: $r0, $r1, $r2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:rgpr = COPY $r2 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:rgpr = COPY $r1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[t2UXTB:%[0-9]+]]:rgpr = t2UXTB [[COPY]], 0, 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2CMPri [[t2UXTB]], 3, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2Bcc %bb.6, 0 /* CC::eq */, $cpsr + ; CHECK-NEXT: t2B %bb.1, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.entry: + ; CHECK-NEXT: successors: %bb.3(0x40000001), %bb.2(0x3fffffff) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: t2CMPri [[t2UXTB]], 4, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2Bcc %bb.3, 0 /* CC::eq */, $cpsr + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2: + ; CHECK-NEXT: successors: %bb.5(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[t2MOVi:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gpr = COPY [[t2MOVi]] + ; CHECK-NEXT: t2B %bb.5, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.for.cond52.preheader: + ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.5(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[t2MOVi1:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:gpr = COPY [[t2MOVi1]] + ; CHECK-NEXT: t2CMPri [[COPY1]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2Bcc %bb.5, 0 /* CC::eq */, $cpsr + ; CHECK-NEXT: t2B %bb.4, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.for.body55.lr.ph: + ; CHECK-NEXT: successors: %bb.7(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[t2LDRi12_:%[0-9]+]]:gpr = t2LDRi12 %fixed-stack.1, 0, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.1) + ; CHECK-NEXT: [[t2LDRi12_1:%[0-9]+]]:gpr = t2LDRi12 %fixed-stack.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0, align 8) + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:gpr = COPY [[COPY1]] + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: $r0 = COPY [[t2LDRi12_1]] + ; CHECK-NEXT: $r1 = COPY [[t2LDRi12_]] + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, &__aeabi_l2f, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def $r0 + ; CHECK-NEXT: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:gpr = COPY [[COPY6]] + ; CHECK-NEXT: [[tMOVr:%[0-9]+]]:gprlr = tMOVr [[COPY1]], 14 /* CC::al */, $noreg + ; CHECK-NEXT: t2B %bb.7, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.5.common.ret1: + ; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[COPY3]], %bb.2, %15, %bb.6, [[COPY4]], %bb.3, %16, %bb.7 + ; CHECK-NEXT: $r0 = COPY [[PHI]] + ; CHECK-NEXT: tBX_RET 14 /* CC::al */, $noreg, implicit $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.6.for.cond37.preheader: + ; CHECK-NEXT: successors: %bb.5(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[t2MOVi2:%[0-9]+]]:rgpr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:gpr = COPY [[t2MOVi2]] + ; CHECK-NEXT: t2B %bb.5, 14 /* CC::al */, $noreg + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.7.for.body55: + ; CHECK-NEXT: successors: %bb.7(0x7c000000), %bb.5(0x04000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gprlr = PHI [[COPY5]], %bb.4, %19, %bb.7 + ; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: $r0 = COPY [[COPY7]] + ; CHECK-NEXT: tBL 14 /* CC::al */, $noreg, &__aeabi_f2lz, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def $r0, implicit-def $r1 + ; CHECK-NEXT: ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp + ; CHECK-NEXT: [[COPY9:%[0-9]+]]:gpr = COPY $r0 + ; CHECK-NEXT: [[COPY10:%[0-9]+]]:gpr = COPY $r1 + ; CHECK-NEXT: t2STRi12 [[COPY10]], [[COPY2]], 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.output + 4, basealign 8) + ; CHECK-NEXT: t2STRi12 [[COPY9]], [[COPY2]], 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.output, align 8) + ; CHECK-NEXT: [[t2SUBri:%[0-9]+]]:gprlr = t2SUBri [[PHI1]], 1, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: [[COPY11:%[0-9]+]]:gpr = COPY [[t2SUBri]] + ; CHECK-NEXT: [[t2MOVi3:%[0-9]+]]:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: [[COPY12:%[0-9]+]]:gpr = COPY [[t2MOVi3]] + ; CHECK-NEXT: t2CMPri [[t2SUBri]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr + ; CHECK-NEXT: t2Bcc %bb.7, 1 /* CC::ne */, $cpsr + ; CHECK-NEXT: t2B %bb.5, 14 /* CC::al */, $noreg + bb.0.entry: + successors: %bb.4(0x2aaaaaab), %bb.6(0x55555555) + liveins: $r0, $r1, $r2 + + %7:rgpr = COPY $r2 + %6:rgpr = COPY $r1 + %5:gpr = COPY $r0 + %12:rgpr = t2UXTB %7, 0, 14 /* CC::al */, $noreg + t2CMPri %12, 3, 14 /* CC::al */, $noreg, implicit-def $cpsr + t2Bcc %bb.4, 0 /* CC::eq */, $cpsr + t2B %bb.6, 14 /* CC::al */, $noreg + + bb.6.entry: + successors: %bb.1(0x40000001), %bb.7(0x3fffffff) + + t2CMPri %12, 4, 14 /* CC::al */, $noreg, implicit-def $cpsr + t2Bcc %bb.1, 0 /* CC::eq */, $cpsr + + bb.7: + successors: %bb.3(0x80000000) + + %13:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + %10:gpr = COPY %13 + t2B %bb.3, 14 /* CC::al */, $noreg + + bb.1.for.cond52.preheader: + successors: %bb.2(0x40000000), %bb.3(0x40000000) + + %17:gprlr = t2WhileLoopSetup %6 + %18:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + %16:gpr = COPY %18 + t2WhileLoopStart %17, %bb.3, implicit-def dead $cpsr + t2B %bb.2, 14 /* CC::al */, $noreg + + bb.2.for.body55.lr.ph: + successors: %bb.5(0x80000000) + + %9:gpr = t2LDRi12 %fixed-stack.0, 0, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.0) + %8:gpr = t2LDRi12 %fixed-stack.1, 0, 14 /* CC::al */, $noreg :: (load (s32) from %fixed-stack.1, align 8) + %0:gpr = COPY %17 + ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp + $r0 = COPY %8 + $r1 = COPY %9 + tBL 14 /* CC::al */, $noreg, &__aeabi_l2f, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit $r1, implicit-def $sp, implicit-def $r0 + ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp + %19:gpr = COPY $r0 + %27:gpr = COPY %19 + t2B %bb.5, 14 /* CC::al */, $noreg + + bb.3.common.ret1: + %2:gpr = PHI %10, %bb.7, %14, %bb.4, %16, %bb.1, %20, %bb.5 + $r0 = COPY %2 + tBX_RET 14 /* CC::al */, $noreg, implicit $r0 + + bb.4.for.cond37.preheader: + successors: %bb.3(0x80000000) + + %15:rgpr = t2MOVi 1, 14 /* CC::al */, $noreg, $noreg + %14:gpr = COPY %15 + t2B %bb.3, 14 /* CC::al */, $noreg + + bb.5.for.body55: + successors: %bb.5(0x7c000000), %bb.3(0x04000000) + + %3:gprlr = PHI %0, %bb.2, %4, %bb.5 + ADJCALLSTACKDOWN 0, 0, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp + $r0 = COPY %27 + tBL 14 /* CC::al */, $noreg, &__aeabi_f2lz, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit $r0, implicit-def $sp, implicit-def $r0, implicit-def $r1 + ADJCALLSTACKUP 0, -1, 14 /* CC::al */, $noreg, implicit-def dead $sp, implicit $sp + %22:gpr = COPY $r0 + %23:gpr = COPY $r1 + t2STRi12 %23, %5, 4, 14 /* CC::al */, $noreg :: (store (s32) into %ir.output + 4, basealign 8) + t2STRi12 %22, %5, 0, 14 /* CC::al */, $noreg :: (store (s32) into %ir.output, align 8) + %24:gprlr = t2LoopDec %3, 1 + %4:gpr = COPY %24 + %26:rgpr = t2MOVi 0, 14 /* CC::al */, $noreg, $noreg + %20:gpr = COPY %26 + t2LoopEnd %24, %bb.5, implicit-def dead $cpsr + t2B %bb.3, 14 /* CC::al */, $noreg +... From 1c39076b571a0427d1501959815fcb52168e2ce8 Mon Sep 17 00:00:00 2001 From: Zhen Wang Date: Sat, 24 Oct 2026 12:57:50 -0700 Subject: [PATCH 22/31] [flang][acc] Name deviceptr objects on the exit of a local declare (#235089) A structured `acc declare deviceptr(a)` inside a procedure lowers to an `acc.declare_enter` whose data operands include the deviceptr op, but the matching `acc.declare_exit` carried no operands for it. The runtime therefore saw the region opened at the enter and never closed, and the entry registered for `a` survived the end of the procedure. With a dummy argument this leaks one present table entry per call. Append the deviceptr entry ops to the `acc.declare_exit` operands in `genDeclareInFunction`, the same way the present clause is handled. No copyout or delete is generated for deviceptr. The runtime conversion then emits the data end call for the exit. The lowering test checks that the exit names the deviceptr object and that no delete is produced. --- flang/lib/Lower/OpenACC.cpp | 11 +++++++++-- flang/test/Lower/OpenACC/acc-declare.f90 | 8 ++++++-- 2 files changed, 15 insertions(+), 4 deletions(-) diff --git a/flang/lib/Lower/OpenACC.cpp b/flang/lib/Lower/OpenACC.cpp index 116d6e24df0f92..473829117b5d6f 100644 --- a/flang/lib/Lower/OpenACC.cpp +++ b/flang/lib/Lower/OpenACC.cpp @@ -4487,7 +4487,7 @@ genDeclareInFunction(Fortran::lower::AbstractConverter &converter, const Fortran::parser::AccClauseList &accClauseList) { llvm::SmallVector dataClauseOperands, copyEntryOperands, copyinEntryOperands, createEntryOperands, copyoutEntryOperands, - presentEntryOperands, deviceResidentEntryOperands; + presentEntryOperands, deviceResidentEntryOperands, devicePtrEntryOperands; Fortran::lower::StatementContext stmtCtx; fir::FirOpBuilder &builder = converter.getFirOpBuilder(); @@ -4551,11 +4551,16 @@ genDeclareInFunction(Fortran::lower::AbstractConverter &converter, } else if (const auto *devicePtrClause = std::get_if( &clause.u)) { + auto crtDataStart = dataClauseOperands.size(); genDeclareDataOperandOperations( devicePtrClause->v, converter, semanticsContext, stmtCtx, dataClauseOperands, mlir::acc::DataClause::acc_deviceptr, /*structured=*/true, /*implicit=*/false); + // No exit action, but the exit still names the object so the runtime + // closes the region it opened at the enter. + devicePtrEntryOperands.append(dataClauseOperands.begin() + crtDataStart, + dataClauseOperands.end()); } else if (const auto *linkClause = std::get_if(&clause.u)) { genDeclareDataOperandOperations operands; operands.append(createEntryOperands); operands.append(deviceResidentEntryOperands); @@ -4614,6 +4620,7 @@ genDeclareInFunction(Fortran::lower::AbstractConverter &converter, operands.append(copyinEntryOperands); operands.append(copyoutEntryOperands); operands.append(presentEntryOperands); + operands.append(devicePtrEntryOperands); mlir::func::FuncOp funcOp = builder.getFunction(); auto ops = funcOp.getOps(); diff --git a/flang/test/Lower/OpenACC/acc-declare.f90 b/flang/test/Lower/OpenACC/acc-declare.f90 index 4aa7203716d6ea..dd0a67347984b5 100644 --- a/flang/test/Lower/OpenACC/acc-declare.f90 +++ b/flang/test/Lower/OpenACC/acc-declare.f90 @@ -134,8 +134,11 @@ subroutine acc_declare_deviceptr(a) ! CHECK-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "a"}) { ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ARG0]](%{{.*}}) dummy_scope %{{[0-9]+}} arg {{[0-9]+}} uniq_name("_QMacc_declareFacc_declare_deviceptrEa") {acc.declare = #acc.declare} : (!fir.ref>, !fir.shape<1>, !fir.dscope) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[DEVICEPTR:.*]] = acc.deviceptr varPtr(%[[DECL]]#0 : !fir.ref>) name("a") -> !fir.ref> -! CHECK: acc.declare_enter dataOperands(%[[DEVICEPTR]] : !fir.ref>) +! CHECK: %[[TOKEN:.*]] = acc.declare_enter dataOperands(%[[DEVICEPTR]] : !fir.ref>) ! CHECK: fir.do_loop %{{.*}} = %{{.*}} to %{{.*}} step %{{.*}} { +! CHECK: acc.declare_exit token(%[[TOKEN]]) dataOperands(%[[DEVICEPTR]] : !fir.ref>) +! CHECK-NOT: acc.delete +! CHECK: return subroutine acc_declare_link(a) integer :: a(100), i @@ -207,7 +210,8 @@ subroutine acc_declare_deviceptr2() ! CHECK: %[[ALLOCA:.*]] = fir.alloca !fir.array<100xf32> <{bindc_name = "dataparam", uniq_name = "_QMacc_declareFacc_declare_deviceptr2Edataparam"}> ! CHECK: %[[DECL:.*]]:2 = hlfir.declare %[[ALLOCA]](%{{.*}}) uniq_name("_QMacc_declareFacc_declare_deviceptr2Edataparam") {acc.declare = #acc.declare} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) ! CHECK: %[[DEVICEPTR:.*]] = acc.deviceptr varPtr(%[[DECL]]#0 : !fir.ref>) name("dataparam") -> !fir.ref> -! CHECK: acc.declare_enter dataOperands(%[[DEVICEPTR]] : !fir.ref>) +! CHECK: %[[TOKEN:.*]] = acc.declare_enter dataOperands(%[[DEVICEPTR]] : !fir.ref>) +! CHECK: acc.declare_exit token(%[[TOKEN]]) dataOperands(%[[DEVICEPTR]] : !fir.ref>) function acc_declare_in_func() real :: a(1024) From e312addd710b80a4dd14389b71c649594fccedd0 Mon Sep 17 00:00:00 2001 From: Popie <86546258+Popie52@users.noreply.github.com> Date: Sun, 25 Oct 2026 01:48:09 +0530 Subject: [PATCH 23/31] [libc] Modify NaN/payload functions for emulated float128 type (#221946) Updated `nanf128`, `getpayloadf128`, `setpayloadf128`, and `setpayloadsigf128` for emulated `float128`, including shared headers, entrypoints, CMake/Bazel dependencies, wrappers, and tests. closes #221574 --- libc/config/baremetal/aarch64/entrypoints.txt | 8 ++-- libc/config/baremetal/arm/entrypoints.txt | 8 ++-- libc/config/baremetal/riscv/entrypoints.txt | 8 ++-- libc/config/darwin/aarch64/entrypoints.txt | 8 ++-- libc/config/freebsd/x86_64/entrypoints.txt | 8 ++-- libc/config/gpu/amdgpu/entrypoints.txt | 4 ++ libc/config/gpu/nvptx/entrypoints.txt | 4 ++ libc/config/linux/aarch64/entrypoints.txt | 8 ++-- libc/config/linux/arm/entrypoints.txt | 4 ++ libc/config/linux/riscv/entrypoints.txt | 8 ++-- libc/config/linux/x86_64/entrypoints.txt | 8 ++-- libc/config/windows/entrypoints.txt | 4 ++ libc/shared/math/getpayloadf128.h | 13 +++---- libc/shared/math/nanf128.h | 13 +++---- libc/shared/math/setpayloadf128.h | 13 +++---- libc/shared/math/setpayloadsigf128.h | 13 +++---- libc/src/__support/math/CMakeLists.txt | 10 ++--- libc/src/__support/math/getpayloadf128.h | 18 +++++---- libc/src/__support/math/nanf128.h | 20 +++++----- libc/src/__support/math/setpayloadf128.h | 18 +++++---- libc/src/__support/math/setpayloadsigf128.h | 18 +++++---- libc/src/math/generic/CMakeLists.txt | 4 ++ libc/src/math/generic/getpayloadf128.cpp | 13 ++++++- libc/src/math/generic/nanf128.cpp | 10 ++++- libc/src/math/generic/setpayloadf128.cpp | 13 ++++++- libc/src/math/generic/setpayloadsigf128.cpp | 13 ++++++- libc/src/math/getpayloadf128.h | 12 +++++- libc/src/math/nanf128.h | 12 +++++- libc/src/math/setpayloadf128.h | 12 +++++- libc/src/math/setpayloadsigf128.h | 12 +++++- libc/test/shared/CMakeLists.txt | 6 +++ .../shared/shared_math_constexpr_test.cpp | 38 +++++++++---------- libc/test/shared/shared_math_test.cpp | 35 +++++++++-------- libc/test/src/math/smoke/CMakeLists.txt | 6 ++- .../src/math/smoke/getpayloadf128_test.cpp | 12 +++++- libc/test/src/math/smoke/nanf128_test.cpp | 12 +++++- .../src/math/smoke/setpayloadf128_test.cpp | 12 +++++- .../src/math/smoke/setpayloadsigf128_test.cpp | 12 +++++- .../llvm-project-overlay/libc/BUILD.bazel | 16 ++++++-- .../libc/test/src/math/smoke/BUILD.bazel | 17 ++++++++- 40 files changed, 329 insertions(+), 154 deletions(-) diff --git a/libc/config/baremetal/aarch64/entrypoints.txt b/libc/config/baremetal/aarch64/entrypoints.txt index 7ec212d8709692..0202bc7a2dc56b 100644 --- a/libc/config/baremetal/aarch64/entrypoints.txt +++ b/libc/config/baremetal/aarch64/entrypoints.txt @@ -486,6 +486,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.fsubl libc.src.math.getpayload libc.src.math.getpayloadf + libc.src.math.getpayloadf128 libc.src.math.getpayloadl libc.src.math.hypot libc.src.math.hypotf @@ -543,6 +544,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.modfl libc.src.math.nan libc.src.math.nanf + libc.src.math.nanf128 libc.src.math.nanl libc.src.math.nearbyint libc.src.math.nearbyintf @@ -588,9 +590,11 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.scalbnl libc.src.math.setpayload libc.src.math.setpayloadf + libc.src.math.setpayloadf128 libc.src.math.setpayloadl libc.src.math.setpayloadsig libc.src.math.setpayloadsigf + libc.src.math.setpayloadsigf128 libc.src.math.setpayloadsigl libc.src.math.sin libc.src.math.sincos @@ -782,13 +786,11 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.fromfpxf128 libc.src.math.fsqrtf128 libc.src.math.fsubf128 - libc.src.math.getpayloadf128 libc.src.math.ilogbf128 libc.src.math.ldexpf128 libc.src.math.llogbf128 libc.src.math.logbf128 libc.src.math.modff128 - libc.src.math.nanf128 libc.src.math.nextafterf128 libc.src.math.nextdownf128 libc.src.math.nextupf128 @@ -796,8 +798,6 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.remquof128 libc.src.math.scalblnf128 libc.src.math.scalbnf128 - libc.src.math.setpayloadf128 - libc.src.math.setpayloadsigf128 libc.src.math.totalorderf128 libc.src.math.totalordermagf128 libc.src.math.ufromfpf128 diff --git a/libc/config/baremetal/arm/entrypoints.txt b/libc/config/baremetal/arm/entrypoints.txt index 779d9fc23b28e8..b7322502d570d4 100644 --- a/libc/config/baremetal/arm/entrypoints.txt +++ b/libc/config/baremetal/arm/entrypoints.txt @@ -498,6 +498,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.fsubl libc.src.math.getpayload libc.src.math.getpayloadf + libc.src.math.getpayloadf128 libc.src.math.getpayloadl libc.src.math.hypot libc.src.math.hypotf @@ -555,6 +556,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.modfl libc.src.math.nan libc.src.math.nanf + libc.src.math.nanf128 libc.src.math.nanl libc.src.math.nearbyint libc.src.math.nearbyintf @@ -600,9 +602,11 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.scalbnl libc.src.math.setpayload libc.src.math.setpayloadf + libc.src.math.setpayloadf128 libc.src.math.setpayloadl libc.src.math.setpayloadsig libc.src.math.setpayloadsigf + libc.src.math.setpayloadsigf128 libc.src.math.setpayloadsigl libc.src.math.sin libc.src.math.sincos @@ -793,13 +797,11 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.fromfpxf128 libc.src.math.fsqrtf128 libc.src.math.fsubf128 - libc.src.math.getpayloadf128 libc.src.math.ilogbf128 libc.src.math.ldexpf128 libc.src.math.llogbf128 libc.src.math.logbf128 libc.src.math.modff128 - libc.src.math.nanf128 libc.src.math.nextafterf128 libc.src.math.nextdownf128 libc.src.math.nextupf128 @@ -807,8 +809,6 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.remquof128 libc.src.math.scalblnf128 libc.src.math.scalbnf128 - libc.src.math.setpayloadf128 - libc.src.math.setpayloadsigf128 libc.src.math.totalorderf128 libc.src.math.totalordermagf128 libc.src.math.ufromfpf128 diff --git a/libc/config/baremetal/riscv/entrypoints.txt b/libc/config/baremetal/riscv/entrypoints.txt index b847a2bb1f47f0..7e68a3c374249d 100644 --- a/libc/config/baremetal/riscv/entrypoints.txt +++ b/libc/config/baremetal/riscv/entrypoints.txt @@ -489,6 +489,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.fsubl libc.src.math.getpayload libc.src.math.getpayloadf + libc.src.math.getpayloadf128 libc.src.math.getpayloadl libc.src.math.hypot libc.src.math.hypotf @@ -546,6 +547,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.modfl libc.src.math.nan libc.src.math.nanf + libc.src.math.nanf128 libc.src.math.nanl libc.src.math.nearbyint libc.src.math.nearbyintf @@ -591,9 +593,11 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.scalbnl libc.src.math.setpayload libc.src.math.setpayloadf + libc.src.math.setpayloadf128 libc.src.math.setpayloadl libc.src.math.setpayloadsig libc.src.math.setpayloadsigf + libc.src.math.setpayloadsigf128 libc.src.math.setpayloadsigl libc.src.math.sin libc.src.math.sincos @@ -785,13 +789,11 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.fromfpxf128 libc.src.math.fsqrtf128 libc.src.math.fsubf128 - libc.src.math.getpayloadf128 libc.src.math.ilogbf128 libc.src.math.ldexpf128 libc.src.math.llogbf128 libc.src.math.logbf128 libc.src.math.modff128 - libc.src.math.nanf128 libc.src.math.nextafterf128 libc.src.math.nextdownf128 libc.src.math.nextupf128 @@ -799,8 +801,6 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.remquof128 libc.src.math.scalblnf128 libc.src.math.scalbnf128 - libc.src.math.setpayloadf128 - libc.src.math.setpayloadsigf128 libc.src.math.totalorderf128 libc.src.math.totalordermagf128 libc.src.math.ufromfpf128 diff --git a/libc/config/darwin/aarch64/entrypoints.txt b/libc/config/darwin/aarch64/entrypoints.txt index 5600b82ad3410b..c0ce5870c862ec 100644 --- a/libc/config/darwin/aarch64/entrypoints.txt +++ b/libc/config/darwin/aarch64/entrypoints.txt @@ -307,6 +307,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.fsubl libc.src.math.getpayload libc.src.math.getpayloadf + libc.src.math.getpayloadf128 libc.src.math.getpayloadl libc.src.math.hypot libc.src.math.hypotf @@ -364,6 +365,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.modfl libc.src.math.nan libc.src.math.nanf + libc.src.math.nanf128 libc.src.math.nanl libc.src.math.nearbyint libc.src.math.nearbyintf @@ -409,9 +411,11 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.scalbnl libc.src.math.setpayload libc.src.math.setpayloadf + libc.src.math.setpayloadf128 libc.src.math.setpayloadl libc.src.math.setpayloadsig libc.src.math.setpayloadsigf + libc.src.math.setpayloadsigf128 libc.src.math.setpayloadsigl libc.src.math.sin libc.src.math.sincos @@ -604,13 +608,11 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.fromfpxf128 libc.src.math.fsqrtf128 libc.src.math.fsubf128 - libc.src.math.getpayloadf128 libc.src.math.ilogbf128 libc.src.math.ldexpf128 libc.src.math.llogbf128 libc.src.math.logbf128 libc.src.math.modff128 - libc.src.math.nanf128 libc.src.math.nextafterf128 libc.src.math.nextdownf128 libc.src.math.nextupf128 @@ -618,8 +620,6 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.remquof128 libc.src.math.scalblnf128 libc.src.math.scalbnf128 - libc.src.math.setpayloadf128 - libc.src.math.setpayloadsigf128 libc.src.math.totalorderf128 libc.src.math.totalordermagf128 libc.src.math.ufromfpf128 diff --git a/libc/config/freebsd/x86_64/entrypoints.txt b/libc/config/freebsd/x86_64/entrypoints.txt index 8f6c178301c2f2..42d52b3ebc6c2c 100644 --- a/libc/config/freebsd/x86_64/entrypoints.txt +++ b/libc/config/freebsd/x86_64/entrypoints.txt @@ -267,6 +267,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.modfl libc.src.math.nan libc.src.math.nanf + libc.src.math.nanf128 libc.src.math.nanl libc.src.math.nearbyint libc.src.math.nearbyintf @@ -347,6 +348,7 @@ list(APPEND TARGET_LIBM_ENTRYPOINTS libc.src.math.fsqrtl libc.src.math.getpayload libc.src.math.getpayloadf + libc.src.math.getpayloadf128 libc.src.math.getpayloadl libc.src.math.iscanonical libc.src.math.iscanonicalf @@ -371,9 +373,11 @@ list(APPEND TARGET_LIBM_ENTRYPOINTS libc.src.math.roundevenl libc.src.math.setpayload libc.src.math.setpayloadf + libc.src.math.setpayloadf128 libc.src.math.setpayloadl libc.src.math.setpayloadsig libc.src.math.setpayloadsigf + libc.src.math.setpayloadsigf128 libc.src.math.setpayloadsigl libc.src.math.sincos libc.src.math.sinpif @@ -537,13 +541,11 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.fromfpxf128 libc.src.math.fsqrtf128 libc.src.math.fsubf128 - libc.src.math.getpayloadf128 libc.src.math.ilogbf128 libc.src.math.ldexpf128 libc.src.math.llogbf128 libc.src.math.logbf128 libc.src.math.modff128 - libc.src.math.nanf128 libc.src.math.nextafterf128 libc.src.math.nextdownf128 libc.src.math.nextupf128 @@ -551,8 +553,6 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.remquof128 libc.src.math.scalblnf128 libc.src.math.scalbnf128 - libc.src.math.setpayloadf128 - libc.src.math.setpayloadsigf128 libc.src.math.totalorderf128 libc.src.math.totalordermagf128 libc.src.math.ufromfpf128 diff --git a/libc/config/gpu/amdgpu/entrypoints.txt b/libc/config/gpu/amdgpu/entrypoints.txt index 2eaef608e9a7ac..ffbcc4b1672403 100644 --- a/libc/config/gpu/amdgpu/entrypoints.txt +++ b/libc/config/gpu/amdgpu/entrypoints.txt @@ -428,6 +428,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.fsubl libc.src.math.getpayload libc.src.math.getpayloadf + libc.src.math.getpayloadf128 libc.src.math.getpayloadl libc.src.math.hypot libc.src.math.hypotf @@ -481,6 +482,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.modfl libc.src.math.nan libc.src.math.nanf + libc.src.math.nanf128 libc.src.math.nanl libc.src.math.nearbyint libc.src.math.nearbyintf @@ -526,9 +528,11 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.scalbnl libc.src.math.setpayload libc.src.math.setpayloadf + libc.src.math.setpayloadf128 libc.src.math.setpayloadl libc.src.math.setpayloadsig libc.src.math.setpayloadsigf + libc.src.math.setpayloadsigf128 libc.src.math.setpayloadsigl libc.src.math.sin libc.src.math.sincos diff --git a/libc/config/gpu/nvptx/entrypoints.txt b/libc/config/gpu/nvptx/entrypoints.txt index 79d0c733ec3c01..ff31536073543e 100644 --- a/libc/config/gpu/nvptx/entrypoints.txt +++ b/libc/config/gpu/nvptx/entrypoints.txt @@ -425,6 +425,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.fsubl libc.src.math.getpayload libc.src.math.getpayloadf + libc.src.math.getpayloadf128 libc.src.math.getpayloadl libc.src.math.hypot libc.src.math.hypotf @@ -478,6 +479,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.modfl libc.src.math.nan libc.src.math.nanf + libc.src.math.nanf128 libc.src.math.nanl libc.src.math.nearbyint libc.src.math.nearbyintf @@ -523,9 +525,11 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.scalbnl libc.src.math.setpayload libc.src.math.setpayloadf + libc.src.math.setpayloadf128 libc.src.math.setpayloadl libc.src.math.setpayloadsig libc.src.math.setpayloadsigf + libc.src.math.setpayloadsigf128 libc.src.math.setpayloadsigl libc.src.math.sin libc.src.math.sincos diff --git a/libc/config/linux/aarch64/entrypoints.txt b/libc/config/linux/aarch64/entrypoints.txt index ae4d060ad2e65c..b193733a02dc5f 100644 --- a/libc/config/linux/aarch64/entrypoints.txt +++ b/libc/config/linux/aarch64/entrypoints.txt @@ -724,6 +724,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.fsubl libc.src.math.getpayload libc.src.math.getpayloadf + libc.src.math.getpayloadf128 libc.src.math.getpayloadl libc.src.math.hypot libc.src.math.hypotf @@ -781,6 +782,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.modfl libc.src.math.nan libc.src.math.nanf + libc.src.math.nanf128 libc.src.math.nanl libc.src.math.nearbyint libc.src.math.nearbyintf @@ -826,9 +828,11 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.scalbnl libc.src.math.setpayload libc.src.math.setpayloadf + libc.src.math.setpayloadf128 libc.src.math.setpayloadl libc.src.math.setpayloadsig libc.src.math.setpayloadsigf + libc.src.math.setpayloadsigf128 libc.src.math.setpayloadsigl libc.src.math.sin libc.src.math.sincos @@ -1014,13 +1018,11 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.fromfpxf128 libc.src.math.fsqrtf128 libc.src.math.fsubf128 - libc.src.math.getpayloadf128 libc.src.math.ilogbf128 libc.src.math.ldexpf128 libc.src.math.llogbf128 libc.src.math.logbf128 libc.src.math.modff128 - libc.src.math.nanf128 libc.src.math.nextafterf128 libc.src.math.nextdownf128 libc.src.math.nextupf128 @@ -1028,8 +1030,6 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.remquof128 libc.src.math.scalblnf128 libc.src.math.scalbnf128 - libc.src.math.setpayloadf128 - libc.src.math.setpayloadsigf128 libc.src.math.totalorderf128 libc.src.math.totalordermagf128 libc.src.math.ufromfpf128 diff --git a/libc/config/linux/arm/entrypoints.txt b/libc/config/linux/arm/entrypoints.txt index e35ca9c7211ab3..8c7ebf61d5786d 100644 --- a/libc/config/linux/arm/entrypoints.txt +++ b/libc/config/linux/arm/entrypoints.txt @@ -513,6 +513,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.fsubl libc.src.math.getpayload libc.src.math.getpayloadf + libc.src.math.getpayloadf128 libc.src.math.getpayloadl libc.src.math.hypot libc.src.math.hypotf @@ -561,6 +562,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.modfl libc.src.math.nan libc.src.math.nanf + libc.src.math.nanf128 libc.src.math.nanl libc.src.math.nearbyint libc.src.math.nearbyintf @@ -603,9 +605,11 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.scalbnl libc.src.math.setpayload libc.src.math.setpayloadf + libc.src.math.setpayloadf128 libc.src.math.setpayloadl libc.src.math.setpayloadsig libc.src.math.setpayloadsigf + libc.src.math.setpayloadsigf128 libc.src.math.setpayloadsigl libc.src.math.sin libc.src.math.sincos diff --git a/libc/config/linux/riscv/entrypoints.txt b/libc/config/linux/riscv/entrypoints.txt index f8906e3adbfd30..273b865173bcec 100644 --- a/libc/config/linux/riscv/entrypoints.txt +++ b/libc/config/linux/riscv/entrypoints.txt @@ -785,6 +785,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.fsubl libc.src.math.getpayload libc.src.math.getpayloadf + libc.src.math.getpayloadf128 libc.src.math.getpayloadl libc.src.math.hypot libc.src.math.hypotf @@ -842,6 +843,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.modfl libc.src.math.nan libc.src.math.nanf + libc.src.math.nanf128 libc.src.math.nanl libc.src.math.nearbyint libc.src.math.nearbyintf @@ -887,9 +889,11 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.scalbnl libc.src.math.setpayload libc.src.math.setpayloadf + libc.src.math.setpayloadf128 libc.src.math.setpayloadl libc.src.math.setpayloadsig libc.src.math.setpayloadsigf + libc.src.math.setpayloadsigf128 libc.src.math.setpayloadsigl libc.src.math.sin libc.src.math.sincos @@ -1092,13 +1096,11 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.fromfpxf128 libc.src.math.fsqrtf128 libc.src.math.fsubf128 - libc.src.math.getpayloadf128 libc.src.math.ilogbf128 libc.src.math.ldexpf128 libc.src.math.llogbf128 libc.src.math.logbf128 libc.src.math.modff128 - libc.src.math.nanf128 libc.src.math.nextafterf128 libc.src.math.nextdownf128 libc.src.math.nextupf128 @@ -1106,8 +1108,6 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.remquof128 libc.src.math.scalblnf128 libc.src.math.scalbnf128 - libc.src.math.setpayloadf128 - libc.src.math.setpayloadsigf128 libc.src.math.totalorderf128 libc.src.math.totalordermagf128 libc.src.math.ufromfpf128 diff --git a/libc/config/linux/x86_64/entrypoints.txt b/libc/config/linux/x86_64/entrypoints.txt index 5d67548617ea5b..1769cfbfaa9b43 100644 --- a/libc/config/linux/x86_64/entrypoints.txt +++ b/libc/config/linux/x86_64/entrypoints.txt @@ -807,6 +807,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.fsubl libc.src.math.getpayload libc.src.math.getpayloadf + libc.src.math.getpayloadf128 libc.src.math.getpayloadl libc.src.math.hypot libc.src.math.hypotf @@ -864,6 +865,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.modfl libc.src.math.nan libc.src.math.nanf + libc.src.math.nanf128 libc.src.math.nanl libc.src.math.nearbyint libc.src.math.nearbyintf @@ -909,9 +911,11 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.scalbnl libc.src.math.setpayload libc.src.math.setpayloadf + libc.src.math.setpayloadf128 libc.src.math.setpayloadl libc.src.math.setpayloadsig libc.src.math.setpayloadsigf + libc.src.math.setpayloadsigf128 libc.src.math.setpayloadsigl libc.src.math.sin libc.src.math.sincos @@ -1114,13 +1118,11 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.fromfpxf128 libc.src.math.fsqrtf128 libc.src.math.fsubf128 - libc.src.math.getpayloadf128 libc.src.math.ilogbf128 libc.src.math.ldexpf128 libc.src.math.llogbf128 libc.src.math.logbf128 libc.src.math.modff128 - libc.src.math.nanf128 libc.src.math.nextafterf128 libc.src.math.nextdownf128 libc.src.math.nextupf128 @@ -1128,8 +1130,6 @@ if(LIBC_TYPES_HAS_NATIVE_FLOAT128) libc.src.math.remquof128 libc.src.math.scalblnf128 libc.src.math.scalbnf128 - libc.src.math.setpayloadf128 - libc.src.math.setpayloadsigf128 libc.src.math.totalorderf128 libc.src.math.totalordermagf128 libc.src.math.ufromfpf128 diff --git a/libc/config/windows/entrypoints.txt b/libc/config/windows/entrypoints.txt index 1712b2ad26fda4..e0477cbf5a6f00 100644 --- a/libc/config/windows/entrypoints.txt +++ b/libc/config/windows/entrypoints.txt @@ -300,6 +300,7 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.modfl libc.src.math.nan libc.src.math.nanf + libc.src.math.nanf128 libc.src.math.nanl libc.src.math.nearbyint libc.src.math.nearbyintf @@ -396,6 +397,7 @@ list(APPEND TARGET_LIBM_ENTRYPOINTS libc.src.math.fromfpbf16 libc.src.math.fromfpxbf16 libc.src.math.getpayloadbf16 + libc.src.math.getpayloadf128 libc.src.math.hypotbf16 libc.src.math.ilogbbf16 libc.src.math.iscanonicalbf16 @@ -423,7 +425,9 @@ list(APPEND TARGET_LIBM_ENTRYPOINTS libc.src.math.scalblnbf16 libc.src.math.scalbnbf16 libc.src.math.setpayloadbf16 + libc.src.math.setpayloadf128 libc.src.math.setpayloadsigbf16 + libc.src.math.setpayloadsigf128 libc.src.math.sqrtbf16 libc.src.math.tanbf16 libc.src.math.truncbf16 diff --git a/libc/shared/math/getpayloadf128.h b/libc/shared/math/getpayloadf128.h index 1a3845e631a8b6..e1f2d0faedbcb2 100644 --- a/libc/shared/math/getpayloadf128.h +++ b/libc/shared/math/getpayloadf128.h @@ -1,18 +1,19 @@ -//===-- Shared getpayloadf128 function --------------------------*- C++ -*-===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Shared getpayloadf128 function. +/// +//===----------------------------------------------------------------------===// #ifndef LLVM_LIBC_SHARED_MATH_GETPAYLOADF128_H #define LLVM_LIBC_SHARED_MATH_GETPAYLOADF128_H -#include "include/llvm-libc-types/float128.h" - -#ifdef LIBC_TYPES_HAS_NATIVE_FLOAT128 - #include "shared/libc_common.h" #include "src/__support/math/getpayloadf128.h" @@ -24,6 +25,4 @@ using math::getpayloadf128; } // namespace shared } // namespace LIBC_NAMESPACE_DECL -#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 - #endif // LLVM_LIBC_SHARED_MATH_GETPAYLOADF128_H diff --git a/libc/shared/math/nanf128.h b/libc/shared/math/nanf128.h index 313b6ed6234c52..9d80936c14c282 100644 --- a/libc/shared/math/nanf128.h +++ b/libc/shared/math/nanf128.h @@ -1,18 +1,19 @@ -//===-- Shared nanf128 function ---------------------------------*- C++ -*-===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Shared nanf128 function. +/// +//===----------------------------------------------------------------------===// #ifndef LLVM_LIBC_SHARED_MATH_NANF128_H #define LLVM_LIBC_SHARED_MATH_NANF128_H -#include "include/llvm-libc-types/float128.h" - -#ifdef LIBC_TYPES_HAS_NATIVE_FLOAT128 - #include "shared/libc_common.h" #include "src/__support/math/nanf128.h" @@ -24,6 +25,4 @@ using math::nanf128; } // namespace shared } // namespace LIBC_NAMESPACE_DECL -#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 - #endif // LLVM_LIBC_SHARED_MATH_NANF128_H diff --git a/libc/shared/math/setpayloadf128.h b/libc/shared/math/setpayloadf128.h index a1f889e89ed394..ceb339e80ac4f7 100644 --- a/libc/shared/math/setpayloadf128.h +++ b/libc/shared/math/setpayloadf128.h @@ -1,18 +1,19 @@ -//===-- Shared setpayloadf128 function --------------------------*- C++ -*-===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Shared setpayloadf128 function. +/// +//===----------------------------------------------------------------------===// #ifndef LLVM_LIBC_SHARED_MATH_SETPAYLOADF128_H #define LLVM_LIBC_SHARED_MATH_SETPAYLOADF128_H -#include "include/llvm-libc-types/float128.h" - -#ifdef LIBC_TYPES_HAS_NATIVE_FLOAT128 - #include "shared/libc_common.h" #include "src/__support/math/setpayloadf128.h" @@ -24,6 +25,4 @@ using math::setpayloadf128; } // namespace shared } // namespace LIBC_NAMESPACE_DECL -#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 - #endif // LLVM_LIBC_SHARED_MATH_SETPAYLOADF128_H diff --git a/libc/shared/math/setpayloadsigf128.h b/libc/shared/math/setpayloadsigf128.h index 3169b610ccb4d5..92f17abd033a26 100644 --- a/libc/shared/math/setpayloadsigf128.h +++ b/libc/shared/math/setpayloadsigf128.h @@ -1,18 +1,19 @@ -//===-- Shared setpayloadsigf128 function -----------------------*- C++ -*-===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Shared setpayloadsigf128 function. +/// +//===----------------------------------------------------------------------===// #ifndef LLVM_LIBC_SHARED_MATH_SETPAYLOADSIGF128_H #define LLVM_LIBC_SHARED_MATH_SETPAYLOADSIGF128_H -#include "include/llvm-libc-types/float128.h" - -#ifdef LIBC_TYPES_HAS_NATIVE_FLOAT128 - #include "shared/libc_common.h" #include "src/__support/math/setpayloadsigf128.h" @@ -24,6 +25,4 @@ using math::setpayloadsigf128; } // namespace shared } // namespace LIBC_NAMESPACE_DECL -#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 - #endif // LLVM_LIBC_SHARED_MATH_SETPAYLOADSIGF128_H diff --git a/libc/src/__support/math/CMakeLists.txt b/libc/src/__support/math/CMakeLists.txt index c0751d7e15f102..400e5e2d6aeaa8 100644 --- a/libc/src/__support/math/CMakeLists.txt +++ b/libc/src/__support/math/CMakeLists.txt @@ -2181,10 +2181,10 @@ add_header_library( HDRS nanf128.h DEPENDS - libc.include.llvm-libc-types.float128 + libc.src.__support.FPUtil.float128 + libc.src.__support.libc_errno libc.src.__support.macros.config libc.src.__support.str_to_float - libc.src.__support.libc_errno ) add_header_library( @@ -3957,8 +3957,8 @@ add_header_library( HDRS getpayloadf128.h DEPENDS - libc.include.llvm-libc-types.float128 libc.src.__support.FPUtil.basic_operations + libc.src.__support.FPUtil.float128 libc.src.__support.macros.config ) @@ -5036,8 +5036,8 @@ add_header_library( HDRS setpayloadf128.h DEPENDS - libc.include.llvm-libc-types.float128 libc.src.__support.FPUtil.basic_operations + libc.src.__support.FPUtil.float128 libc.src.__support.macros.config ) @@ -5093,8 +5093,8 @@ add_header_library( HDRS setpayloadsigf128.h DEPENDS - libc.include.llvm-libc-types.float128 libc.src.__support.FPUtil.basic_operations + libc.src.__support.FPUtil.float128 libc.src.__support.macros.config ) diff --git a/libc/src/__support/math/getpayloadf128.h b/libc/src/__support/math/getpayloadf128.h index aed53ee4adbce9..b162f227b11cf6 100644 --- a/libc/src/__support/math/getpayloadf128.h +++ b/libc/src/__support/math/getpayloadf128.h @@ -1,32 +1,34 @@ -//===-- Implementation header for getpayloadf128 ----------------*- C++ -*-===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Implementation header for getpayloadf128. +/// +//===----------------------------------------------------------------------===// #ifndef LLVM_LIBC_SRC___SUPPORT_MATH_GETPAYLOADF128_H #define LLVM_LIBC_SRC___SUPPORT_MATH_GETPAYLOADF128_H -#include "include/llvm-libc-types/float128.h" - -#ifdef LIBC_TYPES_HAS_NATIVE_FLOAT128 - #include "src/__support/FPUtil/BasicOperations.h" +#include "src/__support/FPUtil/float128.h" #include "src/__support/macros/config.h" namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE constexpr float128 getpayloadf128(const float128 *x) { +using LIBC_NAMESPACE::fputil::Float128; + +LIBC_INLINE constexpr Float128 getpayloadf128(const Float128 *x) { return fputil::getpayload(*x); } } // namespace math } // namespace LIBC_NAMESPACE_DECL -#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 - #endif // LLVM_LIBC_SRC___SUPPORT_MATH_GETPAYLOADF128_H diff --git a/libc/src/__support/math/nanf128.h b/libc/src/__support/math/nanf128.h index 5cc1010939d3c6..4aaad176059f9b 100644 --- a/libc/src/__support/math/nanf128.h +++ b/libc/src/__support/math/nanf128.h @@ -1,18 +1,20 @@ -//===-- Implementation header for nanf128 -----------------------*- C++ -*-===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Implementation header for nanf128. +/// +//===----------------------------------------------------------------------===// #ifndef LLVM_LIBC_SRC___SUPPORT_MATH_NANF128_H #define LLVM_LIBC_SRC___SUPPORT_MATH_NANF128_H -#include "include/llvm-libc-types/float128.h" - -#ifdef LIBC_TYPES_HAS_NATIVE_FLOAT128 - +#include "src/__support/FPUtil/float128.h" #include "src/__support/libc_errno.h" #include "src/__support/macros/config.h" #include "src/__support/str_to_float.h" @@ -20,8 +22,10 @@ namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE constexpr float128 nanf128(const char *arg) { - auto result = internal::strtonan(arg); +using LIBC_NAMESPACE::fputil::Float128; + +LIBC_INLINE constexpr Float128 nanf128(const char *arg) { + auto result = internal::strtonan(arg); if (result.has_error()) libc_errno = result.error; return result.value; @@ -30,6 +34,4 @@ LIBC_INLINE constexpr float128 nanf128(const char *arg) { } // namespace math } // namespace LIBC_NAMESPACE_DECL -#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 - #endif // LLVM_LIBC_SRC___SUPPORT_MATH_NANF128_H diff --git a/libc/src/__support/math/setpayloadf128.h b/libc/src/__support/math/setpayloadf128.h index 4e022d8ec91d40..8feeef8b9fa9cc 100644 --- a/libc/src/__support/math/setpayloadf128.h +++ b/libc/src/__support/math/setpayloadf128.h @@ -1,32 +1,34 @@ -//===-- Implementation header for setpayloadf128 ----------------*- C++ -*-===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Implementation header for setpayloadf128. +/// +//===----------------------------------------------------------------------===// #ifndef LLVM_LIBC_SRC___SUPPORT_MATH_SETPAYLOADF128_H #define LLVM_LIBC_SRC___SUPPORT_MATH_SETPAYLOADF128_H -#include "include/llvm-libc-types/float128.h" - -#ifdef LIBC_TYPES_HAS_NATIVE_FLOAT128 - #include "src/__support/FPUtil/BasicOperations.h" +#include "src/__support/FPUtil/float128.h" #include "src/__support/macros/config.h" namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE constexpr int setpayloadf128(float128 *res, float128 pl) { +using LIBC_NAMESPACE::fputil::Float128; + +LIBC_INLINE constexpr int setpayloadf128(Float128 *res, Float128 pl) { return static_cast(fputil::setpayload(*res, pl)); } } // namespace math } // namespace LIBC_NAMESPACE_DECL -#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 - #endif // LLVM_LIBC_SRC___SUPPORT_MATH_SETPAYLOADF128_H diff --git a/libc/src/__support/math/setpayloadsigf128.h b/libc/src/__support/math/setpayloadsigf128.h index c9bd9498cfb744..bb7ca8afc0d718 100644 --- a/libc/src/__support/math/setpayloadsigf128.h +++ b/libc/src/__support/math/setpayloadsigf128.h @@ -1,32 +1,34 @@ -//===-- Implementation header for setpayloadsigf128 -------------*- C++ -*-===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Implementation header for setpayloadsigf128. +/// +//===----------------------------------------------------------------------===// #ifndef LLVM_LIBC_SRC___SUPPORT_MATH_SETPAYLOADSIGF128_H #define LLVM_LIBC_SRC___SUPPORT_MATH_SETPAYLOADSIGF128_H -#include "include/llvm-libc-types/float128.h" - -#ifdef LIBC_TYPES_HAS_NATIVE_FLOAT128 - #include "src/__support/FPUtil/BasicOperations.h" +#include "src/__support/FPUtil/float128.h" #include "src/__support/macros/config.h" namespace LIBC_NAMESPACE_DECL { namespace math { -LIBC_INLINE constexpr int setpayloadsigf128(float128 *res, float128 pl) { +using LIBC_NAMESPACE::fputil::Float128; + +LIBC_INLINE constexpr int setpayloadsigf128(Float128 *res, Float128 pl) { return static_cast(fputil::setpayload(*res, pl)); } } // namespace math } // namespace LIBC_NAMESPACE_DECL -#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 - #endif // LLVM_LIBC_SRC___SUPPORT_MATH_SETPAYLOADSIGF128_H diff --git a/libc/src/math/generic/CMakeLists.txt b/libc/src/math/generic/CMakeLists.txt index 13cb65ff37e0b5..b4b2465b384b10 100644 --- a/libc/src/math/generic/CMakeLists.txt +++ b/libc/src/math/generic/CMakeLists.txt @@ -3190,6 +3190,7 @@ add_entrypoint_object( HDRS ../nanf128.h DEPENDS + libc.src.__support.CPP.bit libc.src.__support.math.nanf128 ) @@ -4417,6 +4418,7 @@ add_entrypoint_object( HDRS ../getpayloadf128.h DEPENDS + libc.src.__support.CPP.bit libc.src.__support.math.getpayloadf128 ) @@ -4477,6 +4479,7 @@ add_entrypoint_object( HDRS ../setpayloadf128.h DEPENDS + libc.src.__support.CPP.bit libc.src.__support.math.setpayloadf128 ) @@ -4537,6 +4540,7 @@ add_entrypoint_object( HDRS ../setpayloadsigf128.h DEPENDS + libc.src.__support.CPP.bit libc.src.__support.math.setpayloadsigf128 ) diff --git a/libc/src/math/generic/getpayloadf128.cpp b/libc/src/math/generic/getpayloadf128.cpp index ba2b1cf798f3b9..f74d1529508fb5 100644 --- a/libc/src/math/generic/getpayloadf128.cpp +++ b/libc/src/math/generic/getpayloadf128.cpp @@ -1,18 +1,27 @@ -//===-- Implementation of getpayloadf128 function -------------------------===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Implementation of getpayloadf128 function. +/// +//===----------------------------------------------------------------------===// #include "src/math/getpayloadf128.h" +#include "src/__support/CPP/bit.h" #include "src/__support/math/getpayloadf128.h" namespace LIBC_NAMESPACE_DECL { +using LIBC_NAMESPACE::fputil::Float128; + LLVM_LIBC_FUNCTION(float128, getpayloadf128, (const float128 *x)) { - return math::getpayloadf128(x); + return cpp::bit_cast( + math::getpayloadf128(cpp::bit_cast(x))); } } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/math/generic/nanf128.cpp b/libc/src/math/generic/nanf128.cpp index 04cb5cf03cc745..6acf4fe8a08298 100644 --- a/libc/src/math/generic/nanf128.cpp +++ b/libc/src/math/generic/nanf128.cpp @@ -1,18 +1,24 @@ -//===-- Implementation of nanf128 function --------------------------------===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Implementation of nanf128 function. +/// +//===----------------------------------------------------------------------===// #include "src/math/nanf128.h" +#include "src/__support/CPP/bit.h" #include "src/__support/math/nanf128.h" namespace LIBC_NAMESPACE_DECL { LLVM_LIBC_FUNCTION(float128, nanf128, (const char *arg)) { - return math::nanf128(arg); + return cpp::bit_cast(math::nanf128(arg)); } } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/math/generic/setpayloadf128.cpp b/libc/src/math/generic/setpayloadf128.cpp index 83a3218688a999..c8834261e58610 100644 --- a/libc/src/math/generic/setpayloadf128.cpp +++ b/libc/src/math/generic/setpayloadf128.cpp @@ -1,18 +1,27 @@ -//===-- Implementation of setpayloadf128 function -------------------------===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Implementation of setpayloadf128 function. +/// +//===----------------------------------------------------------------------===// #include "src/math/setpayloadf128.h" +#include "src/__support/CPP/bit.h" #include "src/__support/math/setpayloadf128.h" namespace LIBC_NAMESPACE_DECL { +using LIBC_NAMESPACE::fputil::Float128; + LLVM_LIBC_FUNCTION(int, setpayloadf128, (float128 * res, float128 pl)) { - return math::setpayloadf128(res, pl); + return math::setpayloadf128(cpp::bit_cast(res), + cpp::bit_cast(pl)); } } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/math/generic/setpayloadsigf128.cpp b/libc/src/math/generic/setpayloadsigf128.cpp index a3972286767b52..dd930ece97752e 100644 --- a/libc/src/math/generic/setpayloadsigf128.cpp +++ b/libc/src/math/generic/setpayloadsigf128.cpp @@ -1,18 +1,27 @@ -//===-- Implementation of setpayloadsigf128 function ----------------------===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Implementation of setpayloadsigf128 function. +/// +//===----------------------------------------------------------------------===// #include "src/math/setpayloadsigf128.h" +#include "src/__support/CPP/bit.h" #include "src/__support/math/setpayloadsigf128.h" namespace LIBC_NAMESPACE_DECL { +using LIBC_NAMESPACE::fputil::Float128; + LLVM_LIBC_FUNCTION(int, setpayloadsigf128, (float128 * res, float128 pl)) { - return math::setpayloadsigf128(res, pl); + return math::setpayloadsigf128(cpp::bit_cast(res), + cpp::bit_cast(pl)); } } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/math/getpayloadf128.h b/libc/src/math/getpayloadf128.h index 7ebb4290d4f8a3..bed0870f74b95b 100644 --- a/libc/src/math/getpayloadf128.h +++ b/libc/src/math/getpayloadf128.h @@ -1,19 +1,29 @@ -//===-- Implementation header for getpayloadf128 ----------------*- C++ -*-===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Implementation header for getpayloadf128. +/// +//===----------------------------------------------------------------------===// #ifndef LLVM_LIBC_SRC_MATH_GETPAYLOADF128_H #define LLVM_LIBC_SRC_MATH_GETPAYLOADF128_H +#include "src/__support/FPUtil/float128.h" #include "src/__support/macros/config.h" #include "src/__support/macros/properties/types.h" namespace LIBC_NAMESPACE_DECL { +#ifndef LIBC_TYPES_HAS_NATIVE_FLOAT128 +using float128 = LIBC_NAMESPACE::fputil::Float128; +#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 + float128 getpayloadf128(const float128 *x); } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/math/nanf128.h b/libc/src/math/nanf128.h index 1c1323adcd7812..13dc64c4d8afe5 100644 --- a/libc/src/math/nanf128.h +++ b/libc/src/math/nanf128.h @@ -1,19 +1,29 @@ -//===-- Implementation header for nanf128 -----------------------*- C++ -*-===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Implementation header for nanf128. +/// +//===----------------------------------------------------------------------===// #ifndef LLVM_LIBC_SRC_MATH_NANF128_H #define LLVM_LIBC_SRC_MATH_NANF128_H +#include "src/__support/FPUtil/float128.h" #include "src/__support/macros/config.h" #include "src/__support/macros/properties/types.h" namespace LIBC_NAMESPACE_DECL { +#ifndef LIBC_TYPES_HAS_NATIVE_FLOAT128 +using float128 = LIBC_NAMESPACE::fputil::Float128; +#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 + float128 nanf128(const char *arg); } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/math/setpayloadf128.h b/libc/src/math/setpayloadf128.h index e46aef38256db6..4ade6153a29c55 100644 --- a/libc/src/math/setpayloadf128.h +++ b/libc/src/math/setpayloadf128.h @@ -1,19 +1,29 @@ -//===-- Implementation header for setpayloadf128 ----------------*- C++ -*-===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Implementation header for setpayloadf128. +/// +//===----------------------------------------------------------------------===// #ifndef LLVM_LIBC_SRC_MATH_SETPAYLOADF128_H #define LLVM_LIBC_SRC_MATH_SETPAYLOADF128_H +#include "src/__support/FPUtil/float128.h" #include "src/__support/macros/config.h" #include "src/__support/macros/properties/types.h" namespace LIBC_NAMESPACE_DECL { +#ifndef LIBC_TYPES_HAS_NATIVE_FLOAT128 +using float128 = LIBC_NAMESPACE::fputil::Float128; +#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 + int setpayloadf128(float128 *res, float128 pl); } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/src/math/setpayloadsigf128.h b/libc/src/math/setpayloadsigf128.h index 4e036b9c8ba007..eaf1a5d94dcead 100644 --- a/libc/src/math/setpayloadsigf128.h +++ b/libc/src/math/setpayloadsigf128.h @@ -1,19 +1,29 @@ -//===-- Implementation header for setpayloadsigf128 -------------*- C++ -*-===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Implementation header for setpayloadsigf128. +/// +//===----------------------------------------------------------------------===// #ifndef LLVM_LIBC_SRC_MATH_SETPAYLOADSIGF128_H #define LLVM_LIBC_SRC_MATH_SETPAYLOADSIGF128_H +#include "src/__support/FPUtil/float128.h" #include "src/__support/macros/config.h" #include "src/__support/macros/properties/types.h" namespace LIBC_NAMESPACE_DECL { +#ifndef LIBC_TYPES_HAS_NATIVE_FLOAT128 +using float128 = LIBC_NAMESPACE::fputil::Float128; +#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 + int setpayloadsigf128(float128 *res, float128 pl); } // namespace LIBC_NAMESPACE_DECL diff --git a/libc/test/shared/CMakeLists.txt b/libc/test/shared/CMakeLists.txt index cde49cd6e3c73d..eff5bea2970fd1 100644 --- a/libc/test/shared/CMakeLists.txt +++ b/libc/test/shared/CMakeLists.txt @@ -790,6 +790,12 @@ else() libc.src.__support.math.setpayloadf128 libc.src.__support.math.setpayloadf16 libc.src.__support.math.setpayloadl + libc.src.__support.math.setpayloadsig + libc.src.__support.math.setpayloadsigbf16 + libc.src.__support.math.setpayloadsigf + libc.src.__support.math.setpayloadsigf128 + libc.src.__support.math.setpayloadsigf16 + libc.src.__support.math.setpayloadsigl libc.src.__support.math.sqrtl libc.src.__support.math.trunc libc.src.__support.math.truncbf16 diff --git a/libc/test/shared/shared_math_constexpr_test.cpp b/libc/test/shared/shared_math_constexpr_test.cpp index ec7f99a9ff40c0..6ca32979bddbde 100644 --- a/libc/test/shared/shared_math_constexpr_test.cpp +++ b/libc/test/shared/shared_math_constexpr_test.cpp @@ -453,6 +453,25 @@ static_assert(Float128(0.0) == LIBC_NAMESPACE::shared::roundf128(Float128(0.0))); static_assert(Float128(0.0) == LIBC_NAMESPACE::shared::truncf128(Float128(0.0))); +static_assert(Float128(-1.0) == [] { + Float128 getpayload_x = Float128(0.0); + return LIBC_NAMESPACE::shared::getpayloadf128(&getpayload_x); +}()); +static_assert(1 == [] { + const char arg{}; + return LIBC_NAMESPACE::fputil::FPBits( + LIBC_NAMESPACE::shared::nanf128(&arg)) + .is_nan(); +}()); +static_assert(0 == [] { + Float128 setpayload_x = Float128(0.0); + return LIBC_NAMESPACE::shared::setpayloadf128(&setpayload_x, Float128(0.0)); +}()); +static_assert(1 == [] { + Float128 setpayloadsigf128_x = Float128(0.0); + return LIBC_NAMESPACE::shared::setpayloadsigf128(&setpayloadsigf128_x, + Float128(0.0)); +}()); //===----------------------------------------------------------------------===// // Native Float128 Tests @@ -482,10 +501,6 @@ static_assert(float128(0.0) == LIBC_NAMESPACE::shared::fromfpf128(float128(0.0), 0, 32)); static_assert(float128(0.0) == LIBC_NAMESPACE::shared::fromfpxf128(float128(0.0), 0, 32)); -static_assert(float128(-1.0) == [] { - float128 getpayload_x = float128(0.0); - return LIBC_NAMESPACE::shared::getpayloadf128(&getpayload_x); -}()); static_assert(float128(0.0) == LIBC_NAMESPACE::shared::ufromfpf128(float128(0.0), 0, 32)); static_assert(float128(0.0) == @@ -516,15 +531,6 @@ static_assert(float128(0.0) == LIBC_NAMESPACE::shared::scalblnf128(float128(0.0), 0.0)); static_assert(float128(0.0) == LIBC_NAMESPACE::shared::scalbnf128(float128(0.0), 0.0)); -static_assert(0 == [] { - float128 setpayload_x = float128(0.0); - return LIBC_NAMESPACE::shared::setpayloadf128(&setpayload_x, float128(0.0)); -}()); -static_assert(1 == [] { - float128 setpayloadsig_x = float128(0.0); - return LIBC_NAMESPACE::shared::setpayloadsigf128(&setpayloadsig_x, - float128(0.0)); -}()); static_assert(0.0f == LIBC_NAMESPACE::shared::fmulf128(float128(0.0), float128(0.0))); static_assert(0.0f == @@ -532,12 +538,6 @@ static_assert(0.0f == static_assert(float128(0.0) == LIBC_NAMESPACE::shared::nextafterf128(float128(0.0), float128(0.0))); -static_assert(1 == [] { - const char arg{}; - return LIBC_NAMESPACE::fputil::FPBits( - LIBC_NAMESPACE::shared::nanf128(&arg)) - .is_nan(); -}()); #endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 diff --git a/libc/test/shared/shared_math_test.cpp b/libc/test/shared/shared_math_test.cpp index d0581b5dababa9..68b562c48931aa 100644 --- a/libc/test/shared/shared_math_test.cpp +++ b/libc/test/shared/shared_math_test.cpp @@ -583,6 +583,8 @@ TEST(LlvmLibcSharedMathTest, AllLongDouble) { // Emulated float128 tests TEST(LlvmLibcSharedMathTest, AllEmuFloat128) { + using FPBits = LIBC_NAMESPACE::fputil::FPBits; + EXPECT_FP_EQ(Float128(0.0), LIBC_NAMESPACE::shared::atan2f128(Float128(0.0), Float128(0.0))); EXPECT_FP_EQ(Float128(0.0), LIBC_NAMESPACE::shared::ceilf128(Float128(0.0))); @@ -612,6 +614,11 @@ TEST(LlvmLibcSharedMathTest, AllEmuFloat128) { Float128(0.0), Float128(0.0))); EXPECT_FP_EQ(Float128(0.0), LIBC_NAMESPACE::shared::fminimum_numf128( Float128(0.0), Float128(0.0))); + + Float128 getpayloadf128_x = Float128(0.0); + EXPECT_FP_EQ(Float128(-1.0), + LIBC_NAMESPACE::shared::getpayloadf128(&getpayloadf128_x)); + EXPECT_EQ(1, LIBC_NAMESPACE::shared::iscanonicalf128(Float128(0.0))); EXPECT_EQ(0, LIBC_NAMESPACE::shared::isnanf128(Float128(0.0))); EXPECT_EQ(0, LIBC_NAMESPACE::shared::issignalingf128(Float128(0.0))); @@ -619,12 +626,25 @@ TEST(LlvmLibcSharedMathTest, AllEmuFloat128) { EXPECT_EQ(0LL, LIBC_NAMESPACE::shared::llroundf128(Float128(0.0))); EXPECT_EQ(0L, LIBC_NAMESPACE::shared::lrintf128(Float128(0.0))); EXPECT_EQ(0L, LIBC_NAMESPACE::shared::lroundf128(Float128(0.0))); + + EXPECT_TRUE(FPBits(LIBC_NAMESPACE::shared::nanf128("")).is_nan()); + EXPECT_FP_EQ(Float128(0.0), LIBC_NAMESPACE::shared::nearbyintf128(Float128(0.0))); EXPECT_FP_EQ(Float128(0.0), LIBC_NAMESPACE::shared::rintf128(Float128(0.0))); EXPECT_FP_EQ(Float128(0.0), LIBC_NAMESPACE::shared::roundevenf128(Float128(0.0))); EXPECT_FP_EQ(Float128(0.0), LIBC_NAMESPACE::shared::roundf128(Float128(0.0))); + + Float128 setpayloadf128_res = Float128(0.0); + EXPECT_EQ(0, LIBC_NAMESPACE::shared::setpayloadf128(&setpayloadf128_res, + Float128(0.0))); + + Float128 setpayloadsigf128_res = Float128(0.0); + EXPECT_EQ(1, LIBC_NAMESPACE::shared::setpayloadsigf128(&setpayloadsigf128_res, + Float128(0.0))); + EXPECT_FP_EQ(Float128(0.0), setpayloadsigf128_res); + EXPECT_FP_EQ(Float128(1.0), LIBC_NAMESPACE::shared::sqrtf128(Float128(1.0))); EXPECT_FP_EQ(Float128(0.0), LIBC_NAMESPACE::shared::truncf128(Float128(0.0))); } @@ -683,20 +703,6 @@ TEST(LlvmLibcSharedMathTest, AllFloat128) { LIBC_NAMESPACE::shared::faddf128(float128(0.0), float128(0.0))); EXPECT_FP_EQ(1.0f, LIBC_NAMESPACE::shared::fdivf128(float128(1.0), float128(1.0))); - - float128 getpayloadf128_x = float128(0.0); - EXPECT_FP_EQ(float128(-1.0), - LIBC_NAMESPACE::shared::getpayloadf128(&getpayloadf128_x)); - - float128 setpayloadf128_res = float128(0.0); - EXPECT_EQ(0, LIBC_NAMESPACE::shared::setpayloadf128(&setpayloadf128_res, - float128(0.0))); - - float128 setpayloadsigf128_res = float128(0.0); - EXPECT_EQ(1, LIBC_NAMESPACE::shared::setpayloadsigf128(&setpayloadsigf128_res, - float128(0.0))); - EXPECT_FP_EQ(float128(0.0), setpayloadsigf128_res); - float128 neg_min_denormal = FPBits::min_subnormal(Sign::NEG).get_val(); EXPECT_FP_EQ(neg_min_denormal, LIBC_NAMESPACE::shared::nextdownf128(float128(0.0))); @@ -756,7 +762,6 @@ TEST(LlvmLibcSharedMathTest, AllFloat128) { LIBC_NAMESPACE::shared::fsubf128(float128(0.0), float128(0.0))); EXPECT_FP_EQ(0x0p+0f, LIBC_NAMESPACE::shared::fmulf128(float128(0.0), float128(0.0))); - EXPECT_TRUE(FPBits(LIBC_NAMESPACE::shared::nanf128("")).is_nan()); } #endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 diff --git a/libc/test/src/math/smoke/CMakeLists.txt b/libc/test/src/math/smoke/CMakeLists.txt index 76caeef863e342..d68eb7786e3b58 100644 --- a/libc/test/src/math/smoke/CMakeLists.txt +++ b/libc/test/src/math/smoke/CMakeLists.txt @@ -3941,9 +3941,10 @@ add_fp_unittest( SRCS nanf128_test.cpp DEPENDS + libc.src.__support.FPUtil.float128 + libc.src.__support.FPUtil.fp_bits libc.hdr.signal_macros libc.src.math.nanf128 - libc.src.__support.FPUtil.fp_bits # FIXME: The nan tests currently have death tests, which aren't supported for # hermetic tests. ) @@ -5584,6 +5585,7 @@ add_fp_unittest( HDRS GetPayloadTest.h DEPENDS + libc.src.__support.FPUtil.float128 libc.src.math.getpayloadf128 ) @@ -5657,6 +5659,7 @@ add_fp_unittest( HDRS SetPayloadTest.h DEPENDS + libc.src.__support.FPUtil.float128 libc.src.math.setpayloadf128 ) @@ -5730,6 +5733,7 @@ add_fp_unittest( HDRS SetPayloadSigTest.h DEPENDS + libc.src.__support.FPUtil.float128 libc.src.math.setpayloadsigf128 ) diff --git a/libc/test/src/math/smoke/getpayloadf128_test.cpp b/libc/test/src/math/smoke/getpayloadf128_test.cpp index 77304abfbbc0a9..f6c7dddb5c3e2f 100644 --- a/libc/test/src/math/smoke/getpayloadf128_test.cpp +++ b/libc/test/src/math/smoke/getpayloadf128_test.cpp @@ -1,13 +1,23 @@ -//===-- Unittests for getpayloadf128 --------------------------------------===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Unittests for getpayloadf128. +/// +//===----------------------------------------------------------------------===// #include "GetPayloadTest.h" +#include "src/__support/FPUtil/float128.h" #include "src/math/getpayloadf128.h" +#ifndef LIBC_TYPES_HAS_NATIVE_FLOAT128 +using float128 = LIBC_NAMESPACE::fputil::Float128; +#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 + LIST_GETPAYLOAD_TESTS(Getpayloadf128, float128, LIBC_NAMESPACE::getpayloadf128) diff --git a/libc/test/src/math/smoke/nanf128_test.cpp b/libc/test/src/math/smoke/nanf128_test.cpp index 40b347de25f7a9..7c3fbafe2198ab 100644 --- a/libc/test/src/math/smoke/nanf128_test.cpp +++ b/libc/test/src/math/smoke/nanf128_test.cpp @@ -1,19 +1,29 @@ -//===-- Unittests for nanf128 ---------------------------------------------===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Unittests for nanf128. +/// +//===----------------------------------------------------------------------===// #include "hdr/signal_macros.h" #include "src/__support/FPUtil/FPBits.h" +#include "src/__support/FPUtil/float128.h" #include "src/__support/uint128.h" #include "src/math/nanf128.h" #include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" +#ifndef LIBC_TYPES_HAS_NATIVE_FLOAT128 +using float128 = LIBC_NAMESPACE::fputil::Float128; +#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 + class LlvmLibcNanf128Test : public LIBC_NAMESPACE::testing::FEnvSafeTest { public: using FPBits128 = LIBC_NAMESPACE::fputil::FPBits; diff --git a/libc/test/src/math/smoke/setpayloadf128_test.cpp b/libc/test/src/math/smoke/setpayloadf128_test.cpp index 3e386972980e13..031c7627effdcf 100644 --- a/libc/test/src/math/smoke/setpayloadf128_test.cpp +++ b/libc/test/src/math/smoke/setpayloadf128_test.cpp @@ -1,13 +1,23 @@ -//===-- Unittests for setpayloadf128 --------------------------------------===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Unittests for setpayloadf128. +/// +//===----------------------------------------------------------------------===// #include "SetPayloadTest.h" +#include "src/__support/FPUtil/float128.h" #include "src/math/setpayloadf128.h" +#ifndef LIBC_TYPES_HAS_NATIVE_FLOAT128 +using float128 = LIBC_NAMESPACE::fputil::Float128; +#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 + LIST_SETPAYLOAD_TESTS(Setpayloadf128, float128, LIBC_NAMESPACE::setpayloadf128) diff --git a/libc/test/src/math/smoke/setpayloadsigf128_test.cpp b/libc/test/src/math/smoke/setpayloadsigf128_test.cpp index 90f2a2aef9569f..c623b45b4c3903 100644 --- a/libc/test/src/math/smoke/setpayloadsigf128_test.cpp +++ b/libc/test/src/math/smoke/setpayloadsigf128_test.cpp @@ -1,14 +1,24 @@ -//===-- Unittests for setpayloadsigf128 -----------------------------------===// +//===----------------------------------------------------------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // //===----------------------------------------------------------------------===// +/// +/// \file +/// Unittests for setpayloadsigf128. +/// +//===----------------------------------------------------------------------===// #include "SetPayloadSigTest.h" +#include "src/__support/FPUtil/float128.h" #include "src/math/setpayloadsigf128.h" +#ifndef LIBC_TYPES_HAS_NATIVE_FLOAT128 +using float128 = LIBC_NAMESPACE::fputil::Float128; +#endif // LIBC_TYPES_HAS_NATIVE_FLOAT128 + LIST_SETPAYLOADSIG_TESTS(Setpayloadsigf128, float128, LIBC_NAMESPACE::setpayloadsigf128) diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index 210e2e1eb4a09a..0e74580b1f84ba 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -5934,8 +5934,8 @@ libc_support_library( hdrs = ["src/__support/math/setpayloadf128.h"], deps = [ ":__support_fputil_basic_operations", + ":__support_fputil_float128", ":__support_macros_config", - ":llvm_libc_types_float128", ], ) @@ -5991,8 +5991,8 @@ libc_support_library( hdrs = ["src/__support/math/setpayloadsigf128.h"], deps = [ ":__support_fputil_basic_operations", + ":__support_fputil_float128", ":__support_macros_config", - ":llvm_libc_types_float128", ], ) @@ -8083,10 +8083,10 @@ libc_support_library( name = "__support_math_nanf128", hdrs = ["src/__support/math/nanf128.h"], deps = [ + ":__support_fputil_float128", ":__support_libc_errno", ":__support_macros_config", ":__support_str_to_float", - ":llvm_libc_types_float128", ], ) @@ -9836,8 +9836,8 @@ libc_support_library( hdrs = ["src/__support/math/getpayloadf128.h"], deps = [ ":__support_fputil_basic_operations", + ":__support_fputil_float128", ":__support_macros_config", - ":llvm_libc_types_float128", ], ) @@ -14209,6 +14209,8 @@ libc_math_function( libc_math_function( name = "getpayloadf128", additional_deps = [ + ":__support_cpp_bit", + ":__support_fputil_float128", ":__support_math_getpayloadf128", ], ) @@ -14745,6 +14747,8 @@ libc_math_function( libc_math_function( name = "nanf128", additional_deps = [ + ":__support_cpp_bit", + ":__support_fputil_float128", ":__support_math_nanf128", ], ) @@ -15320,6 +15324,8 @@ libc_math_function( libc_math_function( name = "setpayloadf128", additional_deps = [ + ":__support_cpp_bit", + ":__support_fputil_float128", ":__support_math_setpayloadf128", ], ) @@ -15362,6 +15368,8 @@ libc_math_function( libc_math_function( name = "setpayloadsigf128", additional_deps = [ + ":__support_cpp_bit", + ":__support_fputil_float128", ":__support_math_setpayloadsigf128", ], ) diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel index 238b2852e4cc6c..dad78bc78a3545 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/math/smoke/BUILD.bazel @@ -1275,6 +1275,9 @@ math_test( math_test( name = "getpayloadf128", hdrs = ["GetPayloadTest.h"], + deps = [ + "//libc:__support_fputil_float128", + ], ) math_test( @@ -1650,7 +1653,13 @@ math_test( hdrs = ["ModfTest.h"], ) -# TODO: add nan tests. +math_test( + name = "nanf128", + deps = [ + "//libc:__support_fputil_float128", + "//libc:hdr_signal_macros", + ], +) math_test( name = "nearbyint", @@ -2100,6 +2109,9 @@ math_test( math_test( name = "setpayloadf128", hdrs = ["SetPayloadTest.h"], + deps = [ + "//libc:__support_fputil_float128", + ], ) math_test( @@ -2133,6 +2145,9 @@ math_test( math_test( name = "setpayloadsigf128", hdrs = ["SetPayloadSigTest.h"], + deps = [ + "//libc:__support_fputil_float128", + ], ) math_test( From e4225302cd112b4f72bb33374f5f800cb7be8d09 Mon Sep 17 00:00:00 2001 From: Srividya Sundaram Date: Sat, 24 Oct 2026 13:22:28 -0700 Subject: [PATCH 24/31] [Driver][SYCL] Link libclang_rt.builtins.bc for spirv64 at compile time via getDeviceLibs (#218528) Add support for linking `libclang_rt.builtins.bc` for the `spirv64` target at compile time by integrating it into the SYCL `getDeviceLibs` mechanism. This ensures built-in runtime library functions are available for SYCL device code targeting `SPIR-V` 64-bit. Re-land of https://github.com/llvm/llvm-project/pull/212550 (Only Clang Driver changes) --------- Co-authored-by: Claude Sonnet 4.6 --- .../clang/Basic/DiagnosticDriverKinds.td | 5 +- clang/include/clang/Driver/Driver.h | 2 +- clang/lib/Driver/Driver.cpp | 47 +++++++------ clang/lib/Driver/ToolChain.cpp | 9 +++ clang/lib/Driver/ToolChains/CommonArgs.cpp | 4 +- clang/lib/Driver/ToolChains/SYCL.cpp | 40 +++++++++++ clang/lib/Driver/ToolChains/SYCL.h | 4 ++ .../lib/linux/libclang_rt.builtins-spirv64.bc | 0 .../libclang_rt.builtins.bc | 0 clang/test/Driver/sycl-device-lib-spirv64.cpp | 57 +++++++++++++++ .../Driver/sycl-msvc-version-propagation.cpp | 1 + clang/test/Driver/sycl-nordc-fatbin.cpp | 12 ++-- clang/test/Driver/sycl-offload-jit-unix.cpp | 9 ++- clang/test/Driver/sycl-offload-jit-xarch.cpp | 6 +- clang/test/Driver/sycl-offload-jit.cpp | 69 ++++++++++++------- .../Driver/sycl-rtlib-sysroot-mismatch.cpp | 6 +- clang/test/Driver/sycl-std-default.cpp | 8 +-- clang/test/Driver/sycl-windows.cpp | 28 ++++---- clang/test/Driver/sycl.cpp | 30 ++++---- 19 files changed, 239 insertions(+), 98 deletions(-) create mode 100644 clang/test/Driver/Inputs/spirv64-sycl-flat-layout/lib/linux/libclang_rt.builtins-spirv64.bc create mode 100644 clang/test/Driver/Inputs/spirv64-sycl/lib/spirv64-unknown-unknown/libclang_rt.builtins.bc create mode 100644 clang/test/Driver/sycl-device-lib-spirv64.cpp diff --git a/clang/include/clang/Basic/DiagnosticDriverKinds.td b/clang/include/clang/Basic/DiagnosticDriverKinds.td index 79859e724a8179..c5836a2012ab69 100644 --- a/clang/include/clang/Basic/DiagnosticDriverKinds.td +++ b/clang/include/clang/Basic/DiagnosticDriverKinds.td @@ -449,7 +449,10 @@ def warn_drv_fraw_string_literals_in_cxx11 : Warning< "ignoring '-f%select{no-|}0raw-string-literals', which is only valid for C and C++ standards before C++11">, InGroup; -def err_drv_libclc_not_found : Error<"no libclc library '%0' found in the clang resource directory">; +def err_drv_device_lib_not_found : Error< + "no %select{libclc|compiler-rt builtins bitcode}0 library '%1' found in the " + "clang resource directory%select{|; build compiler-rt with SPIR-V support or " + "pass '--no-offloadlib' to compile without it}0">; def err_drv_invalid_malign_branch_EQ : Error< "invalid argument '%0' to -malign-branch=; each element must be one of: %1">; diff --git a/clang/include/clang/Driver/Driver.h b/clang/include/clang/Driver/Driver.h index 914ef62cd62fa9..6ba0acacdeaf26 100644 --- a/clang/include/clang/Driver/Driver.h +++ b/clang/include/clang/Driver/Driver.h @@ -338,7 +338,7 @@ class Driver { // TODO: Much of what getFinalPhase returns are not actually true compiler // modes. Fold this functionality into Types::getCompilationPhases and // handleArguments. - phases::ID getFinalPhase(const llvm::opt::DerivedArgList &DAL, + phases::ID getFinalPhase(const llvm::opt::ArgList &Args, llvm::opt::Arg **FinalPhaseArg = nullptr) const; llvm::Expected> diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 707d6847caf446..955443bc142ed4 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -354,52 +354,51 @@ InputArgList Driver::ParseArgStrings(ArrayRef ArgStrings, // Determine which compilation mode we are in. We look for options which // affect the phase, starting with the earliest phases, and record which // option we used to determine the final phase. -phases::ID Driver::getFinalPhase(const DerivedArgList &DAL, +phases::ID Driver::getFinalPhase(const ArgList &Args, Arg **FinalPhaseArg) const { Arg *PhaseArg = nullptr; phases::ID FinalPhase; // -{E,EP,P,M,MM} only run the preprocessor. - if (CCCIsCPP() || (PhaseArg = DAL.getLastArg(options::OPT_E)) || - (PhaseArg = DAL.getLastArg(options::OPT__SLASH_EP)) || - (PhaseArg = DAL.getLastArg(options::OPT_M, options::OPT_MM)) || - (PhaseArg = DAL.getLastArg(options::OPT__SLASH_P)) || - CCGenDiagnostics) { + if (CCCIsCPP() || (PhaseArg = Args.getLastArg(options::OPT_E)) || + (PhaseArg = Args.getLastArg(options::OPT__SLASH_EP)) || + (PhaseArg = Args.getLastArg(options::OPT_M, options::OPT_MM)) || + (PhaseArg = Args.getLastArg(options::OPT__SLASH_P)) || CCGenDiagnostics) { FinalPhase = phases::Preprocess; // --precompile only runs up to precompilation. // Options that cause the output of C++20 compiled module interfaces or // header units have the same effect. - } else if ((PhaseArg = DAL.getLastArg(options::OPT__precompile)) || + } else if ((PhaseArg = Args.getLastArg(options::OPT__precompile)) || (PhaseArg = - DAL.getLastArg(options::OPT__precompile_reduced_bmi)) || - (PhaseArg = DAL.getLastArg(options::OPT_extract_api)) || - (PhaseArg = DAL.getLastArg(options::OPT_fmodule_header, - options::OPT_fmodule_header_EQ))) { + Args.getLastArg(options::OPT__precompile_reduced_bmi)) || + (PhaseArg = Args.getLastArg(options::OPT_extract_api)) || + (PhaseArg = Args.getLastArg(options::OPT_fmodule_header, + options::OPT_fmodule_header_EQ))) { FinalPhase = phases::Precompile; // -{fsyntax-only,-analyze,emit-ast} only run up to the compiler. - } else if ((PhaseArg = DAL.getLastArg(options::OPT_fsyntax_only)) || - (PhaseArg = DAL.getLastArg(options::OPT_print_supported_cpus)) || + } else if ((PhaseArg = Args.getLastArg(options::OPT_fsyntax_only)) || + (PhaseArg = Args.getLastArg(options::OPT_print_supported_cpus)) || (PhaseArg = - DAL.getLastArg(options::OPT_print_enabled_extensions)) || - (PhaseArg = DAL.getLastArg(options::OPT_module_file_info)) || - (PhaseArg = DAL.getLastArg(options::OPT_verify_pch)) || - (PhaseArg = DAL.getLastArg(options::OPT_rewrite_objc)) || - (PhaseArg = DAL.getLastArg(options::OPT_rewrite_legacy_objc)) || - (PhaseArg = DAL.getLastArg(options::OPT__analyze)) || - (PhaseArg = DAL.getLastArg(options::OPT_emit_cir)) || - (PhaseArg = DAL.getLastArg(options::OPT_emit_ast))) { + Args.getLastArg(options::OPT_print_enabled_extensions)) || + (PhaseArg = Args.getLastArg(options::OPT_module_file_info)) || + (PhaseArg = Args.getLastArg(options::OPT_verify_pch)) || + (PhaseArg = Args.getLastArg(options::OPT_rewrite_objc)) || + (PhaseArg = Args.getLastArg(options::OPT_rewrite_legacy_objc)) || + (PhaseArg = Args.getLastArg(options::OPT__analyze)) || + (PhaseArg = Args.getLastArg(options::OPT_emit_cir)) || + (PhaseArg = Args.getLastArg(options::OPT_emit_ast))) { FinalPhase = phases::Compile; // -S only runs up to the backend. - } else if ((PhaseArg = DAL.getLastArg(options::OPT_S))) { + } else if ((PhaseArg = Args.getLastArg(options::OPT_S))) { FinalPhase = phases::Backend; // -c compilation only runs up to the assembler. - } else if ((PhaseArg = DAL.getLastArg(options::OPT_c))) { + } else if ((PhaseArg = Args.getLastArg(options::OPT_c))) { FinalPhase = phases::Assemble; - } else if ((PhaseArg = DAL.getLastArg(options::OPT_emit_interface_stubs))) { + } else if ((PhaseArg = Args.getLastArg(options::OPT_emit_interface_stubs))) { FinalPhase = phases::IfsMerge; // Otherwise do everything. diff --git a/clang/lib/Driver/ToolChain.cpp b/clang/lib/Driver/ToolChain.cpp index 242f75af52d7b0..b3e7043a64fe56 100644 --- a/clang/lib/Driver/ToolChain.cpp +++ b/clang/lib/Driver/ToolChain.cpp @@ -1137,6 +1137,15 @@ ToolChain::getTargetSubDirPath(StringRef BaseDir) const { return *Path; } + // Short SPIR-V spellings like "spirv64" are installed under the three-part + // name, "spirv64-unknown-unknown". + if (T.isSPIRV()) { + llvm::Triple SPIRVTriple( + T.normalize(llvm::Triple::CanonicalForm::THREE_IDENT)); + if (auto Path = getPathForTriple(SPIRVTriple)) + return *Path; + } + if (T.isOSAIX()) { llvm::Triple AIXTriple; if (T.getEnvironment() == Triple::UnknownEnvironment) { diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 7d77cd0b916324..39dcec2f823bdd 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -2937,7 +2937,7 @@ bool tools::addOpenCLBuiltinsLib(const Driver &D, const llvm::Triple &TT, CC1Args.push_back(DriverArgs.MakeArgString(LibclcFile)); return true; } - D.Diag(diag::err_drv_libclc_not_found) << LibclcFile; + D.Diag(diag::err_drv_device_lib_not_found) << /*libclc*/ 0 << LibclcFile; return false; } @@ -3004,7 +3004,7 @@ bool tools::addOpenCLBuiltinsLib(const Driver &D, const llvm::Triple &TT, return true; } - D.Diag(diag::err_drv_libclc_not_found) << "libclc.bc"; + D.Diag(diag::err_drv_device_lib_not_found) << /*libclc*/ 0 << "libclc.bc"; return false; } diff --git a/clang/lib/Driver/ToolChains/SYCL.cpp b/clang/lib/Driver/ToolChains/SYCL.cpp index b0c07dd1be2eeb..ec694ff9f151a4 100644 --- a/clang/lib/Driver/ToolChains/SYCL.cpp +++ b/clang/lib/Driver/ToolChains/SYCL.cpp @@ -8,6 +8,7 @@ #include "SYCL.h" #include "SPIRV.h" #include "clang/Driver/CommonArgs.h" +#include "llvm/Support/Path.h" #include "llvm/Support/VirtualFileSystem.h" using namespace clang::driver; @@ -128,6 +129,18 @@ void SYCLToolChain::addClangTargetOptions( const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, BoundArch BA, Action::OffloadKind DeviceOffloadingKind) const { HostTC.addClangTargetOptions(DriverArgs, CC1Args, BA, DeviceOffloadingKind); + + // Compilations that stop at or before the compile phase (-E, --precompile, + // -fsyntax-only) emit no IR, so they need no device libraries. + if (getDriver().getFinalPhase(DriverArgs) <= phases::Compile) + return; + + for (const auto &BCFile : + getDeviceLibs(DriverArgs, BA, DeviceOffloadingKind)) { + CC1Args.push_back(BCFile.ShouldInternalize ? "-mlink-builtin-bitcode" + : "-mlink-bitcode-file"); + CC1Args.push_back(DriverArgs.MakeArgStringRef(BCFile.Path)); + } } llvm::opt::DerivedArgList * @@ -211,3 +224,30 @@ VersionTuple SYCLToolChain::computeMSVCVersion(const Driver *D, const ArgList &Args) const { return HostTC.computeMSVCVersion(D, Args); } + +llvm::SmallVector +SYCLToolChain::getDeviceLibs( + const llvm::opt::ArgList &DriverArgs, BoundArch /*BA*/, + const Action::OffloadKind /*DeviceOffloadingKind*/) const { + if (getTriple().getArch() != llvm::Triple::spirv64) + return {}; + if (!DriverArgs.hasFlag(options::OPT_offloadlib, options::OPT_no_offloadlib, + true)) + return {}; + // Per-target layout: lib//libclang_rt.builtins.bc. + if (std::optional RuntimeDir = getRuntimePath()) { + SmallString<128> BCPath(*RuntimeDir); + llvm::sys::path::append(BCPath, "libclang_rt.builtins.bc"); + if (getVFS().exists(BCPath)) + return {{std::string(BCPath), /*ShouldInternalize=*/true}}; + } + // Flat layout (LLVM_ENABLE_PER_TARGET_RUNTIME_DIR=OFF): + // lib//libclang_rt.builtins-spirv64.bc. + SmallString<128> BCPath(HostTC.getCompilerRTPath()); + llvm::sys::path::append(BCPath, "libclang_rt.builtins-spirv64.bc"); + if (getVFS().exists(BCPath)) + return {{std::string(BCPath), /*ShouldInternalize=*/true}}; + getDriver().Diag(diag::err_drv_device_lib_not_found) + << /*compiler-rt builtins*/ 1 << BCPath; + return {}; +} diff --git a/clang/lib/Driver/ToolChains/SYCL.h b/clang/lib/Driver/ToolChains/SYCL.h index 969199ef249494..d754544e30d971 100644 --- a/clang/lib/Driver/ToolChains/SYCL.h +++ b/clang/lib/Driver/ToolChains/SYCL.h @@ -58,6 +58,10 @@ class LLVM_LIBRARY_VISIBILITY SYCLToolChain : public ToolChain { computeMSVCVersion(const Driver *D, const llvm::opt::ArgList &Args) const override; + llvm::SmallVector + getDeviceLibs(const llvm::opt::ArgList &Args, BoundArch BA, + const Action::OffloadKind DeviceOffloadingKind) const override; + protected: Tool *buildLinker() const override; diff --git a/clang/test/Driver/Inputs/spirv64-sycl-flat-layout/lib/linux/libclang_rt.builtins-spirv64.bc b/clang/test/Driver/Inputs/spirv64-sycl-flat-layout/lib/linux/libclang_rt.builtins-spirv64.bc new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/Inputs/spirv64-sycl/lib/spirv64-unknown-unknown/libclang_rt.builtins.bc b/clang/test/Driver/Inputs/spirv64-sycl/lib/spirv64-unknown-unknown/libclang_rt.builtins.bc new file mode 100644 index 00000000000000..e69de29bb2d1d6 diff --git a/clang/test/Driver/sycl-device-lib-spirv64.cpp b/clang/test/Driver/sycl-device-lib-spirv64.cpp new file mode 100644 index 00000000000000..4ae884bec8c738 --- /dev/null +++ b/clang/test/Driver/sycl-device-lib-spirv64.cpp @@ -0,0 +1,57 @@ +// Tests that the SYCL toolchain links libclang_rt.builtins.bc for spirv64 +// via -mlink-builtin-bitcode, that --no-offloadlib suppresses it, and that +// -nolibsycl does not suppress it (builtins are target infrastructure, not +// SYCL runtime). + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: -resource-dir=%S/Inputs/spirv64-sycl %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-BUILTIN-BC +// CHECK-BUILTIN-BC: "-triple" "spirv64-unknown-unknown" +// CHECK-BUILTIN-BC: "-mlink-builtin-bitcode" "{{.*}}lib{{[/\\]+}}spirv64-unknown-unknown{{[/\\]+}}libclang_rt.builtins.bc" + +// A short --offload-targets= spelling finds the same per-target directory. +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: --offload-targets=spirv64 -resource-dir=%S/Inputs/spirv64-sycl %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-SHORT-TRIPLE +// CHECK-SHORT-TRIPLE: "-triple" "spirv64" +// CHECK-SHORT-TRIPLE: "-mlink-builtin-bitcode" "{{.*}}lib{{[/\\]+}}spirv64-unknown-unknown{{[/\\]+}}libclang_rt.builtins.bc" + +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl --no-offloadlib \ +// RUN: -resource-dir=%S/Inputs/spirv64-sycl %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-NO-OFFLOADLIB +// CHECK-NO-OFFLOADLIB: "-cc1" "-triple" "spirv64-unknown-unknown" +// CHECK-NO-OFFLOADLIB-NOT: "-mlink-builtin-bitcode" + +// -nolibsycl suppresses the SYCL runtime library but NOT compiler-rt builtins. +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl -nolibsycl \ +// RUN: -resource-dir=%S/Inputs/spirv64-sycl %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-NOLIBSYCL +// CHECK-NOLIBSYCL: "-triple" "spirv64-unknown-unknown" +// CHECK-NOLIBSYCL: "-mlink-builtin-bitcode" "{{.*}}lib{{[/\\]+}}spirv64-unknown-unknown{{[/\\]+}}libclang_rt.builtins.bc" + +// Test the flat layout used with LLVM_ENABLE_PER_TARGET_RUNTIME_DIR=OFF: +// lib//libclang_rt.builtins-spirv64.bc +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: -resource-dir=%S/Inputs/spirv64-sycl-flat-layout %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-FLAT-LAYOUT-BC +// CHECK-FLAT-LAYOUT-BC: "-triple" "spirv64-unknown-unknown" +// CHECK-FLAT-LAYOUT-BC: "-mlink-builtin-bitcode" "{{.*}}lib{{[/\\]+}}linux{{[/\\]+}}libclang_rt.builtins-spirv64.bc" + +// RUN: not %clang -### --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: -resource-dir=%t/nonexistent %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-MISSING +// CHECK-MISSING: error: no compiler-rt builtins bitcode library '{{.*}}libclang_rt.builtins{{.*}}.bc' found in the clang resource directory + +// Compilations that stop at or before the compile phase never link bitcode, so +// a missing builtins library is not an error for them. +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl -E \ +// RUN: -resource-dir=%t/nonexistent %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-NO-CODEGEN +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl -fsyntax-only \ +// RUN: -resource-dir=%t/nonexistent %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-NO-CODEGEN +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl --precompile \ +// RUN: -resource-dir=%t/nonexistent -x c++-header %s 2>&1 \ +// RUN: | FileCheck %s --check-prefix=CHECK-NO-CODEGEN +// CHECK-NO-CODEGEN-NOT: error: +// CHECK-NO-CODEGEN-NOT: "-mlink-builtin-bitcode" diff --git a/clang/test/Driver/sycl-msvc-version-propagation.cpp b/clang/test/Driver/sycl-msvc-version-propagation.cpp index c542ceef80ade7..1c45a6ff1602a8 100644 --- a/clang/test/Driver/sycl-msvc-version-propagation.cpp +++ b/clang/test/Driver/sycl-msvc-version-propagation.cpp @@ -2,6 +2,7 @@ /// SPIR-V device compilation. // RUN: %clang -### -fsycl --target=x86_64-pc-windows-msvc \ +// RUN: -resource-dir=%S/Inputs/spirv64-sycl \ // RUN: -x c++ %s 2>&1 | FileCheck %s // CHECK: "-triple" "spirv64-unknown-unknown" diff --git a/clang/test/Driver/sycl-nordc-fatbin.cpp b/clang/test/Driver/sycl-nordc-fatbin.cpp index 6bc75a27f49fcd..e6652d91911aa0 100644 --- a/clang/test/Driver/sycl-nordc-fatbin.cpp +++ b/clang/test/Driver/sycl-nordc-fatbin.cpp @@ -1,23 +1,27 @@ // REQUIRES: spirv-registered-target, x86-registered-target /// Verify which section carries the SYCL device binary in the host object. -// RUN: %clangxx --target=x86_64-unknown-linux-gnu -fsycl -fno-gpu-rdc \ +// RUN: %clangxx --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: --no-offloadlib -fno-gpu-rdc \ // RUN: -c %s -o %t.nordc.o // RUN: llvm-readelf -S %t.nordc.o \ // RUN: | FileCheck -check-prefix=NORDC %s --implicit-check-not='.llvm.offloading' -// RUN: %clangxx --target=x86_64-unknown-linux-gnu -fsycl -fgpu-rdc \ +// RUN: %clangxx --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: --no-offloadlib -fgpu-rdc \ // RUN: -c %s -o %t.rdc.o // RUN: llvm-readelf -S %t.rdc.o \ // RUN: | FileCheck -check-prefix=RDC %s --implicit-check-not='.sycl_fatbin' /// The choice does not depend on the object format. -// RUN: %clangxx --target=x86_64-pc-windows-msvc -fsycl -fno-gpu-rdc \ +// RUN: %clangxx --target=x86_64-pc-windows-msvc -fsycl \ +// RUN: --no-offloadlib -fno-gpu-rdc \ // RUN: -c %s -o %t.nordc.obj // RUN: llvm-readobj --sections %t.nordc.obj \ // RUN: | FileCheck -check-prefix=NORDC %s --implicit-check-not='.llvm.offloading' -// RUN: %clangxx --target=x86_64-pc-windows-msvc -fsycl -fgpu-rdc \ +// RUN: %clangxx --target=x86_64-pc-windows-msvc -fsycl \ +// RUN: --no-offloadlib -fgpu-rdc \ // RUN: -c %s -o %t.rdc.obj // RUN: llvm-readobj --sections %t.rdc.obj \ // RUN: | FileCheck -check-prefix=RDC %s --implicit-check-not='.sycl_fatbin' diff --git a/clang/test/Driver/sycl-offload-jit-unix.cpp b/clang/test/Driver/sycl-offload-jit-unix.cpp index 34812576f78746..c6d78a189ac56c 100644 --- a/clang/test/Driver/sycl-offload-jit-unix.cpp +++ b/clang/test/Driver/sycl-offload-jit-unix.cpp @@ -10,7 +10,8 @@ // RUN: rm -rf %t && mkdir -p %t/bin %t/lib/x86_64-unknown-linux-gnu // RUN: touch %t/lib/x86_64-unknown-linux-gnu/libLLVMSYCL.so // RUN: ln -s %clang %t/bin/clang -// RUN: %t/bin/clang -### -no-canonical-prefixes --target=x86_64-unknown-linux-gnu -fsycl %s 2>&1 \ +// RUN: %t/bin/clang -### -no-canonical-prefixes --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: -resource-dir=%S/Inputs/spirv64-sycl %s 2>&1 \ // RUN: | FileCheck -check-prefixes=CHECK-LSYCL,CHECK-SYCL-HEADERS-HOST,CHECK-SYCL-HEADERS-DEVICE %s // CHECK-SYCL-HEADERS-DEVICE: "-fsycl-is-device"{{.*}} "-internal-isystem" "{{.*}}bin{{[/\\]+}}..{{[/\\]+}}include" // CHECK-SYCL-HEADERS-HOST: "-fsycl-is-host"{{.*}} "-internal-isystem" "{{.*}}bin{{[/\\]+}}..{{[/\\]+}}include" @@ -20,7 +21,8 @@ // RUN: rm -rf %t && mkdir -p %t/bin %t/lib // RUN: touch %t/lib/libLLVMSYCL.so // RUN: ln -s %clang %t/bin/clang -// RUN: %t/bin/clang -### -no-canonical-prefixes --target=x86_64-unknown-linux-gnu -fsycl %s 2>&1 \ +// RUN: %t/bin/clang -### -no-canonical-prefixes --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: -resource-dir=%S/Inputs/spirv64-sycl %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LSYCL-FLAT %s // CHECK-LSYCL-FLAT: clang-linker-wrapper{{.*}} "{{.*}}bin{{[/\\]+}}..{{[/\\]+}}lib{{[/\\]+}}libLLVMSYCL.so" @@ -28,6 +30,7 @@ // RUN: rm -rf %t && mkdir -p %t/bin %t/lib/x86_64-unknown-linux-gnu // RUN: touch %t/lib/x86_64-unknown-linux-gnu/libLLVMSYCL.so // RUN: ln -s %clang %t/bin/clang -// RUN: %t/bin/clang -### -no-canonical-prefixes --target=x86_64-unknown-linux-gnu -fsycl -nolibsycl %s 2>&1 \ +// RUN: %t/bin/clang -### -no-canonical-prefixes --target=x86_64-unknown-linux-gnu -fsycl -nolibsycl \ +// RUN: -resource-dir=%S/Inputs/spirv64-sycl %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-NOLIBSYCL %s // CHECK-NOLIBSYCL-NOT: libLLVMSYCL.so diff --git a/clang/test/Driver/sycl-offload-jit-xarch.cpp b/clang/test/Driver/sycl-offload-jit-xarch.cpp index 53af2b16a33f1b..6801cb5e6da9bc 100644 --- a/clang/test/Driver/sycl-offload-jit-xarch.cpp +++ b/clang/test/Driver/sycl-offload-jit-xarch.cpp @@ -2,12 +2,14 @@ // Verify that -Xarch_spirv64 forwards options to the SYCL device compilation // and clang-linker-wrapper call. -// RUN: %clang -fsycl --offload-targets=spirv64-unknown-unknown -Xarch_spirv64 -O3 -### %s 2>&1 \ +// RUN: %clang -fsycl --no-offloadlib \ +// RUN: --offload-targets=spirv64-unknown-unknown -Xarch_spirv64 -O3 -### %s 2>&1 \ // RUN: | FileCheck -check-prefix=SYCL-DEVICE-O3 %s // SYCL-DEVICE-O3: "-triple" "spirv64-unknown-unknown" "-aux-triple" "{{.*}}" "-O3"{{.*}} "-fsycl-is-device" // SYCL-DEVICE-O3: {{"[^"]*clang-linker-wrapper[^"]*".* "--device-compiler=spirv64-unknown-unknown=-O3"}} // Verify that `-Xarch_spirv64` forwards libraries to the device linker. -// RUN: %clang -fsycl --offload-targets=spirv64-unknown-unknown -Xarch_spirv64 -Wl,-lfoo -### %s 2>&1 \ +// RUN: %clang -fsycl --no-offloadlib \ +// RUN: --offload-targets=spirv64-unknown-unknown -Xarch_spirv64 -Wl,-lfoo -### %s 2>&1 \ // RUN: | FileCheck -check-prefix=DEVICE-LINKER %s // DEVICE-LINKER: {{"[^"]*clang-linker-wrapper[^"]*".* "--device-linker=spirv64-unknown-unknown=-lfoo"}} diff --git a/clang/test/Driver/sycl-offload-jit.cpp b/clang/test/Driver/sycl-offload-jit.cpp index 82733ccd2bc6f2..6060bc4632f5d7 100644 --- a/clang/test/Driver/sycl-offload-jit.cpp +++ b/clang/test/Driver/sycl-offload-jit.cpp @@ -21,7 +21,8 @@ /// Check expected default values for device compilation when using -fsycl as /// well as llvm-offload-binary inputs. -// RUN: %clang -### -fsycl -c --target=x86_64-unknown-linux-gnu %s 2>&1 \ +// RUN: %clang -### -fsycl --no-offloadlib \ +// RUN: -c --target=x86_64-unknown-linux-gnu %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-DEVICE-TRIPLE %s // CHK-DEVICE-TRIPLE: "-cc1"{{.*}} "-triple" "spirv64-unknown-unknown" // CHK-DEVICE-TRIPLE-SAME: "-aux-triple" "x86_64-unknown-linux-gnu" @@ -36,22 +37,23 @@ /// Check -fsycl-is-device is passed when compiling for the device. /// Check -fsycl-is-host is passed when compiling for host. -// RUN: %clang -### -fsycl -c %s 2>&1 \ +// RUN: %clang -### -fsycl --no-offloadlib -c %s 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FSYCL-IS-DEVICE,CHK-FSYCL-IS-HOST %s -// RUN: %clang -### -fsycl -fsycl-device-only %s 2>&1 \ +// RUN: %clang -### -fsycl --no-offloadlib -fsycl-device-only %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FSYCL-IS-DEVICE %s -// RUN: %clang_cl -### -fsycl -c -- %s 2>&1 \ +// RUN: %clang_cl -### -fsycl --no-offloadlib -c -- %s 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-FSYCL-IS-DEVICE,CHK-FSYCL-IS-HOST %s -// RUN: %clang -### -fsycl -fsycl-host-only %s 2>&1 \ +// RUN: %clang -### -fsycl --no-offloadlib -fsycl-host-only %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-FSYCL-IS-HOST %s // CHK-FSYCL-IS-DEVICE: "-cc1"{{.*}} "-fsycl-is-device" {{.*}} "-emit-llvm-bc" // CHK-FSYCL-IS-HOST: "-cc1"{{.*}} "-fsycl-is-host" /// Check that -S with a device-only compilation produces textual SPIR-V, while /// -S -emit-llvm continues to produce textual LLVM IR. -// RUN: %clang -### -fsycl -fsycl-device-only -S %s 2>&1 \ +// RUN: %clang -### -fsycl --no-offloadlib -fsycl-device-only -S %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-DEVICE-ONLY-ASM %s -// RUN: %clang -### -fsycl -fsycl-device-only -S -emit-llvm %s 2>&1 \ +// RUN: %clang -### -fsycl \ +// RUN: --no-offloadlib -fsycl-device-only -S -emit-llvm %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-DEVICE-ONLY-LL %s // CHK-DEVICE-ONLY-ASM: "-cc1"{{.*}} "-fsycl-is-device" // CHK-DEVICE-ONLY-ASM-NOT: "-emit-llvm" @@ -63,11 +65,11 @@ /// Check that SYCL compilation defaults to relocatable device code (-fgpu-rdc /// is passed to both the device and the host -cc1 invocation) and that /// -fno-gpu-rdc disables it. -// RUN: %clang -### -fsycl -c %s 2>&1 \ +// RUN: %clang -### -fsycl --no-offloadlib -c %s 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-SYCL-RDC,CHK-SYCL-RDC-HOST %s -// RUN: %clang -### -fsycl -fgpu-rdc -c %s 2>&1 \ +// RUN: %clang -### -fsycl --no-offloadlib -fgpu-rdc -c %s 2>&1 \ // RUN: | FileCheck -check-prefixes=CHK-SYCL-RDC,CHK-SYCL-RDC-HOST %s -// RUN: %clang -### -fsycl -fno-gpu-rdc -c %s 2>&1 \ +// RUN: %clang -### -fsycl --no-offloadlib -fno-gpu-rdc -c %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-SYCL-NORDC %s // CHK-SYCL-RDC: "-cc1"{{.*}} "-fsycl-is-device" {{.*}} "-fgpu-rdc" // CHK-SYCL-RDC-HOST: "-cc1"{{.*}} "-fsycl-is-host" {{.*}} "-fgpu-rdc" @@ -96,13 +98,15 @@ // CHK-PHASES-NORDC-ARCHS-NEXT: 14: clang-linker-wrapper, {13}, sycl-fatbin, (device-sycl) /// Multiple device triples are not supported today in non-RDC mode. -// RUN: not %clang -### --target=x86_64-unknown-linux-gnu -fsycl -fno-gpu-rdc \ +// RUN: not %clang -### --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: --no-offloadlib -fno-gpu-rdc \ // RUN: --offload-targets=spirv64-unknown-unknown,spirv32-unknown-unknown -c %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-NORDC-MULTI-TRIPLE %s // CHK-NORDC-MULTI-TRIPLE: error: '-fno-gpu-rdc' is not supported with multiple SYCL offloading targets /// Multiple device triples are supported in RDC mode. -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl -fgpu-rdc \ +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: --no-offloadlib -fgpu-rdc \ // RUN: --offload-targets=spirv64-unknown-unknown,spirv32-unknown-unknown -c %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-RDC-MULTI-TRIPLE %s // CHK-RDC-MULTI-TRIPLE-NOT: error: @@ -110,7 +114,8 @@ // CHK-RDC-MULTI-TRIPLE: "-cc1" "-triple" "spirv64-unknown-unknown"{{.*}} "-fsycl-is-device" /// A single target repeated is one target. -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl -fno-gpu-rdc \ +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: --no-offloadlib -fno-gpu-rdc \ // RUN: --offload-targets=spirv64-unknown-unknown,spirv64-unknown-unknown -c %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-NORDC-DUP-TRIPLE %s // CHK-NORDC-DUP-TRIPLE-NOT: error: @@ -119,21 +124,22 @@ /// Check that in non-RDC mode clang-linker-wrapper finalizes the packaged /// device images into a fat binary rather than a host object, and that the /// binary is included into the host compilation via -foffload-include-binary. -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl -fno-gpu-rdc -c %s 2>&1 \ +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl --no-offloadlib -fno-gpu-rdc -c %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-NORDC-INCLUDE %s \ // RUN: --implicit-check-not='"-fembed-offload-object=' // CHK-NORDC-INCLUDE: clang-linker-wrapper{{.*}} "--linker-path={{.*}}clang-sycl-linker" "--emit-fatbin-only" "-o" "[[FB:.*]].syclfb" // CHK-NORDC-INCLUDE: "-cc1"{{.*}} "-fsycl-is-host"{{.*}} "-foffload-include-binary" "[[FB]].syclfb" /// Conversely, RDC mode embeds unlinked device code via -fembed-offload-object. -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl -fgpu-rdc %s 2>&1 \ +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: --no-offloadlib -fgpu-rdc %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-RDC-EMBED %s \ // RUN: --implicit-check-not='"-foffload-include-binary"' \ // RUN: --implicit-check-not='"--emit-fatbin-only"' // CHK-RDC-EMBED: "-cc1"{{.*}} "-fsycl-is-host"{{.*}} "-fembed-offload-object= /// -v reaches the per-TU device finalize and the wrapper itself. -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl -fno-gpu-rdc -v -c %s 2>&1 \ +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl --no-offloadlib -fno-gpu-rdc -v -c %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-NORDC-VERBOSE %s // CHK-NORDC-VERBOSE: clang-linker-wrapper{{.*}} "--device-compiler=spirv64-unknown-unknown=-v" // CHK-NORDC-VERBOSE-SAME: "--wrapper-verbose" @@ -143,10 +149,12 @@ /// per-TU device finalize to llvm-lto, which would write bitcode where a /// finalized device image is expected; the device link is unaffected and the /// binary is still included at compile time. -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl -fno-gpu-rdc \ +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: --no-offloadlib -fno-gpu-rdc \ // RUN: -flto -c %s 2>&1 | FileCheck -check-prefix=CHK-NORDC-LTO %s \ // RUN: --implicit-check-not=llvm-lto -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl -fno-gpu-rdc \ +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: --no-offloadlib -fno-gpu-rdc \ // RUN: -flto %s 2>&1 | FileCheck -check-prefix=CHK-NORDC-LTO %s \ // RUN: --implicit-check-not=llvm-lto // CHK-NORDC-LTO: clang-linker-wrapper{{.*}} "--linker-path={{.*}}clang-sycl-linker" "--emit-fatbin-only" @@ -154,29 +162,35 @@ // Check that --allow-partial-linkage and --create-library are not passed to // clang-linker-wrapper for SYCL (they are spirv-link flags, not clang-sycl-linker flags). -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl %s 2>&1 \ +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: --no-offloadlib %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-NO-SPIRVLINK-FLAGS %s // CHECK-NO-SPIRVLINK-FLAGS-NOT: --device-linker=spirv64-unknown-unknown=--allow-partial-linkage // CHECK-NO-SPIRVLINK-FLAGS-NOT: --device-linker=spirv64-unknown-unknown=--create-library /// Check -fsycl-device-image-split= is forwarded to clang-sycl-linker as the /// corresponding --module-split-mode= value. -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl -fsycl-device-image-split=kernel %s 2>&1 \ +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl --no-offloadlib \ +// RUN: -fsycl-device-image-split=kernel %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-SPLIT-KERNEL %s // CHK-SPLIT-KERNEL: clang-linker-wrapper{{.*}}"--device-linker=spirv64-unknown-unknown=--module-split-mode=kernel" -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl -fsycl-device-image-split=translation_unit %s 2>&1 \ +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl --no-offloadlib \ +// RUN: -fsycl-device-image-split=translation_unit %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-SPLIT-TU %s // CHK-SPLIT-TU: clang-linker-wrapper{{.*}}"--device-linker=spirv64-unknown-unknown=--module-split-mode=translation_unit" -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl -fsycl-device-image-split=link_unit %s 2>&1 \ +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl --no-offloadlib \ +// RUN: -fsycl-device-image-split=link_unit %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-SPLIT-LU %s // CHK-SPLIT-LU: clang-linker-wrapper{{.*}}"--device-linker=spirv64-unknown-unknown=--module-split-mode=link_unit" /// Check the bare -fsycl-device-image-split flag aliases to 'translation_unit'. -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl -fsycl-device-image-split %s 2>&1 \ +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl --no-offloadlib \ +// RUN: -fsycl-device-image-split %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-SPLIT-TU %s /// Check that without -fsycl-device-image-split, no --module-split-mode= is passed. -// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl %s 2>&1 \ +// RUN: %clang -### --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: --no-offloadlib %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-NO-SPLIT %s // CHK-NO-SPLIT-NOT: --module-split-mode= @@ -186,12 +200,15 @@ // CHK-SPLIT-INVALID: error: invalid value 'bogus' in '-fsycl-device-image-split=' /// Check -fsycl-device-image-split is unused when not linking (e.g. -c). -// RUN: %clang -### -c --target=x86_64-unknown-linux-gnu -fsycl -fsycl-device-image-split=kernel %s 2>&1 \ +// RUN: %clang -### -c --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: --no-offloadlib \ +// RUN: -fsycl-device-image-split=kernel %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-SPLIT-UNUSED %s // CHK-SPLIT-UNUSED: warning: argument unused during compilation: '-fsycl-device-image-split=kernel' /// In non-RDC mode the split does happen while compiling. -// RUN: %clang -### -c --target=x86_64-unknown-linux-gnu -fsycl -fno-gpu-rdc \ +// RUN: %clang -### -c --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: --no-offloadlib -fno-gpu-rdc \ // RUN: -fsycl-device-image-split=kernel %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHK-SPLIT-KERNEL %s \ // RUN: --implicit-check-not='argument unused during compilation' diff --git a/clang/test/Driver/sycl-rtlib-sysroot-mismatch.cpp b/clang/test/Driver/sycl-rtlib-sysroot-mismatch.cpp index 87ed4ba1f9ff79..8a339edaeeeca2 100644 --- a/clang/test/Driver/sycl-rtlib-sysroot-mismatch.cpp +++ b/clang/test/Driver/sycl-rtlib-sysroot-mismatch.cpp @@ -5,13 +5,15 @@ // RUN: rm -rf %t && mkdir -p %t/bin %t/lib // RUN: touch %t/lib/libLLVMSYCL.so // RUN: ln -s %clang %t/bin/clang -// RUN: %t/bin/clang -### -no-canonical-prefixes --target=x86_64-unknown-linux-gnu -fsycl --sysroot=/nonexistent-prefix %s 2>&1 \ +// RUN: %t/bin/clang -### -no-canonical-prefixes --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: -resource-dir=%S/Inputs/spirv64-sycl --sysroot=/nonexistent-prefix %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-FLAT %s // RUN: rm -rf %t && mkdir -p %t/bin %t/lib/x86_64-unknown-linux-gnu // RUN: touch %t/lib/x86_64-unknown-linux-gnu/libLLVMSYCL.so // RUN: ln -s %clang %t/bin/clang -// RUN: %t/bin/clang -### -no-canonical-prefixes --target=x86_64-unknown-linux-gnu -fsycl --sysroot=/nonexistent-prefix %s 2>&1 \ +// RUN: %t/bin/clang -### -no-canonical-prefixes --target=x86_64-unknown-linux-gnu -fsycl \ +// RUN: -resource-dir=%S/Inputs/spirv64-sycl --sysroot=/nonexistent-prefix %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-PER-TARGET %s // CHECK-FLAT: "{{.*}}/bin/../lib/libLLVMSYCL.so" diff --git a/clang/test/Driver/sycl-std-default.cpp b/clang/test/Driver/sycl-std-default.cpp index df377169a39441..ad73522bed1c63 100644 --- a/clang/test/Driver/sycl-std-default.cpp +++ b/clang/test/Driver/sycl-std-default.cpp @@ -1,6 +1,6 @@ // Tests that SYCL defaults to C++17 when no -std= is specified -// RUN: %clangxx -### -fsycl -c %s 2>&1 | FileCheck %s --check-prefixes=CHECK-DEVICE,CHECK-HOST +// RUN: %clangxx -### -fsycl --no-offloadlib -c %s 2>&1 | FileCheck %s --check-prefixes=CHECK-DEVICE,CHECK-HOST // CHECK-DEVICE: "-cc1"{{.*}} "-fsycl-is-device" // CHECK-DEVICE-SAME: "-std=c++17" @@ -8,7 +8,7 @@ // CHECK-HOST-SAME: "-std=c++17" // Test that explicit -std= overrides the default -// RUN: %clangxx -### -fsycl -std=c++20 -c %s 2>&1 | FileCheck %s --check-prefixes=CHECK-OVERRIDE-DEVICE,CHECK-OVERRIDE-HOST +// RUN: %clangxx -### -fsycl --no-offloadlib -std=c++20 -c %s 2>&1 | FileCheck %s --check-prefixes=CHECK-OVERRIDE-DEVICE,CHECK-OVERRIDE-HOST // CHECK-OVERRIDE-DEVICE: "-cc1"{{.*}} "-fsycl-is-device" // CHECK-OVERRIDE-DEVICE-SAME: "-std=c++20" @@ -34,7 +34,7 @@ // CHECK-C99-ERROR: error: invalid argument '-std=c99' not allowed with '-fsycl' // Test on Windows with clang-cl (MSVC mode) -// RUN: %clang_cl --target=x86_64-pc-windows-msvc -### -fsycl -- %s 2>&1 | FileCheck %s --check-prefixes=CHECK-MSVC-DEVICE,CHECK-MSVC-HOST +// RUN: %clang_cl --target=x86_64-pc-windows-msvc -### -fsycl --no-offloadlib -- %s 2>&1 | FileCheck %s --check-prefixes=CHECK-MSVC-DEVICE,CHECK-MSVC-HOST // CHECK-MSVC-DEVICE: "-cc1"{{.*}} "-fsycl-is-device" // CHECK-MSVC-DEVICE-SAME: "-std=c++17" @@ -42,7 +42,7 @@ // CHECK-MSVC-HOST-SAME: "-std=c++17" // Test that /std: override works on Windows -// RUN: %clang_cl --target=x86_64-pc-windows-msvc -### -fsycl /std:c++20 -- %s 2>&1 | FileCheck %s --check-prefixes=CHECK-MSVC-OVERRIDE-DEVICE,CHECK-MSVC-OVERRIDE-HOST +// RUN: %clang_cl --target=x86_64-pc-windows-msvc -### -fsycl --no-offloadlib /std:c++20 -- %s 2>&1 | FileCheck %s --check-prefixes=CHECK-MSVC-OVERRIDE-DEVICE,CHECK-MSVC-OVERRIDE-HOST // CHECK-MSVC-OVERRIDE-DEVICE: "-cc1"{{.*}} "-fsycl-is-device" // CHECK-MSVC-OVERRIDE-DEVICE-SAME: "-std=c++20" diff --git a/clang/test/Driver/sycl-windows.cpp b/clang/test/Driver/sycl-windows.cpp index f07c05e74c3c7c..e4b26feaa9292c 100644 --- a/clang/test/Driver/sycl-windows.cpp +++ b/clang/test/Driver/sycl-windows.cpp @@ -6,7 +6,7 @@ // -libpath: in linker output. /// Test 1: /MD (explicit) and release library dependency -// RUN: %clang_cl -### -fsycl /MD --target=x86_64-pc-windows-msvc -- %s 2>&1 \ +// RUN: %clang_cl -### -fsycl --no-offloadlib /MD --target=x86_64-pc-windows-msvc -- %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-MD %s // CHECK-MD: "-cc1" // CHECK-MD: "--dependent-lib=LLVMSYCL" @@ -24,14 +24,14 @@ // CHECK-MTD-ERROR: error: SYCL requires dynamic C++ runtime /// Test 4: /MD uses release library -// RUN: %clang_cl -### -fsycl /MD --target=x86_64-pc-windows-msvc -- %s 2>&1 \ +// RUN: %clang_cl -### -fsycl --no-offloadlib /MD --target=x86_64-pc-windows-msvc -- %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-RELEASE %s // CHECK-RELEASE: "-cc1" // CHECK-RELEASE: "--dependent-lib=LLVMSYCL" // CHECK-RELEASE-NOT: LLVMSYCLd /// Test 5: /MDd uses debug library -// RUN: %clang_cl -### -fsycl /MDd --target=x86_64-pc-windows-msvc -- %s 2>&1 \ +// RUN: %clang_cl -### -fsycl --no-offloadlib /MDd --target=x86_64-pc-windows-msvc -- %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-DEBUG %s // CHECK-DEBUG: "-cc1" // CHECK-DEBUG: "--dependent-lib=LLVMSYCLd" @@ -44,70 +44,70 @@ // CHECK-STATIC-ERROR: error: SYCL requires dynamic C++ runtime /// Test 7: -fms-runtime-lib=dll_dbg uses debug library -// RUN: %clang_cl -### -fsycl -fms-runtime-lib=dll_dbg \ +// RUN: %clang_cl -### -fsycl --no-offloadlib -fms-runtime-lib=dll_dbg \ // RUN: --target=x86_64-pc-windows-msvc -- %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-FLAG-DEBUG %s // CHECK-FLAG-DEBUG: "-cc1" // CHECK-FLAG-DEBUG: "--dependent-lib=LLVMSYCLd" /// Test 8: LNK4078 warning is suppressed -// RUN: %clang_cl -### -fsycl --target=x86_64-pc-windows-msvc -- %s 2>&1 \ +// RUN: %clang_cl -### -fsycl --no-offloadlib --target=x86_64-pc-windows-msvc -- %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-IGNORE %s // CHECK-IGNORE: clang-linker-wrapper" // CHECK-IGNORE: "/IGNORE:4078" /// Test 9: -nolibsycl skips library dependency and CRT check -// RUN: %clang_cl -### -fsycl -nolibsycl /MT \ +// RUN: %clang_cl -### -fsycl -nolibsycl --no-offloadlib /MT \ // RUN: --target=x86_64-pc-windows-msvc -- %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-NOLIBSYCL %s // CHECK-NOLIBSYCL-NOT: error: // CHECK-NOLIBSYCL-NOT: "--dependent-lib=LLVMSYCL" /// Test 10: Explicit /MD results in correct library -// RUN: %clang_cl -### -fsycl /MD --target=x86_64-pc-windows-msvc -- %s 2>&1 \ +// RUN: %clang_cl -### -fsycl --no-offloadlib /MD --target=x86_64-pc-windows-msvc -- %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-EXPLICIT-MD %s // CHECK-EXPLICIT-MD: "-cc1" // CHECK-EXPLICIT-MD: "--dependent-lib=LLVMSYCL" /// Test 11: Library search path is added at linker stage -// RUN: %clang_cl -### -fsycl /MD --target=x86_64-pc-windows-msvc -- %s 2>&1 \ +// RUN: %clang_cl -### -fsycl --no-offloadlib /MD --target=x86_64-pc-windows-msvc -- %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-LIBPATH %s // CHECK-LIBPATH: clang-linker-wrapper" // CHECK-LIBPATH: "-libpath:{{.*}}{{[/\\]+}}lib" /// Test 12: clang (non-clang-cl) with MSVC target uses -defaultlib: -// RUN: %clang -### -fsycl -fms-runtime-lib=dll --target=x86_64-pc-windows-msvc -- %s 2>&1 \ +// RUN: %clang -### -fsycl --no-offloadlib -fms-runtime-lib=dll --target=x86_64-pc-windows-msvc -- %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-CLANG-DEFAULTLIB %s // CHECK-CLANG-DEFAULTLIB: clang-linker-wrapper" // CHECK-CLANG-DEFAULTLIB: "-libpath:{{.*}}{{[/\\]+}}lib" // CHECK-CLANG-DEFAULTLIB: "-defaultlib:LLVMSYCL" /// Test 13: clang with -fms-runtime-lib=dll_dbg uses debug library via -defaultlib: -// RUN: %clang -### -fsycl -fms-runtime-lib=dll_dbg --target=x86_64-pc-windows-msvc -- %s 2>&1 \ +// RUN: %clang -### -fsycl --no-offloadlib -fms-runtime-lib=dll_dbg --target=x86_64-pc-windows-msvc -- %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-CLANG-DEBUG %s // CHECK-CLANG-DEBUG: clang-linker-wrapper" // CHECK-CLANG-DEBUG: "-defaultlib:LLVMSYCLd" /// Test 14: Default CRT behavior - release library when no CRT flag specified -// RUN: %clang -### -fsycl -fms-runtime-lib=dll --target=x86_64-pc-windows-msvc -- %s 2>&1 \ +// RUN: %clang -### -fsycl --no-offloadlib -fms-runtime-lib=dll --target=x86_64-pc-windows-msvc -- %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-DEFAULT-CRT %s // CHECK-DEFAULT-CRT: "-cc1" // CHECK-DEFAULT-CRT: "--dependent-lib=LLVMSYCL" // CHECK-DEFAULT-CRT-NOT: LLVMSYCLd /// Test 15: Separate compilation - compile step embeds --dependent-lib in object -// RUN: %clang -### -fsycl -c -fms-runtime-lib=dll --target=x86_64-pc-windows-msvc -- %s 2>&1 \ +// RUN: %clang -### -fsycl --no-offloadlib -c -fms-runtime-lib=dll --target=x86_64-pc-windows-msvc -- %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-SEP-COMPILE %s // CHECK-SEP-COMPILE: "--dependent-lib=LLVMSYCL" /// Test 16: Separate compilation - link step adds -libpath: and -defaultlib: for pre-compiled object // RUN: touch %t.obj -// RUN: %clang -### -fsycl -fms-runtime-lib=dll --target=x86_64-pc-windows-msvc -- %t.obj 2>&1 \ +// RUN: %clang -### -fsycl --no-offloadlib -fms-runtime-lib=dll --target=x86_64-pc-windows-msvc -- %t.obj 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-SEP-LINK %s // CHECK-SEP-LINK: "-libpath:{{.*}}{{[/\\]+}}lib" // CHECK-SEP-LINK: "-defaultlib:LLVMSYCL" /// Test 17: clang (non-clang-cl) with -nolibsycl suppresses -defaultlib:LLVMSYCL -// RUN: %clang -### -fsycl -nolibsycl -fms-runtime-lib=dll --target=x86_64-pc-windows-msvc -- %s 2>&1 \ +// RUN: %clang -### -fsycl -nolibsycl --no-offloadlib -fms-runtime-lib=dll --target=x86_64-pc-windows-msvc -- %s 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-CLANG-NOLIBSYCL %s // CHECK-CLANG-NOLIBSYCL-NOT: "-defaultlib:LLVMSYCL" diff --git a/clang/test/Driver/sycl.cpp b/clang/test/Driver/sycl.cpp index e78b2a75933232..fdd397579af0fa 100644 --- a/clang/test/Driver/sycl.cpp +++ b/clang/test/Driver/sycl.cpp @@ -1,18 +1,18 @@ -// RUN: %clang -### -fsycl -c %s 2>&1 | FileCheck %s --check-prefix=ENABLED -// RUN: %clang -### -fsycl %s 2>&1 | FileCheck %s --check-prefix=ENABLED -// RUN: %clang -### -fsycl -sycl-std=1.2.1 %s 2>&1 | FileCheck %s --check-prefix=ENABLED -// RUN: %clang -### -fsycl -sycl-std=121 %s 2>&1 | FileCheck %s --check-prefix=ENABLED -// RUN: %clang -### -fsycl -sycl-std=2017 %s 2>&1 | FileCheck %s --check-prefix=ENABLED -// RUN: %clang -### -fsycl -sycl-std=2020 %s 2>&1 | FileCheck %s --check-prefix=ENABLED -// RUN: %clang -### -fsycl -sycl-std=sycl-1.2.1 %s 2>&1 | FileCheck %s --check-prefix=ENABLED -// RUN: %clang -### -fno-sycl -fsycl %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clang -### -fsycl --no-offloadlib -c %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clang -### -fsycl --no-offloadlib %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clang -### -fsycl --no-offloadlib -sycl-std=1.2.1 %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clang -### -fsycl --no-offloadlib -sycl-std=121 %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clang -### -fsycl --no-offloadlib -sycl-std=2017 %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clang -### -fsycl --no-offloadlib -sycl-std=2020 %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clang -### -fsycl --no-offloadlib -sycl-std=sycl-1.2.1 %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clang -### -fno-sycl -fsycl --no-offloadlib %s 2>&1 | FileCheck %s --check-prefix=ENABLED // RUN: %clang -### -sycl-std=2017 %s 2>&1 | FileCheck %s --check-prefix=DISABLED -// RUN: %clangxx -### -fsycl %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clangxx -### -fsycl --no-offloadlib %s 2>&1 | FileCheck %s --check-prefix=ENABLED // RUN: %clangxx -### -fno-sycl %s 2>&1 | FileCheck %s --check-prefix=DISABLED // RUN: %clangxx -### -fsycl -fno-sycl %s 2>&1 | FileCheck %s --check-prefix=DISABLED // RUN: %clangxx -### %s 2>&1 | FileCheck %s --check-prefix=DISABLED -// RUN: %clang_cl -### -fsycl -sycl-std=2017 -- %s 2>&1 | FileCheck %s --check-prefix=ENABLED -// RUN: %clang_cl -### -fsycl -- %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clang_cl -### -fsycl --no-offloadlib -sycl-std=2017 -- %s 2>&1 | FileCheck %s --check-prefix=ENABLED +// RUN: %clang_cl -### -fsycl --no-offloadlib -- %s 2>&1 | FileCheck %s --check-prefix=ENABLED // RUN: %clang_cl -### -- %s 2>&1 | FileCheck %s --check-prefix=DISABLED // ENABLED: "-cc1"{{.*}} "-fsycl-is-device" @@ -20,9 +20,9 @@ // DISABLED-NOT: "-fsycl-is-device" // DISABLED-NOT: "-sycl-std=" -// RUN: %clang -### -fsycl %s 2>&1 | FileCheck %s --check-prefix=DEFAULT -// RUN: %clangxx -### -fsycl %s 2>&1 | FileCheck %s --check-prefix=DEFAULT -// RUN: %clang_cl -### -fsycl -- %s 2>&1 | FileCheck %s --check-prefix=DEFAULT +// RUN: %clang -### -fsycl --no-offloadlib %s 2>&1 | FileCheck %s --check-prefix=DEFAULT +// RUN: %clangxx -### -fsycl --no-offloadlib %s 2>&1 | FileCheck %s --check-prefix=DEFAULT +// RUN: %clang_cl -### -fsycl --no-offloadlib -- %s 2>&1 | FileCheck %s --check-prefix=DEFAULT // DEFAULT: "-sycl-std=2020" @@ -32,5 +32,5 @@ // CHECK-NO-OFFLOADLIB-NOT: warning: unknown argument ignored in clang-cl: '--no-offloadlib' // Verify that -fsycl with a C input is an error (enforced in the frontend). -// RUN: not %clang -fsycl -x c %s 2>&1 | FileCheck %s --check-prefix=CHECK-C-INPUT +// RUN: not %clang -fsycl --no-offloadlib -x c %s 2>&1 | FileCheck %s --check-prefix=CHECK-C-INPUT // CHECK-C-INPUT: error: invalid argument 'C' not allowed with '-fsycl' From 406dbc298faa25b1f8c2f1ce3d081a842e551786 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Sat, 24 Oct 2026 21:25:00 +0100 Subject: [PATCH 25/31] [VPlan] Drop poison-gen attributes & metadata on replicated clones. (#234613) VPReplicateRecipe::execute clones the original instruction, carrying over all metadata & attributes. Clear poison-generating attributes & metadata, to make sure we only apply the attributes & metadata carried by the recipe itself. PR: https://github.com/llvm/llvm-project/pull/234613 --- .../lib/Transforms/Vectorize/VPlanRecipes.cpp | 2 ++ .../illegal-parallel-loop-uniform-write.ll | 2 +- .../cse-replicate-poison-generating.ll | 22 +++++++++---------- ...eref-pred-poison-ub-ops-feeding-pointer.ll | 2 +- .../test/Transforms/LoopVectorize/metadata.ll | 8 +++---- 5 files changed, 18 insertions(+), 18 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp index 295cb47def8b70..420c04350f8a2c 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp @@ -4109,6 +4109,8 @@ void VPReplicateRecipe::execute(VPTransformState &State) { Cloned->mutateType(ResultTy); } + Cloned->dropUBImplyingAttrsAndUnknownMetadata(); + Cloned->dropPoisonGeneratingAttributes(); applyFlags(*Cloned); applyMetadata(*Cloned); diff --git a/llvm/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll b/llvm/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll index 0c65df4e449366..8966ba072f3b92 100644 --- a/llvm/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll +++ b/llvm/test/Transforms/LoopVectorize/X86/illegal-parallel-loop-uniform-write.ll @@ -73,7 +73,7 @@ define void @foo(ptr nocapture %a, ptr nocapture %b, i32 %k, i32 %m) #0 { ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP15]], align 4 ; CHECK-NEXT: [[TMP17:%.*]] = add nsw <4 x i32> [[WIDE_LOAD]], splat (i32 1) ; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i32> [[TMP17]], i64 3 -; CHECK-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX7_US]], align 4, !llvm.mem.parallel_loop_access [[META0]] +; CHECK-NEXT: store i32 [[TMP16]], ptr [[ARRAYIDX7_US]], align 4 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[OFFSET_IDX]], 4 ; CHECK-NEXT: [[TMP19:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP19]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] diff --git a/llvm/test/Transforms/LoopVectorize/cse-replicate-poison-generating.ll b/llvm/test/Transforms/LoopVectorize/cse-replicate-poison-generating.ll index 72396a3bdf109e..a1b777add8596a 100644 --- a/llvm/test/Transforms/LoopVectorize/cse-replicate-poison-generating.ll +++ b/llvm/test/Transforms/LoopVectorize/cse-replicate-poison-generating.ll @@ -73,7 +73,6 @@ exit: ; Replicated calls differ only in a range return attribute; the merged call ; must not keep it. -; FIXME: currently miscompiled. define void @call_range_attr(ptr noalias %src, ptr noalias %dst.1, ptr noalias %dst.2, i64 %n) { ; CHECK-LABEL: define void @call_range_attr( ; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST_1:%.*]], ptr noalias [[DST_2:%.*]], i64 [[N:%.*]]) { @@ -89,13 +88,13 @@ define void @call_range_attr(ptr noalias %src, ptr noalias %dst.1, ptr noalias % ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i64 0 -; CHECK-NEXT: [[TMP3:%.*]] = call range(i32 0, 10) i32 @g(i32 [[TMP2]]) #[[ATTR1:[0-9]+]] +; CHECK-NEXT: [[TMP3:%.*]] = call i32 @g(i32 [[TMP2]]) #[[ATTR1:[0-9]+]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i64 1 -; CHECK-NEXT: [[TMP5:%.*]] = call range(i32 0, 10) i32 @g(i32 [[TMP4]]) #[[ATTR1]] +; CHECK-NEXT: [[TMP5:%.*]] = call i32 @g(i32 [[TMP4]]) #[[ATTR1]] ; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i64 2 -; CHECK-NEXT: [[TMP7:%.*]] = call range(i32 0, 10) i32 @g(i32 [[TMP6]]) #[[ATTR1]] +; CHECK-NEXT: [[TMP7:%.*]] = call i32 @g(i32 [[TMP6]]) #[[ATTR1]] ; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i64 3 -; CHECK-NEXT: [[TMP9:%.*]] = call range(i32 0, 10) i32 @g(i32 [[TMP8]]) #[[ATTR1]] +; CHECK-NEXT: [[TMP9:%.*]] = call i32 @g(i32 [[TMP8]]) #[[ATTR1]] ; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> poison, i32 [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP5]], i64 1 ; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP7]], i64 2 @@ -152,7 +151,6 @@ exit: ; Replicated calls differ only in !range metadata; the merged call must not ; keep it. -; FIXME: currently miscompiled. define void @call_range_md(ptr noalias %src, ptr noalias %dst.1, ptr noalias %dst.2, i64 %n) { ; CHECK-LABEL: define void @call_range_md( ; CHECK-SAME: ptr noalias [[SRC:%.*]], ptr noalias [[DST_1:%.*]], ptr noalias [[DST_2:%.*]], i64 [[N:%.*]]) { @@ -168,13 +166,13 @@ define void @call_range_md(ptr noalias %src, ptr noalias %dst.1, ptr noalias %ds ; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[INDEX]] ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i64 0 -; CHECK-NEXT: [[TMP3:%.*]] = call i32 @g(i32 [[TMP2]]) #[[ATTR1]], !range [[RNG6:![0-9]+]] +; CHECK-NEXT: [[TMP3:%.*]] = call i32 @g(i32 [[TMP2]]) #[[ATTR1]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i64 1 -; CHECK-NEXT: [[TMP5:%.*]] = call i32 @g(i32 [[TMP4]]) #[[ATTR1]], !range [[RNG6]] +; CHECK-NEXT: [[TMP5:%.*]] = call i32 @g(i32 [[TMP4]]) #[[ATTR1]] ; CHECK-NEXT: [[TMP6:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i64 2 -; CHECK-NEXT: [[TMP7:%.*]] = call i32 @g(i32 [[TMP6]]) #[[ATTR1]], !range [[RNG6]] +; CHECK-NEXT: [[TMP7:%.*]] = call i32 @g(i32 [[TMP6]]) #[[ATTR1]] ; CHECK-NEXT: [[TMP8:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i64 3 -; CHECK-NEXT: [[TMP9:%.*]] = call i32 @g(i32 [[TMP8]]) #[[ATTR1]], !range [[RNG6]] +; CHECK-NEXT: [[TMP9:%.*]] = call i32 @g(i32 [[TMP8]]) #[[ATTR1]] ; CHECK-NEXT: [[TMP10:%.*]] = insertelement <4 x i32> poison, i32 [[TMP3]], i64 0 ; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP10]], i32 [[TMP5]], i64 1 ; CHECK-NEXT: [[TMP12:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP7]], i64 2 @@ -196,7 +194,7 @@ define void @call_range_md(ptr noalias %src, ptr noalias %dst.1, ptr noalias %ds ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] ; CHECK-NEXT: [[GEP_SRC:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[IV]] ; CHECK-NEXT: [[L:%.*]] = load i32, ptr [[GEP_SRC]], align 4 -; CHECK-NEXT: [[C_1:%.*]] = call i32 @g(i32 [[L]]) #[[ATTR1]], !range [[RNG6]] +; CHECK-NEXT: [[C_1:%.*]] = call i32 @g(i32 [[L]]) #[[ATTR1]], !range [[RNG6:![0-9]+]] ; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr inbounds i32, ptr [[DST_1]], i64 [[IV]] ; CHECK-NEXT: store i32 [[C_1]], ptr [[GEP_DST_1]], align 4 ; CHECK-NEXT: [[C_2:%.*]] = call i32 @g(i32 [[L]]) #[[ATTR1]] @@ -243,7 +241,7 @@ attributes #1 = { nounwind willreturn memory(none) } ; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} ; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} ; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} -; CHECK: [[RNG6]] = !{i32 0, i32 10} ; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]]} +; CHECK: [[RNG6]] = !{i32 0, i32 10} ; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META2]], [[META1]]} ;. diff --git a/llvm/test/Transforms/LoopVectorize/load-deref-pred-poison-ub-ops-feeding-pointer.ll b/llvm/test/Transforms/LoopVectorize/load-deref-pred-poison-ub-ops-feeding-pointer.ll index 0f8967f11bf249..41423b51d6440a 100644 --- a/llvm/test/Transforms/LoopVectorize/load-deref-pred-poison-ub-ops-feeding-pointer.ll +++ b/llvm/test/Transforms/LoopVectorize/load-deref-pred-poison-ub-ops-feeding-pointer.ll @@ -286,7 +286,7 @@ define void @ptr_depends_on_noundef_load(ptr noalias %dst) { ; CHECK: [[VECTOR_PH]]: ; CHECK-NEXT: br label %[[VECTOR_BODY:.*]] ; CHECK: [[VECTOR_BODY]]: -; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr @src, align 1, !noundef [[META0:![0-9]+]] +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr @src, align 1 ; CHECK-NEXT: [[TMP2:%.*]] = sub i16 1, [[TMP0]] ; CHECK-NEXT: [[TMP3:%.*]] = add i16 [[TMP2]], [[TMP0]] ; CHECK-NEXT: [[TMP4:%.*]] = add i16 9, [[TMP3]] diff --git a/llvm/test/Transforms/LoopVectorize/metadata.ll b/llvm/test/Transforms/LoopVectorize/metadata.ll index 0d4f96cba9ea4f..f13c96152363ce 100644 --- a/llvm/test/Transforms/LoopVectorize/metadata.ll +++ b/llvm/test/Transforms/LoopVectorize/metadata.ll @@ -401,7 +401,7 @@ define void @unknown_metadata(ptr nocapture %a, ptr noalias %b, i64 %size) { ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND:%.*]] = phi <2 x i64> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] ; CHECK-NEXT: [[VEC_IND1:%.*]] = phi <2 x i32> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT2:%.*]], %[[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[INDEX]], !custom_md [[META2:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[INDEX]] ; CHECK-NEXT: [[WIDE_GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], <2 x i64> [[VEC_IND]] ; CHECK-NEXT: [[TMP2:%.*]] = extractelement <2 x ptr> [[WIDE_GEP]], i64 0 ; CHECK-NEXT: store <2 x i32> [[VEC_IND1]], ptr [[TMP2]], align 4 @@ -419,7 +419,7 @@ define void @unknown_metadata(ptr nocapture %a, ptr noalias %b, i64 %size) { ; CHECK-NEXT: br label %[[LOOP:.*]] ; CHECK: [[LOOP]]: ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] -; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[IV]], !custom_md [[META2]] +; CHECK-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[IV]], !custom_md [[META2:![0-9]+]] ; CHECK-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]], !custom_md [[META2]] ; CHECK-NEXT: [[T:%.*]] = trunc i64 [[IV]] to i32, !custom_md [[META3]] ; CHECK-NEXT: store i32 [[T]], ptr [[ARRAYIDX_2]], align 4, !custom_md [[META2]] @@ -445,7 +445,7 @@ define void @unknown_metadata(ptr nocapture %a, ptr noalias %b, i64 %size) { ; INTERLEAVE-NEXT: [[VEC_IND1:%.*]] = phi <2 x i32> [ , %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT4:%.*]], %[[VECTOR_BODY]] ] ; INTERLEAVE-NEXT: [[STEP_ADD:%.*]] = add nuw <2 x i64> [[VEC_IND]], splat (i64 2) ; INTERLEAVE-NEXT: [[STEP_ADD2:%.*]] = add <2 x i32> [[VEC_IND1]], splat (i32 2) -; INTERLEAVE-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[INDEX]], !custom_md [[META2:![0-9]+]] +; INTERLEAVE-NEXT: [[TMP1:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[INDEX]] ; INTERLEAVE-NEXT: [[WIDE_GEP:%.*]] = getelementptr inbounds i32, ptr [[B]], <2 x i64> [[VEC_IND]] ; INTERLEAVE-NEXT: [[TMP2:%.*]] = extractelement <2 x ptr> [[WIDE_GEP]], i64 0 ; INTERLEAVE-NEXT: [[WIDE_GEP3:%.*]] = getelementptr inbounds i32, ptr [[B]], <2 x i64> [[STEP_ADD]] @@ -468,7 +468,7 @@ define void @unknown_metadata(ptr nocapture %a, ptr noalias %b, i64 %size) { ; INTERLEAVE-NEXT: br label %[[LOOP:.*]] ; INTERLEAVE: [[LOOP]]: ; INTERLEAVE-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] -; INTERLEAVE-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[IV]], !custom_md [[META2]] +; INTERLEAVE-NEXT: [[ARRAYIDX_1:%.*]] = getelementptr inbounds ptr, ptr [[A]], i64 [[IV]], !custom_md [[META2:![0-9]+]] ; INTERLEAVE-NEXT: [[ARRAYIDX_2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]], !custom_md [[META2]] ; INTERLEAVE-NEXT: [[T:%.*]] = trunc i64 [[IV]] to i32, !custom_md [[META3]] ; INTERLEAVE-NEXT: store i32 [[T]], ptr [[ARRAYIDX_2]], align 4, !custom_md [[META2]] From 8f8e41f7cb5800e4a31db152a322435d31722ffd Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Sat, 24 Oct 2026 21:51:55 +0100 Subject: [PATCH 26/31] [VPlan] Simplify epilogue connection (NFC). (#235344) Follow-up to https://github.com/llvm/llvm-project/pull/229921 to slightly simplify the code. --- .../Vectorize/LoopVectorizationPlanner.h | 6 ++- .../Transforms/Vectorize/LoopVectorize.cpp | 28 +++++++---- llvm/lib/Transforms/Vectorize/VPlan.cpp | 23 ++++------ .../Vectorize/VPlanConstruction.cpp | 46 +++++++++---------- .../Transforms/Vectorize/VPlanTransforms.h | 10 ++-- .../VPlan/epilogue-vectorization-printing.ll | 10 ++-- 6 files changed, 66 insertions(+), 57 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h index c31a85be1920b7..04a5528c3e2fc0 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h +++ b/llvm/lib/Transforms/Vectorize/LoopVectorizationPlanner.h @@ -991,6 +991,9 @@ class LoopVectorizationPlanner { /// TODO: \p EpilogueVecKind should be removed once the re-use issue has been /// fixed. /// + /// When vectorizing the main loop, \p TrackedBlocks are updated to the + /// VPIRBasicBlocks wrapping the blocks generated for them. + /// /// Returns a mapping of SCEVs to their expanded IR values. /// Note that this is a temporary workaround needed due to the current /// epilogue handling. @@ -1003,7 +1006,8 @@ class LoopVectorizationPlanner { executePlan(ElementCount VF, unsigned UF, VPlan &BestPlan, InnerLoopVectorizer &LB, DominatorTree *DT, EpilogueVectorizationKind EpilogueVecKind = - EpilogueVectorizationKind::None); + EpilogueVectorizationKind::None, + MutableArrayRef TrackedBlocks = {}); #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) void printPlans(raw_ostream &O); diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 49d5c5631e8a8e..67dcdf8a035ca1 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -5473,7 +5473,8 @@ void LoopVectorizationPlanner::clearCostModel() { CM.reset(); } DenseMap LoopVectorizationPlanner::executePlan( ElementCount BestVF, unsigned BestUF, VPlan &BestVPlan, InnerLoopVectorizer &ILV, DominatorTree *DT, - EpilogueVectorizationKind EpilogueVecKind) { + EpilogueVectorizationKind EpilogueVecKind, + MutableArrayRef TrackedBlocks) { assert(BestVPlan.hasVF(BestVF) && "Trying to execute plan with unsupported VF"); assert(BestVPlan.hasUF(BestUF) && @@ -5678,8 +5679,11 @@ DenseMap LoopVectorizationPlanner::executePlan( if (EpilogueVecKind == EpilogueVectorizationKind::MainLoop) for (VPBasicBlock *VPBB : to_vector(VPBlockUtils::blocksAs( vp_depth_first_shallow(BestVPlan.getEntry())))) - if (!isa(VPBB)) - replaceVPBBWithIRVPBB(VPBB, State.CFG.VPBB2IRBB.at(VPBB), &BestVPlan); + if (!isa(VPBB)) { + VPBasicBlock *IRVPBB = replaceVPBBWithIRVPBB( + VPBB, State.CFG.VPBB2IRBB.at(VPBB), &BestVPlan); + replace(TrackedBlocks, VPBB, IRVPBB); + } return ExpandedSCEVs; } @@ -7051,7 +7055,8 @@ static void preparePlanForEpilogueVectorLoop( VPlan &MainPlan, VPlan &Plan, Loop *L, const SCEV2ValueTy &ExpandedSCEVs, ElementCount MainLoopVF, unsigned MainLoopUF, ElementCount EpilogueVF, LoopVectorizationPlanner &LVP, VFSelectionContext &Config, - ScalarEvolution &SE, const MainPlanResumeMarkers &Markers) { + ScalarEvolution &SE, const MainPlanResumeMarkers &Markers, + VPBasicBlock *MainCheck) { // Build a map from the scalar-header PHI to the ResumeForEpilogue markers // from the main plan. // TODO: Replace the IR PHI key. @@ -7060,7 +7065,7 @@ static void preparePlanForEpilogueVectorLoop( zip_equal(MainPlan.getScalarHeader()->phis(), Markers.ResumeValues)) IRPhiToResumeForEpi[&cast(HeaderPhi).getIRPhi()] = ResumeForEpi; VPIRBasicBlock *EpilogueCheck = RUN_VPLAN_PASS( - VPlanTransforms::modelGeneratedMainLoopBlocks, Plan, MainPlan); + VPlanTransforms::modelGeneratedMainLoopBlocks, Plan, MainPlan, MainCheck); VPRegionBlock *VectorLoop = Plan.getVectorLoopRegion(); VPBasicBlock *Header = VectorLoop->getEntryBasicBlock(); Header->setName("vec.epilog.vector.body"); @@ -7753,9 +7758,14 @@ bool LoopVectorizePass::processLoop(Loop *L) { << ", Epilogue Loop VF:" << EpilogueVF << ", Epilogue Loop UF:1\n"; }); InnerLoopVectorizer MainILV(L, PSE, LI, DT, TTI, AC, VF.Width, IC, Checks); + // Keep track of the iteration count check of the main vector loop. + VPBasicBlock *MainBlocks[] = {cast( + BestMainPlan.getVectorPreheader()->getSinglePredecessor())}; auto ExpandedSCEVs = LVP.executePlan( VF.Width, IC, BestMainPlan, MainILV, DT, - LoopVectorizationPlanner::EpilogueVectorizationKind::MainLoop); + LoopVectorizationPlanner::EpilogueVectorizationKind::MainLoop, + MainBlocks); + VPBasicBlock *MainCheck = MainBlocks[0]; ++LoopsVectorized; DEBUG_WITH_TYPE(VerboseDebug, { dbgs() << "intermediate fn:\n" << *L->getHeader()->getParent() << "\n"; @@ -7772,9 +7782,9 @@ bool LoopVectorizePass::processLoop(Loop *L) { // edges from the first pass. InnerLoopVectorizer EpilogILV(L, PSE, LI, DT, TTI, AC, EpilogueVF, /*UnrollFactor=*/1, Checks); - preparePlanForEpilogueVectorLoop(BestMainPlan, BestEpiPlan, L, - ExpandedSCEVs, VF.Width, IC, EpilogueVF, - LVP, Config, *PSE.getSE(), Markers); + preparePlanForEpilogueVectorLoop( + BestMainPlan, BestEpiPlan, L, ExpandedSCEVs, VF.Width, IC, EpilogueVF, + LVP, Config, *PSE.getSE(), Markers, MainCheck); RUN_VPLAN_PASS(VPlanTransforms::simplifyLiveInsWithSCEV, BestEpiPlan, PSE); LLVM_DEBUG({ dbgs() << "Create Skeleton for epilogue vectorized loop (second pass)\n" diff --git a/llvm/lib/Transforms/Vectorize/VPlan.cpp b/llvm/lib/Transforms/Vectorize/VPlan.cpp index 4268b3b1cb1b23..f666c0bff8769f 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlan.cpp @@ -1030,24 +1030,19 @@ InstructionCost VPlan::cost(ElementCount VF, VPCostContext &Ctx) { VPRegionBlock *VPlan::getVectorLoopRegion() { // Find the vector loop region by following the last successor of each block, // starting from the plan's entry; the vector code path is always the last - // successor, except for the block bypassing the main vector loop when - // vectorizing the epilogue, which has the vector preheader as first - // successor. Every block on the path has a single predecessor, except the - // vector preheader, which is also entered from the block bypassing the main - // vector loop when vectorizing the epilogue. Stop at any other block with - // multiple predecessors: in a plain CFG that is the loop header (no region - // exists yet), in a region based CFG the scalar preheader. + // successor. When vectorizing the epilogue, the path leads through the blocks + // generated for the main vector loop. Each block on the path is entered from + // its first predecessor. Stop at a block entered from another predecessor, + // e.g. a loop header entered via its back-edge in a plain CFG, before regions + // are created or after they have been dissolved. for (VPBlockBase *B = Entry; B;) { if (auto *R = dyn_cast(B)) return R->isReplicator() || R->getNumPredecessors() != 1 ? nullptr : R; - VPBlockBase *Succ = - B->hasSuccessors() ? B->getSuccessors().back() : nullptr; - if (B->getNumPredecessors() > 1 && !isa_and_present(Succ)) + if (!B->hasSuccessors()) + return nullptr; + VPBlockBase *Succ = B->getSuccessors().back(); + if (Succ->getPredecessors().front() != B) return nullptr; - if (B->getNumSuccessors() == 2 && - isa_and_present( - B->getSuccessors().front()->getSingleSuccessor())) - Succ = B->getSuccessors().front(); B = Succ; } return nullptr; diff --git a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp index 8f67d6d580b673..2bb96418700c15 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanConstruction.cpp @@ -1484,8 +1484,9 @@ static void insertCheckBlockBeforeVectorLoop(VPlan &Plan, addIncomingForLastPredecessor(ScalarPH); } -VPIRBasicBlock *VPlanTransforms::modelGeneratedMainLoopBlocks(VPlan &EpiPlan, - VPlan &MainPlan) { +VPIRBasicBlock * +VPlanTransforms::modelGeneratedMainLoopBlocks(VPlan &EpiPlan, VPlan &MainPlan, + VPBasicBlock *MainCheck) { VPBasicBlock *VectorPH = EpiPlan.getVectorPreheader(); assert(VectorPH && VectorPH->phis().empty() && "vector preheader must exist and have no phis to update"); @@ -1514,37 +1515,34 @@ VPIRBasicBlock *VPlanTransforms::modelGeneratedMainLoopBlocks(VPlan &EpiPlan, // First, connect the edges from the bypass blocks (minimum iteration checks, // runtime checks) to the scalar preheader, in reverse order, to preserve the - // predecessor order of the generated IR. + // predecessor order of the generated IR. The middle block is the first + // predecessor. MainCheck only bypasses the main vector loop; connect it to + // the epilogue vector preheader instead. VPBasicBlock *EpiScalarPH = EpiPlan.getScalarPreheader(); for (VPBlockBase *MainVPBB : - reverse(drop_end(drop_begin(MainScalarPH->predecessors())))) { - VPBlockUtils::connectBlocks(MainToEpiVPBB.lookup(MainVPBB), EpiScalarPH); + reverse(drop_begin(MainScalarPH->predecessors()))) { + VPBlockBase *EpiVPBB = MainToEpiVPBB.lookup(MainVPBB); + if (MainVPBB == MainCheck) { + VPBlockUtils::connectBlocks(EpiVPBB, VectorPH); + continue; + } + VPBlockUtils::connectBlocks(EpiVPBB, EpiScalarPH); addIncomingForLastPredecessor(EpiScalarPH); } - // The main loop's minimum iteration check is the last predecessor of - // MainScalarPH and only bypasses the main vector loop; connect it to the - // epilogue vector preheader. - VPBlockBase *MainCheck = MainScalarPH->getPredecessors().back(); - assert(match(cast(MainCheck)->getTerminator(), - m_BranchOnCond(m_CombineOr( - m_ICmp(m_Specific(MainPlan.getTripCount()), m_VPValue()), - m_True(), m_False()))) && - "expected the main loop's minimum iteration check"); - assert(MainCheck->getNumSuccessors() == 2 && - MainCheck->getSuccessors()[0] == MainScalarPH && - !is_contained(MainScalarPH->getPredecessors(), - MainCheck->getSuccessors()[1]) && - "the iteration count check must bypass the main vector loop"); - VPBlockUtils::connectBlocks(MainToEpiVPBB.lookup(MainCheck), VectorPH); - // Mirror MainPlan's CFG, skipping the bypass edges connected above, which - // come first, and edges to blocks not modeled in EpiPlan. - for (auto &[MainVPBB, EpiVPBB] : drop_end(MainToEpiVPBB)) + // come first, edges to blocks not modeled in EpiPlan and the main vector + // loop's back-edge (to a block earlier in RPO), so EpiPlan contains no loop + // it does not own. + SmallPtrSet Visited; + for (auto &[MainVPBB, EpiVPBB] : drop_end(MainToEpiVPBB)) { + Visited.insert(MainVPBB); for (VPBlockBase *Succ : drop_begin(MainVPBB->getSuccessors(), EpiVPBB->getNumSuccessors())) - if (auto *SuccVPBB = MainToEpiVPBB.lookup(Succ)) + if (auto *SuccVPBB = MainToEpiVPBB.lookup(Succ); + SuccVPBB && !Visited.contains(Succ)) VPBlockUtils::connectBlocks(EpiVPBB, SuccVPBB); + } return EpilogueCheck; } diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.h b/llvm/lib/Transforms/Vectorize/VPlanTransforms.h index 11d06b22326da2..3c793df2bf5324 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.h +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.h @@ -226,11 +226,13 @@ struct VPlanTransforms { /// Model the blocks the executed \p MainPlan generated for the main vector /// loop in \p EpiPlan during epilogue vectorization, wrapping each in a /// VPIRBasicBlock. Bypass edges are redirected to \p EpiPlan's scalar - /// preheader, or its vector preheader if only bypassing the main vector loop. - /// Returns the block wrapping \p MainPlan's scalar preheader, which becomes - /// the epilogue iteration check. + /// preheader, or its vector preheader for \p MainCheck, which only bypasses + /// the main vector loop. The main vector loop's back-edge is not modeled. + /// Returns the block wrapping \p MainPlan's scalar + /// preheader, which becomes the epilogue iteration check. static VPIRBasicBlock *modelGeneratedMainLoopBlocks(VPlan &EpiPlan, - VPlan &MainPlan); + VPlan &MainPlan, + VPBasicBlock *MainCheck); /// Replaces the VPInstructions in \p Plan with corresponding /// widen recipes. Returns false if any VPInstructions could not be converted diff --git a/llvm/test/Transforms/LoopVectorize/VPlan/epilogue-vectorization-printing.ll b/llvm/test/Transforms/LoopVectorize/VPlan/epilogue-vectorization-printing.ll index 055c55c86da2b4..f763635e36543f 100644 --- a/llvm/test/Transforms/LoopVectorize/VPlan/epilogue-vectorization-printing.ll +++ b/llvm/test/Transforms/LoopVectorize/VPlan/epilogue-vectorization-printing.ll @@ -78,7 +78,7 @@ define i64 @resume_values(ptr noalias %A, i64 %n) { ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): ir-bb, ir-bb +; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: ; CHECK-NEXT: Successor(s): ir-bb @@ -255,7 +255,7 @@ define i64 @bypass_blocks(ptr %A, ptr %B, i32 %n) { ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): ir-bb, ir-bb +; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: ; CHECK-NEXT: Successor(s): ir-bb @@ -421,7 +421,7 @@ define void @all_iterations_in_main_loop_with_memcheck(ptr %dst, ptr %src) { ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): ir-bb, ir-bb +; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: ; CHECK-NEXT: Successor(s): ir-bb @@ -568,7 +568,7 @@ define void @all_iterations_in_main_loop_with_scevcheck(ptr %p, i32 %off) { ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): ir-bb, ir-bb +; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: ; CHECK-NEXT: Successor(s): ir-bb @@ -835,7 +835,7 @@ define i32 @nested_loop(ptr noalias %p, ptr noalias %end, ptr noalias %dst, i64 ; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: -; CHECK-NEXT: Successor(s): ir-bb, ir-bb +; CHECK-NEXT: Successor(s): ir-bb ; CHECK-EMPTY: ; CHECK-NEXT: ir-bb: ; CHECK-NEXT: Successor(s): ir-bb From 78a9c8d0d021c2e64826098488be92b983da6001 Mon Sep 17 00:00:00 2001 From: Sivapriya Date: Sun, 25 Oct 2026 02:49:31 +0530 Subject: [PATCH 27/31] [CIR][CUDA] Add host-side surface registration support (#225146) Related: #179278. This patch adds host-side registration support for CUDA built-in surface references in CIR. Previously, CIR recognized CUDA surface variables during registration, but host-side surface handling was not implemented. This change preserves the surface type information in CIR registration metadata and emits the corresponding `__cudaRegisterSurface` runtime registration call. ## Changes - Internalize CUDA surface and texture host shadow variables to match original CodeGen behavior - Extend `CUDAVarRegistrationInfoAttr` with the CUDA surface type - Extract the surface type from the CUDA surface template arguments during CIRGen - Add `__cudaRegisterSurface` runtime declaration and call generation in `LoweringPrepare` - Keep texture runtime registration explicitly NYI - Add host-side CIR and LLVM test coverage for surface registration - Check generated LLVM registration against original CodeGen behavior ## Testing - `git diff --check` - `clang/test/CIR/CodeGenCUDA/surface.cu` - `ninja -C build -j1 clang` --- .../clang/CIR/Dialect/IR/CIRCUDAAttrs.td | 3 +- clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp | 34 +++++--- clang/lib/CIR/Dialect/IR/CIRAttrs.cpp | 10 ++- .../Dialect/Transforms/LoweringPrepare.cpp | 84 ++++++++++++------- clang/test/CIR/CodeGenCUDA/surface.cu | 45 ++++++++++ 5 files changed, 133 insertions(+), 43 deletions(-) diff --git a/clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td b/clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td index ebe8eaf60cc432..8d6cb1bdbdd86d 100644 --- a/clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td +++ b/clang/include/clang/CIR/Dialect/IR/CIRCUDAAttrs.td @@ -71,7 +71,8 @@ def CIR_CUDAVarRegistrationInfoAttr : CIR_Attr<"CUDAVarRegistrationInfo", "cu.va // handleVarRegistration via hasAttr(). "bool":$isExtern, "bool":$isConstant, - "bool":$isManaged + "bool":$isManaged, + "int32_t":$surfTexType ); let hasCustomAssemblyFormat = 1; diff --git a/clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp b/clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp index 680486411a479f..03dfdfba65c7a4 100644 --- a/clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp +++ b/clang/lib/CIR/CodeGen/CIRGenCUDANV.cpp @@ -100,7 +100,8 @@ class CIRGenNVCUDARuntime : public CIRGenCUDARuntime { builder.getContext(), getDeviceSideName(cast(vd)), cir::CUDADeviceVarKind::Variable, isExtern, isConstant, - vd->hasAttr())); + vd->hasAttr(), + /*surfTexType=*/0)); deviceVars.push_back({ var, vd, @@ -108,8 +109,8 @@ class CIRGenNVCUDARuntime : public CIRGenCUDARuntime { }); } - void registerDeviceSurf(const VarDecl *vd, cir::GlobalOp &var, - bool isExtern) { + void registerDeviceSurf(const VarDecl *vd, cir::GlobalOp &var, bool isExtern, + int32_t surfaceType) { auto &builder = cgm.getBuilder(); var->setAttr(cir::CUDAVarRegistrationInfoAttr::getMnemonic(), @@ -118,7 +119,7 @@ class CIRGenNVCUDARuntime : public CIRGenCUDARuntime { getDeviceSideName(cast(vd)), cir::CUDADeviceVarKind::Surface, isExtern, /*isConstant=*/false, - /*isManaged=*/false)); + /*isManaged=*/false, surfaceType)); deviceVars.push_back({ var, @@ -136,7 +137,8 @@ class CIRGenNVCUDARuntime : public CIRGenCUDARuntime { getDeviceSideName(cast(vd)), cir::CUDADeviceVarKind::Texture, isExtern, /*isConstant=*/false, - /*isManaged=*/false)); + /*isManaged=*/false, + /*surfTexType=*/0)); deviceVars.push_back({ var, @@ -450,14 +452,15 @@ void CIRGenNVCUDARuntime::internalizeDeviceSideVar( // counterparts. It's not clear yet whether it's nvcc's bug or // a feature, but we've got to do the same for compatibility. if (d->hasAttr() || d->hasAttr() || - d->hasAttr()) { + d->hasAttr() || + d->getType()->isCUDADeviceBuiltinSurfaceType() || + d->getType()->isCUDADeviceBuiltinTextureType()) { linkage = cir::GlobalLinkageKind::InternalLinkage; } - if (d->getType()->isCUDADeviceBuiltinSurfaceType() || - d->getType()->isCUDADeviceBuiltinTextureType()) + if (d->getType()->isCUDADeviceBuiltinTextureType()) cgm.errorNYI(d->getSourceRange(), - "internalizeDeviceSideVar: CUDA Surface/Texture support"); + "internalizeDeviceSideVar: CUDA Texture support"); } std::string CIRGenNVCUDARuntime::getDeviceSideName(const NamedDecl *nd) { @@ -518,8 +521,19 @@ void CIRGenNVCUDARuntime::handleVarRegistration(const VarDecl *vd, } else if (vd->getType()->isCUDADeviceBuiltinSurfaceType()) { // Builtin surfaces and their template arguments are also registered // with CUDA runtime. + const auto *td = cast( + vd->getType()->castAsCXXRecordDecl()); + const TemplateArgumentList &args = td->getTemplateArgs(); + + assert(args.size() == 2 && + "Unexpected number of template arguments of CUDA device " + "builtin surface type."); + + llvm::APSInt surfaceType = args[1].getAsIntegral(); + if (!vd->hasExternalStorage()) - registerDeviceSurf(vd, var, !vd->hasDefinition()); + registerDeviceSurf(vd, var, !vd->hasDefinition(), + surfaceType.getSExtValue()); } else if (vd->getType()->isCUDADeviceBuiltinTextureType()) { // Builtin textures and their template arguments are also registered diff --git a/clang/lib/CIR/Dialect/IR/CIRAttrs.cpp b/clang/lib/CIR/Dialect/IR/CIRAttrs.cpp index 023ac73178152a..0c92e222fe2c5b 100644 --- a/clang/lib/CIR/Dialect/IR/CIRAttrs.cpp +++ b/clang/lib/CIR/Dialect/IR/CIRAttrs.cpp @@ -616,6 +616,8 @@ void CUDAVarRegistrationInfoAttr::print(AsmPrinter &p) const { p << ", constant"; if (getIsManaged()) p << ", managed"; + if (getKind() == CUDADeviceVarKind::Surface) + p << ", surface_type = " << getSurfTexType(); p << ">"; } @@ -650,6 +652,7 @@ Attribute CUDAVarRegistrationInfoAttr::parse(AsmParser &parser, Type odsType) { bool isExtern = false; bool isConstant = false; bool isManaged = false; + int32_t surfTexType = 0; while (parser.parseOptionalGreater().failed()) { if (parser.parseComma()) @@ -665,14 +668,17 @@ Attribute CUDAVarRegistrationInfoAttr::parse(AsmParser &parser, Type odsType) { isConstant = true; else if (flag == "managed") isManaged = true; - else { + else if (flag == "surface_type") { + if (parser.parseEqual() || parser.parseInteger(surfTexType)) + return {}; + } else { parser.emitError(parser.getCurrentLocation(), "unknown flag: ") << flag; return {}; } } return get(parser.getContext(), deviceSideName, *kind, isExtern, isConstant, - isManaged); + isManaged, surfTexType); } //===----------------------------------------------------------------------===// diff --git a/clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp b/clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp index 10f36c5ec8f0e2..0af8f16f190f4e 100644 --- a/clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp +++ b/clang/lib/CIR/Dialect/Transforms/LoweringPrepare.cpp @@ -3345,6 +3345,17 @@ void LoweringPreparePass::buildCUDARegisterVars(cir::CIRBaseBuilderTy &builder, FuncOp cudaRegisterVar; FuncOp cudaRegisterManagedVar; + // void __cudaRegisterSurface(void **fatbinHandle, + // const struct surfaceReference *hostVar, + // const void **deviceAddress, + // const char *deviceName, + // int type, int ext); + FuncOp cudaRegisterSurface = buildRuntimeFunction( + globalBuilder, addUnderscoredPrefix(cudaPrefix, "RegisterSurface"), loc, + FuncType::get( + {voidPtrPtrTy, voidPtrTy, voidPtrTy, voidPtrTy, intTy, intTy}, + voidTy)); + auto makeConstantString = [&](llvm::StringRef str) -> GlobalOp { auto strType = ArrayType::get(&getContext(), charTy, 1 + str.size()); auto tmpString = cir::GlobalOp::create( @@ -3360,15 +3371,6 @@ void LoweringPreparePass::buildCUDARegisterVars(cir::CIRBaseBuilderTy &builder, mlir::Value fatbinHandle = *regGlobalFunc.args_begin(); for (auto &[global, regAttr] : cudaDeviceVars) { - switch (regAttr.getKind()) { - case cir::CUDADeviceVarKind::Variable: - break; - case cir::CUDADeviceVarKind::Surface: - llvm_unreachable("Surface registration NYI"); - case cir::CUDADeviceVarKind::Texture: - llvm_unreachable("Texture registration NYI"); - } - // External managed variables are registered by their defining TU. if (regAttr.getIsManaged() && global.isDeclaration()) continue; @@ -3392,6 +3394,7 @@ void LoweringPreparePass::buildCUDARegisterVars(cir::CIRBaseBuilderTy &builder, FuncType::get( {voidPtrPtrTy, voidPtrTy, voidPtrTy, voidPtrTy, sizeTy, intTy}, voidTy)); + llvm::StringRef name = global.getSymName(); assert(name.ends_with(".managed") && "HIP managed variables not transformed"); @@ -3407,29 +3410,50 @@ void LoweringPreparePass::buildCUDARegisterVars(cir::CIRBaseBuilderTy &builder, loc, cudaRegisterManagedVar, {fatbinHandle, managedPtr, hostVar, deviceName, varSize, align}); } else { - // void __{cuda|hip}RegisterVar(void **fatbinHandle, - // char *hostVar, char *deviceAddress, - // const char *deviceName, int ext, - // size_t size, int constant, - // int normalized); - // OG ignores parameter types, treating pointers as void*. - if (!cudaRegisterVar) - cudaRegisterVar = buildRuntimeFunction( - globalBuilder, addUnderscoredPrefix(cudaPrefix, "RegisterVar"), loc, - FuncType::get({voidPtrPtrTy, voidPtrTy, voidPtrTy, voidPtrTy, intTy, - sizeTy, intTy, intTy}, - voidTy)); auto isExtern = ConstantOp::create( builder, loc, IntAttr::get(intTy, regAttr.getIsExtern() ? 1 : 0)); - auto varSize = ConstantOp::create( - builder, loc, IntAttr::get(sizeTy, size.getFixedValue())); - auto isConstant = ConstantOp::create( - builder, loc, IntAttr::get(intTy, regAttr.getIsConstant() ? 1 : 0)); - auto normalized = - ConstantOp::create(builder, loc, IntAttr::get(intTy, 0)); - builder.createCallOp(loc, cudaRegisterVar, - {fatbinHandle, hostVar, deviceName, deviceName, - isExtern, varSize, isConstant, normalized}); + + switch (regAttr.getKind()) { + case cir::CUDADeviceVarKind::Variable: { + // void __{cuda|hip}RegisterVar(void **fatbinHandle, + // char *hostVar, char *deviceAddress, + // const char *deviceName, int ext, + // size_t size, int constant, + // int normalized); + // OG ignores parameter types, treating pointers as void*. + if (!cudaRegisterVar) + cudaRegisterVar = buildRuntimeFunction( + globalBuilder, addUnderscoredPrefix(cudaPrefix, "RegisterVar"), + loc, + FuncType::get({voidPtrPtrTy, voidPtrTy, voidPtrTy, voidPtrTy, + intTy, sizeTy, intTy, intTy}, + voidTy)); + + auto varSize = ConstantOp::create( + builder, loc, IntAttr::get(sizeTy, size.getFixedValue())); + auto isConstant = ConstantOp::create( + builder, loc, IntAttr::get(intTy, regAttr.getIsConstant() ? 1 : 0)); + auto normalized = + ConstantOp::create(builder, loc, IntAttr::get(intTy, 0)); + + builder.createCallOp(loc, cudaRegisterVar, + {fatbinHandle, hostVar, deviceName, deviceName, + isExtern, varSize, isConstant, normalized}); + break; + } + + case cir::CUDADeviceVarKind::Surface: { + cir::ConstantOp surfaceType = ConstantOp::create( + builder, loc, IntAttr::get(intTy, regAttr.getSurfTexType())); + builder.createCallOp(loc, cudaRegisterSurface, + {fatbinHandle, hostVar, deviceName, deviceName, + surfaceType, isExtern}); + break; + } + + case cir::CUDADeviceVarKind::Texture: + llvm_unreachable("Texture registration NYI"); + } } } } diff --git a/clang/test/CIR/CodeGenCUDA/surface.cu b/clang/test/CIR/CodeGenCUDA/surface.cu index 67d7257c07c6e5..b4bb5ea0f623ee 100644 --- a/clang/test/CIR/CodeGenCUDA/surface.cu +++ b/clang/test/CIR/CodeGenCUDA/surface.cu @@ -1,9 +1,21 @@ // REQUIRES: x86-registered-target // REQUIRES: nvptx-registered-target + // RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-cir -o - %s | FileCheck --check-prefix=CIR-DEVICE %s // RUN: %clang_cc1 -fclangir -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=LLVM-DEVICE %s // RUN: %clang_cc1 -std=c++11 -fcuda-is-device -triple nvptx64-nvidia-cuda -emit-llvm -o - %s | FileCheck --check-prefix=OGCG-DEVICE %s +// RUN: echo -n "GPU binary would be here." > %t +// RUN: %clang_cc1 -fclangir -std=c++11 -triple x86_64-unknown-linux-gnu \ +// RUN: -target-sdk-version=12.3 -fcuda-include-gpubinary %t \ +// RUN: -emit-cir -o - %s | FileCheck --check-prefix=CIR-HOST %s +// RUN: %clang_cc1 -fclangir -std=c++11 -triple x86_64-unknown-linux-gnu \ +// RUN: -target-sdk-version=12.3 -fcuda-include-gpubinary %t \ +// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=LLVM-HOST %s +// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-linux-gnu \ +// RUN: -target-sdk-version=12.3 -fcuda-include-gpubinary %t \ +// RUN: -emit-llvm -o - %s | FileCheck --check-prefix=LLVM-HOST %s + struct surfaceReference { int desc; }; @@ -18,8 +30,41 @@ struct __attribute__((device_builtin_surface_type)) surface surface surf; +//===----------------------------------------------------------------------===// +// Device-side checks +//===----------------------------------------------------------------------===// + // CIR-DEVICE: cir.global external target_address_space(1) @surf = #cir.undef : !cir.cuda_surface // CIR now matches OG CodeGen and emits undef for CUDA shadow variables. // LLVM-DEVICE: @surf ={{.*}} addrspace(1) externally_initialized global i64 undef // OGCG-DEVICE: @surf ={{.*}} addrspace(1) externally_initialized global i64 undef + +//===----------------------------------------------------------------------===// +// Host-side checks +//===----------------------------------------------------------------------===// + +// Check the CUDA surface registration runtime declaration. +// CIR-HOST: cir.func private @__cudaRegisterSurface(!cir.ptr>, !cir.ptr, !cir.ptr, !cir.ptr, !s32i, !s32i) + +// Check that __cuda_register_globals registers the surface using the host +// shadow, device-side name, surface type, and extern flag. +// CIR-HOST-LABEL: cir.func internal private @__cuda_register_globals +// CIR-HOST-SAME: (%[[FATBIN:.*]]: !cir.ptr> +// CIR-HOST: %[[NAME_RAW:.*]] = cir.get_global @".strsurf" +// CIR-HOST-NEXT: %[[NAME:.*]] = cir.cast bitcast %[[NAME_RAW]] +// CIR-HOST-NEXT: %[[HOST_RAW:.*]] = cir.get_global @surf +// CIR-HOST-NEXT: %[[HOST:.*]] = cir.cast bitcast %[[HOST_RAW]] +// CIR-HOST-NEXT: %[[EXTERN:.*]] = cir.const #cir.int<0> : !s32i +// CIR-HOST-NEXT: %[[SURFACE_TYPE:.*]] = cir.const #cir.int<2> : !s32i +// CIR-HOST-NEXT: cir.call @__cudaRegisterSurface(%[[FATBIN]], %[[HOST]], %[[NAME]], %[[NAME]], %[[SURFACE_TYPE]], %[[EXTERN]]) + +// Check that the host-side shadow is internalized and carries the surface +// registration metadata, including the surface type from surface. +// CIR-HOST: cir.global "private" internal dso_local @surf = {{.*}}cu.var_registration = #cir.cu.var_registration +// LLVM-HOST: @surf = internal global %{{.*}} zeroinitializer + +// Check both CIR-lowered LLVM and original CodeGen registration. +// LLVM-HOST-LABEL: define internal void @__cuda_register_globals +// LLVM-HOST-SAME: (ptr %[[FATBIN:.*]]) +// LLVM-HOST: call void @__cudaRegisterSurface(ptr %[[FATBIN]], ptr @surf, ptr @[[NAME:.*]], ptr @[[NAME]], i32 2, i32 0) \ No newline at end of file From a48ab421cf081d4f44f5660e11f00af3472c5b67 Mon Sep 17 00:00:00 2001 From: Michael Kruse Date: Sat, 24 Oct 2026 23:19:37 +0200 Subject: [PATCH 28/31] [Flang][test] Use x86 triple (#235354) `REAL(10)` is only available on x86 targets. x86-registered-target enabled in #235068 is insufficient, it also needs to be compiled to the x86 target triple. Apply the same -triple as other tests such as flang/test/Semantics/real10-x86-01.f90 do. Note: Some constant foldings are only available if the flang compiler itself runs under x86, but folding is not what is tested here. Should fix the [clang-aarch64-sve-vls-2stage](https://lab.llvm.org/buildbot/#/builders/4) buildbot --- flang/test/Semantics/kinds01.f90 | 2 +- flang/test/Semantics/kinds02.f90 | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/flang/test/Semantics/kinds01.f90 b/flang/test/Semantics/kinds01.f90 index 7659b042b181a3..876b0abfe096ff 100644 --- a/flang/test/Semantics/kinds01.f90 +++ b/flang/test/Semantics/kinds01.f90 @@ -1,5 +1,5 @@ ! REQUIRES: x86-registered-target, flang-supports-f128-math -! RUN: %python %S/test_symbols.py %s %flang_fc1 +! RUN: %python %S/test_symbols.py %s %flang_fc1 -triple x86_64-unknown-linux-gnu !DEF: /MainProgram1/jk1 ObjectEntity INTEGER(1) integer(kind=1) jk1 !DEF: /MainProgram1/js1 ObjectEntity INTEGER(1) diff --git a/flang/test/Semantics/kinds02.f90 b/flang/test/Semantics/kinds02.f90 index 5ed38b14f8acb3..ae423c5de2f4f3 100644 --- a/flang/test/Semantics/kinds02.f90 +++ b/flang/test/Semantics/kinds02.f90 @@ -1,5 +1,5 @@ ! REQUIRES: x86-registered-target -! RUN: %python %S/test_errors.py %s %flang_fc1 +! RUN: %python %S/test_errors.py %s %flang_fc1 -triple x86_64-unknown-linux-gnu ! C712 The value of scalar-int-constant-expr shall be nonnegative and ! shall specify a representation method that exists on the processor. ! C714 The value of kind-param shall be nonnegative. From b1db34427810b2d14af8293a8c5493119c5ccb45 Mon Sep 17 00:00:00 2001 From: Ikhlas Ajbar Date: Sat, 24 Oct 2026 16:39:09 -0500 Subject: [PATCH 29/31] [WindowScheduler] Preserve loop-carried memory dependences (#231364) The WindowScheduler clones the loop body into TripleMBB and advances the base registers of memory accesses to later iterations, but the clones keep the original iteration's memory operands. The per-window scheduler could therefore treat a store and a load from different copies as non-aliasing and reorder them, even though they touch the same address in consecutive iterations, producing wrong code. Detect loop-carried memory dependences on the original loop and enforce them with a DAG mutation while list scheduling each window. Fixes #209946 --- llvm/include/llvm/CodeGen/MachinePipeliner.h | 13 +- llvm/include/llvm/CodeGen/WindowScheduler.h | 28 +- llvm/lib/CodeGen/MachinePipeliner.cpp | 69 ++-- llvm/lib/CodeGen/WindowScheduler.cpp | 198 ++++++++++- .../Hexagon/swp-ws-loop-carried-dep.mir | 325 ++++++++++++++++++ 5 files changed, 588 insertions(+), 45 deletions(-) create mode 100644 llvm/test/CodeGen/Hexagon/swp-ws-loop-carried-dep.mir diff --git a/llvm/include/llvm/CodeGen/MachinePipeliner.h b/llvm/include/llvm/CodeGen/MachinePipeliner.h index 9b8beef1a1677b..bd9c52d6ed5e24 100644 --- a/llvm/include/llvm/CodeGen/MachinePipeliner.h +++ b/llvm/include/llvm/CodeGen/MachinePipeliner.h @@ -62,6 +62,15 @@ class LiveIntervals; class NodeSet; class SMSchedule; +/// Return true if BaseMI and OtherMI may access overlapping memory in a later +/// iteration of the loop LoopBB. Returns true conservatively whenever overlap +/// cannot be ruled out. +LLVM_ABI bool mayOverlapInLaterIter(const MachineInstr *BaseMI, + const MachineInstr *OtherMI, + const MachineBasicBlock *LoopBB, + const MachineRegisterInfo &MRI, + const TargetInstrInfo &TII); + /// Software pipelining policy for a loop, which a target can customize by /// implementing TargetSubtargetInfo::overridePipelinerPolicy. struct MachinePipelinerPolicy { @@ -424,9 +433,6 @@ class LLVM_ABI SwingSchedulerDAG : public ScheduleDAGInstrs { const SwingSchedulerDDG *getDDG() const { return DDG.get(); } - bool mayOverlapInLaterIter(const MachineInstr *BaseMI, - const MachineInstr *OtherMI) const; - private: /// Set the policy for this loop, allowing the target to override it. void initPolicy(); @@ -448,7 +454,6 @@ class LLVM_ABI SwingSchedulerDAG : public ScheduleDAGInstrs { void computeNodeOrder(NodeSetType &NodeSets); void checkValidNodeOrder(const NodeSetType &Circuits) const; bool schedulePipeline(SMSchedule &Schedule); - bool computeDelta(const MachineInstr &MI, int &Delta) const; MachineInstr *findDefInLoop(Register Reg); bool canUseLastOffsetValue(MachineInstr *MI, unsigned &BasePos, unsigned &OffsetPos, Register &NewBase, diff --git a/llvm/include/llvm/CodeGen/WindowScheduler.h b/llvm/include/llvm/CodeGen/WindowScheduler.h index 12b3474dfa784a..2a89b8aa0ccb8a 100644 --- a/llvm/include/llvm/CodeGen/WindowScheduler.h +++ b/llvm/include/llvm/CodeGen/WindowScheduler.h @@ -42,6 +42,7 @@ #ifndef LLVM_CODEGEN_WINDOWSCHEDULER_H #define LLVM_CODEGEN_WINDOWSCHEDULER_H +#include "llvm/ADT/DenseSet.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/MachineScheduler.h" @@ -56,6 +57,13 @@ enum WindowSchedulingFlag { WS_Force /// Use window algorithm instead of SMS algorithm. }; +/// TriCloneInfo describes an MI clone in TripleMBB: the original MI it was +/// cloned from and the index of the copy (0, 1, or 2) it belongs to. +struct TriCloneInfo { + MachineInstr *Ori = nullptr; + unsigned Copy = 0; +}; + /// The main class in the implementation of the target independent window /// scheduler. class LLVM_ABI WindowScheduler { @@ -80,11 +88,20 @@ class LLVM_ABI WindowScheduler { SmallVector OriMIs; /// TriMIs keeps the MIs of TripleMBB, which is used to restore TripleMBB. SmallVector TriMIs; - /// TriToOri keeps the mappings between the MI clones in TripleMBB and their - /// original MI. - DenseMap TriToOri; + /// TriToOri keeps the mappings between the MI clones in TripleMBB and the + /// information about their original MI and copy index. + DenseMap TriToOri; /// OriToCycle keeps the mappings between the original MI and its issue cycle. DenseMap OriToCycle; + /// LoopCarriedMemDeps keeps ordered pairs (Pred, Succ) of original memory MIs + /// such that the iteration-N access Pred must be ordered before the + /// iteration-(N+1) access Succ. + DenseSet> LoopCarriedMemDeps; + /// MemDepEdgeFailed is set when enforcing a loop-carried memory dependence as + /// an artificial DAG edge would have created a cycle, so the edge could not + /// be added. In that case the current window must be abandoned, as its + /// schedule would not honor the dependence. + bool MemDepEdgeFailed = false; /// SchedResult keeps the result of each list scheduling, and the format of /// the tuple is . SmallVector, 256> SchedResult; @@ -118,6 +135,11 @@ class LLVM_ABI WindowScheduler { virtual bool initialize(); /// Add some related processing before running window scheduling. virtual void preProcess(); + /// Detect loop-carried memory dependences in the original MBB that must be + /// preserved across loop iterations. This must run on the live MBB before + /// backupMBB(), as it analyzes the induction recurrence of memory accesses. + /// The hazardous pairs of original MIs are recorded in LoopCarriedMemDeps. + void collectLoopCarriedMemDeps(); /// Add some related processing after running window scheduling. virtual void postProcess(); /// Back up the MIs in the original MBB and remove them from MBB. diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp index dd0dd264785511..3dea309d1ad193 100644 --- a/llvm/lib/CodeGen/MachinePipeliner.cpp +++ b/llvm/lib/CodeGen/MachinePipeliner.cpp @@ -318,12 +318,10 @@ class LoopCarriedOrderDepsTracker { std::vector TaggedSUnits; const TargetInstrInfo *TII = nullptr; - const TargetRegisterInfo *TRI = nullptr; public: LoopCarriedOrderDepsTracker(SwingSchedulerDAG *SSD, BatchAAResults *BAA, - const TargetInstrInfo *TII, - const TargetRegisterInfo *TRI); + const TargetInstrInfo *TII); /// The main function to compute loop-carried order-dependencies. void computeDependencies(); @@ -1077,7 +1075,7 @@ void SwingSchedulerDAG::finishBlock() { /// Return the register values for the operands of a Phi instruction. /// This function assume the instruction is a Phi. -static void getPhiRegs(MachineInstr &Phi, MachineBasicBlock *Loop, +static void getPhiRegs(const MachineInstr &Phi, const MachineBasicBlock *Loop, Register &InitVal, Register &LoopVal) { assert(Phi.isPHI() && "Expecting a Phi."); @@ -1171,9 +1169,7 @@ bool SUnitWithMemInfo::getUnderlyingObjects() { static bool hasLoopCarriedMemDep(const SUnitWithMemInfo &Src, const SUnitWithMemInfo &Dst, BatchAAResults &BAA, - const TargetInstrInfo *TII, - const TargetRegisterInfo *TRI, - const SwingSchedulerDAG *SSD) { + const TargetInstrInfo *TII) { if (Src.isTriviallyDisjoint(Dst)) return false; if (isSuccOrder(Src.SU, Dst.SU)) @@ -1182,7 +1178,9 @@ static bool hasLoopCarriedMemDep(const SUnitWithMemInfo &Src, MachineInstr &SrcMI = *Src.SU->getInstr(); MachineInstr &DstMI = *Dst.SU->getInstr(); - if (!SSD->mayOverlapInLaterIter(&SrcMI, &DstMI)) + const MachineBasicBlock *LoopBB = SrcMI.getParent(); + const MachineRegisterInfo &MRI = LoopBB->getParent()->getRegInfo(); + if (!mayOverlapInLaterIter(&SrcMI, &DstMI, LoopBB, MRI, *TII)) return false; // Second, the more expensive check that uses alias analysis on the @@ -1223,10 +1221,9 @@ void LoopCarriedOrderDepsTracker::NoBarrierInstsChunk::append(SUnit *SU) { } LoopCarriedOrderDepsTracker::LoopCarriedOrderDepsTracker( - SwingSchedulerDAG *SSD, BatchAAResults *BAA, const TargetInstrInfo *TII, - const TargetRegisterInfo *TRI) + SwingSchedulerDAG *SSD, BatchAAResults *BAA, const TargetInstrInfo *TII) : DAG(SSD), BAA(BAA), SUnits(DAG->SUnits), N(SUnits.size()), - LoopCarried(N, BitVector(N)), TII(TII), TRI(TRI) {} + LoopCarried(N, BitVector(N)), TII(TII) {} void LoopCarriedOrderDepsTracker::computeDependencies() { // Traverse all instructions and extract only what we are targetting. @@ -1264,7 +1261,7 @@ void LoopCarriedOrderDepsTracker::addDependenciesBetweenSUs( if (Src.SU == Dst.SU) return; - if (hasLoopCarriedMemDep(Src, Dst, *BAA, TII, TRI, DAG)) + if (hasLoopCarriedMemDep(Src, Dst, *BAA, TII)) setLoopCarriedDep(Src.SU, Dst.SU); } @@ -1373,7 +1370,7 @@ LoopCarriedEdges SwingSchedulerDAG::addLoopCarriedDependences() { LoopCarriedEdges LCE; // Add loop-carried order-dependencies - LoopCarriedOrderDepsTracker LCODTracker(this, &BAA, TII, TRI); + LoopCarriedOrderDepsTracker LCODTracker(this, &BAA, TII); LCODTracker.computeDependencies(); for (unsigned I = 0; I != SUnits.size(); I++) for (const int Succ : LCODTracker.getLoopCarried(I).set_bits()) @@ -3055,7 +3052,7 @@ static bool findLoopIncrementValue(const MachineInstr &MI, if (!CurReg.isValid() || !CurReg.isVirtual()) return false; MachineInstr *Def = MRI.getVRegDef(CurReg); - if (Def->getParent() != LoopBB) + if (!Def || Def->getParent() != LoopBB) return false; if (Def->isCopy()) { @@ -3105,11 +3102,12 @@ static bool findLoopIncrementValue(const MachineInstr &MI, /// Return true if we can compute the amount the instruction changes /// during each iteration. Set Delta to the amount of the change. -bool SwingSchedulerDAG::computeDelta(const MachineInstr &MI, int &Delta) const { +static bool computeDelta(const MachineInstr &MI, const TargetInstrInfo &TII, + int &Delta) { const MachineOperand *BaseOp; int64_t Offset; bool OffsetIsScalable; - if (!TII->getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable)) + if (!TII.getMemOperandWithOffset(MI, BaseOp, Offset, OffsetIsScalable)) return false; // FIXME: This algorithm assumes instructions have fixed-size offsets. @@ -3239,21 +3237,24 @@ MachineInstr *SwingSchedulerDAG::findDefInLoop(Register Reg) { /// Return false if there is no overlap between the region accessed by BaseMI in /// an iteration and the region accessed by OtherMI in subsequent iterations. -bool SwingSchedulerDAG::mayOverlapInLaterIter( - const MachineInstr *BaseMI, const MachineInstr *OtherMI) const { +bool llvm::mayOverlapInLaterIter(const MachineInstr *BaseMI, + const MachineInstr *OtherMI, + const MachineBasicBlock *LoopBB, + const MachineRegisterInfo &MRI, + const TargetInstrInfo &TII) { int DeltaB, DeltaO, Delta; - if (!computeDelta(*BaseMI, DeltaB) || !computeDelta(*OtherMI, DeltaO) || - DeltaB != DeltaO) + if (!computeDelta(*BaseMI, TII, DeltaB) || + !computeDelta(*OtherMI, TII, DeltaO) || DeltaB != DeltaO) return true; Delta = DeltaB; const MachineOperand *BaseOpB, *BaseOpO; int64_t OffsetB, OffsetO; bool OffsetBIsScalable, OffsetOIsScalable; - if (!TII->getMemOperandWithOffset(*BaseMI, BaseOpB, OffsetB, - OffsetBIsScalable) || - !TII->getMemOperandWithOffset(*OtherMI, BaseOpO, OffsetO, - OffsetOIsScalable)) + if (!TII.getMemOperandWithOffset(*BaseMI, BaseOpB, OffsetB, + OffsetBIsScalable) || + !TII.getMemOperandWithOffset(*OtherMI, BaseOpO, OffsetO, + OffsetOIsScalable)) return true; if (OffsetBIsScalable || OffsetOIsScalable) @@ -3269,24 +3270,24 @@ bool SwingSchedulerDAG::mayOverlapInLaterIter( if (!RegB.isVirtual() || !RegO.isVirtual()) return true; - MachineInstr *DefB = MRI.getVRegDef(BaseOpB->getReg()); - MachineInstr *DefO = MRI.getVRegDef(BaseOpO->getReg()); + MachineInstr *DefB = MRI.getVRegDef(RegB); + MachineInstr *DefO = MRI.getVRegDef(RegO); if (!DefB || !DefO || !DefB->isPHI() || !DefO->isPHI()) return true; - Register InitValB; - Register LoopValB; - Register InitValO; - Register LoopValO; - getPhiRegs(*DefB, BB, InitValB, LoopValB); - getPhiRegs(*DefO, BB, InitValO, LoopValO); + Register InitValB, LoopValB, InitValO, LoopValO; + getPhiRegs(*DefB, LoopBB, InitValB, LoopValB); + getPhiRegs(*DefO, LoopBB, InitValO, LoopValO); + if (!InitValB.isValid() || !InitValO.isValid()) + return true; MachineInstr *InitDefB = MRI.getVRegDef(InitValB); MachineInstr *InitDefO = MRI.getVRegDef(InitValO); - - if (!InitDefB->isIdenticalTo(*InitDefO)) + if (!InitDefB || !InitDefO || !InitDefB->isIdenticalTo(*InitDefO)) return true; } + if (BaseMI->memoperands_empty() || OtherMI->memoperands_empty()) + return true; LocationSize AccessSizeB = (*BaseMI->memoperands_begin())->getSize(); LocationSize AccessSizeO = (*OtherMI->memoperands_begin())->getSize(); diff --git a/llvm/lib/CodeGen/WindowScheduler.cpp b/llvm/lib/CodeGen/WindowScheduler.cpp index 3849a2c2caddf1..cb4f4dfa9295b4 100644 --- a/llvm/lib/CodeGen/WindowScheduler.cpp +++ b/llvm/lib/CodeGen/WindowScheduler.cpp @@ -37,10 +37,14 @@ //===----------------------------------------------------------------------===// #include "llvm/CodeGen/WindowScheduler.h" #include "llvm/ADT/Statistic.h" +#include "llvm/Analysis/AliasAnalysis.h" +#include "llvm/Analysis/MemoryLocation.h" +#include "llvm/Analysis/ValueTracking.h" #include "llvm/CodeGen/LiveIntervals.h" #include "llvm/CodeGen/MachineLoopInfo.h" #include "llvm/CodeGen/MachinePipeliner.h" #include "llvm/CodeGen/ModuloSchedule.h" +#include "llvm/CodeGen/ScheduleDAGMutation.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" @@ -101,6 +105,136 @@ static cl::opt cl::desc("The upper limit of II in the window algorithm."), cl::Hidden, cl::init(1000)); +/// Collect the underlying objects and alias metadata for the single memory +/// operand of MI. Returns false when MI does not have exactly one memory +/// operand with a known IR value. +static bool getMemInfo(const MachineInstr *MI, const Value *&MemOpValue, + int64_t &MemOpOffset, + SmallVectorImpl &UnderlyingObjs, + AAMDNodes &AATags, bool &IsAllIdentified) { + if (!MI->hasOneMemOperand()) + return false; + MachineMemOperand *MM = *MI->memoperands_begin(); + if (!MM->getValue()) + return false; + MemOpValue = MM->getValue(); + MemOpOffset = MM->getOffset(); + getUnderlyingObjects(MemOpValue, UnderlyingObjs); + AATags = MM->getAAInfo(); + IsAllIdentified = llvm::all_of(UnderlyingObjs, isIdentifiedObject); + return true; +} + +/// Return true if there is a loop-carried order dependency from memory access +/// SrcMI to DstMI in loop LoopBB. +static bool hasLoopCarriedMemDep(const MachineInstr *SrcMI, + const MachineInstr *DstMI, BatchAAResults &BAA, + const MachineBasicBlock *LoopBB, + const MachineRegisterInfo &MRI, + const TargetInstrInfo *TII) { + const Value *SrcVal = nullptr, *DstVal = nullptr; + int64_t SrcOffset = 0, DstOffset = 0; + SmallVector SrcObjs, DstObjs; + AAMDNodes SrcAATags, DstAATags; + bool SrcAllIdentified = false, DstAllIdentified = false; + bool SrcKnown = getMemInfo(SrcMI, SrcVal, SrcOffset, SrcObjs, SrcAATags, + SrcAllIdentified); + bool DstKnown = getMemInfo(DstMI, DstVal, DstOffset, DstObjs, DstAATags, + DstAllIdentified); + + // If all underlying objects are identified and disjoint, the accesses cannot + // alias. + if (SrcKnown && DstKnown && SrcAllIdentified && DstAllIdentified && + llvm::none_of(SrcObjs, [&](const Value *Obj) { + return llvm::is_contained(DstObjs, Obj); + })) + return false; + + // The overlap helper inspects only the first memory operand. Multi-MMO + // instructions could carry an overlap through a later operand, so be + // conservative and keep the dependency for them. + if (!SrcMI->hasOneMemOperand() || !DstMI->hasOneMemOperand()) + return true; + + if (!mayOverlapInLaterIter(SrcMI, DstMI, LoopBB, MRI, *TII)) + return false; + + // The more expensive check that uses alias analysis on the base values. + if (!SrcKnown || !DstKnown) + return true; + if (SrcVal == DstVal && SrcOffset <= DstOffset) + return true; + + if (BAA.isNoAlias(MemoryLocation::getBeforeOrAfter(SrcVal, SrcAATags), + MemoryLocation::getBeforeOrAfter(DstVal, DstAATags))) + return false; + + // AliasAnalysis sometimes gives up on following the underlying object. In + // such a case, separate checks for underlying objects may prove that there + // are no aliases between two accesses. + for (const Value *SrcObj : SrcObjs) + for (const Value *DstObj : DstObjs) + if (!BAA.isNoAlias(MemoryLocation::getBeforeOrAfter(SrcObj, SrcAATags), + MemoryLocation::getBeforeOrAfter(DstObj, DstAATags))) + return true; + + return false; +} + +namespace { +/// A DAG mutation that enforces the loop-carried memory dependences discovered +/// on the original loop while list scheduling each window of TripleMBB. +/// +/// For each recorded hazard pair (Pred, Succ) we add an artificial order edge +/// between the clone of Pred and the clone of Succ belonging to a later copy, +/// so that the iteration-N Pred is kept before the iteration-(N+1) Succ. +class WindowMemDepMutation : public ScheduleDAGMutation { + const DenseSet> &LoopCarriedMemDeps; + const DenseMap &TriToOri; + bool &EdgeFailed; + +public: + WindowMemDepMutation( + const DenseSet> &Deps, + const DenseMap &TriToOri, bool &EdgeFailed) + : LoopCarriedMemDeps(Deps), TriToOri(TriToOri), EdgeFailed(EdgeFailed) {} + + void apply(ScheduleDAGInstrs *DAG) override { + if (LoopCarriedMemDeps.empty()) + return; + for (SUnit &PredSU : DAG->SUnits) { + MachineInstr *PredMI = PredSU.getInstr(); + if (!PredMI || !PredMI->mayLoadOrStore()) + continue; + auto PredIt = TriToOri.find(PredMI); + if (PredIt == TriToOri.end()) + continue; + for (SUnit &SuccSU : DAG->SUnits) { + MachineInstr *SuccMI = SuccSU.getInstr(); + if (&PredSU == &SuccSU || !SuccMI || !SuccMI->mayLoadOrStore()) + continue; + auto SuccIt = TriToOri.find(SuccMI); + if (SuccIt == TriToOri.end()) + continue; + // Only order a Pred from an earlier copy before a Succ from a later + // copy, which models the iteration-N to iteration-(N+1) dependence. + if (PredIt->second.Copy >= SuccIt->second.Copy) + continue; + if (!LoopCarriedMemDeps.contains( + {PredIt->second.Ori, SuccIt->second.Ori})) + continue; + // If the edge would create a cycle, addEdge() returns false and does + // not insert it. The required dependence then cannot be enforced in + // this window, so mark it to make the caller abandon this window's + // schedule. + if (!DAG->addEdge(&SuccSU, SDep(&PredSU, SDep::Barrier))) + EdgeFailed = true; + } + } + } +}; +} // end anonymous namespace + WindowScheduler::WindowScheduler(MachineSchedContext *C, MachineLoop &ML) : Context(C), MF(C->MF), MBB(ML.getHeader()), Loop(ML), Subtarget(&MF->getSubtarget()), TII(Subtarget->getInstrInfo()), @@ -122,6 +256,20 @@ bool WindowScheduler::run() { preProcess(); // The main window scheduling begins. std::unique_ptr SchedDAG(createMachineScheduler()); + // A target may decline to provide a scheduler, in which case fall back to the + // generic live scheduler so that window scheduling still has one to drive. + if (!SchedDAG) + SchedDAG.reset(createSchedLive(Context)); + // Attach the mutation that enforces the loop-carried memory dependences. + // This requires the scheduler to support DAG mutations, i.e. to be a + // ScheduleDAGMI. Every in-tree target's pre-RA machine scheduler is a + // ScheduleDAGMI (or ScheduleDAGMILive), and the generic fallback + // createSchedLive() above returns one as well, so the cast below is safe. + // The assert documents and guards this invariant. + assert(SchedDAG && "Expected a scheduler for window scheduling"); + auto *SchedDAGMI = static_cast(SchedDAG.get()); + SchedDAGMI->addMutation(std::make_unique( + LoopCarriedMemDeps, TriToOri, MemDepEdgeFailed)); auto SearchIndexes = getSearchIndexes(WindowSearchNum, WindowSearchRatio); for (unsigned Idx : SearchIndexes) { OriToCycle.clear(); @@ -130,10 +278,17 @@ bool WindowScheduler::run() { // be added to Idx. unsigned Offset = Idx + SchedPhiNum; auto Range = getScheduleRange(Offset, SchedInstrNum); + MemDepEdgeFailed = false; SchedDAG->startBlock(MBB); SchedDAG->enterRegion(MBB, Range.begin(), Range.end(), SchedInstrNum); SchedDAG->schedule(); LLVM_DEBUG(SchedDAG->dump()); + if (MemDepEdgeFailed) { + restoreTripleMBB(); + LLVM_DEBUG(dbgs() << "Can't enforce a loop-carried memory dependence. " + "Keep searching...\n"); + continue; + } unsigned II = analyseII(*SchedDAG, Offset); if (II == WindowIILimit) { restoreTripleMBB(); @@ -249,6 +404,9 @@ bool WindowScheduler::initialize() { void WindowScheduler::preProcess() { // Prior to window scheduling, it's necessary to backup the original MBB, // generate a new TripleMBB, and build a TripleDAG based on the TripleMBB. + // Collect loop-carried memory dependences first, while the original MBB is + // still live (see collectLoopCarriedMemDeps() and run()). + collectLoopCarriedMemDeps(); backupMBB(); generateTripleMBB(); TripleDAG->startBlock(MBB); @@ -258,6 +416,38 @@ void WindowScheduler::preProcess() { TripleDAG->buildSchedGraph(Context->AA); } +void WindowScheduler::collectLoopCarriedMemDeps() { + LoopCarriedMemDeps.clear(); + MachineBasicBlock *LoopBB = MBB; + + // Collect the memory instructions of the original loop in program order. + SmallVector MemMIs; + for (MachineInstr &MI : *LoopBB) + if (MI.mayLoadOrStore() && !MI.isDebugInstr()) + MemMIs.push_back(&MI); + + // Nothing to do unless there is at least one store to order against. + if (llvm::none_of(MemMIs, + [](const MachineInstr *MI) { return MI->mayStore(); })) + return; + + BatchAAResults BAA(*Context->AA); + BAA.enableCrossIterationMode(); + + for (MachineInstr *SrcMI : MemMIs) { + for (MachineInstr *DstMI : MemMIs) { + if (SrcMI == DstMI) + continue; + // A loop-carried order edge is only required when at least one of the + // accesses stores. + if (!SrcMI->mayStore() && !DstMI->mayStore()) + continue; + if (hasLoopCarriedMemDep(SrcMI, DstMI, BAA, LoopBB, *MRI, TII)) + LoopCarriedMemDeps.insert({SrcMI, DstMI}); + } + } +} + void WindowScheduler::postProcess() { // After window scheduling, it's necessary to clear the TripleDAG and restore // to the original MBB. @@ -305,7 +495,7 @@ void WindowScheduler::generateTripleMBB() { auto *NewMI = MF->CloneMachineInstr(MI); MBB->push_back(NewMI); TriMIs.push_back(NewMI); - TriToOri[NewMI] = MI; + TriToOri[NewMI] = {MI, 0}; } // Step 2: Performing the remaining two copies of MBB instructions excluding // phis, and the last one contains terminators. At the same time, registers @@ -365,7 +555,7 @@ void WindowScheduler::generateTripleMBB() { DefPairs[NewDef.first] = NewDef.second; MBB->push_back(NewMI); TriMIs.push_back(NewMI); - TriToOri[NewMI] = MI; + TriToOri[NewMI] = {MI, static_cast(Cnt)}; } } // Step 3: The registers used by phis are updated, and they are generated in @@ -668,14 +858,14 @@ WindowScheduler::getScheduleRange(unsigned Offset, unsigned Num) { int WindowScheduler::getOriCycle(MachineInstr *NewMI) { assert(TriToOri.count(NewMI) && "Cannot find original MI!"); - auto *OriMI = TriToOri[NewMI]; + auto *OriMI = TriToOri[NewMI].Ori; assert(OriToCycle.count(OriMI) && "Cannot find schedule cycle!"); return OriToCycle[OriMI]; } MachineInstr *WindowScheduler::getOriMI(MachineInstr *NewMI) { assert(TriToOri.count(NewMI) && "Cannot find original MI!"); - return TriToOri[NewMI]; + return TriToOri[NewMI].Ori; } unsigned WindowScheduler::getOriStage(MachineInstr *OriMI, unsigned Offset) { diff --git a/llvm/test/CodeGen/Hexagon/swp-ws-loop-carried-dep.mir b/llvm/test/CodeGen/Hexagon/swp-ws-loop-carried-dep.mir new file mode 100644 index 00000000000000..1d389465d31a5e --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/swp-ws-loop-carried-dep.mir @@ -0,0 +1,325 @@ +# REQUIRES: asserts +# RUN: llc --mtriple=hexagon -mcpu=hexagonv68 %s -run-pass=pipeliner \ +# RUN: -debug-only=pipeliner -window-sched=force -filetype=null \ +# RUN: -verify-machineinstrs 2>&1 | FileCheck %s + +# This is the SHA-512 message-schedule loop from llvm.org/PR209946. Each +# iteration advances the base pointer %1 by 32 bytes and stores to offsets +# +48/+56/+64/+72. The store to +72 of iteration N writes the same address +# that a load from +40 of iteration N+1 reads (72 == 32 + 40), a loop-carried +# store->load dependence. If the WindowScheduler does not honor it, the +# aliasing load is scheduled ahead of the store and the loop computes wrong +# results. With the dependence modeled, window scheduling finds no profitable +# reordering here, so it declines (checked below). + +# CHECK: Window scheduling is not needed! + +--- | + target triple = "hexagon" + + ; Function Attrs: nofree noinline norecurse nosync nounwind memory(argmem: readwrite) + define dso_local void @schedule(ptr noundef captures(none) %W) local_unnamed_addr #0 { + entry: + %cgep = getelementptr i8, ptr %W, i32 80 + br label %for.body + + for.cond.cleanup: ; preds = %for.body + ret void + + for.body: ; preds = %for.body, %entry + %lsr.iv1 = phi ptr [ %cgep21, %for.body ], [ %cgep, %entry ] + %lsr.iv = phi i32 [ %lsr.iv.next, %for.body ], [ 64, %entry ] + %cgep20 = getelementptr i8, ptr %lsr.iv1, i32 -72 + %0 = load i64, ptr %cgep20, align 8, !tbaa !9 + %or = tail call i64 @llvm.fshl.i64(i64 %0, i64 %0, i64 63) + %or9 = tail call i64 @llvm.fshl.i64(i64 %0, i64 %0, i64 56) + %xor = xor i64 %or, %or9 + %shr12 = lshr i64 %0, 7 + %xor13 = xor i64 %xor, %shr12 + %cgep21 = getelementptr i8, ptr %lsr.iv1, i32 32 + %1 = load i64, ptr %cgep21, align 8, !tbaa !9 + %or20 = tail call i64 @llvm.fshl.i64(i64 %1, i64 %1, i64 45) + %or27 = tail call i64 @llvm.fshl.i64(i64 %1, i64 %1, i64 3) + %xor28 = xor i64 %or20, %or27 + %shr31 = lshr i64 %1, 6 + %xor32 = xor i64 %xor28, %shr31 + %cgep22 = getelementptr i8, ptr %lsr.iv1, i32 -80 + %2 = load i64, ptr %cgep22, align 8, !tbaa !9 + %add = add i64 %xor13, %2 + %cgep23 = getelementptr i8, ptr %lsr.iv1, i32 -8 + %3 = load i64, ptr %cgep23, align 8, !tbaa !9 + %add37 = add i64 %add, %3 + %add38 = add i64 %add37, %xor32 + %cgep19 = getelementptr i8, ptr %lsr.iv1, i32 48 + store i64 %add38, ptr %cgep19, align 8, !tbaa !9 + %cgep25 = getelementptr i8, ptr %lsr.iv1, i32 -64 + %4 = load i64, ptr %cgep25, align 8, !tbaa !9 + %or.1 = tail call i64 @llvm.fshl.i64(i64 %4, i64 %4, i64 63) + %or9.1 = tail call i64 @llvm.fshl.i64(i64 %4, i64 %4, i64 56) + %xor.1 = xor i64 %or.1, %or9.1 + %shr12.1 = lshr i64 %4, 7 + %xor13.1 = xor i64 %xor.1, %shr12.1 + %cgep26 = getelementptr i8, ptr %lsr.iv1, i32 40 + %5 = load i64, ptr %cgep26, align 8, !tbaa !9 + %or20.1 = tail call i64 @llvm.fshl.i64(i64 %5, i64 %5, i64 45) + %or27.1 = tail call i64 @llvm.fshl.i64(i64 %5, i64 %5, i64 3) + %xor28.1 = xor i64 %or20.1, %or27.1 + %shr31.1 = lshr i64 %5, 6 + %xor32.1 = xor i64 %xor28.1, %shr31.1 + %add.1 = add i64 %xor13.1, %0 + %6 = load i64, ptr %lsr.iv1, align 8, !tbaa !9 + %add37.1 = add i64 %add.1, %6 + %add38.1 = add i64 %add37.1, %xor32.1 + %cgep24 = getelementptr i8, ptr %lsr.iv1, i32 56 + store i64 %add38.1, ptr %cgep24, align 8, !tbaa !9 + %cgep28 = getelementptr i8, ptr %lsr.iv1, i32 -56 + %7 = load i64, ptr %cgep28, align 8, !tbaa !9 + %or.2 = tail call i64 @llvm.fshl.i64(i64 %7, i64 %7, i64 63) + %or9.2 = tail call i64 @llvm.fshl.i64(i64 %7, i64 %7, i64 56) + %xor.2 = xor i64 %or.2, %or9.2 + %shr12.2 = lshr i64 %7, 7 + %xor13.2 = xor i64 %xor.2, %shr12.2 + %8 = load i64, ptr %cgep19, align 8, !tbaa !9 + %or20.2 = tail call i64 @llvm.fshl.i64(i64 %8, i64 %8, i64 45) + %or27.2 = tail call i64 @llvm.fshl.i64(i64 %8, i64 %8, i64 3) + %xor28.2 = xor i64 %or20.2, %or27.2 + %shr31.2 = lshr i64 %8, 6 + %xor32.2 = xor i64 %xor28.2, %shr31.2 + %add.2 = add i64 %xor13.2, %4 + %cgep29 = getelementptr i8, ptr %lsr.iv1, i32 8 + %9 = load i64, ptr %cgep29, align 8, !tbaa !9 + %add37.2 = add i64 %add.2, %9 + %add38.2 = add i64 %add37.2, %xor32.2 + %cgep27 = getelementptr i8, ptr %lsr.iv1, i32 64 + store i64 %add38.2, ptr %cgep27, align 8, !tbaa !9 + %cgep31 = getelementptr i8, ptr %lsr.iv1, i32 -48 + %10 = load i64, ptr %cgep31, align 8, !tbaa !9 + %or.3 = tail call i64 @llvm.fshl.i64(i64 %10, i64 %10, i64 63) + %or9.3 = tail call i64 @llvm.fshl.i64(i64 %10, i64 %10, i64 56) + %xor.3 = xor i64 %or.3, %or9.3 + %shr12.3 = lshr i64 %10, 7 + %xor13.3 = xor i64 %xor.3, %shr12.3 + %11 = load i64, ptr %cgep24, align 8, !tbaa !9 + %or20.3 = tail call i64 @llvm.fshl.i64(i64 %11, i64 %11, i64 45) + %or27.3 = tail call i64 @llvm.fshl.i64(i64 %11, i64 %11, i64 3) + %xor28.3 = xor i64 %or20.3, %or27.3 + %shr31.3 = lshr i64 %11, 6 + %xor32.3 = xor i64 %xor28.3, %shr31.3 + %add.3 = add i64 %xor13.3, %7 + %cgep32 = getelementptr i8, ptr %lsr.iv1, i32 16 + %12 = load i64, ptr %cgep32, align 8, !tbaa !9 + %add37.3 = add i64 %add.3, %12 + %add38.3 = add i64 %add37.3, %xor32.3 + %cgep30 = getelementptr i8, ptr %lsr.iv1, i32 72 + store i64 %add38.3, ptr %cgep30, align 8, !tbaa !9 + %lsr.iv.next = add nsw i32 %lsr.iv, -4 + %exitcond.not.3 = icmp eq i32 %lsr.iv.next, 0 + br i1 %exitcond.not.3, label %for.cond.cleanup, label %for.body, !llvm.loop !11 + } + + ; Function Attrs: nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) + declare i64 @llvm.fshl.i64(i64, i64, i64) #1 + + attributes #0 = { nofree noinline norecurse nosync nounwind memory(argmem: readwrite) "frame-pointer"="all" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="hexagonv68" "target-features"="+v68,-long-calls" } + attributes #1 = { nocallback nocreateundeforpoison nofree nosync nounwind speculatable willreturn memory(none) "target-cpu"="hexagonv68" } + + !llvm.module.flags = !{!0, !1, !2, !3} + !llvm.ident = !{!4} + !llvm.errno.tbaa = !{!5} + + !0 = !{i32 1, !"wchar_size", i32 4} + !1 = !{i32 8, !"PIC Level", i32 2} + !2 = !{i32 7, !"PIE Level", i32 2} + !3 = !{i32 7, !"frame-pointer", i32 2} + !4 = !{!"clang version 22.1.8"} + !5 = !{!6, !6, i64 0} + !6 = !{!"int", !7, i64 0} + !7 = !{!"omnipotent char", !8, i64 0} + !8 = !{!"Simple C/C++ TBAA"} + !9 = !{!10, !10, i64 0} + !10 = !{!"long long", !7, i64 0} + !11 = distinct !{!11, !12} + !12 = !{!"llvm.loop.mustprogress"} +... +--- +name: schedule +alignment: 4 +exposesReturnsTwice: false +legalized: false +regBankSelected: false +selected: false +failedISel: false +tracksRegLiveness: true +hasWinCFI: false +noPhis: false +isSSA: true +noVRegs: false +hasFakeUses: false +callsEHReturn: false +callsUnwindInit: false +hasEHContTarget: false +hasEHScopes: false +hasEHFunclets: false +isOutlined: false +debugInstrRef: false +failsVerification: false +tracksDebugUserValues: false +registers: + - { id: 0, class: intregs, preferred-register: '', flags: [ ] } + - { id: 1, class: intregs, preferred-register: '', flags: [ ] } + - { id: 2, class: intregs, preferred-register: '', flags: [ ] } + - { id: 3, class: intregs, preferred-register: '', flags: [ ] } + - { id: 4, class: intregs, preferred-register: '', flags: [ ] } + - { id: 5, class: intregs, preferred-register: '', flags: [ ] } + - { id: 6, class: intregs, preferred-register: '', flags: [ ] } + - { id: 7, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 8, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 9, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 10, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 11, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 12, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 13, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 14, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 15, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 16, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 17, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 18, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 19, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 20, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 21, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 22, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 23, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 24, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 25, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 26, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 27, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 28, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 29, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 30, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 31, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 32, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 33, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 34, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 35, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 36, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 37, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 38, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 39, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 40, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 41, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 42, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 43, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 44, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 45, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 46, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 47, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 48, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 49, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 50, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 51, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 52, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 53, class: doubleregs, preferred-register: '', flags: [ ] } + - { id: 54, class: predregs, preferred-register: '', flags: [ ] } +liveins: + - { reg: '$r0', virtual-reg: '%5' } +frameInfo: + isFrameAddressTaken: false + isReturnAddressTaken: false + hasStackMap: false + hasPatchPoint: false + stackSize: 0 + offsetAdjustment: 0 + maxAlignment: 1 + adjustsStack: false + hasCalls: false + framePointerPolicy: all + stackProtector: '' + functionContext: '' + maxCallFrameSize: 4294967295 + cvBytesOfCalleeSavedRegisters: 0 + hasOpaqueSPAdjustment: false + hasVAStart: false + hasMustTailInVarArgFunc: false + hasTailCall: false + isCalleeSavedInfoValid: false + localFrameSize: 0 +fixedStack: [] +stack: [] +entry_values: [] +callSites: [] +debugValueSubstitutions: [] +constants: [] +machineFunctionInfo: + stackAlignBaseReg: '' +body: | + bb.0.entry: + successors: %bb.2(0x80000000) + liveins: $r0 + + %5:intregs = COPY $r0 + %0:intregs = A2_addi %5, 80 + J2_loop0i %bb.2, 16, implicit-def $lc0, implicit-def $sa0, implicit-def $usr + J2_jump %bb.2, implicit-def dead $pc + + bb.1.for.cond.cleanup: + PS_jmpret $r31, implicit-def dead $pc + + bb.2.for.body (machine-block-address-taken): + successors: %bb.1(0x04000000), %bb.2(0x7c000000) + + %1:intregs = PHI %0, %bb.0, %3, %bb.2 + %7:doubleregs = L2_loadrd_io %1, -72 :: (load (s64) from %ir.cgep20, !tbaa !9) + %8:doubleregs = S6_rol_i_p %7, 63 + %9:doubleregs = S6_rol_i_p_xacc %8, %7, 56 + %10:doubleregs = S2_lsr_i_p_xacc %9, %7, 7 + %3:intregs = A2_addi %1, 32 + %11:doubleregs = L2_loadrd_io %1, 32 :: (load (s64) from %ir.cgep21, !tbaa !9) + %12:doubleregs = S6_rol_i_p %11, 45 + %13:doubleregs = S6_rol_i_p_xacc %12, %11, 3 + %14:doubleregs = S2_lsr_i_p_xacc %13, %11, 6 + %15:doubleregs = L2_loadrd_io %1, -80 :: (load (s64) from %ir.cgep22, !tbaa !9) + %16:doubleregs = A2_addp killed %10, killed %15 + %17:doubleregs = L2_loadrd_io %1, -8 :: (load (s64) from %ir.cgep23, !tbaa !9) + %18:doubleregs = A2_addp killed %16, killed %17 + %19:doubleregs = A2_addp killed %18, killed %14 + S2_storerd_io %1, 48, %19 :: (store (s64) into %ir.cgep19, !tbaa !9) + %20:doubleregs = L2_loadrd_io %1, -64 :: (load (s64) from %ir.cgep25, !tbaa !9) + %21:doubleregs = S6_rol_i_p %20, 63 + %22:doubleregs = S6_rol_i_p_xacc %21, %20, 56 + %23:doubleregs = S2_lsr_i_p_xacc %22, %20, 7 + %24:doubleregs = L2_loadrd_io %1, 40 :: (load (s64) from %ir.cgep26, !tbaa !9) + %25:doubleregs = S6_rol_i_p %24, 45 + %26:doubleregs = S6_rol_i_p_xacc %25, %24, 3 + %27:doubleregs = S2_lsr_i_p_xacc %26, %24, 6 + %28:doubleregs = A2_addp killed %23, %7 + %29:doubleregs = L2_loadrd_io %1, 0 :: (load (s64) from %ir.lsr.iv1, !tbaa !9) + %30:doubleregs = A2_addp killed %28, killed %29 + %31:doubleregs = A2_addp killed %30, killed %27 + S2_storerd_io %1, 56, %31 :: (store (s64) into %ir.cgep24, !tbaa !9) + %32:doubleregs = L2_loadrd_io %1, -56 :: (load (s64) from %ir.cgep28, !tbaa !9) + %33:doubleregs = S6_rol_i_p %32, 63 + %34:doubleregs = S6_rol_i_p_xacc %33, %32, 56 + %35:doubleregs = S2_lsr_i_p_xacc %34, %32, 7 + %36:doubleregs = S6_rol_i_p %19, 45 + %37:doubleregs = S6_rol_i_p_xacc %36, %19, 3 + %38:doubleregs = S2_lsr_i_p_xacc %37, %19, 6 + %39:doubleregs = A2_addp killed %35, %20 + %40:doubleregs = L2_loadrd_io %1, 8 :: (load (s64) from %ir.cgep29, !tbaa !9) + %41:doubleregs = A2_addp killed %39, killed %40 + %42:doubleregs = A2_addp killed %41, killed %38 + S2_storerd_io %1, 64, killed %42 :: (store (s64) into %ir.cgep27, !tbaa !9) + %43:doubleregs = L2_loadrd_io %1, -48 :: (load (s64) from %ir.cgep31, !tbaa !9) + %44:doubleregs = S6_rol_i_p %43, 63 + %45:doubleregs = S6_rol_i_p_xacc %44, %43, 56 + %46:doubleregs = S2_lsr_i_p_xacc %45, %43, 7 + %47:doubleregs = S6_rol_i_p %31, 45 + %48:doubleregs = S6_rol_i_p_xacc %47, %31, 3 + %49:doubleregs = S2_lsr_i_p_xacc %48, %31, 6 + %50:doubleregs = A2_addp killed %46, %32 + %51:doubleregs = L2_loadrd_io %1, 16 :: (load (s64) from %ir.cgep32, !tbaa !9) + %52:doubleregs = A2_addp killed %50, killed %51 + %53:doubleregs = A2_addp killed %52, killed %49 + S2_storerd_io %1, 72, killed %53 :: (store (s64) into %ir.cgep30, !tbaa !9) + ENDLOOP0 %bb.2, implicit-def $pc, implicit-def $lc0, implicit $sa0, implicit $lc0 + J2_jump %bb.1, implicit-def $pc +... From 25385baacc635c7159644f612dcee0cd3ff88451 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Sat, 24 Oct 2026 15:25:45 -0700 Subject: [PATCH 30/31] [Passes] Make runCodeGenPipeline take raw_pwrite_stream for DwoOS (#235339) The std::unique_ptr reference was mostly cargo-culting from clang/flang that does not necessarily make sense for other frontends (case study right now is rustc). Change to a raw_pwrite_stream given that makes more sense internally and gives frontends more flexibility. --- clang/lib/CodeGen/BackendUtil.cpp | 3 ++- flang/lib/Frontend/FrontendActions.cpp | 4 ++-- llvm/include/llvm/Passes/RunCodeGen.h | 6 +++--- llvm/lib/Passes/RunCodeGen.cpp | 16 ++++++---------- 4 files changed, 13 insertions(+), 16 deletions(-) diff --git a/clang/lib/CodeGen/BackendUtil.cpp b/clang/lib/CodeGen/BackendUtil.cpp index 8331ad64df3dff..fe1454026f569d 100644 --- a/clang/lib/CodeGen/BackendUtil.cpp +++ b/clang/lib/CodeGen/BackendUtil.cpp @@ -1282,7 +1282,8 @@ void EmitAssemblyHelper::RunCodegenPipeline( TimeCodegenPasses([&]() { Error CodeGenError = runCodeGenPipeline( - *TM, *TheModule, *OS, DwoOS, CGFT, !CodeGenOpts.VerifyModule, + *TM, *TheModule, *OS, DwoOS ? &DwoOS->os() : nullptr, CGFT, + !CodeGenOpts.VerifyModule, /*DisableSimplifyLibCalls=*/false, CI.getVirtualFileSystemPtr()); if (CodeGenError) Diags.Report(diag::err_fe_unable_to_interface_with_target); diff --git a/flang/lib/Frontend/FrontendActions.cpp b/flang/lib/Frontend/FrontendActions.cpp index 8ebcafa9426aa1..9191f22b7024e8 100644 --- a/flang/lib/Frontend/FrontendActions.cpp +++ b/flang/lib/Frontend/FrontendActions.cpp @@ -937,8 +937,8 @@ static void generateMachineCodeOrAssemblyImpl( return; } } - llvm::Error codeGenError = - runCodeGenPipeline(tm, llvmModule, os, dwoOS, cgft); + llvm::Error codeGenError = runCodeGenPipeline( + tm, llvmModule, os, dwoOS ? &dwoOS->os() : nullptr, cgft); if (codeGenError) { unsigned diagID = diags.getCustomDiagID(clang::DiagnosticsEngine::Error, diff --git a/llvm/include/llvm/Passes/RunCodeGen.h b/llvm/include/llvm/Passes/RunCodeGen.h index 39f06746817c8f..87db2562b7acae 100644 --- a/llvm/include/llvm/Passes/RunCodeGen.h +++ b/llvm/include/llvm/Passes/RunCodeGen.h @@ -10,16 +10,16 @@ #define LLVM_PASSES_RUN_CODEGEN_H #include "llvm/IR/Module.h" -#include "llvm/Support/ToolOutputFile.h" #include "llvm/Support/VirtualFileSystem.h" +#include "llvm/Support/raw_ostream.h" #include "llvm/Target/TargetMachine.h" namespace llvm { LLVM_ABI Error runCodeGenPipeline( TargetMachine &TM, Module &M, raw_pwrite_stream &OS, - std::unique_ptr &DwoOS, CodeGenFileType CGFT, - bool DisableVerify = true, bool DisableSimplifyLibCalls = false, + raw_pwrite_stream *DwoOS, CodeGenFileType CGFT, bool DisableVerify = true, + bool DisableSimplifyLibCalls = false, IntrusiveRefCntPtr VFS = vfs::getRealFileSystem()); } // namespace llvm diff --git a/llvm/lib/Passes/RunCodeGen.cpp b/llvm/lib/Passes/RunCodeGen.cpp index 7dd4a02c778ca6..67aecdb6f5494c 100644 --- a/llvm/lib/Passes/RunCodeGen.cpp +++ b/llvm/lib/Passes/RunCodeGen.cpp @@ -20,7 +20,6 @@ #include "llvm/Passes/PassBuilder.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/Error.h" -#include "llvm/Support/ToolOutputFile.h" #include "llvm/Support/raw_ostream.h" #include "llvm/Target/CGPassBuilderOption.h" @@ -28,7 +27,7 @@ using namespace llvm; static Error runCodeGenPipelineLegacy(TargetMachine &TM, Module &M, raw_pwrite_stream &OS, - std::unique_ptr &DwoOS, + raw_pwrite_stream *DwoOS, CodeGenFileType CGFT, bool DisableVerify, bool DisableSimplifyLibCalls) { legacy::PassManager CodeGenPasses; @@ -44,8 +43,7 @@ static Error runCodeGenPipelineLegacy(TargetMachine &TM, Module &M, CodeGenPasses.add( new RuntimeLibraryInfoWrapper(Options.MCOptions.ABIName, Options.VecLib)); - if (TM.addPassesToEmitFile(CodeGenPasses, OS, DwoOS ? &DwoOS->os() : nullptr, - CGFT, DisableVerify)) + if (TM.addPassesToEmitFile(CodeGenPasses, OS, DwoOS, CGFT, DisableVerify)) return createStringError("Failed to construct CodeGen pipeline"); CodeGenPasses.run(M); @@ -54,7 +52,7 @@ static Error runCodeGenPipelineLegacy(TargetMachine &TM, Module &M, static Error runCodeGenPipelineNewPM(TargetMachine &TM, Module &M, raw_pwrite_stream &OS, - std::unique_ptr &DwoOS, + raw_pwrite_stream *DwoOS, CodeGenFileType CGFT, bool DisableVerify, IntrusiveRefCntPtr VFS) { ModulePassManager MPM; @@ -79,9 +77,8 @@ static Error runCodeGenPipelineNewPM(TargetMachine &TM, Module &M, MAM.registerPass([&] { return MachineModuleAnalysis(MMI); }); - Error BuildPipelineError = - TM.buildCodeGenPipeline(MPM, MAM, OS, DwoOS ? &DwoOS->os() : nullptr, - CGFT, Opt, MMI.getContext(), &PIC); + Error BuildPipelineError = TM.buildCodeGenPipeline( + MPM, MAM, OS, DwoOS, CGFT, Opt, MMI.getContext(), &PIC); if (BuildPipelineError) return BuildPipelineError; @@ -90,8 +87,7 @@ static Error runCodeGenPipelineNewPM(TargetMachine &TM, Module &M, } Error llvm::runCodeGenPipeline(TargetMachine &TM, Module &M, - raw_pwrite_stream &OS, - std::unique_ptr &DwoOS, + raw_pwrite_stream &OS, raw_pwrite_stream *DwoOS, CodeGenFileType CGFT, bool DisableVerify, bool DisableSimplifyLibCalls, IntrusiveRefCntPtr VFS) { From a16800b01de2b2936a60a30eed1fceb45f7dc811 Mon Sep 17 00:00:00 2001 From: Ron Lieberman Date: Sat, 24 Oct 2026 18:15:51 -0500 Subject: [PATCH 31/31] Revert "[mlir] Skip uniquer locks when a context starts without threading (#235294)" This reverts commit 34379c8a88246f340a20a76df24714c41f0a163e. --- mlir/lib/IR/MLIRContext.cpp | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/mlir/lib/IR/MLIRContext.cpp b/mlir/lib/IR/MLIRContext.cpp index 9eae9676a2b2c3..5c1c3b062f37cc 100644 --- a/mlir/lib/IR/MLIRContext.cpp +++ b/mlir/lib/IR/MLIRContext.cpp @@ -287,16 +287,8 @@ class MLIRContextImpl { if (threadingIsEnabled) { ownedThreadPool = std::make_unique(); threadPool = ownedThreadPool.get(); - } else { - disableUniquerMultithreading(true); } } - /// Update the threading mode for each of the uniquers. - void disableUniquerMultithreading(bool disable) { - affineUniquer.disableMultithreading(disable); - attributeUniquer.disableMultithreading(disable); - typeUniquer.disableMultithreading(disable); - } ~MLIRContextImpl() { for (auto typeMapping : registeredTypes) typeMapping.second->~AbstractType(); @@ -633,7 +625,10 @@ void MLIRContext::disableMultithreading(bool disable) { impl->threadingIsEnabled = !disable; - impl->disableUniquerMultithreading(disable); + // Update the threading mode for each of the uniquers. + impl->affineUniquer.disableMultithreading(disable); + impl->attributeUniquer.disableMultithreading(disable); + impl->typeUniquer.disableMultithreading(disable); // Destroy thread pool (stop all threads) if it is no longer needed, or create // a new one if multithreading was re-enabled.