From 2d6b4725df92ba12e7f6d3809d7077c064778e6b Mon Sep 17 00:00:00 2001 From: Mark Stevens Date: Wed, 14 Oct 2026 20:23:23 +0100 Subject: [PATCH 1/2] Use the NuttX 12 stack bounds as they are Since NuttX 10.2.0 (upstream commit 2335b69120a) pthread_get_stackaddr_np returns stack_base_ptr, the lowest usable stack address, and pthread_get_stacksize_np the usable size. The NuttX port still assumed the NuttX 7 behaviour (the initial stack pointer at the top) and subtracted the size, so the bounds lay below the real stack and the sanity check in mono_thread_info_get_stack_bounds asserted during GC initialisation. Co-Authored-By: Claude Opus 5.5 --- src/mono/mono/utils/mono-threads-nuttx.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/src/mono/mono/utils/mono-threads-nuttx.c b/src/mono/mono/utils/mono-threads-nuttx.c index 391d649b488049..29798bdc4f3daa 100644 --- a/src/mono/mono/utils/mono-threads-nuttx.c +++ b/src/mono/mono/utils/mono-threads-nuttx.c @@ -20,16 +20,14 @@ mono_threads_platform_get_stack_bounds (guint8 **staddr, size_t *stsize) *staddr = (guint8*)pthread_get_stackaddr_np (pthread_self ()); *stsize = pthread_get_stacksize_np (pthread_self ()); - /* NuttX's pthread_get_stackaddr_np returns adj_stack_ptr (initial SP) and - * pthread_get_stacksize_np returns adj_stack_size. However, up_stack_frame() - * carves a frame off the top of the stack for argument passing BEFORE the - * thread starts, reducing adj_stack_ptr/adj_stack_size. The actual allocated - * memory extends above adj_stack_ptr by up to ~4KB (argument frame + alignment). - * MONO_CONTEXT_GET_CURRENT captures the real SP which may land in this - * carved-off region, causing is_thread_in_critical_region to think the thread - * is on an alternate stack. Add a 4KB guard to cover the frame area. */ - *staddr -= *stsize; - *stsize += 4096; + /* Since NuttX 10.2.0 (upstream commit 2335b69120a, "arch: Allocate the + * space from the beginning in up_stack_frame"), pthread_get_stackaddr_np + * returns stack_base_ptr, the lowest usable address, and + * pthread_get_stacksize_np the usable size, so the stack is + * [staddr, staddr + stsize) and needs no adjustment. The same commit moved + * the argument frame to the base of the stack (up_stack_frame() raises + * stack_base_ptr), so it is outside these bounds. Up to NuttX 10.1 the + * address was adj_stack_ptr, the initial stack pointer at the top. */ } guint64 From 70d0c7b32ea25600f019db217aab64e801939f6e Mon Sep 17 00:00:00 2001 From: Mark Stevens Date: Wed, 14 Oct 2026 20:23:23 +0100 Subject: [PATCH 2/2] Access the Thumb-2 code buffer with halfword alignment Thumb-2 code is only halfword aligned, but the JIT wrote 32-bit instructions and literal words through uint32_t/guint32 pointers and 32-bit bit-field structures, which tell the compiler the address is word aligned. GCC 15 combined two such stores in get_throw_trampoline into an STRD, which takes a UsageFault (UNALIGNED) on a halfword aligned address. In thumb-codegen.h arminstr_t and armword_t are now 2-byte aligned, the 36 32-bit instruction structures are packed with 2-byte alignment (sizes are unchanged), and the code-buffer accesses in thumb-codegen.h, mini-arm.c and tramp-arm.c use arminstr_t. arm-codegen.h (A32, always word aligned) is unchanged. Co-Authored-By: Claude Opus 5.5 --- src/mono/mono/arch/arm/thumb-codegen.h | 179 +++++++++++++------------ src/mono/mono/mini/mini-arm.c | 30 ++--- src/mono/mono/mini/tramp-arm.c | 30 ++--- 3 files changed, 126 insertions(+), 113 deletions(-) diff --git a/src/mono/mono/arch/arm/thumb-codegen.h b/src/mono/mono/arch/arm/thumb-codegen.h index 36c6ff75ccc6b2..376b6c079edd6d 100644 --- a/src/mono/mono/arch/arm/thumb-codegen.h +++ b/src/mono/mono/arch/arm/thumb-codegen.h @@ -9,8 +9,21 @@ extern "C" { #define __THUMB_INLINE__ __inline__ // __attribute__((always_inline)) -typedef unsigned int arminstr_t; -typedef unsigned int armword_t; +/* + * Thumb-2 code is only halfword aligned, so a 32-bit instruction or a literal + * word in the code buffer may start at an address that is not a multiple of + * 4. Every 32-bit access to the code buffer therefore goes through a type + * with 2-byte alignment. With a 4-byte aligned type the compiler may combine + * adjacent accesses into LDRD/STRD or LDM/STM, which fault on a halfword + * aligned address even where single LDR/STR accesses are allowed (GCC 15 + * emitted an STRD in get_throw_trampoline that took a UsageFault). + */ +typedef unsigned int __attribute__((aligned(2))) arminstr_t; +typedef unsigned int __attribute__((aligned(2))) armword_t; + +/* For the 32-bit instruction bit-field structures below; the layout is + * unchanged, only the alignment is reduced to 2. */ +#define THUMB_INSN32_ALIGN __attribute__((packed, aligned(2))) typedef enum { ARMREG_R0 = 0, @@ -900,14 +913,14 @@ typedef struct { uint32_t rd:4; /* Register d */ uint32_t imm3:3; /* Bits 8-10 of immediate */ uint32_t typec:1; /* '0'b */ -} dpm32_t; +} THUMB_INSN32_ALIGN dpm32_t; #define OP_DPM32 0x0000f000 static __THUMB_INLINE__ void arm_dpm32(void **code, int rd, int rn, int imm, int cond, int opcode) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; dpm32_t *op = *(dpm32_t **) code; *p = OP_DPM32; imm = arm_imm12(imm); @@ -955,14 +968,14 @@ typedef struct { uint32_t rd:4; /* Register d */ uint32_t imm3:3; /* Bits 8-10 of immediate */ uint32_t typec:1; /* '0'b */ -} asp32_t; +} THUMB_INSN32_ALIGN asp32_t; #define OP_ASP32 0x0000f200 static __THUMB_INLINE__ void arm_asp32(void **code, int rd, int rn, int imm, int opcode) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; asp32_t *op = *(asp32_t **) code; *p = OP_ASP32; imm = arm_imm12(imm); @@ -991,14 +1004,14 @@ typedef struct { uint32_t rd:4; /* Register d */ uint32_t imm3:3; /* Bits 8-10 of immediate */ uint32_t typec:1; /* '0'b */ -} mvp32_t; +} THUMB_INSN32_ALIGN mvp32_t; #define OP_MVP32 0x0000f240 static __THUMB_INLINE__ void arm_mvp32(void **code, int rd, int imm, int opcode) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; mvp32_t *op = *(mvp32_t **) code; *p = OP_MVP32; op->rd = rd; @@ -1026,14 +1039,14 @@ typedef struct { uint32_t rd:4; /* Register d */ uint32_t imm3:3; /* Bits 7-10 of immediate */ uint32_t typec:1; /* '0'b */ -} bfo32_t; +} THUMB_INSN32_ALIGN bfo32_t; #define OP_BFO32 0x0000f300 static __THUMB_INLINE__ void arm_bfo32(void **code, int rd, int imm, int opcode) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; bfo32_t *op = *(bfo32_t **) code; *p = OP_BFO32; op->rd = rd; @@ -1058,14 +1071,14 @@ typedef struct { uint32_t rd:4; /* Register d */ uint32_t imm3:3; /* Bits 2-4 of immediate */ uint32_t sbz:1; /* '0'b */ -} dpc32_t; +} THUMB_INSN32_ALIGN dpc32_t; #define OP_DPC32 0x0000ea00 static __THUMB_INLINE__ void arm_dpc32(void **code, int rd, int rn, int rm, int imm, int cond, int opcode, int optype) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; dpc32_t *op = *(dpc32_t **) code; *p = OP_DPC32; op->rn = rn; @@ -1090,14 +1103,14 @@ typedef struct { uint32_t op2:4; /* Op-code */ uint32_t rd:4; /* Register d */ uint32_t typea:4; /* '1111'b */ -} rcs32_t; +} THUMB_INSN32_ALIGN rcs32_t; #define OP_RCS32 0xf000fa00 static __THUMB_INLINE__ void arm_rcs32(void **code, int rd, int rn, int rm, int opcode, int op2) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; rcs32_t *op = *(rcs32_t **) code; *p = OP_RCS32; op->rn = rn; @@ -1120,14 +1133,14 @@ typedef struct { uint32_t typea:2; /* '01'b */ uint32_t rd:4; /* Register d */ uint32_t typeb:4; /* '1111'b */ -} szx32_t; +} THUMB_INSN32_ALIGN szx32_t; #define OP_SZX32 0xf080fa00 static __THUMB_INLINE__ void arm_szx32(void **code, int rd, int rn, int rm, int rot, int opcode) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; szx32_t *op = *(szx32_t **) code; *p = OP_SZX32; op->rn = rn; @@ -1150,14 +1163,14 @@ typedef struct { uint32_t typea:1; /* '0'b */ uint32_t rd:4; /* Register d */ uint32_t typeb:4; /* '1111'b */ -} sim32_t; +} THUMB_INSN32_ALIGN sim32_t; #define OP_SIM32 0xf000fa80 static __THUMB_INLINE__ void arm_sim32(void **code, int rd, int rn, int rm, int pfx, int opcode) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; sim32_t *op = *(sim32_t **) code; *p = OP_SIM32; op->rn = rn; @@ -1180,14 +1193,14 @@ typedef struct { uint32_t rn:4; /* Register n */ uint32_t op:2; /* Op-code */ uint32_t type:9; /* '111110101'b */ -} odp32_t; +} THUMB_INSN32_ALIGN odp32_t; #define OP_ODP32 0xf080fa80 static __THUMB_INLINE__ void arm_odp32(void **code, int rd, int rn, int rm, int opcode) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; odp32_t *op = *(odp32_t **) code; *p = OP_ODP32; op->rn = rn; @@ -1210,14 +1223,14 @@ typedef struct { uint32_t typea:2; /* '00'b */ uint32_t rd:4; /* Register d */ uint32_t ra:4; /* Accumulator register */ -} msa32_t; +} THUMB_INSN32_ALIGN msa32_t; #define OP_MSA32 0x0000fb00 static __THUMB_INLINE__ void arm_msa32(void **code, int rd, int rn, int rm, int ra, int op1, int op2) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; msa32_t *op = *(msa32_t **) code; *p = OP_MSA32; op->rn = rn; @@ -1240,14 +1253,14 @@ typedef struct { uint32_t op2:4; /* Op-code part 2 */ uint32_t rdhi:4; /* Register d high */ uint32_t rdlo:4; /* Register d low */ -} mad32_t; +} THUMB_INSN32_ALIGN mad32_t; #define OP_MAD32 0x0000fbc0 static __THUMB_INLINE__ void arm_mad32(void **code, int rdhi, int rdlo, int rn, int rm, int op1, int op2) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; mad32_t *op = *(mad32_t **) code; *p = OP_MAD32; op->rn = rn; @@ -1272,14 +1285,14 @@ typedef struct { uint32_t op:4; /* Op-code */ uint32_t coproc:4; /* Coprocessor */ uint32_t rt:4; /* Register t */ -} crr32_t; +} THUMB_INSN32_ALIGN crr32_t; #define OP_CRR32 0x0000ec20 static __THUMB_INLINE__ void arm_crr32(void **code, int c, int l, int rt, int rt2, int coproc, int crm, int opcode) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; crr32_t *op = *(crr32_t **) code; *p = OP_CRR32; op->crm = crm; @@ -1308,7 +1321,7 @@ typedef struct { uint32_t imm:8; /* Immediate value */ uint32_t coproc:4; /* Coprocessor */ uint32_t crd:4; /* Coprocessor Register d */ -} lsc32_t; +} THUMB_INSN32_ALIGN lsc32_t; #define OP_LSC32 0x0000ec20 @@ -1316,7 +1329,7 @@ static __THUMB_INLINE__ void arm_lsc32(void **code, int c, int p, int u, int n, int w, int l, int rn, int crd, int coproc, int imm) { - uint32_t *x = *(uint32_t **) code; + arminstr_t *x = *(arminstr_t **) code; lsc32_t *op = *(lsc32_t **) code; *x = OP_LSC32; op->imm = imm; @@ -1346,14 +1359,14 @@ typedef struct { uint32_t opc2:3; /* Op-code 2 */ uint32_t coproc:4; /* Coprocessor */ uint32_t crd:4; /* Coprocessor Register d */ -} cdp32_t; +} THUMB_INSN32_ALIGN cdp32_t; #define OP_CDP32 0x0000ee00 static __THUMB_INLINE__ void arm_cdp32(void **code, int crd, int crn, int crm, int c, int coproc, int opc2, int opc1) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; cdp32_t *op = *(cdp32_t **) code; *p = OP_CDP32; op->crm = crm; @@ -1381,14 +1394,14 @@ typedef struct { uint32_t opc2:3; /* Op-code 2 */ uint32_t coproc:4; /* Coprocessor */ uint32_t rxf:4; /* RXF */ -} mrt32_t; +} THUMB_INSN32_ALIGN mrt32_t; #define OP_MRT32 0x0010ee00 static __THUMB_INLINE__ void arm_mrt32(void **code, int c, int l, int crn, int rxf, int crm, int coproc, int opc1, int opc2) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; mrt32_t *op = *(mrt32_t **) code; *p = OP_MRT32; op->crm = crm; @@ -1414,7 +1427,7 @@ typedef struct { uint32_t type:7; /* '1111100'b */ uint32_t imm:12; /* +/- immediate */ uint32_t rt:4; /* Register t */ -} lspr32_t; +} THUMB_INSN32_ALIGN lspr32_t; #define OP_LSPR32 0x0000f800 #define LDRPC_TEMPLATE 0xc000f8df @@ -1422,7 +1435,7 @@ typedef struct { static __THUMB_INLINE__ void arm_lspr32(void **code, int rt, int rn, int ls, int size, int up, int imm, int sign) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; lspr32_t *op = *(lspr32_t **) code; *p = OP_LSPR32; op->rt = rt; @@ -1451,7 +1464,7 @@ typedef struct { uint32_t prep:1; /* Pre/post selector */ uint32_t shift:1; /* Shift selector */ uint32_t rt:4; /* Register t */ -} lsrn32_t; +} THUMB_INSN32_ALIGN lsrn32_t; #define OP_LSRN32 0x0000f800 @@ -1459,7 +1472,7 @@ static __THUMB_INLINE__ void arm_lsrn32(void **code, int rt, int rn, int ls, int size, int imm, int sign, int idx, int priv) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; lsrn32_t *op = *(lsrn32_t **) code; *p = OP_LSRN32; op->rt = rt; @@ -1495,14 +1508,14 @@ typedef struct { uint32_t shift:2; /* Pre/post index */ uint32_t typeb:6; /* '000000'b */ uint32_t rt:4; /* Register t */ -} lsro32_t; +} THUMB_INSN32_ALIGN lsro32_t; #define OP_LSRO32 0x0000f800 static __THUMB_INLINE__ void arm_lsro32(void **code, int rt, int rn, int rm, int ls, int size, int sign, int shift) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; lsro32_t *op = *(lsro32_t **) code; *p = OP_LSRO32; op->rt = rt; @@ -1529,14 +1542,14 @@ typedef struct { uint32_t imm:8; /* Immediate */ uint32_t rt2d:4; /* Register t2 or d */ uint32_t rt:4; /* Register t */ -} lsd32_t; +} THUMB_INSN32_ALIGN lsd32_t; #define OP_LSD32 0x0000e840 static __THUMB_INLINE__ void arm_lsd32(void **code, int rt, int rt2d, int rn, int ls, int up, int prep) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; lsd32_t *op = *(lsd32_t **) code; *p = OP_LSD32; op->rt = rt; @@ -1558,14 +1571,14 @@ typedef struct { uint32_t imm:8; /* Immediate value */ uint32_t rd:4; /* Register d */ uint32_t rt:4; /* Register t */ -} lsxt32_t; +} THUMB_INSN32_ALIGN lsxt32_t; #define OP_LSXT32 0x0000e840 static __THUMB_INLINE__ void arm_lsxt32(void **code, int rd, int rt, int rn, int ls, int imm) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; lsxt32_t *op = *(lsxt32_t **) code; *p = OP_LSXT32; op->rd = rd; @@ -1591,14 +1604,14 @@ typedef struct { uint32_t sbz:1; /* '0'b */ uint32_t m:1; /* Load/Store Register 14 */ uint32_t p:1; /* Load PC */ -} lsm32_t; +} THUMB_INSN32_ALIGN lsm32_t; #define OP_LSM32 0x0000e800 static __THUMB_INLINE__ void arm_lsm32(void **code, int rn, int mask, int ls, int up, int wb) { - uint32_t *x = *(uint32_t **) code; + arminstr_t *x = *(arminstr_t **) code; lsm32_t *op = *(lsm32_t **) code; *x = OP_LSM32; op->rn = rn; @@ -1625,7 +1638,7 @@ typedef struct { uint32_t i1:1; /* Offset bit 19 */ uint32_t link:1; /* With link selector */ uint32_t typea:1; /* '1'b */ -} brl32_t; +} THUMB_INSN32_ALIGN brl32_t; #define OP_BRL32 0x9000f000 #define BL_TEMPLATE (OP_BRL32 | 0x40000000) @@ -1634,7 +1647,7 @@ typedef struct { static __THUMB_INLINE__ void arm_brl32(void **code, int offset, int link) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; brl32_t *op = *(brl32_t **) code; offset -= 4; int imm = offset >> 1; @@ -1663,14 +1676,14 @@ typedef struct { uint32_t i1:1; /* Offset bit 19 */ uint32_t link:1; /* With link selector */ uint32_t typeb:1; /* '1'b */ -} cbr32_t; +} THUMB_INSN32_ALIGN cbr32_t; #define OP_CBR32 0x8000f000 static __THUMB_INLINE__ void arm_cbr32(void **code, int cond, int offset) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; cbr32_t *op = *(cbr32_t **) code; int imm = (offset - 4) >> 1; *p = OP_CBR32; @@ -1700,7 +1713,7 @@ typedef struct { uint32_t size:1; /* Size */ uint32_t typeb:3; /* '101'b */ uint32_t opr1:4; /* Operand 1 */ -} fdp_t; +} THUMB_INSN32_ALIGN fdp_t; #define OP_FDP 0x0a00ee00 @@ -1712,7 +1725,7 @@ typedef struct { static __THUMB_INLINE__ void arm_fdp(void **code, int t, int opc1, int opc2, int opc3, int opc4, int opr1, int opr2, int size) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; fdp_t *op = *(fdp_t **) code; *p = OP_FDP; op->t = t; @@ -2042,7 +2055,7 @@ typedef struct { uint32_t size:1; /* Single/Double selector */ uint32_t typee:3; /* '101'B */ uint32_t vd:4; /* FP register m */ -} fcvt_t; +} THUMB_INSN32_ALIGN fcvt_t; #define OP_VFCVT 0x0a40eebc @@ -2214,14 +2227,14 @@ typedef struct { uint32_t vrmhi:1; /* Hi-bit of FP register m */ uint32_t typed:6; /* '101100'b */ uint32_t vrt:4; /* FP register t */ -} fmovd_t; +} THUMB_INSN32_ALIGN fmovd_t; #define OP_FVMOVD 0x0b10ec40 static __THUMB_INLINE__ void arm_fmovd(void **code, int vrt, int vrt2, int vrm, int opr) { - uint32_t *x = *(uint32_t **) code; + arminstr_t *x = *(arminstr_t **) code; fmovd_t *op = *(fmovd_t **) code; *x = OP_FVMOVD; vrm >>= 1; @@ -2247,14 +2260,14 @@ typedef struct { uint32_t rnlo:1; /* Lo-bit of [FP|core] register n */ uint32_t typeb:4; /* '1010'b */ uint32_t rt:4; /* [FP|core] Register t */ -} fmovs_t; +} THUMB_INSN32_ALIGN fmovs_t; #define OP_FVMOVS 0x0a10ee00 static __THUMB_INLINE__ void arm_fmovs(void **code, int rt, int rn, int opr) { - uint32_t *x = *(uint32_t **) code; + arminstr_t *x = *(arminstr_t **) code; fmovs_t *op = *(fmovs_t **) code; *x = OP_FVMOVS; op->op = opr; @@ -2282,14 +2295,14 @@ typedef struct { uint32_t size:1; /* Double/single selector */ uint32_t typeb:3; /* '101'b */ uint32_t vrd:4; /* FP register d */ -} fpls_t; +} THUMB_INSN32_ALIGN fpls_t; #define OP_VFPLD 0x0a00ed00 static __THUMB_INLINE__ void arm_fpls(void **code, int vrd, int rn, int count, int size, int ls, int p, int w) { - uint32_t *x = *(uint32_t **) code; + arminstr_t *x = *(arminstr_t **) code; fpls_t *op = *(fpls_t **) code; *x = OP_VFPLD; op->size = size; @@ -2324,14 +2337,14 @@ typedef struct { uint32_t type:16; /* '1110111011110001'b */ uint32_t typea:12; /* '101000010000'b */ uint32_t rt:4; /* Register t */ -} fvmrs_t; +} THUMB_INSN32_ALIGN fvmrs_t; #define OP_FVMRS 0x0a10eef1 static __THUMB_INLINE__ void arm_fvmrs(void **code, int rt) { - uint32_t *x = *(uint32_t **) code; + arminstr_t *x = *(arminstr_t **) code; fvmrs_t *op = *(fvmrs_t **) code; *x = OP_FVMRS; op->rt = rt; @@ -2347,14 +2360,14 @@ typedef struct { uint32_t type:16; /* '1110111011100001'b */ uint32_t typea:12; /* '101000010000'b */ uint32_t rt:4; /* Register t */ -} fvmsr_t; +} THUMB_INSN32_ALIGN fvmsr_t; #define OP_FVMSR 0x0a10eee1 static __THUMB_INLINE__ void arm_fvmsr(void **code, int rt) { - uint32_t *x = *(uint32_t **) code; + arminstr_t *x = *(arminstr_t **) code; fvmsr_t *op = *(fvmsr_t **) code; *x = OP_FVMSR; op->rt = rt; @@ -2374,7 +2387,7 @@ typedef struct { uint32_t size:1; /* Single/Double selector */ uint32_t typeb:3; /* '101'b */ uint32_t vrd:4; /* FP register d */ -} fldr_t; +} THUMB_INSN32_ALIGN fldr_t; #define OP_FLDR 0x0a00ed10 @@ -2382,7 +2395,7 @@ static __THUMB_INLINE__ void arm_fldr(void **code, int vrd, int rn, int size, int offset) { uintptr_t loc = ((uintptr_t) *code % 4); - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; fldr_t *op = *(fldr_t **) code; *p = OP_FLDR; @@ -2423,7 +2436,7 @@ typedef struct { uint32_t size:1; /* Single/Double selector */ uint32_t typeb:3; /* '101'b */ uint32_t vrd:4; /* FP register d */ -} fstr_t; +} THUMB_INSN32_ALIGN fstr_t; #define OP_FSTR 0x0a00ed00 @@ -2431,7 +2444,7 @@ static __THUMB_INLINE__ void arm_fstr(void **code, int vrd, int rn, int size, int offset) { uintptr_t loc = ((uintptr_t) *code % 4); - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; fstr_t *op = *(fstr_t **) code; *p = OP_FSTR; @@ -2513,14 +2526,14 @@ typedef struct { uint32_t size:1; /* Size */ uint32_t typea:3; /* '101'b */ uint32_t vrd:4; /* Register d */ -} fpush_t; +} THUMB_INSN32_ALIGN fpush_t; #define OP_FPUSH 0x0a00ed2d static __THUMB_INLINE__ void arm_vpush(void **code, int vrd, int count, int size) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; fpush_t *op = *(fpush_t **) code; *p = OP_FPUSH; @@ -2553,14 +2566,14 @@ typedef struct { uint32_t size:1; /* Size */ uint32_t typea:3; /* '101'b */ uint32_t vrd:4; /* Register d */ -} fpop_t; +} THUMB_INSN32_ALIGN fpop_t; #define OP_FPOP 0x0a00ecbd static __THUMB_INLINE__ void arm_vpop(void **code, int vrd, int count, int size) { - uint32_t *p = *(uint32_t **) code; + arminstr_t *p = *(arminstr_t **) code; fpop_t *op = *(fpop_t **) code; *p = OP_FPOP; @@ -2590,14 +2603,14 @@ typedef struct { uint32_t op1:3; /* Operation part 1 */ uint32_t op2:5; /* Operation part 2 */ uint32_t typea:4; /* Operations specific */ -} hint32_t; +} THUMB_INSN32_ALIGN hint32_t; #define OP_NOP32 0x8000f3af static __THUMB_INLINE__ void arm_hint32(void **code, int opr) { - uint32_t *x = *(uint32_t **) code; + arminstr_t *x = *(arminstr_t **) code; hint32_t *op = *(hint32_t **) code; *x = opr; *code = (void *)((uintptr_t) *code + sizeof(*op)); @@ -2612,14 +2625,14 @@ typedef struct { uint32_t option:4; /* Option */ uint32_t op:4; /* OP - e.g. 5 = DMB */ uint32_t typea:8; /* Operations specific */ -} mci32_t; +} THUMB_INSN32_ALIGN mci32_t; #define OP_DMB 0x8f50f3bf static __THUMB_INLINE__ void arm_mci(void **code, int opr, int option) { - uint32_t *x = *(uint32_t **) code; + arminstr_t *x = *(arminstr_t **) code; *x = opr; mci32_t *op = *(mci32_t **) code; op->option = option; @@ -2642,7 +2655,7 @@ typedef struct { static __THUMB_INLINE__ void arm_mrs(void **code, int rd, int sr) { - uint32_t *x = *(uint32_t **) code; + arminstr_t *x = *(arminstr_t **) code; mrs32_t *op = *(mrs32_t **) code; *x = OP_MRS; op->sr = sr; @@ -2667,7 +2680,7 @@ typedef struct { static __THUMB_INLINE__ void arm_msr(void **code, int rn, int sr, int fm) { - uint32_t *x = *(uint32_t **) code; + arminstr_t *x = *(arminstr_t **) code; msr32_t *op = *(msr32_t **) code; *x = OP_MSR; op->sr = sr; @@ -2679,7 +2692,7 @@ arm_msr(void **code, int rn, int sr, int fm) static __THUMB_INLINE__ void arm_msr32(void **code, int sr, int rn) { - uint32_t *x = *(uint32_t **) code; + arminstr_t *x = *(arminstr_t **) code; msr32_t *op = *(msr32_t **) code; *x = OP_MSR; op->sr = sr; @@ -4341,7 +4354,7 @@ arm_umull(void **code, int rdhi, int rdlo, int rm, int rs) do { \ ARM_LDR_IMM(p, r, ARMREG_PC, 6); \ ARM_BX(p, r); \ - *(guint32 *)p = (guint32) addr; \ + *(arminstr_t *)p = (guint32) addr; \ p += 4; \ } while (0) @@ -4349,9 +4362,9 @@ arm_umull(void **code, int rdhi, int rdlo, int rm, int rs) do { \ ARM_ADR_IMM(p, r1, 4); \ ARM_LDR_IMM(p, ARMREG_PC, ARMREG_PC, 4);\ - *(guint32 *)p = (guint32) arg; \ + *(arminstr_t *)p = (guint32) arg; \ p += 4; \ - *(guint32 *)p = (guint32) addr; \ + *(arminstr_t *)p = (guint32) addr; \ p += 4; \ } while (0) @@ -4359,9 +4372,9 @@ arm_umull(void **code, int rdhi, int rdlo, int rm, int rs) do { \ ARM_LDR_IMM(p, r1, ARMREG_PC, 4); \ ARM_LDR_IMM(p, ARMREG_PC, ARMREG_PC, 4);\ - *(guint32 *)p = (guint32) arg; \ + *(arminstr_t *)p = (guint32) arg; \ p += 4; \ - *(guint32 *)p = (guint32) addr; \ + *(arminstr_t *)p = (guint32) addr; \ p += 4; \ } while (0) @@ -4370,9 +4383,9 @@ arm_umull(void **code, int rdhi, int rdlo, int rm, int rs) ARM_LDR_IMM(p, r1, ARMREG_PC, 2 * sizeof(gpointer)); \ ARM_LDR_IMM(p, ARMREG_LR, ARMREG_PC, ARMDISP_LDRPC); \ p = emit_bx(p, r1); \ - *(guint32 *)p = (guint32) arg; \ + *(arminstr_t *)p = (guint32) arg; \ p += 4; \ - *(guint32 *)p = (guint32) addr; \ + *(arminstr_t *)p = (guint32) addr; \ p += 4; \ } while (0) diff --git a/src/mono/mono/mini/mini-arm.c b/src/mono/mono/mini/mini-arm.c index ed43eeff44d6f0..891e9560464d26 100644 --- a/src/mono/mono/mini/mini-arm.c +++ b/src/mono/mono/mini/mini-arm.c @@ -3785,7 +3785,7 @@ emit_thunk (guint8 *code, gconstpointer target) arm_ldr_lit ((void **)&code, ARMREG_IP, 4); arm_bxis16 ((void **)&code, ARMREG_IP, 0); arm_nop16 ((void **)&code, OP_NOP16); - *(guint32*)code = (guint32)(gsize)target | 1; + *(arminstr_t *)code = (guint32)(gsize)target | 1; code += 4; #else ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0); @@ -3793,7 +3793,7 @@ emit_thunk (guint8 *code, gconstpointer target) ARM_BX (code, ARMREG_IP); else ARM_MOV_REG_REG (code, ARMREG_PC, ARMREG_IP); - *(guint32*)code = (guint32)(gsize)target; + *(arminstr_t *)code = (guint32)(gsize)target; code += 4; #endif mono_arch_flush_icache (p, GPTRDIFF_TO_INT (code - p)); @@ -3826,7 +3826,7 @@ handle_thunk (MonoCompile *cfg, guchar *code, const guchar *target) g_assert_not_reached (); } - g_assert (*(guint32*)thunks == 0); + g_assert (*(arminstr_t *)thunks == 0); emit_thunk (thunks, target); arm_patch (code, thunks); @@ -3851,11 +3851,11 @@ handle_thunk (MonoCompile *cfg, guchar *code, const guchar *target) target_thunk = orig_target; } else { for (p = thunks; p < thunks + thunks_size; p += THUNK_SIZE) { - if (((guint32*)p) [0] == 0) { + if (((arminstr_t *)p) [0] == 0) { /* Free entry */ target_thunk = p; break; - } else if ((((guint32*)p) [2] & ~(guint32)1) == ((guint32)(gsize)target & ~(guint32)1)) { + } else if ((((arminstr_t *)p) [2] & ~(guint32)1) == ((guint32)(gsize)target & ~(guint32)1)) { /* Thunk already points to target */ target_thunk = p; break; @@ -3895,7 +3895,7 @@ arm_patch_general (MonoCompile *cfg, guchar *code, const guchar *target) } } #endif - guint32 *code32 = (guint32*)code; + arminstr_t *code32 = (arminstr_t *)code; guint32 ins = *code32; guint32 prim = (ins >> 25) & 7; guint32 tval = GPOINTER_TO_UINT (target); @@ -3966,7 +3966,7 @@ arm_patch_general (MonoCompile *cfg, guchar *code, const guchar *target) guint32 imm12 = hw2 & 0xFFF; /* PC = Align(instruction_address, 4) + 4 */ guint8 *pc = (guint8 *)(((gsize)code & ~(gsize)3) + 4); - guint32 *literal = (guint32 *)(pc + imm12); + arminstr_t *literal = (arminstr_t *)(pc + imm12); *literal = tval; return; } @@ -5753,9 +5753,9 @@ mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb) if (cfg->compile_aot) { ARM_FLDD (code, ins->dreg, ARMREG_PC, 0); ARM_B (code, 1); - *(guint32*)code = ((guint32*)(ins->inst_p0))[0]; + *(arminstr_t *)code = ((guint32*)(ins->inst_p0))[0]; code += 4; - *(guint32*)code = ((guint32*)(ins->inst_p0))[1]; + *(arminstr_t *)code = ((guint32*)(ins->inst_p0))[1]; code += 4; } else { /* FIXME: we can optimize the imm load by dealing with part of @@ -5769,7 +5769,7 @@ mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb) if (cfg->compile_aot) { ARM_FLDS (code, ins->dreg, ARMREG_PC, 0); ARM_B (code, 0); - *(guint32*)code = ((guint32*)(ins->inst_p0))[0]; + *(arminstr_t *)code = ((guint32*)(ins->inst_p0))[0]; code += 4; } else { code = mono_arm_emit_load_imm (code, ARMREG_LR, (guint32)(gsize)ins->inst_p0); @@ -6062,9 +6062,9 @@ mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb) ARM_ABSD (code, vfp_scratch2, ins->sreg1); ARM_FLDD (code, vfp_scratch1, ARMREG_PC, 0); ARM_B (code, 1); - *(guint32*)code = 0xffffffff; + *(arminstr_t *)code = 0xffffffff; code += 4; - *(guint32*)code = 0x7fefffff; + *(arminstr_t *)code = 0x7fefffff; code += 4; ARM_CMPD (code, vfp_scratch2, vfp_scratch1); ARM_FMSTAT (code); @@ -7058,7 +7058,7 @@ mono_arch_emit_exceptions (MonoCompile *cfg) patch_info->ip.i = GPTRDIFF_TO_INT (code - cfg->native_code); ARM_BL (code, 0); cfg->thunk_area += THUNK_SIZE; - *(guint32*)(gpointer)code = m_class_get_type_token (exc_class) - MONO_TOKEN_TYPE_DEF; + *(arminstr_t *)(gpointer)code = m_class_get_type_token (exc_class) - MONO_TOKEN_TYPE_DEF; code += 4; break; } @@ -7174,7 +7174,7 @@ mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoIMTCheckItem **imt_entri int size, i; arminstr_t *code, *start; gboolean large_offsets = FALSE; - guint32 **constant_pool_starts; + arminstr_t **constant_pool_starts; arminstr_t *vtable_target = NULL; int extra_space = 0; #ifdef ENABLE_WRONG_METHOD_CHECK @@ -7184,7 +7184,7 @@ mono_arch_build_imt_trampoline (MonoVTable *vtable, MonoIMTCheckItem **imt_entri MonoMemoryManager *mem_manager = m_class_get_mem_manager (vtable->klass); size = BASE_SIZE; - constant_pool_starts = g_new0 (guint32*, count); + constant_pool_starts = g_new0 (arminstr_t *, count); for (i = 0; i < count; ++i) { MonoIMTCheckItem *item = imt_entries [i]; diff --git a/src/mono/mono/mini/tramp-arm.c b/src/mono/mono/mini/tramp-arm.c index f373809c2b2545..60cc913c41428e 100644 --- a/src/mono/mono/mini/tramp-arm.c +++ b/src/mono/mono/mini/tramp-arm.c @@ -67,7 +67,7 @@ mono_arch_patch_callsite (guint8 *method_start, guint8 *code_ptr, guint8 *addr) guint16 ldr_hw2 = *(guint16 *)(ldr + 2); guint32 imm12 = ldr_hw2 & 0xFFF; guint8 *pc = (guint8 *)(((gsize)ldr & ~(gsize)3) + 4); - guint32 *literal = (guint32 *)(pc + imm12); + arminstr_t *literal = (arminstr_t *)(pc + imm12); *literal = (guint32)(gsize)addr; mono_arch_flush_icache ((guint8 *)literal, 4); } @@ -76,7 +76,7 @@ mono_arch_patch_callsite (guint8 *method_start, guint8 *code_ptr, guint8 *addr) g_assert_not_reached (); #else - guint32 *code = (guint32*)code_ptr; + arminstr_t *code = (arminstr_t *)code_ptr; /* This is the 'bl' or the 'mov pc' instruction */ --code; @@ -108,9 +108,9 @@ mono_arch_patch_plt_entry (guint8 *code, gpointer *got, host_mgreg_t *regs, guin guint8 *jump_entry; /* Patch the jump table entry used by the plt entry */ - if (*(guint32*)code == 0xe59fc000) { + if (*(arminstr_t *)code == 0xe59fc000) { /* ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0); */ - guint32 offset = ((guint32*)code)[2]; + guint32 offset = ((arminstr_t *)code)[2]; jump_entry = code + offset + 12; } else if (*(guint16*)(code - 4) == 0xf8df) { @@ -121,7 +121,7 @@ mono_arch_patch_plt_entry (guint8 *code, gpointer *got, host_mgreg_t *regs, guin guint32 offset; code -= 4; - offset = *(guint32*)(code + 12); + offset = *(arminstr_t *)(code + 12); jump_entry = code + offset + 8; } else { g_assert_not_reached (); @@ -487,7 +487,7 @@ gpointer mono_arch_create_specific_trampoline (gpointer arg1, MonoTrampolineType tramp_type, MonoMemoryManager *mem_manager, guint32 *code_len) { guint8 *code, *buf, *tramp; - guint32 *constants; + arminstr_t *constants; guint32 short_branch = FALSE; guint32 size = SPEC_TRAMP_SIZE; @@ -520,10 +520,10 @@ mono_arch_create_specific_trampoline (gpointer arg1, MonoTrampolineType tramp_ty ARM_PUSH (code, 0x5fff); if (short_branch) { #ifdef __thumb2__ - constants = (guint32*)code; + constants = (arminstr_t *)code; constants [0] = short_branch; #else - constants = (guint32*)code; + constants = (arminstr_t *)code; constants [0] = short_branch | (1 << 24); #endif constants [1] = GPOINTER_TO_UINT (arg1); @@ -574,7 +574,7 @@ mono_arch_get_unbox_trampoline (MonoMethod *m, gpointer addr) ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 4); ARM_ADD_REG_IMM8 (code, ARMREG_R0, ARMREG_R0, MONO_ABI_SIZEOF (MonoObject)); code = emit_bx (code, ARMREG_IP); - *(guint32*)code = (guint32)(gsize)addr; + *(arminstr_t *)code = (guint32)(gsize)addr; code += 4; #endif mono_arch_flush_icache (start, GPTRDIFF_TO_INT (code - start)); @@ -602,9 +602,9 @@ mono_arch_get_static_rgctx_trampoline (MonoMemoryManager *mem_manager, gpointer #else ARM_LDR_IMM (code, MONO_ARCH_RGCTX_REG, ARMREG_PC, 0); ARM_LDR_IMM (code, ARMREG_PC, ARMREG_PC, 0); - *(guint32*)code = (guint32)(gsize)arg; + *(arminstr_t *)code = (guint32)(gsize)arg; code += 4; - *(guint32*)code = (guint32)(gsize)addr; + *(arminstr_t *)code = (guint32)(gsize)addr; code += 4; #endif @@ -635,9 +635,9 @@ mono_arch_get_ftnptr_arg_trampoline (MonoMemoryManager *mem_manager, gpointer ar #else ARM_LDR_IMM (code, ARMREG_IP, ARMREG_PC, 0); ARM_LDR_IMM (code, ARMREG_PC, ARMREG_PC, 0); - *(guint32*)code = (guint32)(gsize)arg; + *(arminstr_t *)code = (guint32)(gsize)arg; code += 4; - *(guint32*)code = (guint32)(gsize)addr; + *(arminstr_t *)code = (guint32)(gsize)addr; code += 4; #endif @@ -1129,7 +1129,7 @@ mono_arch_get_native_to_interp_trampoline (MonoTrampInfo **info) guint8* mono_arch_get_call_target (guint8 *code) { - guint32 ins = ((guint32*)code) [-1]; + guint32 ins = ((arminstr_t *)code) [-1]; /* Should be a 'bl' or a 'b' */ if (((ins >> 25) & 0x7) == 0x5) { @@ -1146,7 +1146,7 @@ guint32 mono_arch_get_plt_info_offset (guint8 *plt_entry, host_mgreg_t *regs, guint8 *code) { /* The offset is stored as the 4th word of the plt entry */ - return ((guint32*)plt_entry) [3]; + return ((arminstr_t *)plt_entry) [3]; } /*