diff --git a/.gitignore b/.gitignore index 6e17576..bdf7a45 100644 --- a/.gitignore +++ b/.gitignore @@ -21,3 +21,5 @@ __pycache__/ *.swo /.cex /cecmiter.aig + +HANDOFF.md diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 1daaff5..fd36b41 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -4,7 +4,7 @@ RustSys is one of the tools of RustEDA, a suite of electronic design automation share their core crates and a disk workspace. This file holds the rules that every change follows: the eight engineering rules of RustEDA, the rules of this repository, ownership and hand-over between work items, and the checks to run before sending a change. The phases of the suite and -their work items are in the [roadmap](docs/roadmap.md). +their work items are in the [scope](https://lab-emi.github.io/RustEDA/verification/). Instruction files for coding agents, such as `AGENTS.md`, stay local and are never committed; this file is the tracked statement of the rules. @@ -193,7 +193,7 @@ the lab checks them: ## Ownership and hand-over -Work is divided into work items (see the [roadmap](docs/roadmap.md)), each with its specification, +Work is divided into work items (see the [scope](https://lab-emi.github.io/RustEDA/verification/)), each with its specification, its acceptance criteria and the paths it owns. - Every path has one owner at a time. A work item edits only the paths it owns, plus minimal diff --git a/README.md b/README.md index 73a0472..0c7422f 100644 --- a/README.md +++ b/README.md @@ -1,38 +1,24 @@

- RustSys — a RustEDA tool + RustSys

-# RustSys +

Synthesis for the next design iteration.

-**Ultrafast Verilog/SystemVerilog synthesis. Built for terminals and agents.** - -[![CI](https://github.com/lab-emi/RustSys/actions/workflows/ci.yml/badge.svg?branch=main)](https://github.com/lab-emi/RustSys/actions/workflows/ci.yml) -[![License: Apache-2.0](https://img.shields.io/badge/license-Apache--2.0-blue.svg)](LICENSE) -[![Rust 1.97.1](https://img.shields.io/badge/rust-1.97.1-orange.svg?logo=rust)](rust-toolchain.toml) -[![Documentation](https://img.shields.io/badge/docs-online-57D6BE)](https://lab-emi.github.io/RustSys/) - -RustSys is a high-performance Verilog/SystemVerilog synthesizer written in Rust. -Map RTL to standard cells, export gate-level Verilog and JSON reports, and check -equivalence from your terminal, CI pipeline, or coding agent. Part of the **RustEDA** family. +

+ Documentation · + RustEDA · + Benchmarks · + Apache-2.0 +

- Verilog source flows through RustSys synthesis into connected standard-cell gates. + RustSys turns RTL into mapped netlists with bounded synthesis, technology mapping and independently checked equivalence -[Static banner](docs/assets/rustsys-banner.svg) · [Get started](#quick-start) · -[Agent guide](docs/guide/agents.md) · [Documentation](https://lab-emi.github.io/RustSys/) · [Benchmarks](#benchmarks) - - - -- **High performance:** 1.50×–42.46× faster than pinned Yosys 0.67 on the measured five-design, three-PDK suite, with 16 physical host cores per tool. -- **Easy to script:** result-only stdout, coded diagnostics on stderr, JSON output, fixed exit statuses. -- **Easy to resume:** recorded commands, input hashes, artifacts, and event logs; query reports as JSON or TSV. -- **Safe to coordinate:** daemonless disk workspaces, immutable revisions, and explicit `--base-rev` conflict checks. -- **Built to check:** an independent synthesis checker, bounded proof work, and external open-source LEC evidence. +RustSys turns RTL into mapped netlists with bounded synthesis, technology mapping and independently checked equivalence. -> **Development preview:** version 0.1.0 is unreleased and is not on crates.io. Build from this -> repository. Linux is tested in CI; other platforms are not tested. +Part of **[RustEDA](https://github.com/lab-emi/RustEDA)**, infrastructure for chip-design recursive self-improvement. Native tools shorten the work between inference steps; verified results guide the next iteration. ## Benchmarks @@ -71,7 +57,7 @@ Aggregate cgroup memory peaks remain in the complete receipts. † **Setup-Fmax is an OpenSTA estimate** at the TT corner with ideal clocks and no wire parasitics. SERV/EZ130 and OpenC910 loads exceed Liberty characterization limits; -these raw estimates do not establish achievable frequency. [Timing scope](https://lab-emi.github.io/RustSys/guide/performance/#interpret-the-timing-estimate). +these raw estimates do not establish achievable frequency. [Timing scope](https://lab-emi.github.io/RustEDA/modules/rustsys/guide/performance/#interpret-the-timing-estimate). Speedup = **Yosys time ÷ RustSys time**. All **30 distinct netlists pass arbitrary-state RTL LEC**, with no reset or input assumption added. @@ -79,7 +65,7 @@ arbitrary-state RTL LEC**, with no reset or input assumption added. [Current runtime audit, three-PDK refresh and LEC](verification/benchmarks/open-hardware/results/2026-10-23-gf180-runtime-audit/README.md) · [Historical Sky130/GF180: full 1/16-core results and LEC certificates](verification/benchmarks/open-hardware/results/2026-10-21-default-multicore/README.md) · [IHP/EZ130: 16-core results and LEC certificates](verification/benchmarks/open-hardware/results/2026-10-23-ez130/README.md) · -[Benchmark method](https://lab-emi.github.io/RustSys/guide/benchmarks/). +[Benchmark method](https://lab-emi.github.io/RustEDA/modules/rustsys/guide/benchmarks/). SERV/EZ130 uses **0.77% less cell area than Yosys**, with **3.55×** faster synthesis. The current runtime repair remeasures RustSys across all three PDKs and retains @@ -87,7 +73,7 @@ the pinned Yosys runs. All fifteen RustSys netlists are unchanged from the area fix; exact-byte LEC and timing reuse is explicit. EZ130 functional LEC follows the vendor’s nominal tie-cell Verilog models; the Liberty driver-type conflict and checked supplement are -[documented explicitly](https://lab-emi.github.io/RustSys/verification/pdk/#additional-ihp-sg13g2-benchmark-library). +[documented explicitly](https://lab-emi.github.io/RustEDA/modules/rustsys/verification/pdk/#additional-ihp-sg13g2-benchmark-library). @@ -241,7 +227,7 @@ of an existing workspace names the expected revision; a stale base fails with | Bounded work | Proof/search budgets report exhaustion as undecided; `unverified` evidence stays unverified. | [Agent integration recipes](docs/guide/agents.md) · [CLI reference](docs/reference/cli.md) · -[JSON and report contracts](docs/reference/reports.md) · [Agent documentation index](https://lab-emi.github.io/RustSys/llms.txt). +[JSON and report contracts](docs/reference/reports.md) · [Agent documentation index](https://lab-emi.github.io/RustEDA/modules/rustsys/llms.txt). ## Synthesis and verification @@ -271,12 +257,12 @@ modports, tri-state logic, `inout`, and dynamic types are among the current limi ## Documentation -The [documentation site](https://lab-emi.github.io/RustSys/) follows a task-based path from a first netlist to repeatable automation +The [documentation site](https://lab-emi.github.io/RustEDA/modules/rustsys/) follows a task-based path from a first netlist to repeatable automation and inspectable proof evidence. All pages also live in this repository. | Start here | Go deeper | |---|---| -| [Documentation home](https://lab-emi.github.io/RustSys/) | [Architecture and crate boundaries](docs/architecture/index.md) | +| [Documentation home](https://lab-emi.github.io/RustEDA/modules/rustsys/) | [Architecture and crate boundaries](docs/architecture/index.md) | | [Install and run your first design](docs/guide/quickstart.md) | [Synthesis specifications](docs/specs/synth/README.md) | | [Automate with scripts and agents](docs/guide/agents.md) | [Workspace and JSON protocol](docs/specs/workspace/README.md) | | [Check equivalence](docs/guide/checking.md) | [Verification evidence and limitations](docs/verification/index.md) | diff --git a/docs/_tools/generate_brand.py b/docs/_tools/generate_brand.py index 694f4db..222cbd2 100644 --- a/docs/_tools/generate_brand.py +++ b/docs/_tools/generate_brand.py @@ -1,264 +1,11 @@ #!/usr/bin/env python3 # SPDX-License-Identifier: Apache-2.0 -# SPDX-FileCopyrightText: 2026 RustSys contributors -"""Render the original RustEDA signal-forge identity and bounded GIF animation. - -Documentation-only dependencies: docs/brand/requirements.txt. No Rust runtime uses -this generator. All frames come from native SVG geometry defined in this file. -""" - -from __future__ import annotations - -import argparse -import hashlib -import html -import io -import json +"""The canonical family renderer lives in the RustEDA superproject.""" from pathlib import Path +import runpy -import cairosvg -from PIL import Image - -ROOT = Path(__file__).resolve().parents[2] -ASSETS = ROOT / "docs" / "assets" -INK, PANEL, BORDER = "#101923", "#17242F", "#304451" -COPPER, TEAL, PAPER, MUTED = "#EF8B52", "#57D6BE", "#F4F1E9", "#A1B0BA" -WIDTH, HEIGHT, FRAMES, DURATION_MS = 1200, 400, 84, 100 -MAX_PIXELS = 1200 * 400 -MAX_FRAMES = 96 -MAX_GIF_BYTES = 1024 * 1024 - - -def text(x: float, y: float, value: str, size: int = 16, fill: str = PAPER, - weight: int = 400, mono: bool = False, **attrs: object) -> str: - extra = " ".join(f'{key.replace("_", "-")}="{value}"' for key, value in attrs.items()) - family = "DejaVu Sans Mono,monospace" if mono else "DejaVu Sans,sans-serif" - return (f'{html.escape(value)}') - - -def svg(width: int, height: int, body: str, title: str, description: str) -> str: - return (f'' - f'{html.escape(title)}' - f'{html.escape(description)}{body}\n') - - -def mark(tool: str = "rustsys") -> str: - """A shared terminal/chip frame surrounding a tool-specific signal glyph.""" - body = f'' - body += (f'' - f'' - f'') - if tool == "rustsys": - body += (f'' - f'' - f'') - else: - body += (f'' - f'') - body += '' - if tool != "rustsys": - body += f'' - else: - body += f'' - body += f'' - return body - - -def wordmark(tool: str, subtitle: str) -> str: - body = f'' - body += f'{mark(tool.lower())}' - body += text(180, 89, tool, 58, weight=700) - body += text(184, 127, subtitle, 19, MUTED) - return svg(760, 176, body, f"{tool} wordmark", subtitle) - - -def wire(path: str, active: bool = False, copper: bool = False, width: int = 2) -> str: - return (f'') - - -def pulse(x1: float, y1: float, x2: float, y2: float, progress: float, color: str) -> str: - if not 0 <= progress <= 1: - return "" - x, y = x1 + (x2 - x1) * progress, y1 + (y2 - y1) * progress - return (f'' - f'') - - -def banner(frame: int) -> str: - """An 8.4-second loop: read RTL, reduce logic, map gates, propagate a pulse.""" - t = frame / FRAMES - phase = min(3, int(t * 4)) - active_labels = ["READ RTL", "OPTIMIZE", "MAP CELLS", "WRITE NETLIST"] - body = f'' - # A very quiet circuit-board grid; no photographic or external assets. - body += '' - for x in range(24, WIDTH, 24): - for y in range(96, 336, 24): - body += f'' - body += '' - body += f'{mark()}' - body += text(98, 57, "RustSys", 29, weight=700) - body += text(1164, 43, "VERILOG → GATE-LEVEL NETLIST", 13, MUTED, - weight=700, text_anchor="end", letter_spacing="1") - body += text(1164, 66, "CLI first. Ready for agents.", 14, TEAL, text_anchor="end") - - cards = [(32, 326, "01", "RTL / VERILOG"), - (438, 278, "02", "SYNTHESIZE"), - (796, 372, "03", "GATE-LEVEL NETLIST")] - for x, width, number, label in cards: - body += (f'') - body += text(x + 18, 126, number, 11, COPPER, mono=True) - body += text(x + 49, 126, label, 12, MUTED, weight=700, letter_spacing=".8") - - # Actual Verilog: a clock-enabled eight-bit AND result register. - code = [("module enabled_and (", PAPER), - (" input clk, en,", MUTED), - (" input [7:0] a, b,", MUTED), - (" output reg [7:0] q", MUTED), - (");", PAPER), - (" always @(posedge clk)", COPPER), - (" if (en) q <= a & b;", TEAL), - ("endmodule", PAPER)] - revealed = min(len(code), 1 + int(t * 33)) - for i, (line, color) in enumerate(code): - opacity = "1" if i < revealed else ".18" - body += text(49, 153 + i * 20, line, 13, color, mono=True, opacity=opacity) - if t < .21: - row = max(0, revealed - 1) - body += f'' - - # Flow arrows are animated, while the pipeline stays understandable in frame 0. - for start, end, offset in [(367, 428, .05), (725, 786, .33)]: - body += wire(f'M{start} 207H{end - 8}', active=True, copper=start < 500) - body += f'' - body += pulse(start, 207, end - 10, 207, ((t - offset) * 4) % 1, - COPPER if start < 500 else TEAL) - - # Bounded optimization graph. A few nodes settle into a compact gate cone. - nodes = [(469, 174), (469, 236), (508, 148), (508, 205), - (508, 269), (555, 174), (555, 236), (605, 205), (654, 205)] - edges = [(0, 3), (1, 3), (2, 5), (3, 5), (3, 6), (4, 6), (5, 7), (6, 7), (7, 8)] - energized = t >= .22 - for i, (a, b) in enumerate(edges): - xa, ya = nodes[a] - xb, yb = nodes[b] - body += wire(f'M{xa} {ya}L{xb} {yb}', energized and (i + frame // 4) % 3 != 0) - # The two peripheral branches visibly dissolve during the optimize phase. - redundant_opacity = .17 if t >= .38 else .8 - for i, (x, y) in enumerate(nodes): - fade = redundant_opacity if i in (2, 4) else 1 - fill = TEAL if energized and (i + frame // 3) % 4 == 0 else PANEL - body += f'' - body += text(577, 296, active_labels[phase], 11, TEAL, weight=700, - text_anchor="middle", letter_spacing="1.5") - - # Exact schematic: a,b -> AND -> MUX -> DFF, with q feedback and en select. - active = t >= .51 - body += text(815, 170, "a", 11, MUTED, mono=True) - body += text(815, 213, "b", 11, MUTED, mono=True) - body += text(815, 145, "en", 10, MUTED, mono=True) - body += text(815, 264, "clk", 11, MUTED, mono=True) - body += wire('M840 166H865M840 208H865', active, copper=True) - body += (f'') - body += text(879, 193, "&", 17, PAPER, mono=True) - body += text(884, 242, "AND × 8", 10, MUTED, mono=True, text_anchor="middle") - body += wire('M908 187H922', active) - body += f'' - body += text(930, 199, "M", 10, MUTED, mono=True) - body += wire('M840 141H934V149', active) - body += wire('M947 193H990M840 259H976V231H990', active) - body += f'' - body += text(1001, 199, "D", 12, PAPER, mono=True) - body += text(1041, 199, "Q", 12, PAPER, mono=True) - body += f'' - body += text(1027, 158, "DFF × 8", 10, MUTED, mono=True, text_anchor="middle") - body += wire('M1063 194H1138M1110 194V282H912V213H922', active) - body += f'' - body += text(1143, 199, "q", 11, TEAL, mono=True) - body += text(980, 304, "Liberty cell library", 10, MUTED, text_anchor="middle") - if active: - body += pulse(1065, 194, 1137, 194, ((t - .51) * 6) % 1, TEAL) - body += pulse(841, 259, 974, 259, ((t - .51) * 6) % 1, COPPER) - if (frame // 3) % 2 == 0: - body += '' - - body += f'' - body += text(48, 361, "$", 14, TEAL, mono=True) - body += text(68, 361, "rustsys synth --top enabled_and --lib cells.lib --out gates.v enabled_and.v", 13, PAPER, mono=True) - body += text(1151, 361, "RTL → gates", 12, COPPER, mono=True, text_anchor="end") - return svg(WIDTH, HEIGHT, body, "RustSys: Verilog to gate-level netlist", - "A clock-enabled eight-bit AND in Verilog maps to an AND, feedback multiplexer and flip-flop bank. " - "Animated pulses describe data flow; this is an illustration, not a run or proof result.") - - -def raster(source: str) -> Image.Image: - png = cairosvg.svg2png(bytestring=source.encode(), output_width=WIDTH, - output_height=HEIGHT) - return Image.open(io.BytesIO(png)).convert("RGB") - - -def main() -> None: - parser = argparse.ArgumentParser(description=__doc__) - parser.add_argument("--static-only", action="store_true", help="Skip rendering the GIF and contact sheet") - args = parser.parse_args() - if WIDTH * HEIGHT > MAX_PIXELS or FRAMES > MAX_FRAMES: - raise SystemExit("ASSET_BUDGET_EXCEEDED: configured dimensions or frames exceed hard caps") - ASSETS.mkdir(parents=True, exist_ok=True) - entries = {} - for name, source in { - "rusteda-logo.svg": svg(256, 256, mark("rusteda"), "RustEDA signal-forge mark", - "A shared terminal and chip frame surrounding crossing copper and teal signals."), - "rustsys-logo.svg": svg(256, 256, mark(), "RustSys synthesis mark", - "Copper input signals enter a logic gate and emerge as a teal output signal."), - "favicon.svg": svg(256, 256, mark(), "RustSys", "RustSys logic synthesis mark."), - "rustsys-wordmark.svg": wordmark("RustSys", "From Verilog to standard cells."), - "rusteda-wordmark.svg": wordmark("RustEDA", "Tools that speak CLI."), - "rustsys-banner.svg": banner(65), - }.items(): - (ASSETS / name).write_text(source) - entries[name] = {"bytes": len(source.encode()), "sha256": hashlib.sha256(source.encode()).hexdigest()} - if not args.static_only: - # 84 indexed frames occupy 38.5 MiB. One RGB frame is 1.4 MiB; Cairo, - # quantization scratch and the contact sheet keep estimated RSS < 256 MiB. - frames = [] - samples = [] - palette = raster(banner(65)).quantize(colors=96, method=Image.Quantize.MEDIANCUT) - for frame in range(FRAMES): - image = raster(banner(frame)) - frames.append(image.quantize(palette=palette, dither=Image.Dither.NONE)) - if frame in (0, 21, 42, 65): - samples.append(image.resize((600, 200))) - output = ASSETS / "rustsys-banner.gif" - frames[0].save(output, save_all=True, append_images=frames[1:], duration=DURATION_MS, - loop=0, optimize=True, disposal=1) - if output.stat().st_size > MAX_GIF_BYTES: - raise SystemExit("ASSET_BUDGET_EXCEEDED: GIF exceeds 1 MiB; reduce frame count or palette") - # QA output is kept in .work rather than distributed with the docs. - qa = ROOT / ".work" / "brand" - qa.mkdir(parents=True, exist_ok=True) - contact = Image.new("RGB", (1200, 400), INK) - for index, sample in enumerate(samples): - contact.paste(sample, ((index % 2) * 600, (index // 2) * 200)) - contact.save(qa / "rustsys-banner-contact-sheet.png") - raster(banner(65)).save(qa / "rustsys-banner-poster.png") - with Image.open(output) as gif: - entries[output.name] = { - "bytes": output.stat().st_size, - "sha256": hashlib.sha256(output.read_bytes()).hexdigest(), - "width": gif.width, "height": gif.height, "frames": gif.n_frames, - "duration_ms": sum((gif.seek(i), gif.info.get("duration", 0))[1] - for i in range(gif.n_frames)), - "loop": gif.info.get("loop"), - } - (qa / "assets-manifest.json").write_text(json.dumps(entries, indent=2) + "\n") - print(json.dumps(entries, indent=2)) - - -if __name__ == "__main__": - main() +root = Path(__file__).resolve().parents[4] +renderer = root / "scripts/generate_brand.py" +if not renderer.is_file(): + raise SystemExit("Use the recursive RustEDA checkout and run scripts/generate_brand.py") +runpy.run_path(str(renderer), run_name="__main__") diff --git a/docs/assets/favicon.svg b/docs/assets/favicon.svg index af10b5d..517721a 100644 --- a/docs/assets/favicon.svg +++ b/docs/assets/favicon.svg @@ -1 +1,5 @@ -RustSysRustSys logic synthesis mark. +RustSysSynthesis for the next design iteration + + + + diff --git a/docs/assets/rusteda-logo.svg b/docs/assets/rusteda-logo.svg index ff67666..7578555 100644 --- a/docs/assets/rusteda-logo.svg +++ b/docs/assets/rusteda-logo.svg @@ -1 +1,5 @@ -RustEDA signal-forge markA shared terminal and chip frame surrounding crossing copper and teal signals. +RustEDAThe RustEDA design feedback loop + + + + diff --git a/docs/assets/rusteda-wordmark.svg b/docs/assets/rusteda-wordmark.svg index c2fbb69..4cf98cc 100644 --- a/docs/assets/rusteda-wordmark.svg +++ b/docs/assets/rusteda-wordmark.svg @@ -1 +1,5 @@ -RustEDA wordmarkTools that speak CLI.RustEDATools that speak CLI. +RustEDAChip-design infrastructure for recursive self-improvement + + + +RustEDA diff --git a/docs/assets/rustsys-banner.gif b/docs/assets/rustsys-banner.gif index b7bd463..5323610 100644 Binary files a/docs/assets/rustsys-banner.gif and b/docs/assets/rustsys-banner.gif differ diff --git a/docs/assets/rustsys-banner.svg b/docs/assets/rustsys-banner.svg index 1d90afd..ba89c18 100644 --- a/docs/assets/rustsys-banner.svg +++ b/docs/assets/rustsys-banner.svg @@ -1 +1,15 @@ -RustSys: Verilog to gate-level netlistA clock-enabled eight-bit AND in Verilog maps to an AND, feedback multiplexer and flip-flop bank. Animated pulses describe data flow; this is an illustration, not a run or proof result.RustSysVERILOG → GATE-LEVEL NETLISTCLI first. Ready for agents.01RTL / VERILOG02SYNTHESIZE03GATE-LEVEL NETLISTmodule enabled_and ( input clk, en, input [7:0] a, b, output reg [7:0] q); always @(posedge clk) if (en) q <= a & b;endmoduleWRITE NETLISTabenclk&AND × 8MDQDFF × 8qLiberty cell library$rustsys synth --top enabled_and --lib cells.lib --out gates.v enabled_and.vRTL → gates +RustSysSynthesis for the next design iteration. RTL → mapped netlist + +RUSTEDA / DESIGN. MEASURE. IMPROVE. +RustSys +Synthesis for the next design iteration + +RTL → mapped netlist + + + + + + + + diff --git a/docs/assets/rustsys-logo.svg b/docs/assets/rustsys-logo.svg index 0b45029..517721a 100644 --- a/docs/assets/rustsys-logo.svg +++ b/docs/assets/rustsys-logo.svg @@ -1 +1,5 @@ -RustSys synthesis markCopper input signals enter a logic gate and emerge as a teal output signal. +RustSysSynthesis for the next design iteration + + + + diff --git a/docs/assets/rustsys-wordmark.svg b/docs/assets/rustsys-wordmark.svg index 94cb462..c1ced2e 100644 --- a/docs/assets/rustsys-wordmark.svg +++ b/docs/assets/rustsys-wordmark.svg @@ -1 +1,5 @@ -RustSys wordmarkFrom Verilog to standard cells.RustSysFrom Verilog to standard cells. +RustSysSynthesis for the next design iteration + + + +RustSys diff --git a/docs/brand/README.md b/docs/brand/README.md index 447f117..5833d0b 100644 --- a/docs/brand/README.md +++ b/docs/brand/README.md @@ -1,137 +1,9 @@ - - - # RustEDA visual identity -**Signal forge** is the shared visual theme for the RustEDA tool family: a command -enters, a signal changes form, and a concrete engineering artifact comes out. -The identity connects terminal workflows with electronic design rather than -using a mascot or a generic gear. - -![RustEDA wordmark](../assets/rusteda-wordmark.svg) - -## The family mark - -The four open corners suggest both a terminal frame and an integrated-circuit -package. Copper marks the input; teal marks the transformed output. The center -glyph identifies the tool without changing the outer frame, proportions, or -palette. - -| Tool | Center glyph | Meaning | -| --- | --- | --- | -| RustEDA | Crossing signals and a shared node | Tools connected by explicit design artifacts | -| RustSys | Two inputs, a logic gate, one output | RTL becomes a standard-cell netlist | - -Future family marks should change only the center glyph: a clock edge or timing -path for RustSTA, an array for compute, or a viewport for the studio. These are -extension rules for the identity, not a claim that those marks or features have -already shipped. - -![RustSys wordmark](../assets/rustsys-wordmark.svg) - -## Color and typography - -| Role | Color | Use | -| --- | --- | --- | -| Ink | `#101923` | Mark and banner backgrounds | -| Copper | `#EF8B52` | Source code, input signals, small accents | -| Teal | `#57D6BE` | Output signals, active paths, links | -| Warm paper | `#F4F1E9` | Primary text and the gate outline | -| Muted text | `#A1B0BA` | Secondary labels | -| Panel | `#17242F` | Diagram cards | - -The artwork uses DejaVu Sans and DejaVu Sans Mono with standard sans-serif and -monospace fallbacks. SVG text remains selectable and editable; fonts are not -embedded. The GIF rasterizes those fonts. Keep the mark's dark tile so it stays -legible on both light and dark pages, and leave at least one-quarter of the -center glyph's width clear around the tile. Use the square mark at small sizes; -reserve the wordmark for headings. Keep both signal colors when space allows. - -## Verilog-to-gates animation - -The banner follows a short, looping story: - -1. A clock-enabled eight-bit Verilog AND register appears in a source pane. -2. Pulses move into a synthesis graph; two peripheral branches fade during - optimization. -3. AND gates feed a feedback multiplexer and eight flip-flops. The enable drives - the multiplexer select; the clock drives the flip-flops. -4. A clock pulse and output pulse travel through the circuit before the loop - begins again. - -The schematic matches the source operation and illustrates what synthesis does; -it is not a capture of a tool run or an equivalence result. Real library cell -choices and packing depend on the target library and mapping settings. -The visible shell command uses the supported `rustsys synth` interface. Benchmark -and proof claims belong in the linked reports, never inside the animation. - -![Static RustSys synthesis pipeline](../assets/rustsys-banner.svg) - -The static poster carries the complete story without motion. On the documentation -site, render it by default and select the GIF only when the user allows motion: - -```html - - - RustSys transforms Verilog through synthesis into a gate-level netlist - -``` - -Use paths relative to the embedding page. All SVGs have accessible titles and -descriptions. The animation uses smooth signal pulses, no flashes, and a -deliberate 8.4-second loop. The static image remains the reduced-motion and -unsupported-format fallback. - -## Asset inventory - -| Asset | Dimensions | Purpose | -| --- | --- | --- | -| [`rusteda-logo.svg`](../assets/rusteda-logo.svg) | 256 × 256 | Family mark | -| [`rusteda-wordmark.svg`](../assets/rusteda-wordmark.svg) | 760 × 176 | Family identity | -| [`rustsys-logo.svg`](../assets/rustsys-logo.svg) | 256 × 256 | RustSys mark | -| [`rustsys-wordmark.svg`](../assets/rustsys-wordmark.svg) | 760 × 176 | README and documentation headers | -| [`favicon.svg`](../assets/favicon.svg) | 256 × 256 | Site icon | -| [`rustsys-banner.svg`](../assets/rustsys-banner.svg) | 1200 × 400 | Static, accessible pipeline illustration | -| [`rustsys-banner.gif`](../assets/rustsys-banner.gif) | 1200 × 400 | 84 frames, 10 fps, 8.4-second loop | - -## Source and reproduction - -The artwork is original native SVG geometry, text, and animation code, distributed -under this repository's Apache-2.0 license. There is no external artwork, -reference-tool implementation, copied logo, or AI-generated raster asset. Original -vector geometry renders the static poster and all animated frames. - -From the repository root: - -```sh -free -h -python3 -m venv .work/brand-venv -.work/brand-venv/bin/python -m pip install -r docs/brand/requirements.txt -mkdir -p .work/brand -( - ulimit -v 1048576 - /usr/bin/time -v -o .work/brand/render.time \ - timeout 180s .work/brand-venv/bin/python docs/_tools/generate_brand.py -) -``` +![RustSys mark](../assets/rustsys-logo.svg) -The renderer is a documentation authoring tool. Python, Pillow, and CairoSVG are -not RustSys runtime dependencies. Only pre-rendered assets are needed to build the -documentation site. Install DejaVu fonts for matching text layout; rendered -results can differ across font, Cairo, and dependency versions. +All six modules share the same chip frame, copper/mint palette and three-second feedback animation. Only the central symbol and product title change. -The generator caps canvas size at 480,000 pixels, frame count at 96, and GIF size -at 1 MiB. Its working estimate is below 256 MiB: 84 indexed frames use about -38.5 MiB, with one RGB raster and Cairo/quantization scratch allocated at a time. -The measured render used less than **180 MiB peak RSS** and took about **4 seconds**; -the GIF is about **140 KiB**. The command above applies a 1 GiB virtual-memory -guard and a 180-second wall-clock guard. These are asset-rendering measurements, -not synthesis performance numbers. +[Canonical brand guide](https://lab-emi.github.io/RustEDA/brand/) · [Artwork generator](https://github.com/lab-emi/RustEDA/blob/main/scripts/generate_brand.py) -The renderer also saves a four-frame contact sheet, poster preview, and SHA-256 -manifest under `.work/brand/`. Those files are local QA artifacts; the distributed -assets live in `docs/assets/`. To refresh only SVGs without the renderer workload, -pass `--static-only`. +Use the SVG fallback for reduced motion, provide alternative text, and keep benchmark claims in their evidence tables. The artwork is original and licensed under Apache-2.0. diff --git a/docs/index.md b/docs/index.md index 3efff92..d95d5b4 100644 --- a/docs/index.md +++ b/docs/index.md @@ -1,41 +1,13 @@ ---- -title: RustSys — Ultrafast Verilog/SystemVerilog synthesis -description: High-performance Verilog/SystemVerilog synthesis in Rust, built for terminals, CI and coding agents. -hide: - - navigation - - toc ---- +# RustSys - - +RustSys turns RTL into mapped netlists with bounded synthesis, technology mapping and independently checked equivalence. -
+[All RustEDA modules](https://lab-emi.github.io/RustEDA/) -

RUSTEDA / LOGIC SYNTHESIS

- -# Ultrafast RTL synthesis.
Ready for CLI and agents. - -RustSys is a high-performance Verilog/SystemVerilog synthesizer written in Rust. -Turn RTL into standard cells with a CLI built for engineers, CI pipelines and coding -agents: explicit inputs, JSON reports, recorded runs and equivalence checks. - -**1.50×–42.46× faster than Yosys** on the measured five-design, three-PDK suite at -16 physical host cores. [See the results and method](guide/benchmarks.md). - -[Run your first synthesis](guide/quickstart.md){ .md-button .md-button--primary } -[Build an agent workflow](guide/agents.md){ .md-button } - -

Source preview · 0.1.0 · Apache-2.0 · CPU reference backend

- -
- -
- - - Verilog source passes through RustSys synthesis and emerges as connected logic gates and flip-flops in a gate-level netlist. - -
An illustration of RTL → synthesis → standard cells.
-
+ + + Synthesis for the next design iteration. + ## 16-core synthesis speed diff --git a/docs/mkdocs.yml b/docs/mkdocs.yml index 93c502a..758f653 100644 --- a/docs/mkdocs.yml +++ b/docs/mkdocs.yml @@ -87,6 +87,7 @@ validation: unrecognized_links: warn nav: + - RustEDA: https://lab-emi.github.io/RustEDA/ - Home: index.md - Get started: - Install from source: guide/installation.md