From d4e9a9ceeb7f8e0db2a0977ff8ced08ed58e7bf3 Mon Sep 17 00:00:00 2001 From: Nirmesh Kumar Singh Date: Fri, 28 Aug 2026 03:00:27 +0530 Subject: [PATCH 1/8] FROMLIST: dt-bindings: arm: qcom: Add Talos Lyra EVK board Add the qcom,talos-lyra-evk compatible string for the Talos Lyra EVK board, which pairs the Talos Lyra EVK SoM with a common carrier board. Signed-off-by: Avaneesh Kumar Dwivedi Signed-off-by: Nirmesh Kumar Singh Link: https://lore.kernel.org/all/20260901-lyra_upstreaming-v1-1-e3a76dc9e21c@oss.qualcomm.com/ --- Documentation/devicetree/bindings/arm/qcom.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index b56fbf968197a..3ac87618a82af 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -878,6 +878,13 @@ properties: - const: qcom,qcs615 - const: qcom,sm6150 + - items: + - enum: + - qcom,talos-lyra-evk + - const: qcom,talos-lyra-evk-som + - const: qcom,qcs615 + - const: qcom,sm6150 + - items: - enum: - qcom,sa8155p-adp From 2ce4b9d6adb5ae1a4b7a390605fab6d5658dff19 Mon Sep 17 00:00:00 2001 From: Nirmesh Kumar Singh Date: Fri, 28 Aug 2026 03:02:46 +0530 Subject: [PATCH 2/8] FROMLIST: arm64: dts: qcom: Add Talos Lyra EVK SoM platform Introduce the device tree for the QCS615-based Talos Lyra EVK SoM. Lyra EVK SoM a compact compute module integrating the QCS615 SoC, PMIC, and essential connectivity, designed to mount on carrier boards. The initial SoM device tree includes basic support for: - CPU and memory - PMIC and board-level regulators - UFS and SD card storage - QUPv3 (I2C/SPI/UART) instances - ADSP/CDSP remoteprocs - GPU Co-developed-by: Monish Chunara Signed-off-by: Monish Chunara Co-developed-by: Rakesh Kota Signed-off-by: Rakesh Kota Co-developed-by: Sayali Lokhande Signed-off-by: Sayali Lokhande Signed-off-by: Avaneesh Kumar Dwivedi Signed-off-by: Nirmesh Kumar Singh Link: https://lore.kernel.org/all/20260901-lyra_upstreaming-v1-2-e3a76dc9e21c@oss.qualcomm.com/ --- .../boot/dts/qcom/talos-lyra-evk-som.dtsi | 282 ++++++++++++++++++ 1 file changed, 282 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi new file mode 100644 index 0000000000000..8c19f050d5b3e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi @@ -0,0 +1,282 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +#include +#include +#include "talos.dtsi" +#include "pm8150.dtsi" +/ { + aliases { + mmc0 = &sdhc_1; + mmc1 = &sdhc_2; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + clocks { + sleep_clk: sleep-clk { + compatible = "fixed-clock"; + clock-frequency = <32764>; + #clock-cells = <0>; + }; + + xo_board_clk: xo-board-clk { + compatible = "fixed-clock"; + clock-frequency = <38400000>; + #clock-cells = <0>; + }; + }; +}; + +&apps_rsc { + regulators-0 { + compatible = "qcom,pm8150-rpmh-regulators"; + qcom,pmic-id = "a"; + + vreg_s3a: smps3 { + regulator-name = "vreg_s3a"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <650000>; + regulator-initial-mode = ; + }; + + vreg_s4a: smps4 { + regulator-name = "vreg_s4a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1829000>; + regulator-initial-mode = ; + }; + + vreg_s5a: smps5 { + regulator-name = "vreg_s5a"; + regulator-min-microvolt = <1896000>; + regulator-max-microvolt = <2040000>; + regulator-initial-mode = ; + }; + + vreg_s6a: smps6 { + regulator-name = "vreg_s6a"; + regulator-min-microvolt = <1304000>; + regulator-max-microvolt = <1404000>; + regulator-initial-mode = ; + }; + + vreg_l1a: ldo1 { + regulator-name = "vreg_l1a"; + regulator-min-microvolt = <488000>; + regulator-max-microvolt = <852000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l2a: ldo2 { + regulator-name = "vreg_l2a"; + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3100000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l3a: ldo3 { + regulator-name = "vreg_l3a"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1248000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l5a: ldo5 { + regulator-name = "vreg_l5a"; + regulator-min-microvolt = <875000>; + regulator-max-microvolt = <975000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l7a: ldo7 { + regulator-name = "vreg_l7a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1900000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l8a: ldo8 { + regulator-name = "vreg_l8a"; + regulator-min-microvolt = <1150000>; + regulator-max-microvolt = <1350000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l10a: ldo10 { + regulator-name = "vreg_l10a"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l11a: ldo11 { + regulator-name = "vreg_l11a"; + regulator-min-microvolt = <1232000>; + regulator-max-microvolt = <1260000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l12a: ldo12 { + regulator-name = "vreg_l12a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1890000>; + regulator-initial-mode = ; + }; + + vreg_l13a: ldo13 { + regulator-name = "vreg_l13a"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3230000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l15a: ldo15 { + regulator-name = "vreg_l15a"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1904000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l16a: ldo16 { + regulator-name = "vreg_l16a"; + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + regulator-allow-set-load; + regulator-allowed-modes = ; + }; + + vreg_l17a: ldo17 { + regulator-name = "vreg_l17a"; + regulator-min-microvolt = <2950000>; + regulator-max-microvolt = <3312000>; + regulator-initial-mode = ; + }; + }; +}; + +&gcc { + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>; +}; + +&gpu { + status = "okay"; +}; + +&gpu_zap_shader { + firmware-name = "qcom/qcs615/a612_zap.mbn"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + +&remoteproc_adsp { + firmware-name = "qcom/qcs615/adsp.mbn"; + + status = "okay"; +}; + +&remoteproc_cdsp { + firmware-name = "qcom/qcs615/cdsp.mbn"; + + status = "okay"; +}; + +&rpmhcc { + clocks = <&xo_board_clk>; +}; + +&sdhc_1 { + pinctrl-0 = <&sdc1_state_on>; + pinctrl-1 = <&sdc1_state_off>; + pinctrl-names = "default", "sleep"; + bus-width = <8>; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + vmmc-supply = <&vreg_l17a>; + vqmmc-supply = <&vreg_s4a>; + non-removable; + no-sd; + no-sdio; + + status = "okay"; +}; + +&sdhc_2 { + pinctrl-0 = <&sdc2_state_on>; + pinctrl-1 = <&sdc2_state_off>; + pinctrl-names = "default", "sleep"; + bus-width = <4>; + cd-gpios = <&tlmm 99 GPIO_ACTIVE_LOW>; + vmmc-supply = <&vreg_l10a>; + vqmmc-supply = <&vreg_s4a>; + + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&ufs_mem_hc { + reset-gpios = <&tlmm 123 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_l17a>; + vcc-max-microamp = <600000>; + vccq2-supply = <&vreg_s4a>; + vccq2-max-microamp = <600000>; + + status = "okay"; +}; + +&ufs_mem_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; From d0f7fa44e785d9bcd338aef52c76c64b8510a3e5 Mon Sep 17 00:00:00 2001 From: Nirmesh Kumar Singh Date: Fri, 28 Aug 2026 03:03:37 +0530 Subject: [PATCH 3/8] FROMLIST: arm64: dts: qcom: Add Talos Lyra EVK board Add the device tree for the Talos Lyra EVK platform which combines the Talos Lyra EVK SoM and Lyra carrier board. This device tree adds board-specific peripheral configuration on top of the SoM, including: - Native DisplayPort output - GPIO expanders on i2c5 - SPI-attached TPM (ST33) - USB host and peripheral controllers - Power and reset keys Co-developed-by: Akash Kumar Signed-off-by: Akash Kumar Co-developed-by: Khalid Faisal Ansari Signed-off-by: Khalid Faisal Ansari Co-developed-by: Vishnu Santhosh Signed-off-by: Vishnu Santhosh Signed-off-by: Avaneesh Kumar Dwivedi Signed-off-by: Nirmesh Kumar Singh Link: https://lore.kernel.org/all/20260901-lyra_upstreaming-v1-3-e3a76dc9e21c@oss.qualcomm.com/ --- arch/arm64/boot/dts/qcom/Makefile | 1 + arch/arm64/boot/dts/qcom/talos-lyra-evk.dts | 138 ++++++++++++++++++++ 2 files changed, 139 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/talos-lyra-evk.dts diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index bb197fc5d86e1..c1bf20bf04e7c 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -353,6 +353,7 @@ dtb-$(CONFIG_ARCH_QCOM) += sm8650-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-mtp.dtb dtb-$(CONFIG_ARCH_QCOM) += sm8750-qrd.dtb dtb-$(CONFIG_ARCH_QCOM) += talos-evk.dtb +dtb-$(CONFIG_ARCH_QCOM) += talos-lyra-evk.dtb dtb-$(CONFIG_ARCH_QCOM) += talos-evk-camera-imx577.dtbo talos-evk-camera-imx577-dtbs := talos-evk.dtb talos-evk-camera-imx577.dtbo talos-evk-lvds-auo,g133han01-dtbs := \ diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts new file mode 100644 index 0000000000000..d7d7c1c403eb8 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts @@ -0,0 +1,138 @@ +// SPDX-License-Identifier: BSD-3-Clause +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ +/dts-v1/; + +#include "talos-lyra-evk-som.dtsi" + +/ { + model = "Qualcomm QCS615 Talos Lyra EVK"; + compatible = "qcom,talos-lyra-evk", "qcom,talos-lyra-evk-som", "qcom,qcs615", + "qcom,sm6150"; + chassis-type = "embedded"; + + dp0-connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + + hpd-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>; + + port { + dp0_connector_in: endpoint { + remote-endpoint = <&mdss_dp0_out>; + }; + }; + }; + +}; + +&i2c5 { + clock-frequency = <100000>; + + status = "okay"; + + expander0: gpio@20 { + compatible = "kinetic,kts1622", "ti,tcal6416"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander1: gpio@21 { + compatible = "kinetic,kts1622", "ti,tcal6416"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander2: gpio@38 { + compatible = "ti,tca9538"; + reg = <0x38>; + #gpio-cells = <2>; + gpio-controller; + }; + + expander3: gpio@3c { + compatible = "ti,tca9538"; + reg = <0x3c>; + #gpio-cells = <2>; + gpio-controller; + }; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dp0 { + status = "okay"; +}; + +&mdss_dp0_out { + link-frequencies = /bits/ 64 <1620000000 2700000000 5400000000>; + remote-endpoint = <&dp0_connector_in>; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + + status = "okay"; +}; + +&spi6 { + status = "okay"; + + tpm@0 { + compatible = "st,st33htpm-spi", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <20000000>; + }; +}; + +&usb_1 { + dr_mode = "peripheral"; + + status = "okay"; +}; + +&usb_hsphy_1 { + vdd-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + vdda-phy-dpdm-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_2 { + dr_mode = "host"; + + status = "okay"; +}; + +&usb_hsphy_2 { + vdd-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + vdda-phy-dpdm-supply = <&vreg_l13a>; + + status = "okay"; +}; + +&usb_qmpphy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; + +&usb_qmpphy_2 { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; From f3f267e048682d363aafdf772d03d72ee8990413 Mon Sep 17 00:00:00 2001 From: Abhishek Reddy Sudugu Date: Fri, 31 Jul 2026 16:46:16 +0530 Subject: [PATCH 4/8] PENDING: arm64: dts: qcom: talos-lyra-evk: Enable PCIe Support Enable PCIe support on Talos-Lyra-EVK Signed-off-by: Abhishek Reddy Sudugu --- .../boot/dts/qcom/talos-lyra-evk-som.dtsi | 47 ++++++++ arch/arm64/boot/dts/qcom/talos-lyra-evk.dts | 101 ++++++++++++++++++ 2 files changed, 148 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi index 8c19f050d5b3e..4fed898226290 100644 --- a/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi @@ -31,6 +31,24 @@ #clock-cells = <0>; }; }; + + vreg_0p9: regulator-0v9 { + compatible = "regulator-fixed"; + regulator-name = "VREG_0P9"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + regulator-boot-on; + }; + + vreg_1p8: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "VREG_1P8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; }; &apps_rsc { @@ -214,6 +232,35 @@ status = "okay"; }; +&i2c5 { + clock-frequency = <100000>; + + status = "okay"; +}; + +&pcie { + wake-gpios = <&tlmm 100 GPIO_ACTIVE_HIGH>; + + iommu-map = <0x0 &apps_smmu 0x400 0x1>, + <0x100 &apps_smmu 0x401 0x1>, + <0x208 &apps_smmu 0x402 0x1>, + <0x210 &apps_smmu 0x403 0x1>, + <0x218 &apps_smmu 0x404 0x1>, + <0x300 &apps_smmu 0x405 0x1>, + <0x400 &apps_smmu 0x406 0x1>, + <0x500 &apps_smmu 0x407 0x1>, + <0x501 &apps_smmu 0x408 0x1>; + + status = "okay"; +}; + +&pcie_phy { + vdda-phy-supply = <&vreg_l5a>; + vdda-pll-supply = <&vreg_l12a>; + + status = "okay"; +}; + &remoteproc_adsp { firmware-name = "qcom/qcs615/adsp.mbn"; diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts index d7d7c1c403eb8..82903856e2d29 100644 --- a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts @@ -75,6 +75,82 @@ remote-endpoint = <&dp0_connector_in>; }; +&pcie_port0 { + tc9563: pcie@0,0 { + compatible = "pci1179,0623"; + reg = <0x10000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + #gpio-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x2 0xff>; + + vddc-supply = <&vreg_0p9>; + vdd18-supply = <&vreg_1p8>; + vdd09-supply = <&vreg_0p9>; + vddio1-supply = <&vreg_1p8>; + vddio2-supply = <&vreg_1p8>; + vddio18-supply = <&vreg_1p8>; + + i2c-parent = <&i2c5 0x77>; + + resx-gpios = <&tlmm 89 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&tc9563_resx_state>; + pinctrl-names = "default"; + + pcie@1,0 { + reg = <0x20800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x3 0xff>; + + ep-pwr-en-gpio = <&tc9563 2 GPIO_ACTIVE_HIGH>; + ep-reset-gpio = <&tc9563 5 GPIO_ACTIVE_HIGH>; + }; + + pcie@2,0 { + reg = <0x21000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x4 0xff>; + + ep-pwr-en-gpio = <&tc9563 4 GPIO_ACTIVE_HIGH>; + ep-reset-gpio = <&tc9563 3 GPIO_ACTIVE_HIGH>; + }; + + pcie@3,0 { + reg = <0x21800 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + bus-range = <0x5 0xff>; + + pci@0,0 { + reg = <0x50000 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + + pci@0,1 { + reg = <0x50100 0x0 0x0 0x0 0x0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges; + }; + }; + }; +}; + &pon_pwrkey { status = "okay"; }; @@ -95,6 +171,31 @@ }; }; +&tlmm { + pcie_default_state: pcie-default-state { + clkreq-pins { + pins = "gpio90"; + function = "pcie_clk_req"; + drive-strength = <2>; + bias-pull-up; + }; + + wake-pins { + pins = "gpio100"; + function = "gpio"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + tc9563_resx_state: tc9563-resx-state { + pins = "gpio89"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + &usb_1 { dr_mode = "peripheral"; From 277ac837cd0e3d11d03f3493b5f35f089c3e3a56 Mon Sep 17 00:00:00 2001 From: Wei Deng Date: Tue, 8 Sep 2026 09:12:04 +0530 Subject: [PATCH 5/8] PENDING: arm64: dts: qcom: talos-lyra-evk: Enable M.2 Key-E QCC2072 WiFi/BT Add support for the M.2 Key-E QCC2072 wireless solution on the Talos Lyra EVK. The M.2 Key-E slot is connected via the QPS615 PCIe switch (TC9563) PCIe1 Downstream port for WiFi, and via SoC UART7 (GPIO10-13) for Bluetooth. - Add compatible = "pciclass,0604" and OF graph endpoint (tc9563_pcie1_ep) to the QPS615 PCIe1 Downstream port (pcie@1,0) to allow PCI subsystem DT node matching for pwrseq. This node now lives in talos-lyra-evk.dts since &pcie_port0 was moved here. - Add GPIO-controlled vreg_keye_3p3 regulator via expander3 GPIO6 - Add wifi-bt-connector (pcie-m2-e-connector) with vpcie3v3-supply, w-disable1 (GPIO51) for WiFi and w-disable2 (GPIO85) for BT - Wire endpoint cross-references via &tc9563_pcie1_ep and &uart7_ep Signed-off-by: Wei Deng --- arch/arm64/boot/dts/qcom/talos-lyra-evk.dts | 84 +++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts index 82903856e2d29..d305cbaea6997 100644 --- a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts @@ -12,6 +12,10 @@ "qcom,sm6150"; chassis-type = "embedded"; + aliases { + serial1 = &uart7; + }; + dp0-connector { compatible = "dp-connector"; label = "DP0"; @@ -26,6 +30,53 @@ }; }; + vreg_keye_3p3: regulator-keye-3p3 { + compatible = "regulator-fixed"; + regulator-name = "vreg_keye_3p3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander3 6 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-boot-on; + }; + + wifi-bt-connector { + compatible = "pcie-m2-e-connector"; + vpcie3v3-supply = <&vreg_keye_3p3>; + + w-disable1-gpios = <&tlmm 51 GPIO_ACTIVE_LOW>; + w-disable2-gpios = <&tlmm 85 GPIO_ACTIVE_LOW>; + + pinctrl-0 = <&wcn_wlan_en>, <&wcn_bt_en>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + m2_e_pcie_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&tc9563_pcie1_ep>; + }; + }; + + port@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + + m2_e_uart_ep: endpoint@0 { + reg = <0>; + remote-endpoint = <&uart7_ep>; + }; + }; + }; + }; }; &i2c5 { @@ -104,12 +155,17 @@ reg = <0x20800 0x0 0x0 0x0 0x0>; #address-cells = <3>; #size-cells = <2>; + compatible = "pciclass,0604"; device_type = "pci"; ranges; bus-range = <0x3 0xff>; ep-pwr-en-gpio = <&tc9563 2 GPIO_ACTIVE_HIGH>; ep-reset-gpio = <&tc9563 5 GPIO_ACTIVE_HIGH>; + + port { + tc9563_pcie1_ep: endpoint {}; + }; }; pcie@2,0 { @@ -171,6 +227,10 @@ }; }; +&tc9563_pcie1_ep { + remote-endpoint = <&m2_e_pcie_ep>; +}; + &tlmm { pcie_default_state: pcie-default-state { clkreq-pins { @@ -194,6 +254,30 @@ drive-strength = <2>; bias-disable; }; + + wcn_wlan_en: wcn-wlan-en-state { + pins = "gpio51"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + wcn_bt_en: wcn-bt-en-state { + pins = "gpio85"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; +}; + +&uart7 { + status = "okay"; + + port { + uart7_ep: endpoint { + remote-endpoint = <&m2_e_uart_ep>; + }; + }; }; &usb_1 { From 5b89aea950e606da5455ee4c82afac5221ed0ce4 Mon Sep 17 00:00:00 2001 From: Mohit Dsor Date: Tue, 8 Sep 2026 09:21:34 +0530 Subject: [PATCH 6/8] PENDING: arm64: dts: qcom: talos-lyra-evk: Add LT9611UXD HDMI bridge support Added LT9611UXD DSI to HDMI bridge node with dual DSI ports, regulators, reset GPIO, and IRQ on I2C2 at address 0x41. Signed-off-by: Mohit Dsor --- arch/arm64/boot/dts/qcom/talos-lyra-evk.dts | 94 +++++++++++++++++++++ 1 file changed, 94 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts index d305cbaea6997..39703be07addd 100644 --- a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts @@ -4,6 +4,7 @@ */ /dts-v1/; +#include #include "talos-lyra-evk-som.dtsi" / { @@ -30,6 +31,28 @@ }; }; + hdmi-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <<9611_out>; + }; + }; + }; + + vreg_lt9611_vcc: regulator-lt9611-vcc { + compatible = "regulator-fixed"; + regulator-name = "lt9611_vcc"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&tlmm 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-0 = <<9611_vcc_pin>; + pinctrl-names = "default"; + }; + vreg_keye_3p3: regulator-keye-3p3 { compatible = "regulator-fixed"; regulator-name = "vreg_keye_3p3"; @@ -79,6 +102,43 @@ }; }; +&i2c2 { + status = "okay"; + + lt9611uxd: lt9611uxd@41 { + compatible = "lontium,lt9611uxd"; + reg = <0x41>; + interrupts-extended = <&tlmm 60 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; + vcc-supply = <&vreg_lt9611_vcc>; + vdd-supply = <&vreg_s4a>; + + pinctrl-0 = <<9611_irq_pin <9611_rst_pin>; + pinctrl-names = "default"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lt9611_a: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + + port@2 { + reg = <2>; + + lt9611_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; +}; + &i2c5 { clock-frequency = <100000>; @@ -126,6 +186,19 @@ remote-endpoint = <&dp0_connector_in>; }; +&mdss_dsi0 { + status = "okay"; +}; + +&mdss_dsi0_out { + remote-endpoint = <<9611_a>; + data-lanes = <0 1 2 3>; +}; + +&mdss_dsi0_phy { + status = "okay"; +}; + &pcie_port0 { tc9563: pcie@0,0 { compatible = "pci1179,0623"; @@ -232,6 +305,27 @@ }; &tlmm { + lt9611_irq_pin: lt9611-irq-state { + pins = "gpio60"; + function = "gpio"; + drive-strength = <2>; + bias-disable; + }; + + lt9611_rst_pin: lt9611-rst-state { + pins = "gpio61"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + lt9611_vcc_pin: lt9611-vcc-state { + pins = "gpio3"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + pcie_default_state: pcie-default-state { clkreq-pins { pins = "gpio90"; From af0b96414463ce61c538a763cb50478018558953 Mon Sep 17 00:00:00 2001 From: Karthik S Date: Tue, 8 Sep 2026 09:32:22 +0530 Subject: [PATCH 7/8] PENDING: arm64: dts: qcom: talos-lyra-evk: enable audio support enable playback and capture over max98091 codec interfaces for talos-lyra-evk platform. Signed-off-by: Karthik S --- .../boot/dts/qcom/talos-lyra-evk-som.dtsi | 1 + arch/arm64/boot/dts/qcom/talos-lyra-evk.dts | 130 ++++++++++++++++++ 2 files changed, 131 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi index 4fed898226290..6a24ca4431d9f 100644 --- a/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include "talos.dtsi" #include "pm8150.dtsi" / { diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts index 39703be07addd..ad5125e3eacd8 100644 --- a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts @@ -100,6 +100,46 @@ }; }; }; + + sound { + compatible = "qcom,talos-lyra-sndcard"; + model = "qcs615-snd-card"; + + pinctrl-names = "default"; + pinctrl-0 = <&lpi_spkr_i2s_mclk_a>, <&lpi_i2s1_clk>, <&lpi_i2s1_data>, <&lpi_i2s1_ws>; + + sec-mi2s-playback-dai-link { + link-name = "Secondary MI2S Playback"; + + cpu { + sound-dai = <&q6apmbedai SECONDARY_MI2S_RX>; + }; + + codec { + sound-dai = <&max98091>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + + sec-mi2s-capture-dai-link { + link-name = "Secondary MI2S Capture"; + + cpu { + sound-dai = <&q6apmbedai SECONDARY_MI2S_TX>; + }; + + codec { + sound-dai = <&max98091>; + }; + + platform { + sound-dai = <&q6apm>; + }; + }; + }; }; &i2c2 { @@ -171,6 +211,18 @@ #gpio-cells = <2>; gpio-controller; }; + + max98091: max98091@10 { + compatible = "maxim,max98091"; + reg = <0x10>; + #sound-dai-cells = <0>; + clock-names = "mclk"; + clocks = <&q6prmcc LPASS_CLK_ID_SPEAKER_I2S_OSR LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + interrupt-parent = <&tlmm>; + interrupts = <119 IRQ_TYPE_NONE>; + pinctrl-names = "default"; + pinctrl-0 = <&int_codec>; + }; }; &mdss { @@ -290,6 +342,79 @@ status = "okay"; }; +&soc { + lpass_tlmm: pinctrl@62B40000 { + compatible = "qcom,qcs615-lpass-lpi-pinctrl"; + reg = <0x0 0x62B40000 0x0 0x20000>, + <0x0 0x62B00000 0x0 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 32>; + }; +}; + +&lpass_tlmm { + lpi_spkr_i2s_mclk_a: lpi-spkr-i2s-mclk-a-state { + pins = "gpio19"; + function = "spkr_i2s_mclk_a"; + drive-strength = <16>; + bias-disable; + output-high; + }; + + lpi_i2s1_clk: lpi-i2s1-clk-state { + pins = "gpio8"; + function = "i2s1_clk"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + lpi_i2s1_clk_sleep: lpi-i2s1-clk-sleep-state { + pins = "gpio8"; + function = "i2s1_clk"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + lpi_i2s1_data: lpi-i2s1-data-state { + pins = "gpio10", "gpio11"; + function = "i2s1_data"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + lpi_i2s1_data_sleep: lpi-i2s1-data-sleep-state { + pins = "gpio10", "gpio11"; + function = "i2s1_data"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; + + lpi_i2s1_ws: lpi-i2s1-ws-state { + pins = "gpio9"; + function = "i2s1_ws"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + lpi_i2s1_ws_sleep: lpi-i2s1-ws-sleep-state { + pins = "gpio9"; + function = "i2s1_ws"; + drive-strength = <2>; + bias-pull-down; + input-enable; + }; +}; + &spi6 { status = "okay"; @@ -305,6 +430,11 @@ }; &tlmm { + int_codec: gpio-irq-state { + pins = "gpio119"; + function = "gpio"; + }; + lt9611_irq_pin: lt9611-irq-state { pins = "gpio60"; function = "gpio"; From d17c981606fc2302fe557a03b0d4de5fe90319a7 Mon Sep 17 00:00:00 2001 From: Ajinkya Inchure Date: Tue, 8 Sep 2026 12:27:53 +0530 Subject: [PATCH 8/8] PENDING: arm64: dts: qcom: talos-lyra-evk: add ethernet support Adding DTS changes for enabling ethernet on talos-lyra board with TI PHY being used. Signed-off-by: Ajinkya Inchure --- .../boot/dts/qcom/talos-lyra-evk-som.dtsi | 51 +++++++++++++++++++ arch/arm64/boot/dts/qcom/talos-lyra-evk.dts | 49 ++++++++++++++++++ 2 files changed, 100 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi b/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi index 6a24ca4431d9f..d8526cc30aa18 100644 --- a/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk-som.dtsi @@ -211,6 +211,57 @@ }; }; +ðernet { + pinctrl-0 = <ðernet_defaults>; + pinctrl-names = "default"; + + phy-handle = <&rgmii_phy>; + phy-mode = "rgmii-id"; + + snps,mtl-rx-config = <&mtl_rx_setup>; + snps,mtl-tx-config = <&mtl_tx_setup>; + + status = "okay"; + + mdio: mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + rgmii_phy: ethernet-phy@7 { + compatible = "ethernet-phy-id2000.a231"; + reg = <0x7>; + + reset-gpios = <&tlmm 105 GPIO_ACTIVE_LOW>; + reset-assert-us = <11000>; + reset-deassert-us = <70000>; + }; + }; + + mtl_rx_setup: rx-queues-config { + snps,rx-queues-to-use = <1>; + snps,rx-sched-sp; + + queue0 { + snps,dcb-algorithm; + snps,map-to-dma-channel = <0x0>; + snps,route-up; + snps,priority = <0x1>; + }; + }; + + mtl_tx_setup: tx-queues-config { + snps,tx-queues-to-use = <1>; + snps,tx-sched-wrr; + + queue0 { + snps,weight = <0x10>; + snps,dcb-algorithm; + snps,priority = <0x0>; + }; + }; +}; + &gcc { clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, diff --git a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts index ad5125e3eacd8..41d01bd363962 100644 --- a/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts +++ b/arch/arm64/boot/dts/qcom/talos-lyra-evk.dts @@ -196,6 +196,13 @@ reg = <0x21>; #gpio-cells = <2>; gpio-controller; + + emac0_phy_en_hog: emac0-phy-en-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "emac0-phy-en"; + }; }; expander2: gpio@38 { @@ -430,6 +437,48 @@ }; &tlmm { + ethernet_defaults: ethernet-defaults-state { + mdc-pins { + pins = "gpio113"; + function = "rgmii"; + bias-pull-up; + }; + + mdio-pins { + pins = "gpio114"; + function = "rgmii"; + bias-pull-up; + }; + + phy-intr-pins { + pins = "gpio121"; + function = "gpio"; + bias-disable; + drive-strength = <8>; + }; + + phy-reset-pins { + pins = "gpio105"; + function = "gpio"; + bias-pull-up; + drive-strength = <16>; + }; + + rgmii-rx-pins { + pins = "gpio81", "gpio82", "gpio83", "gpio102", "gpio103", "gpio112"; + function = "rgmii"; + bias-disable; + drive-strength = <2>; + }; + + rgmii-tx-pins { + pins = "gpio92", "gpio93", "gpio94", "gpio95", "gpio96", "gpio97"; + function = "rgmii"; + bias-pull-up; + drive-strength = <16>; + }; + }; + int_codec: gpio-irq-state { pins = "gpio119"; function = "gpio";