diff --git a/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml b/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml index 4b2d8ad242ccf..98079df61cbb3 100644 --- a/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml @@ -37,56 +37,18 @@ properties: properties: port@0: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false + $ref: /schemas/graph.yaml#/properties/port description: Primary MIPI DSI port-1 for MIPI input or LVDS port-1 for LVDS input or DPI input. - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - - properties: - data-lanes: - description: array of physical DSI data lane indexes. - minItems: 1 - items: - - const: 1 - - const: 2 - - const: 3 - - const: 4 - - required: - - data-lanes - port@1: - $ref: /schemas/graph.yaml#/$defs/port-base - unevaluatedProperties: false + $ref: /schemas/graph.yaml#/properties/port description: Additional MIPI port-2 for MIPI input or LVDS port-2 for LVDS input. Used in combination with primary port-1 to drive higher resolution displays - properties: - endpoint: - $ref: /schemas/media/video-interfaces.yaml# - unevaluatedProperties: false - - properties: - data-lanes: - description: array of physical DSI data lane indexes. - minItems: 1 - items: - - const: 1 - - const: 2 - - const: 3 - - const: 4 - - required: - - data-lanes - port@2: $ref: /schemas/graph.yaml#/properties/port description: @@ -138,7 +100,6 @@ examples: reg = <0>; endpoint { - data-lanes = <1 2 3 4>; remote-endpoint = <&dsi0_out>; }; }; diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple-lvds-dual-ports.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple-lvds-dual-ports.yaml index c72f80e530263..548f5ac14500a 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple-lvds-dual-ports.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple-lvds-dual-ports.yaml @@ -42,8 +42,6 @@ properties: - auo,g190ean01 # BOE AV123Z7M-N17 12.3" (1920x720) LVDS TFT LCD panel - boe,av123z7m-n17 - # BOE DV215FHM-R01 21.5" FHD (1920x1080) dual-channel LVDS panel - - boe,dv215fhm-r01 # Kaohsiung Opto-Electronics Inc. 10.1" WUXGA (1920 x 1200) LVDS TFT LCD panel - koe,tx26d202vm0bwa # Lincoln Technology Solutions, LCD185-101CT 10.1" TFT 1920x1200 diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml index 5fafbc9f3de17..ffdb308352c3f 100644 --- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml @@ -12,15 +12,6 @@ maintainers: allOf: - $ref: dma-controller.yaml# - - if: - not: - properties: - compatible: - contains: - const: qcom,shikra-bam-dma - then: - properties: - qcom,vmid: false properties: compatible: @@ -36,8 +27,6 @@ properties: - enum: # SDM845, SM6115, SM8150, SM8250 and QCM2290 - qcom,bam-v1.7.4 - # Shikra - - qcom,shikra-bam-dma - const: qcom,bam-v1.7.0 clocks: @@ -90,21 +79,6 @@ properties: Indicates that the bam is powered up by a remote processor but must be initialized by the local processor. - qcom,vmid: - $ref: /schemas/types.yaml#/definitions/uint32-array - minItems: 1 - maxItems: 8 - items: - minimum: 1 - maximum: 63 - description: - Destination VMIDs of the remote processor(s) that read the per-channel - descriptor FIFOs as an AXI master. When present, the driver SCM-assigns - each FIFO to these VMIDs so the remote access does not trigger an XPU - violation. HLOS is always retained as the source owner and must not be - listed. Optional even when the qcom,shikra-bam-dma compatible is - present; not valid on any other compatible in this schema. - reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml b/Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml index 12f1b2bc46d6e..b30544410d092 100644 --- a/Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml +++ b/Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml @@ -22,13 +22,7 @@ description: | properties: compatible: - oneOf: - - const: qcom,bam-dmux - - items: - - enum: - # Shikra - - qcom,shikra-bam-dmux - - const: qcom,bam-dmux + const: qcom,bam-dmux interrupts: description: diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,shikra-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,shikra-pas.yaml index 17461d92165b2..253b14eb2b598 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,shikra-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,shikra-pas.yaml @@ -44,11 +44,6 @@ properties: - description: Firmware name of the Hexagon core - description: Firmware name of the Hexagon Devicetree - bam-dmux: - $ref: /schemas/net/qcom,bam-dmux.yaml# - description: - Qualcomm BAM Data Multiplexer (provides network interface to the modem) - glink-edge: $ref: /schemas/remoteproc/qcom,glink-edge.yaml# description: diff --git a/arch/arm64/boot/dts/qcom/Makefile b/arch/arm64/boot/dts/qcom/Makefile index 86790b131e0b0..6577a1c826bc5 100644 --- a/arch/arm64/boot/dts/qcom/Makefile +++ b/arch/arm64/boot/dts/qcom/Makefile @@ -60,9 +60,6 @@ dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-el2.dtb lemans-evk-ifp-mezzanine-dtbs := lemans-evk.dtb lemans-evk-ifp-mezzanine.dtbo -lemans-evk-lvds-boe,dv215fhm-r01-dtbs := lemans-evk.dtb lemans-evk-ifp-mezzanine.dtbo lemans-evk-lvds-boe,dv215fhm-r01.dtbo -dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-lvds-boe,dv215fhm-r01.dtb - dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += lemans-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-ac-evk.dtb @@ -84,9 +81,6 @@ monaco-evk-ifp-mezzanine-dtbs := monaco-evk.dtb monaco-evk-ifp-mezzanine.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-ifp-mezzanine.dtbo -monaco-evk-lvds-boe,dv215fhm-r01-dtbs := monaco-evk.dtb monaco-evk-ifp-mezzanine.dtbo monaco-evk-lvds-boe,dv215fhm-r01.dtbo -dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-lvds-boe,dv215fhm-r01.dtb - monaco-evk-sd-card-dtbs := monaco-evk.dtb monaco-evk-sd-card.dtbo dtb-$(CONFIG_ARCH_QCOM) += monaco-evk-sd-card.dtb @@ -210,11 +204,6 @@ dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine.dtbo qcs6490-rb3gen2-industrial-mezzanine-el2-dtbs := qcs6490-rb3gen2-industrial-mezzanine.dtb kodiak-el2.dtbo dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine-el2.dtb -qcs6490-rb3gen2-industrial-mezzanine-lvds-boe,dv215fhm-r01-dtbs := \ - qcs6490-rb3gen2.dtb qcs6490-rb3gen2-industrial-mezzanine.dtbo \ - qcs6490-rb3gen2-industrial-mezzanine-lvds-boe,dv215fhm-r01.dtbo -dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine-lvds-boe,dv215fhm-r01.dtb - dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-industrial-mezzanine-bt-uart.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtb dtb-$(CONFIG_ARCH_QCOM) += qcs6490-rb3gen2-vision-mezzanine.dtbo diff --git a/arch/arm64/boot/dts/qcom/hamoa-camera-sensor.dtsi b/arch/arm64/boot/dts/qcom/hamoa-camera-sensor.dtsi index 9ac0b32e94181..dc2babd42555e 100644 --- a/arch/arm64/boot/dts/qcom/hamoa-camera-sensor.dtsi +++ b/arch/arm64/boot/dts/qcom/hamoa-camera-sensor.dtsi @@ -18,7 +18,7 @@ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1808000>; + rgltr-min-voltage = <1800000>; rgltr-max-voltage = <1808000>; rgltr-load-current = <120000>; gpio-no-mux = <0>; @@ -57,7 +57,7 @@ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1808000 2912000>; + rgltr-min-voltage = <1800000 2912000>; rgltr-max-voltage = <1808000 2912000>; rgltr-load-current = <120000 120000>; gpio-no-mux = <0>; @@ -95,7 +95,7 @@ power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; rgltr-cntrl-support; pwm-switch; - rgltr-min-voltage = <1808000 1808000 1056000 2800000>; + rgltr-min-voltage = <1800000 1800000 1056000 2800000>; rgltr-max-voltage = <1808000 1808000 1200000 2800000>; rgltr-load-current = <120000 120000 120000 120000>; gpio-no-mux = <0>; diff --git a/arch/arm64/boot/dts/qcom/lemans-evk-lvds-boe,dv215fhm-r01.dtso b/arch/arm64/boot/dts/qcom/lemans-evk-lvds-boe,dv215fhm-r01.dtso deleted file mode 100644 index bd3e13c46a1e7..0000000000000 --- a/arch/arm64/boot/dts/qcom/lemans-evk-lvds-boe,dv215fhm-r01.dtso +++ /dev/null @@ -1,113 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -/dts-v1/; -/plugin/; - -#include - -&{/} { - model = "Qualcomm Technologies, Inc. Lemans EVK LVDS"; - - panel_lvds: panel-lvds { - compatible = "boe,dv215fhm-r01"; - power-supply = <&lcd_disp_bias>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dual-lvds-odd-pixels; - - panel_in_lvds_odd: endpoint { - remote-endpoint = <<9211c_out_odd>; - }; - }; - - port@1 { - reg = <1>; - dual-lvds-even-pixels; - - panel_in_lvds_even: endpoint { - remote-endpoint = <<9211c_out_even>; - }; - }; - }; - }; - - lcd_disp_bias: regulator-lcd-disp-bias { - compatible = "regulator-fixed"; - regulator-name = "lcd_disp_bias"; - regulator-min-microvolt = <5500000>; - regulator-max-microvolt = <5500000>; - gpio = <&expander3 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&i2c1 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c1_default>; - - status = "okay"; - - lt9211c_codec: lvds-bridge@2d { - compatible = "lontium,lt9211c"; - reg = <0x2d>; - reset-gpios = <&tlmm 37 GPIO_ACTIVE_HIGH>; - vccio-supply = <&vreg_s4a>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lt9211c_in: endpoint { - data-lanes = <1 2 3 4>; - remote-endpoint = <&mdss0_dsi0_out>; - }; - }; - - port@2 { - reg = <2>; - - lt9211c_out_odd: endpoint { - remote-endpoint = <&panel_in_lvds_odd>; - }; - }; - - port@3 { - reg = <3>; - - lt9211c_out_even: endpoint { - remote-endpoint = <&panel_in_lvds_even>; - }; - }; - }; - }; -}; - -&mdss0_dsi0 { - vdda-supply = <&vreg_l1c>; - - status = "okay"; -}; - -&mdss0_dsi0_out { - data-lanes = <0 1 2 3>; - remote-endpoint = <<9211c_in>; -}; - -&mdss0_dsi0_phy { - vdds-supply = <&vreg_l4a>; - - status = "okay"; -}; diff --git a/arch/arm64/boot/dts/qcom/lemans.dtsi b/arch/arm64/boot/dts/qcom/lemans.dtsi index 8f74aeb579d7c..e59f30ce6dd1d 100644 --- a/arch/arm64/boot/dts/qcom/lemans.dtsi +++ b/arch/arm64/boot/dts/qcom/lemans.dtsi @@ -339,7 +339,17 @@ idle-states { entry-method = "psci"; - gold_rail_cpu_sleep_0: cpu-sleep-0 { + gold_cpu_sleep_0: cpu-sleep-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + local-timer-stop; + }; + + gold_rail_cpu_sleep_0: cpu-sleep-1 { compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -646,49 +656,57 @@ cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&cluster_0_pd>; - domain-idle-states = <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&cluster_0_pd>; - domain-idle-states = <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&cluster_0_pd>; - domain-idle-states = <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&cluster_0_pd>; - domain-idle-states = <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; cpu_pd4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&cluster_1_pd>; - domain-idle-states = <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; cpu_pd5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&cluster_1_pd>; - domain-idle-states = <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; cpu_pd6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&cluster_1_pd>; - domain-idle-states = <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; cpu_pd7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&cluster_1_pd>; - domain-idle-states = <&gold_rail_cpu_sleep_0>; + domain-idle-states = <&gold_cpu_sleep_0>, + <&gold_rail_cpu_sleep_0>; }; cluster_0_pd: power-domain-cluster0 { diff --git a/arch/arm64/boot/dts/qcom/monaco-evk-lvds-boe,dv215fhm-r01.dtso b/arch/arm64/boot/dts/qcom/monaco-evk-lvds-boe,dv215fhm-r01.dtso deleted file mode 100644 index b796df28037bf..0000000000000 --- a/arch/arm64/boot/dts/qcom/monaco-evk-lvds-boe,dv215fhm-r01.dtso +++ /dev/null @@ -1,114 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -/dts-v1/; -/plugin/; - -#include - -&{/} { - model = "Qualcomm Technologies, Inc. Monaco EVK LVDS"; - - panel_lvds: panel-lvds { - compatible = "boe,dv215fhm-r01"; - power-supply = <&lcd_disp_bias>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dual-lvds-odd-pixels; - - panel_in_lvds_odd: endpoint { - remote-endpoint = <<9211c_out_odd>; - }; - }; - - port@1 { - reg = <1>; - dual-lvds-even-pixels; - - panel_in_lvds_even: endpoint { - remote-endpoint = <<9211c_out_even>; - }; - }; - }; - }; - - lcd_disp_bias: regulator-lcd-disp-bias { - compatible = "regulator-fixed"; - regulator-name = "lcd_disp_bias"; - regulator-min-microvolt = <5500000>; - regulator-max-microvolt = <5500000>; - gpio = <&expander3 1 GPIO_ACTIVE_HIGH>; - enable-active-high; - }; -}; - -&i2c8 { - #address-cells = <1>; - #size-cells = <0>; - pinctrl-names = "default"; - pinctrl-0 = <&qup_i2c8_data_clk>; - - status = "okay"; - - lt9211c_codec: lvds-bridge@2d { - compatible = "lontium,lt9211c"; - reg = <0x2d>; - reset-gpios = <&tlmm 66 GPIO_ACTIVE_HIGH>; - vccio-supply = <&vreg_l5a>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lt9211c_in: endpoint { - data-lanes = <1 2 3 4>; - remote-endpoint = <&mdss_dsi0_out>; - }; - }; - - port@2 { - reg = <2>; - - lt9211c_out_odd: endpoint { - remote-endpoint = <&panel_in_lvds_odd>; - }; - }; - - port@3 { - reg = <3>; - - lt9211c_out_even: endpoint { - remote-endpoint = <&panel_in_lvds_even>; - }; - }; - }; - }; -}; - -&mdss_dsi0 { - vdda-supply = <&vreg_l5a>; - - status = "okay"; -}; - -&mdss_dsi0_out { - data-lanes = <0 1 2 3>; - remote-endpoint = <<9211c_in>; -}; - -&mdss_dsi0_phy { - vdds-supply = <&vreg_l4a>; - - status = "okay"; -}; - diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 8e426d4c1e76e..a32ee14603e7f 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -349,6 +349,16 @@ entry-method = "psci"; little_cpu_sleep_0: cpu-sleep-0-0 { + compatible = "arm,idle-state"; + idle-state-name = "silver-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <449>; + exit-latency-us = <801>; + min-residency-us = <1574>; + local-timer-stop; + }; + + little_cpu_sleep_1: cpu-sleep-0-1 { compatible = "arm,idle-state"; idle-state-name = "silver-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -359,6 +369,16 @@ }; big_cpu_sleep_0: cpu-sleep-1-0 { + compatible = "arm,idle-state"; + idle-state-name = "gold-power-collapse"; + arm,psci-suspend-param = <0x40000003>; + entry-latency-us = <549>; + exit-latency-us = <901>; + min-residency-us = <1774>; + local-timer-stop; + }; + + big_cpu_sleep_1: cpu-sleep-1-1 { compatible = "arm,idle-state"; idle-state-name = "gold-rail-power-collapse"; arm,psci-suspend-param = <0x40000004>; @@ -701,49 +721,49 @@ cpu_pd0: power-domain-cpu0 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; - domain-idle-states = <&big_cpu_sleep_0>; + domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; cpu_pd1: power-domain-cpu1 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; - domain-idle-states = <&big_cpu_sleep_0>; + domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; cpu_pd2: power-domain-cpu2 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; - domain-idle-states = <&big_cpu_sleep_0>; + domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; cpu_pd3: power-domain-cpu3 { #power-domain-cells = <0>; power-domains = <&cluster_pd0>; - domain-idle-states = <&big_cpu_sleep_0>; + domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; }; cpu_pd4: power-domain-cpu4 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; - domain-idle-states = <&little_cpu_sleep_0>; + domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; cpu_pd5: power-domain-cpu5 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; - domain-idle-states = <&little_cpu_sleep_0>; + domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; cpu_pd6: power-domain-cpu6 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; - domain-idle-states = <&little_cpu_sleep_0>; + domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; cpu_pd7: power-domain-cpu7 { #power-domain-cells = <0>; power-domains = <&cluster_pd1>; - domain-idle-states = <&little_cpu_sleep_0>; + domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; }; cluster_pd0: power-domain-cluster0 { diff --git a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine-lvds-boe,dv215fhm-r01.dtso b/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine-lvds-boe,dv215fhm-r01.dtso deleted file mode 100644 index 5501ea09f43ba..0000000000000 --- a/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2-industrial-mezzanine-lvds-boe,dv215fhm-r01.dtso +++ /dev/null @@ -1,106 +0,0 @@ -// SPDX-License-Identifier: BSD-3-Clause -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ - -/dts-v1/; -/plugin/; - -#include - -&{/} { - model = "Qualcomm Technologies, Inc. Industrial RB3gen2 LVDS"; - - hdmi-connector { - status = "disabled"; - }; - - panel_lvds: panel-lvds { - compatible = "boe,dv215fhm-r01"; - power-supply = <&lcd_disp_bias>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - dual-lvds-odd-pixels; - - panel_in_lvds_odd: endpoint { - remote-endpoint = <<9211c_out_odd>; - }; - }; - - port@1 { - reg = <1>; - dual-lvds-even-pixels; - - panel_in_lvds_even: endpoint { - remote-endpoint = <<9211c_out_even>; - }; - }; - }; - }; - - lcd_disp_bias: regulator-lcd-disp-bias { - compatible = "regulator-fixed"; - regulator-name = "lcd_disp_bias"; - regulator-min-microvolt = <5500000>; - regulator-max-microvolt = <5500000>; - vin-supply = <&vreg_l18b_1p8>; - }; -}; - -&i2c1 { - #address-cells = <1>; - #size-cells = <0>; - - status = "okay"; - - lvds_bridge: lvds-bridge@29 { - compatible = "lontium,lt9211c"; - reg = <0x29>; - reset-gpios = <&tlmm 117 GPIO_ACTIVE_HIGH>; - vccio-supply = <&vreg_l18b_1p8>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - lt9211c_in: endpoint { - data-lanes = <1 2 3 4>; - remote-endpoint = <&mdss_dsi0_out>; - }; - }; - - port@2 { - reg = <2>; - - lt9211c_out_odd: endpoint { - remote-endpoint = <&panel_in_lvds_odd>; - }; - }; - - port@3 { - reg = <3>; - - lt9211c_out_even: endpoint { - remote-endpoint = <&panel_in_lvds_even>; - }; - }; - }; - }; -}; - -<9611_codec { - status = "disabled"; -}; - -&mdss_dsi0_out { - remote-endpoint = <<9211c_in>; -}; - diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts index f829e0082ce7f..cde5190563c55 100644 --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts @@ -648,7 +648,7 @@ }; &tlmm { - gpio-reserved-ranges = <6 4>, <14 4>, <30 2>, <115 2>, <49 1>, <155 11>; + gpio-reserved-ranges = <6 4>, <14 4>, <30 2>, <115 2>, <138 1>, <155 11>; dmic_eldo_en_default: dmic-eldo-default-active-state { pins = "gpio71"; diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi index 4509a1f6c8ef8..141fbc51b0768 100644 --- a/arch/arm64/boot/dts/qcom/shikra.dtsi +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi @@ -27,6 +27,22 @@ #address-cells = <2>; #size-cells = <2>; + bam_dmux: bam-dmux { + compatible = "qcom,bam-dmux"; + + interrupts-extended = <&modem_smsm 1 IRQ_TYPE_EDGE_BOTH>, + <&modem_smsm 11 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "pc", + "pc-ack"; + + qcom,smem-states = <&apps_smsm 1>, <&apps_smsm 11>; + qcom,smem-state-names = "pc", + "pc-ack"; + + dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; + dma-names = "tx", "rx"; + }; + clocks { xo_board: xo-board { compatible = "fixed-clock"; @@ -2661,6 +2677,18 @@ }; }; + bam_dmux_dma: dma-controller@6044000 { + compatible = "qcom,bam-v1.7.0"; + reg = <0x0 0x06044000 0x0 0x19000>; + interrupts = ; + #dma-cells = <1>; + qcom,ee = <0>; + + num-channels = <6>; + qcom,num-ees = <1>; + qcom,powered-remotely; + }; + remoteproc_mpss: remoteproc@6080000 { compatible = "qcom,shikra-mpss-pas"; reg = <0x0 0x06080000 0x0 0x100>; @@ -2693,23 +2721,6 @@ status = "disabled"; - bam_dmux: bam-dmux { - compatible = "qcom,shikra-bam-dmux", "qcom,bam-dmux"; - - interrupts-extended = <&modem_smsm 1 IRQ_TYPE_EDGE_BOTH>, - <&modem_smsm 11 IRQ_TYPE_EDGE_BOTH>; - interrupt-names = "pc", - "pc-ack"; - - qcom,smem-states = <&apps_smsm 1>, - <&apps_smsm 11>; - qcom,smem-state-names = "pc", - "pc-ack"; - - dmas = <&bam_dmux_dma 4>, <&bam_dmux_dma 5>; - dma-names = "tx", "rx"; - }; - glink-edge { interrupts = ; mboxes = <&apcs_glb 12>; @@ -4740,19 +4751,6 @@ label = "cti_apss_2"; }; - bam_dmux_dma: dma-controller@6044000 { - compatible = "qcom,shikra-bam-dma", "qcom,bam-v1.7.0"; - reg = <0x0 0x06044000 0x0 0x19000>; - interrupts = ; - #dma-cells = <1>; - qcom,ee = <0>; - - num-channels = <6>; - qcom,num-ees = <1>; - qcom,powered-remotely; - qcom,vmid = ; - }; - sram@c11e000 { compatible = "qcom,shikra-imem", "mmio-sram"; reg = <0x0 0x0c11e000 0x0 0x1000>; diff --git a/drivers/dma/qcom/Kconfig b/drivers/dma/qcom/Kconfig index 63105b8cc1276..ace75d7b835a2 100644 --- a/drivers/dma/qcom/Kconfig +++ b/drivers/dma/qcom/Kconfig @@ -15,7 +15,6 @@ config QCOM_BAM_DMA depends on ARCH_QCOM || (COMPILE_TEST && OF && ARM) select DMA_ENGINE select DMA_VIRTUAL_CHANNELS - select QCOM_SCM help Enable support for the QCOM BAM DMA controller. This controller provides DMA capabilities for a variety of on-chip devices. diff --git a/drivers/dma/qcom/bam_dma.c b/drivers/dma/qcom/bam_dma.c index d1b60a34cc877..cf1b2e512921b 100644 --- a/drivers/dma/qcom/bam_dma.c +++ b/drivers/dma/qcom/bam_dma.c @@ -23,26 +23,24 @@ * indication of where the hardware is currently working. */ -#include -#include -#include -#include -#include -#include -#include -#include -#include #include +#include +#include +#include #include +#include +#include +#include +#include +#include +#include #include -#include #include -#include -#include +#include +#include +#include +#include #include -#include -#include -#include #include "../dmaengine.h" #include "../virt-dma.h" @@ -382,9 +380,6 @@ struct bam_chan { struct bam_desc_hw *fifo_virt; dma_addr_t fifo_phys; - /* SCM source-VMID bitmask of the FIFO, 0 if not SCM-assigned */ - u64 fifo_src_perms; - /* fifo markers */ unsigned short head; /* start of active descriptor entries */ unsigned short tail; /* end of active descriptor entries */ @@ -422,10 +417,6 @@ struct bam_device { const struct bam_device_data *dev_data; - /* destination VMIDs for SCM assignment of descriptor FIFOs */ - u32 *vmids; - int num_vmids; - struct clk *bamclk; int irq; @@ -562,126 +553,6 @@ static void bam_chan_init_hw(struct bam_chan *bchan, bchan->tail = 0; } -/** - * bam_parse_vmids - Parse the optional qcom,vmid property - * @bdev: bam device - * - * Reads the list of destination VMIDs from qcom,vmid, if present. HLOS is - * always the source owner and must not be listed. Absent property leaves - * num_vmids 0. - */ -static int bam_parse_vmids(struct bam_device *bdev) -{ - struct device *dev = bdev->dev; - int n, i, ret; - - n = of_property_count_u32_elems(dev->of_node, "qcom,vmid"); - if (n == -EINVAL) - return 0; - - if (n < 0) - return n; - - if (!qcom_scm_is_available()) - return -EPROBE_DEFER; - - bdev->vmids = devm_kcalloc(dev, n, sizeof(*bdev->vmids), GFP_KERNEL); - if (!bdev->vmids) - return -ENOMEM; - - ret = of_property_read_u32_array(dev->of_node, "qcom,vmid", - bdev->vmids, n); - if (ret) - return ret; - - for (i = 0; i < n; i++) { - if (bdev->vmids[i] == QCOM_SCM_VMID_HLOS) { - dev_err(dev, "qcom,vmid must not include HLOS (%u)\n", - QCOM_SCM_VMID_HLOS); - return -EINVAL; - } - } - - bdev->num_vmids = n; - - return 0; -} - -/** - * bam_assign_fifo - SCM-assign a channel's descriptor FIFO to the remote VMIDs - * @bdev: bam device - * @bchan: bam channel - * - * Grants HLOS plus the configured qcom,vmid VMIDs access to the FIFO, so - * the remote EE can read it. The updated source-VMID bitmask is stored in - * bchan->fifo_src_perms for bam_fifo_can_free() to reverse. - */ -static int bam_assign_fifo(struct bam_device *bdev, struct bam_chan *bchan) -{ - struct qcom_scm_vmperm *dst __free(kfree) = NULL; - u64 src = BIT_ULL(QCOM_SCM_VMID_HLOS); - int i, ret; - - if (!bdev->num_vmids) - return 0; - - dst = kcalloc(bdev->num_vmids + 1, sizeof(*dst), GFP_KERNEL); - if (!dst) - return -ENOMEM; - - dst[0].vmid = QCOM_SCM_VMID_HLOS; - dst[0].perm = QCOM_SCM_PERM_RW; - - for (i = 0; i < bdev->num_vmids; i++) { - dst[i + 1].vmid = bdev->vmids[i]; - dst[i + 1].perm = QCOM_SCM_PERM_RW; - } - - ret = qcom_scm_assign_mem(bchan->fifo_phys, BAM_DESC_FIFO_SIZE, - &src, dst, bdev->num_vmids + 1); - if (ret) { - dev_err(bdev->dev, "SCM assign fifo chan %u failed: %d\n", - bchan->id, ret); - return ret; - } - - bchan->fifo_src_perms = src; - - return 0; -} - -/** - * bam_fifo_can_free - Reclaim a channel's descriptor FIFO to HLOS - * @bdev: bam device - * @bchan: bam channel - * - * Returns true if the FIFO may now be freed. On SCM failure the remote VMID - * still has access, so the caller must leak the buffer instead of freeing it. - */ -static bool bam_fifo_can_free(struct bam_device *bdev, struct bam_chan *bchan) -{ - struct qcom_scm_vmperm hlos = { - .vmid = QCOM_SCM_VMID_HLOS, - .perm = QCOM_SCM_PERM_RW, - }; - int ret; - - if (!bchan->fifo_src_perms) - return true; - - ret = qcom_scm_assign_mem(bchan->fifo_phys, BAM_DESC_FIFO_SIZE, - &bchan->fifo_src_perms, &hlos, 1); - if (ret) { - dev_err(bdev->dev, "SCM reclaim fifo chan %u failed: %d; leaking\n", - bchan->id, ret); - return false; - } - - bchan->fifo_src_perms = 0; - - return true; -} - /** * bam_alloc_chan - Allocate channel resources for DMA channel. * @chan: specified channel @@ -693,29 +564,16 @@ static int bam_alloc_chan(struct dma_chan *chan) struct bam_chan *bchan = to_bam_chan(chan); struct bam_device *bdev = bchan->bdev; - /* - * Remote-owned BAMs keep the FIFO allocated and SCM-assigned to the - * remote VMID across power cycles (see bam_free_chan), so allocate and - * assign it only once; the block and pipe are still re-initialised on - * every power-on below. - */ - if (!bchan->fifo_virt) { - /* allocate FIFO descriptor space, but only if necessary */ - bchan->fifo_virt = dma_alloc_wc(bdev->dev, BAM_DESC_FIFO_SIZE, - &bchan->fifo_phys, GFP_KERNEL); - if (!bchan->fifo_virt) { - dev_err(bdev->dev, "Failed to allocate desc fifo\n"); - return -ENOMEM; - } - - if (bam_assign_fifo(bdev, bchan)) { - dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, - bchan->fifo_virt, bchan->fifo_phys); - bchan->fifo_virt = NULL; - return -EIO; - } - } else if (!bdev->num_vmids) { + if (bchan->fifo_virt) return 0; + + /* allocate FIFO descriptor space, but only if necessary */ + bchan->fifo_virt = dma_alloc_wc(bdev->dev, BAM_DESC_FIFO_SIZE, + &bchan->fifo_phys, GFP_KERNEL); + + if (!bchan->fifo_virt) { + dev_err(bdev->dev, "Failed to allocate desc fifo\n"); + return -ENOMEM; } if (bdev->active_channels++ == 0 && bdev->powered_remotely) @@ -736,6 +594,7 @@ static void bam_free_chan(struct dma_chan *chan) struct bam_chan *bchan = to_bam_chan(chan); struct bam_device *bdev = bchan->bdev; u32 val; + unsigned long flags; int ret; ret = pm_runtime_get_sync(bdev->dev); @@ -749,29 +608,13 @@ static void bam_free_chan(struct dma_chan *chan) goto err; } - /* - * Remote-owned BAMs (qcom,vmid) keep the descriptor FIFO allocated and - * SCM-assigned across power cycles: the remote may already have cut - * power, so pipe-register access would fault, and TZ still holds the - * grant for the next restart (the FIFO is reclaimed and freed once in - * bam_dma_remove). Only drop local channel state here so the block and - * pipe are re-initialised on the next power-on; skip all MMIO. - */ - if (bdev->num_vmids) { - scoped_guard(spinlock_irqsave, &bchan->vc.lock) - bchan->initialized = 0; - bdev->active_channels--; - goto err; - } - - scoped_guard(spinlock_irqsave, &bchan->vc.lock) - bam_reset_channel(bchan); + spin_lock_irqsave(&bchan->vc.lock, flags); + bam_reset_channel(bchan); + spin_unlock_irqrestore(&bchan->vc.lock, flags); - if (bam_fifo_can_free(bdev, bchan)) - dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, - bchan->fifo_virt, bchan->fifo_phys); + dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, bchan->fifo_virt, + bchan->fifo_phys); bchan->fifo_virt = NULL; - bdev->active_channels--; /* mask irq for pipe/channel */ val = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_MSK_EE)); @@ -781,7 +624,7 @@ static void bam_free_chan(struct dma_chan *chan) /* disable irq */ writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_IRQ_EN)); - if (bdev->active_channels == 0 && bdev->powered_remotely) { + if (--bdev->active_channels == 0 && bdev->powered_remotely) { /* s/w reset bam */ val = readl_relaxed(bam_addr(bdev, 0, BAM_CTRL)); val |= BAM_SW_RST; @@ -805,11 +648,12 @@ static int bam_slave_config(struct dma_chan *chan, struct dma_slave_config *cfg) { struct bam_chan *bchan = to_bam_chan(chan); + unsigned long flag; - guard(spinlock_irqsave)(&bchan->vc.lock); - + spin_lock_irqsave(&bchan->vc.lock, flag); memcpy(&bchan->slave, cfg, sizeof(*cfg)); bchan->reconfigure = 1; + spin_unlock_irqrestore(&bchan->vc.lock, flag); return 0; } @@ -836,17 +680,22 @@ static struct dma_async_tx_descriptor *bam_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sg; u32 i; struct bam_desc_hw *desc; - unsigned int num_alloc; + unsigned int num_alloc = 0; + if (!is_slave_direction(direction)) { dev_err(bdev->dev, "invalid dma direction\n"); return NULL; } + /* calculate number of required entries */ + for_each_sg(sgl, sg, sg_len, i) + num_alloc += DIV_ROUND_UP(sg_dma_len(sg), BAM_FIFO_SIZE); + /* allocate enough room to accommodate the number of entries */ - num_alloc = sg_nents_for_dma(sgl, sg_len, BAM_FIFO_SIZE); async_desc = kzalloc(struct_size(async_desc, desc, num_alloc), GFP_NOWAIT); + if (!async_desc) return NULL; @@ -927,40 +776,39 @@ static int bam_dma_terminate_all(struct dma_chan *chan) { struct bam_chan *bchan = to_bam_chan(chan); struct bam_async_desc *async_desc, *tmp; + unsigned long flag; LIST_HEAD(head); /* remove all transactions, including active transaction */ - scoped_guard(spinlock_irqsave, &bchan->vc.lock) { - /* - * If we have transactions queued, then some might be committed to the - * hardware in the desc fifo. The only way to reset the desc fifo is - * to do a hardware reset (either by pipe or the entire block). - * bam_chan_init_hw() will trigger a pipe reset, and also reinit the - * pipe. If the pipe is left disabled (default state after pipe reset) - * and is accessed by a connected hardware engine, a fatal error in - * the BAM will occur. There is a small window where this could happen - * with bam_chan_init_hw(), but it is assumed that the caller has - * stopped activity on any attached hardware engine. Make sure to do - * this first so that the BAM hardware doesn't cause memory corruption - * by accessing freed resources. - */ - if (!list_empty(&bchan->desc_list)) { - async_desc = list_first_entry(&bchan->desc_list, - struct bam_async_desc, desc_node); - /* Remote-owned BAM: pipe reset may fault, skip it. */ - if (!bchan->bdev->num_vmids) - bam_chan_init_hw(bchan, async_desc->dir); - } - - list_for_each_entry_safe(async_desc, tmp, - &bchan->desc_list, desc_node) { - list_add(&async_desc->vd.node, &bchan->vc.desc_issued); - list_del(&async_desc->desc_node); - } + spin_lock_irqsave(&bchan->vc.lock, flag); + /* + * If we have transactions queued, then some might be committed to the + * hardware in the desc fifo. The only way to reset the desc fifo is + * to do a hardware reset (either by pipe or the entire block). + * bam_chan_init_hw() will trigger a pipe reset, and also reinit the + * pipe. If the pipe is left disabled (default state after pipe reset) + * and is accessed by a connected hardware engine, a fatal error in + * the BAM will occur. There is a small window where this could happen + * with bam_chan_init_hw(), but it is assumed that the caller has + * stopped activity on any attached hardware engine. Make sure to do + * this first so that the BAM hardware doesn't cause memory corruption + * by accessing freed resources. + */ + if (!list_empty(&bchan->desc_list)) { + async_desc = list_first_entry(&bchan->desc_list, + struct bam_async_desc, desc_node); + bam_chan_init_hw(bchan, async_desc->dir); + } - vchan_get_all_descriptors(&bchan->vc, &head); + list_for_each_entry_safe(async_desc, tmp, + &bchan->desc_list, desc_node) { + list_add(&async_desc->vd.node, &bchan->vc.desc_issued); + list_del(&async_desc->desc_node); } + vchan_get_all_descriptors(&bchan->vc, &head); + spin_unlock_irqrestore(&bchan->vc.lock, flag); + vchan_dma_desc_free_list(&bchan->vc, &head); return 0; @@ -975,16 +823,17 @@ static int bam_pause(struct dma_chan *chan) { struct bam_chan *bchan = to_bam_chan(chan); struct bam_device *bdev = bchan->bdev; + unsigned long flag; int ret; ret = pm_runtime_get_sync(bdev->dev); if (ret < 0) return ret; - scoped_guard(spinlock_irqsave, &bchan->vc.lock) { - writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_HALT)); - bchan->paused = 1; - } + spin_lock_irqsave(&bchan->vc.lock, flag); + writel_relaxed(1, bam_addr(bdev, bchan->id, BAM_P_HALT)); + bchan->paused = 1; + spin_unlock_irqrestore(&bchan->vc.lock, flag); pm_runtime_mark_last_busy(bdev->dev); pm_runtime_put_autosuspend(bdev->dev); @@ -1000,16 +849,17 @@ static int bam_resume(struct dma_chan *chan) { struct bam_chan *bchan = to_bam_chan(chan); struct bam_device *bdev = bchan->bdev; + unsigned long flag; int ret; ret = pm_runtime_get_sync(bdev->dev); if (ret < 0) return ret; - scoped_guard(spinlock_irqsave, &bchan->vc.lock) { - writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_HALT)); - bchan->paused = 0; - } + spin_lock_irqsave(&bchan->vc.lock, flag); + writel_relaxed(0, bam_addr(bdev, bchan->id, BAM_P_HALT)); + bchan->paused = 0; + spin_unlock_irqrestore(&bchan->vc.lock, flag); pm_runtime_mark_last_busy(bdev->dev); pm_runtime_put_autosuspend(bdev->dev); @@ -1026,6 +876,7 @@ static int bam_resume(struct dma_chan *chan) static u32 process_channel_irqs(struct bam_device *bdev) { u32 i, srcs, pipe_stts, offset, avail; + unsigned long flags; struct bam_async_desc *async_desc, *tmp; srcs = readl_relaxed(bam_addr(bdev, 0, BAM_IRQ_SRCS_EE)); @@ -1045,7 +896,7 @@ static u32 process_channel_irqs(struct bam_device *bdev) writel_relaxed(pipe_stts, bam_addr(bdev, i, BAM_P_IRQ_CLR)); - guard(spinlock_irqsave)(&bchan->vc.lock); + spin_lock_irqsave(&bchan->vc.lock, flags); offset = readl_relaxed(bam_addr(bdev, i, BAM_P_SW_OFSTS)) & P_SW_OFSTS_MASK; @@ -1084,6 +935,8 @@ static u32 process_channel_irqs(struct bam_device *bdev) } list_del(&async_desc->desc_node); } + + spin_unlock_irqrestore(&bchan->vc.lock, flags); } return srcs; @@ -1147,6 +1000,7 @@ static enum dma_status bam_tx_status(struct dma_chan *chan, dma_cookie_t cookie, int ret; size_t residue = 0; unsigned int i; + unsigned long flags; ret = dma_cookie_status(chan, cookie, txstate); if (ret == DMA_COMPLETE) @@ -1155,22 +1009,23 @@ static enum dma_status bam_tx_status(struct dma_chan *chan, dma_cookie_t cookie, if (!txstate) return bchan->paused ? DMA_PAUSED : ret; - scoped_guard(spinlock_irqsave, &bchan->vc.lock) { - vd = vchan_find_desc(&bchan->vc, cookie); - if (vd) { - residue = container_of(vd, struct bam_async_desc, vd)->length; - } else { - list_for_each_entry(async_desc, &bchan->desc_list, desc_node) { - if (async_desc->vd.tx.cookie != cookie) - continue; - - for (i = 0; i < async_desc->num_desc; i++) - residue += le16_to_cpu( - async_desc->curr_desc[i].size); - } + spin_lock_irqsave(&bchan->vc.lock, flags); + vd = vchan_find_desc(&bchan->vc, cookie); + if (vd) { + residue = container_of(vd, struct bam_async_desc, vd)->length; + } else { + list_for_each_entry(async_desc, &bchan->desc_list, desc_node) { + if (async_desc->vd.tx.cookie != cookie) + continue; + + for (i = 0; i < async_desc->num_desc; i++) + residue += le16_to_cpu( + async_desc->curr_desc[i].size); } } + spin_unlock_irqrestore(&bchan->vc.lock, flags); + dma_set_residue(txstate, residue); if (ret == DMA_IN_PROGRESS && bchan->paused) @@ -1311,16 +1166,17 @@ static void dma_tasklet(struct tasklet_struct *t) { struct bam_device *bdev = from_tasklet(bdev, t, task); struct bam_chan *bchan; + unsigned long flags; unsigned int i; /* go through the channels and kick off transactions */ for (i = 0; i < bdev->num_channels; i++) { bchan = &bdev->channels[i]; - - guard(spinlock_irqsave)(&bchan->vc.lock); + spin_lock_irqsave(&bchan->vc.lock, flags); if (!list_empty(&bchan->vc.desc_issued) && !IS_BUSY(bchan)) bam_start_dma(bchan); + spin_unlock_irqrestore(&bchan->vc.lock, flags); } } @@ -1334,12 +1190,15 @@ static void dma_tasklet(struct tasklet_struct *t) static void bam_issue_pending(struct dma_chan *chan) { struct bam_chan *bchan = to_bam_chan(chan); + unsigned long flags; - guard(spinlock_irqsave)(&bchan->vc.lock); + spin_lock_irqsave(&bchan->vc.lock, flags); /* if work pending and idle, start a transaction */ if (vchan_issue_pending(&bchan->vc) && !IS_BUSY(bchan)) bam_start_dma(bchan); + + spin_unlock_irqrestore(&bchan->vc.lock, flags); } /** @@ -1463,10 +1322,6 @@ static int bam_dma_probe(struct platform_device *pdev) bdev->powered_remotely = of_property_read_bool(pdev->dev.of_node, "qcom,powered-remotely"); - ret = bam_parse_vmids(bdev); - if (ret) - return ret; - if (bdev->controlled_remotely || bdev->powered_remotely) bdev->bamclk = devm_clk_get_optional(bdev->dev, "bam_clk"); else @@ -1603,10 +1458,9 @@ static void bam_dma_remove(struct platform_device *pdev) if (!bdev->channels[i].fifo_virt) continue; - if (bam_fifo_can_free(bdev, &bdev->channels[i])) - dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, - bdev->channels[i].fifo_virt, - bdev->channels[i].fifo_phys); + dma_free_wc(bdev->dev, BAM_DESC_FIFO_SIZE, + bdev->channels[i].fifo_virt, + bdev->channels[i].fifo_phys); } tasklet_kill(&bdev->task); diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c index 2b3e41a29cd52..ef1c4b9299ee4 100644 --- a/drivers/gpu/drm/panel/panel-simple.c +++ b/drivers/gpu/drm/panel/panel-simple.c @@ -1538,31 +1538,6 @@ static const struct panel_desc boe_bp101wx1_100 = { .connector_type = DRM_MODE_CONNECTOR_LVDS, }; -static const struct display_timing boe_dv215fhm_r01_timing = { - .pixelclock = { 148500000, 148500000, 148500000 }, - .hactive = { 1920, 1920, 1920 }, - .hfront_porch = { 88, 88, 88 }, - .hback_porch = { 148, 148, 148 }, - .hsync_len = { 44, 44, 44 }, - .vactive = { 1080, 1080, 1080 }, - .vfront_porch = { 4, 4, 4 }, - .vback_porch = { 36, 36, 36 }, - .vsync_len = { 5, 5, 5 }, - .flags = DISPLAY_FLAGS_DE_HIGH, -}; - -static const struct panel_desc boe_dv215fhm_r01 = { - .timings = &boe_dv215fhm_r01_timing, - .num_timings = 1, - .bpc = 8, - .size = { - .width = 476, - .height = 268, - }, - .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, - .connector_type = DRM_MODE_CONNECTOR_LVDS, -}; - static const struct display_timing boe_ev121wxm_n10_1850_timing = { .pixelclock = { 69922000, 71000000, 72293000 }, .hactive = { 1280, 1280, 1280 }, @@ -5074,9 +5049,6 @@ static const struct of_device_id platform_of_match[] = { }, { .compatible = "boe,bp101wx1-100", .data = &boe_bp101wx1_100, - }, { - .compatible = "boe,dv215fhm-r01", - .data = &boe_dv215fhm_r01, }, { .compatible = "boe,ev121wxm-n10-1850", .data = &boe_ev121wxm_n10_1850, diff --git a/drivers/net/wwan/Kconfig b/drivers/net/wwan/Kconfig index 18f761165cdc0..410b0245114e8 100644 --- a/drivers/net/wwan/Kconfig +++ b/drivers/net/wwan/Kconfig @@ -64,7 +64,6 @@ config MHI_WWAN_MBIM config QCOM_BAM_DMUX tristate "Qualcomm BAM-DMUX WWAN network driver" depends on (DMA_ENGINE && PM && QCOM_SMEM_STATE) || COMPILE_TEST - select QCOM_SCM help The BAM Data Multiplexer provides access to the network data channels of modems integrated into many older Qualcomm SoCs, e.g. Qualcomm diff --git a/drivers/net/wwan/qcom_bam_dmux.c b/drivers/net/wwan/qcom_bam_dmux.c index f8f4a078db80a..64dab8b57611c 100644 --- a/drivers/net/wwan/qcom_bam_dmux.c +++ b/drivers/net/wwan/qcom_bam_dmux.c @@ -9,13 +9,11 @@ #include #include #include -#include #include #include #include #include #include -#include #include #include #include @@ -27,13 +25,11 @@ #define BAM_DMUX_BUFFER_SIZE SZ_2K #define BAM_DMUX_HDR_SIZE sizeof(struct bam_dmux_hdr) #define BAM_DMUX_MAX_DATA_SIZE (BAM_DMUX_BUFFER_SIZE - BAM_DMUX_HDR_SIZE) -/* Header + max data + up to sizeof(u32) word-alignment pad, see bam_dmux_tx_prepare_skb() */ -#define BAM_DMUX_TX_BUFFER_SIZE (BAM_DMUX_BUFFER_SIZE + sizeof(u32)) #define BAM_DMUX_NUM_SKB 32 #define BAM_DMUX_HDR_MAGIC 0x33fc -#define BAM_DMUX_AUTOSUSPEND_DELAY 10000 +#define BAM_DMUX_AUTOSUSPEND_DELAY 1000 #define BAM_DMUX_REMOTE_TIMEOUT msecs_to_jiffies(2000) enum { @@ -67,7 +63,6 @@ struct bam_dmux_skb_dma { struct bam_dmux *dmux; struct sk_buff *skb; dma_addr_t addr; - void *virt; /* non-NULL: slot in the coherent RX/TX block */ }; struct bam_dmux { @@ -81,10 +76,6 @@ struct bam_dmux { struct completion pc_ack_completion; struct dma_chan *rx, *tx; - /* Single coherent block backing all RX and TX buffers, NULL if unused */ - void *buf; - dma_addr_t buf_dma; - u64 buf_perms; /* SCM source-VMID bitmask of buf */ struct bam_dmux_skb_dma rx_skbs[BAM_DMUX_NUM_SKB]; struct bam_dmux_skb_dma tx_skbs[BAM_DMUX_NUM_SKB]; spinlock_t tx_lock; /* Protect tx_skbs, tx_next_skb */ @@ -102,10 +93,6 @@ struct bam_dmux_netdev { u8 ch; }; -struct bam_dmux_data { - u32 vmid; -}; - static void bam_dmux_pc_vote(struct bam_dmux *dmux, bool enable) { reinit_completion(&dmux->pc_ack_completion); @@ -125,19 +112,6 @@ static bool bam_dmux_skb_dma_map(struct bam_dmux_skb_dma *skb_dma, { struct device *dev = skb_dma->dmux->dev; - if (skb_dma->virt) { - /* Coherent slot: addr pre-assigned, copy TX payload into it */ - if (dir == DMA_TO_DEVICE) { - if (skb_dma->skb->len > BAM_DMUX_TX_BUFFER_SIZE) { - dev_err(dev, "TX skb too large for coherent slot: %u\n", - skb_dma->skb->len); - return false; - } - memcpy(skb_dma->virt, skb_dma->skb->data, skb_dma->skb->len); - } - return true; - } - skb_dma->addr = dma_map_single(dev, skb_dma->skb->data, skb_dma->skb->len, dir); if (dma_mapping_error(dev, skb_dma->addr)) { dev_err(dev, "Failed to DMA map buffer\n"); @@ -151,9 +125,6 @@ static bool bam_dmux_skb_dma_map(struct bam_dmux_skb_dma *skb_dma, static void bam_dmux_skb_dma_unmap(struct bam_dmux_skb_dma *skb_dma, enum dma_data_direction dir) { - if (skb_dma->virt) /* coherent slot: nothing to unmap */ - return; - dma_unmap_single(skb_dma->dmux->dev, skb_dma->addr, skb_dma->skb->len, dir); skb_dma->addr = 0; } @@ -500,10 +471,9 @@ static bool bam_dmux_skb_dma_submit_rx(struct bam_dmux_skb_dma *skb_dma) { struct bam_dmux *dmux = skb_dma->dmux; struct dma_async_tx_descriptor *desc; - size_t len = skb_dma->virt ? BAM_DMUX_BUFFER_SIZE : skb_dma->skb->len; desc = dmaengine_prep_slave_single(dmux->rx, skb_dma->addr, - len, DMA_DEV_TO_MEM, + skb_dma->skb->len, DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); if (!desc) { dev_err(dmux->dev, "Failed to prepare RX DMA buffer\n"); @@ -518,10 +488,6 @@ static bool bam_dmux_skb_dma_submit_rx(struct bam_dmux_skb_dma *skb_dma) static bool bam_dmux_skb_dma_queue_rx(struct bam_dmux_skb_dma *skb_dma, gfp_t gfp) { - /* Coherent RX slots have virt and addr pre-assigned at probe. */ - if (skb_dma->virt) - return bam_dmux_skb_dma_submit_rx(skb_dma); - if (!skb_dma->skb) { skb_dma->skb = __netdev_alloc_skb(NULL, BAM_DMUX_BUFFER_SIZE, gfp); if (!skb_dma->skb) @@ -536,10 +502,9 @@ static bool bam_dmux_skb_dma_queue_rx(struct bam_dmux_skb_dma *skb_dma, gfp_t gf static void bam_dmux_cmd_data(struct bam_dmux_skb_dma *skb_dma) { struct bam_dmux *dmux = skb_dma->dmux; - struct bam_dmux_hdr *hdr = skb_dma->virt ? skb_dma->virt : - (struct bam_dmux_hdr *)skb_dma->skb->data; + struct sk_buff *skb = skb_dma->skb; + struct bam_dmux_hdr *hdr = (struct bam_dmux_hdr *)skb->data; struct net_device *netdev = dmux->netdevs[hdr->ch]; - struct sk_buff *skb; if (!netdev || !netif_running(netdev)) { dev_warn(dmux->dev, "Data for inactive channel %u\n", hdr->ch); @@ -552,18 +517,10 @@ static void bam_dmux_cmd_data(struct bam_dmux_skb_dma *skb_dma) return; } - if (skb_dma->virt) { - /* Coherent block is not page-backed: copy out to a real skb */ - skb = netdev_alloc_skb(netdev, hdr->len); - if (!skb) - return; - skb_put_data(skb, (u8 *)skb_dma->virt + sizeof(*hdr), hdr->len); - } else { - skb = skb_dma->skb; - skb_dma->skb = NULL; /* Hand over to network stack */ - skb_pull(skb, sizeof(*hdr)); - skb_trim(skb, hdr->len); - } + skb_dma->skb = NULL; /* Hand over to network stack */ + + skb_pull(skb, sizeof(*hdr)); + skb_trim(skb, hdr->len); skb->dev = netdev; /* Only Raw-IP/QMAP is supported by this driver */ @@ -620,14 +577,10 @@ static void bam_dmux_rx_callback(void *data) { struct bam_dmux_skb_dma *skb_dma = data; struct bam_dmux *dmux = skb_dma->dmux; - struct bam_dmux_hdr *hdr; + struct sk_buff *skb = skb_dma->skb; + struct bam_dmux_hdr *hdr = (struct bam_dmux_hdr *)skb->data; - if (skb_dma->virt) { - hdr = skb_dma->virt; /* coherent RX: no skb to unmap */ - } else { - bam_dmux_skb_dma_unmap(skb_dma, DMA_FROM_DEVICE); - hdr = (struct bam_dmux_hdr *)skb_dma->skb->data; - } + bam_dmux_skb_dma_unmap(skb_dma, DMA_FROM_DEVICE); if (hdr->magic != BAM_DMUX_HDR_MAGIC) { dev_err(dmux->dev, "Invalid magic in header: %#x\n", hdr->magic); @@ -694,9 +647,6 @@ static void bam_dmux_free_skbs(struct bam_dmux_skb_dma skbs[], for (i = 0; i < BAM_DMUX_NUM_SKB; i++) { struct bam_dmux_skb_dma *skb_dma = &skbs[i]; - if (skb_dma->virt) /* coherent block freed at remove */ - continue; - if (skb_dma->addr) bam_dmux_skb_dma_unmap(skb_dma, dir); if (skb_dma->skb) { @@ -815,92 +765,6 @@ static int __maybe_unused bam_dmux_runtime_resume(struct device *dev) return 0; } -/* - * Lay out BAM_DMUX_NUM_SKB RX slots (BAM_DMUX_BUFFER_SIZE each) followed by - * BAM_DMUX_NUM_SKB TX slots (BAM_DMUX_TX_BUFFER_SIZE each) in a single - * coherent block, each region individually page-aligned so a future size - * change to either slot size cannot perturb the other region's offset. - */ -static size_t bam_dmux_rx_region_size(void) -{ - return PAGE_ALIGN(BAM_DMUX_NUM_SKB * BAM_DMUX_BUFFER_SIZE); -} - -static size_t bam_dmux_tx_region_size(void) -{ - return PAGE_ALIGN(BAM_DMUX_NUM_SKB * BAM_DMUX_TX_BUFFER_SIZE); -} - -static int bam_dmux_alloc_coherent_block(struct bam_dmux *dmux) -{ - struct device *dev = dmux->dev; - const struct bam_dmux_data *data = of_device_get_match_data(dev); - size_t rx_region = bam_dmux_rx_region_size(); - size_t tx_region = bam_dmux_tx_region_size(); - size_t size = rx_region + tx_region; - u64 src = BIT_ULL(QCOM_SCM_VMID_HLOS); - struct qcom_scm_vmperm dst[2]; - int i, ret; - - if (!data) - return 0; - - if (!qcom_scm_is_available()) - return -EPROBE_DEFER; - - dst[0].vmid = QCOM_SCM_VMID_HLOS; - dst[0].perm = QCOM_SCM_PERM_RW; - dst[1].vmid = data->vmid; - dst[1].perm = QCOM_SCM_PERM_RW; - - dmux->buf = dma_alloc_coherent(dev, size, &dmux->buf_dma, GFP_KERNEL); - if (!dmux->buf) - return -ENOMEM; - - for (i = 0; i < BAM_DMUX_NUM_SKB; i++) { - dmux->rx_skbs[i].virt = dmux->buf + i * BAM_DMUX_BUFFER_SIZE; - dmux->rx_skbs[i].addr = dmux->buf_dma + i * BAM_DMUX_BUFFER_SIZE; - - dmux->tx_skbs[i].virt = dmux->buf + rx_region + i * BAM_DMUX_TX_BUFFER_SIZE; - dmux->tx_skbs[i].addr = dmux->buf_dma + rx_region + i * BAM_DMUX_TX_BUFFER_SIZE; - } - - ret = qcom_scm_assign_mem(dmux->buf_dma, size, &src, dst, ARRAY_SIZE(dst)); - if (ret) { - dev_err(dev, "SCM assign block failed: %d\n", ret); - dma_free_coherent(dev, size, dmux->buf, dmux->buf_dma); - dmux->buf = NULL; - return ret; - } - dmux->buf_perms = src; - - return 0; -} - -static void bam_dmux_free_coherent_block(struct bam_dmux *dmux) -{ - struct qcom_scm_vmperm hlos = { - .vmid = QCOM_SCM_VMID_HLOS, - .perm = QCOM_SCM_PERM_RW, - }; - size_t size = bam_dmux_rx_region_size() + bam_dmux_tx_region_size(); - - if (!dmux->buf) - return; - - if (dmux->buf_perms) { - if (qcom_scm_assign_mem(dmux->buf_dma, size, &dmux->buf_perms, - &hlos, 1)) { - dev_err(dmux->dev, "SCM reclaim block failed; leaking\n"); - return; - } - dmux->buf_perms = 0; - } - - dma_free_coherent(dmux->dev, size, dmux->buf, dmux->buf_dma); - dmux->buf = NULL; -} - static int bam_dmux_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; @@ -948,10 +812,6 @@ static int bam_dmux_probe(struct platform_device *pdev) dmux->tx_skbs[i].dmux = dmux; } - ret = bam_dmux_alloc_coherent_block(dmux); - if (ret) - return ret; - /* Runtime PM manages our own power vote. * Note that the RX path may be active even if we are runtime suspended, * since it is controlled by the remote side. @@ -988,7 +848,6 @@ static int bam_dmux_probe(struct platform_device *pdev) err_disable_pm: pm_runtime_disable(dev); pm_runtime_dont_use_autosuspend(dev); - bam_dmux_free_coherent_block(dmux); return ret; } @@ -1023,19 +882,13 @@ static void bam_dmux_remove(struct platform_device *pdev) disable_irq(dmux->pc_irq); bam_dmux_power_off(dmux); bam_dmux_free_skbs(dmux->tx_skbs, DMA_TO_DEVICE); - bam_dmux_free_coherent_block(dmux); } static const struct dev_pm_ops bam_dmux_pm_ops = { SET_RUNTIME_PM_OPS(bam_dmux_runtime_suspend, bam_dmux_runtime_resume, NULL) }; -static const struct bam_dmux_data shikra_data = { - .vmid = QCOM_SCM_VMID_NAV, -}; - static const struct of_device_id bam_dmux_of_match[] = { - { .compatible = "qcom,shikra-bam-dmux", .data = &shikra_data }, { .compatible = "qcom,bam-dmux" }, { /* sentinel */ } }; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index 374c0cf1528bd..efe6335091507 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -263,12 +263,6 @@ #define PCIE_RAS_DES_EVENT_COUNTER_DATA 0xc -/* SD-EQ (Gen5 32 GT/s per-lane pre/post cursor equalization) registers */ -#define PCIE_RAS_DES_SD_EQ_CONTROL1 0xd0 -#define PCIE_RAS_DES_SD_EQ_CONTROL1_LANE_SEL GENMASK(3, 0) -#define PCIE_RAS_DES_SD_EQ_STATUS2 0xe4 -#define PCIE_RAS_DES_SD_EQ_STATUS3 0xe8 - /* PTM register definitions */ #define PTM_RES_REQ_CTRL 0x8 #define PTM_RES_CCONTEXT_VALID BIT(0) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 260a9a701267b..eb6928d4f83ca 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include @@ -35,10 +34,8 @@ #include #include #include -#include #include #include -#include #include "../../pci.h" #include "../pci-host-common.h" @@ -48,8 +45,6 @@ /* PARF registers */ #define PARF_SYS_CTRL 0x00 #define PARF_PM_CTRL 0x20 -#define PARF_PM_STTS 0x24 -#define PARF_PM_STTS_1 0x28 #define PARF_PCS_DEEMPH 0x34 #define PARF_PCS_SWING 0x38 #define PARF_PHY_CTRL 0x40 @@ -62,21 +57,13 @@ #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 #define PARF_Q2A_FLUSH 0x1ac #define PARF_LTSSM 0x1b0 -#define PARF_INT_ALL_STATUS 0x228 -#define PARF_STATUS 0x230 #define PARF_SID_OFFSET 0x234 #define PARF_BDF_TRANSLATE_CFG 0x24c -#define PARF_CLKREQ_OVERRIDE 0x2b0 #define PARF_DBI_BASE_ADDR_V2 0x350 #define PARF_DBI_BASE_ADDR_V2_HI 0x354 #define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c #define PARF_NO_SNOOP_OVERRIDE 0x3d4 -#define PARF_CORE_ERRORS 0x3c0 -#define PARF_L1SS_SLEEP_MODE_HANDLER_STATUS 0x4d0 -#define PARF_L1SS_SLEEP_MODE_HANDLER_CFG 0x4d4 -#define PARF_INT_ALL_2_STATUS 0x500 -#define PARF_LINK_DOWN_AXI_ECAM_BLOCK_STATUS 0x630 #define PARF_ATU_BASE_ADDR 0x634 #define PARF_ATU_BASE_ADDR_HI 0x638 #define PARF_DEVICE_TYPE 0x1000 @@ -93,12 +80,8 @@ /* MHI registers */ #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04 -#define PARF_DEBUG_CNT_PM_LINKST_IN_L1SUB 0xc08 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10 -#define PARF_DEBUG_CNT_AUX_CLK_APP_REQ_EXIT_L1 0xc14 -#define PARF_DEBUG_CNT_AUX_CLK_APP_READY_ENTER_L23 0xc18 -#define PARF_DEBUG_CNT_AUX_CLK_APP_READY_ENTER_L1 0xc1c #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88 @@ -191,9 +174,6 @@ #define PERST_DELAY_US 1000 -/* Dump buffer size for the link-down register dump */ -#define QCOM_PCIE_DUMP_BUF_SIZE SZ_8K - #define QCOM_PCIE_CRC8_POLYNOMIAL (BIT(2) | BIT(1) | BIT(0)) #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \ @@ -281,15 +261,12 @@ struct qcom_pcie_ops { * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache * snooping * @firmware_managed: Set if the Root Complex is firmware managed - * @has_ext_parf_regs: Set if the PARF block implements the extended - * register set used by qcom_pcie_dump_regs(). */ struct qcom_pcie_cfg { const struct qcom_pcie_ops *ops; bool override_no_snoop; bool firmware_managed; bool no_l0s; - bool has_ext_parf_regs; }; struct qcom_pcie_port { @@ -1555,14 +1532,12 @@ static const struct qcom_pcie_cfg cfg_1_0_0 = { static const struct qcom_pcie_cfg cfg_1_9_0 = { .ops = &ops_1_9_0, - .has_ext_parf_regs = true, }; static const struct qcom_pcie_cfg cfg_1_34_0 = { .ops = &ops_1_9_0, .override_no_snoop = true, .no_l0s = true, - .has_ext_parf_regs = true, }; static const struct qcom_pcie_cfg cfg_2_1_0 = { @@ -1584,7 +1559,6 @@ static const struct qcom_pcie_cfg cfg_2_4_0 = { static const struct qcom_pcie_cfg cfg_2_7_0 = { .ops = &ops_2_7_0, - .has_ext_parf_regs = true, }; static const struct qcom_pcie_cfg cfg_2_9_0 = { @@ -1594,7 +1568,6 @@ static const struct qcom_pcie_cfg cfg_2_9_0 = { static const struct qcom_pcie_cfg cfg_sc8280xp = { .ops = &ops_1_21_0, .no_l0s = true, - .has_ext_parf_regs = true, }; static const struct qcom_pcie_cfg cfg_fw_managed = { @@ -1709,321 +1682,6 @@ static int qcom_pcie_set_max_opp(struct device *dev) return ret; } -#define QCOM_PCIE_DUMP_REGS_PER_LINE 4 - -static const u32 qcom_pcie_parf_dump_regs[] = { - PARF_LTSSM, - PARF_INT_ALL_STATUS, - PARF_SYS_CTRL, -}; - -static const u32 qcom_pcie_ext_parf_dump_regs[] = { - PARF_PM_STTS, - PARF_PM_STTS_1, - PARF_INT_ALL_STATUS, - PARF_INT_ALL_2_STATUS, - PARF_CLKREQ_OVERRIDE, - PARF_L1SS_SLEEP_MODE_HANDLER_STATUS, - PARF_L1SS_SLEEP_MODE_HANDLER_CFG, - PARF_CORE_ERRORS, - PARF_LINK_DOWN_AXI_ECAM_BLOCK_STATUS, - PARF_STATUS, - PARF_SYS_CTRL, -}; - -static const u32 qcom_pcie_mhi_dump_regs[] = { - PARF_DEBUG_CNT_PM_LINKST_IN_L2, - PARF_DEBUG_CNT_PM_LINKST_IN_L1SUB, - PARF_DEBUG_CNT_PM_LINKST_IN_L1, - PARF_DEBUG_CNT_PM_LINKST_IN_L0S, - PARF_DEBUG_CNT_AUX_CLK_APP_REQ_EXIT_L1, - PARF_DEBUG_CNT_AUX_CLK_APP_READY_ENTER_L23, - PARF_DEBUG_CNT_AUX_CLK_APP_READY_ENTER_L1, - PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1, - PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2, -}; - -static int qcom_pcie_has_storage_ep_cb(struct pci_dev *pdev, void *data) -{ - bool *found = data; - - if (pdev->class >> 16 == PCI_BASE_CLASS_STORAGE) { - *found = true; - return 1; - } - - return 0; -} - -static bool qcom_pcie_has_storage_ep(struct qcom_pcie *pcie) -{ - struct dw_pcie_rp *pp = &pcie->pci->pp; - bool found = false; - - pci_walk_bus(pp->bridge->bus, qcom_pcie_has_storage_ep_cb, &found); - - return found; -} - -/* - * qcom_pcie_dump_advance_col - advance @col and append a separator to @buf. - * - * @col tracks the current column within the active section and must be - * reset to 0 by the caller at the start of each new section; a newline is - * emitted every QCOM_PCIE_DUMP_REGS_PER_LINE entries to keep the dump - * compact in dmesg. - */ -static size_t qcom_pcie_dump_advance_col(char *buf, size_t buf_size, int *col) -{ - *col += 1; - - return scnprintf(buf, buf_size, - (*col % QCOM_PCIE_DUMP_REGS_PER_LINE) ? " " : "\n"); -} - -static size_t qcom_pcie_dump_reg_val(char *buf, size_t buf_size, int *col, - u32 offset, u32 val) -{ - size_t len; - - len = scnprintf(buf, buf_size, "0x%03x: 0x%08x", offset, val); - len += qcom_pcie_dump_advance_col(buf + len, buf_size - len, col); - - return len; -} - -/* Same as qcom_pcie_dump_reg_val(), but tags the entry with a lane number - * since the RAS-DES SD-EQ status registers are read once per lane at a - * fixed offset, so the offset alone can't tell entries apart. - */ -static size_t qcom_pcie_dump_lane_reg_val(char *buf, size_t buf_size, int *col, - int lane, u32 offset, u32 val) -{ - size_t len; - - len = scnprintf(buf, buf_size, "L%d/0x%03x: 0x%08x", lane, offset, val); - len += qcom_pcie_dump_advance_col(buf + len, buf_size - len, col); - - return len; -} - -static size_t qcom_pcie_dump_reg_table(void __iomem *base, const u32 *regs, - int nregs, char *buf, size_t buf_size) -{ - size_t len = 0; - int col = 0; - int i; - - for (i = 0; i < nregs; i++) - len += qcom_pcie_dump_reg_val(buf + len, buf_size - len, &col, - regs[i], readl_relaxed(base + regs[i])); - - if (col % QCOM_PCIE_DUMP_REGS_PER_LINE) - len += scnprintf(buf + len, buf_size - len, "\n"); - - return len; -} - -/* - * qcom_pcie_fill_dump_buf - fill @buf with key PCIe register values captured - * at Link Down time. - * - * Returns the number of bytes written into @buf. - */ -static size_t qcom_pcie_fill_dump_buf(struct qcom_pcie *pcie, char *buf, - size_t buf_size) -{ - struct dw_pcie *pci = pcie->pci; - u16 exp_cap, aer_cap, l1ss_cap, secpci_cap, pl16gt_cap, pl32gt_cap; - size_t len = 0; - int col = 0; - u32 val; - - len += scnprintf(buf + len, buf_size - len, "DBI registers:\n"); - - exp_cap = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); - if (exp_cap) { - val = dw_pcie_readl_dbi(pci, exp_cap + PCI_EXP_LNKCAP); - len += qcom_pcie_dump_reg_val(buf + len, buf_size - len, &col, - exp_cap + PCI_EXP_LNKCAP, val); - - val = dw_pcie_readl_dbi(pci, exp_cap + PCI_EXP_LNKCTL); - len += qcom_pcie_dump_reg_val(buf + len, buf_size - len, &col, - exp_cap + PCI_EXP_LNKCTL, val); - - val = dw_pcie_readl_dbi(pci, exp_cap + PCI_EXP_LNKCTL2); - len += qcom_pcie_dump_reg_val(buf + len, buf_size - len, &col, - exp_cap + PCI_EXP_LNKCTL2, val); - } - - aer_cap = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_ERR); - if (aer_cap) { - val = dw_pcie_readl_dbi(pci, aer_cap + PCI_ERR_UNCOR_STATUS); - len += qcom_pcie_dump_reg_val(buf + len, buf_size - len, &col, - aer_cap + PCI_ERR_UNCOR_STATUS, val); - - val = dw_pcie_readl_dbi(pci, aer_cap + PCI_ERR_COR_STATUS); - len += qcom_pcie_dump_reg_val(buf + len, buf_size - len, &col, - aer_cap + PCI_ERR_COR_STATUS, val); - } - - l1ss_cap = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_L1SS); - if (l1ss_cap) { - val = dw_pcie_readl_dbi(pci, l1ss_cap + PCI_L1SS_CTL1); - len += qcom_pcie_dump_reg_val(buf + len, buf_size - len, &col, - l1ss_cap + PCI_L1SS_CTL1, val); - } - - secpci_cap = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_SECPCI); - if (secpci_cap) { - val = dw_pcie_readl_dbi(pci, secpci_cap + PCI_SECPCI_LE_CTRL); - len += qcom_pcie_dump_reg_val(buf + len, buf_size - len, &col, - secpci_cap + PCI_SECPCI_LE_CTRL, val); - - val = dw_pcie_readl_dbi(pci, secpci_cap + PCI_SECPCI_LE_CTRL + 4); - len += qcom_pcie_dump_reg_val(buf + len, buf_size - len, &col, - secpci_cap + PCI_SECPCI_LE_CTRL + 4, val); - } - - pl16gt_cap = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PL_16GT); - if (pl16gt_cap) { - val = dw_pcie_readl_dbi(pci, pl16gt_cap + PCI_PL_16GT_LE_CTRL); - len += qcom_pcie_dump_reg_val(buf + len, buf_size - len, &col, - pl16gt_cap + PCI_PL_16GT_LE_CTRL, val); - - val = dw_pcie_readl_dbi(pci, pl16gt_cap + PCI_PL_16GT_STATUS); - len += qcom_pcie_dump_reg_val(buf + len, buf_size - len, &col, - pl16gt_cap + PCI_PL_16GT_STATUS, val); - } - - pl32gt_cap = dw_pcie_find_ext_capability(pci, PCI_EXT_CAP_ID_PL_32GT); - if (pl32gt_cap) { - val = dw_pcie_readl_dbi(pci, pl32gt_cap + PCI_PL_32GT_LE_CTRL); - len += qcom_pcie_dump_reg_val(buf + len, buf_size - len, &col, - pl32gt_cap + PCI_PL_32GT_LE_CTRL, val); - - val = dw_pcie_readl_dbi(pci, pl32gt_cap + PCI_PL_32GT_STATUS); - len += qcom_pcie_dump_reg_val(buf + len, buf_size - len, &col, - pl32gt_cap + PCI_PL_32GT_STATUS, val); - } - - /* - * Gen5 (32 GT/s) local/remote pre/post cursor status, read through the - * SD-EQ registers inside the DWC RAS-DES vendor-specific extended - * capability. For each lane, write the lane selector into - * PCIE_RAS_DES_SD_EQ_CONTROL1 then read back - * PCIE_RAS_DES_SD_EQ_STATUS2/3, which carry the local/remote pre/post - * cursor values. - */ - if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_32_0GT) { - u16 rasdes_cap = dw_pcie_find_rasdes_capability(pci); - - if (rasdes_cap) { - int num_lanes = dw_pcie_link_get_max_link_width(pci); - int lane; - - for (lane = 0; lane < num_lanes; lane++) { - dw_pcie_writel_dbi(pci, - rasdes_cap + PCIE_RAS_DES_SD_EQ_CONTROL1, - lane & PCIE_RAS_DES_SD_EQ_CONTROL1_LANE_SEL); - - val = dw_pcie_readl_dbi(pci, - rasdes_cap + PCIE_RAS_DES_SD_EQ_STATUS2); - len += qcom_pcie_dump_lane_reg_val(buf + len, buf_size - len, &col, - lane, - rasdes_cap + PCIE_RAS_DES_SD_EQ_STATUS2, - val); - - val = dw_pcie_readl_dbi(pci, - rasdes_cap + PCIE_RAS_DES_SD_EQ_STATUS3); - len += qcom_pcie_dump_lane_reg_val(buf + len, buf_size - len, &col, - lane, - rasdes_cap + PCIE_RAS_DES_SD_EQ_STATUS3, - val); - } - } - } - - if (col % QCOM_PCIE_DUMP_REGS_PER_LINE) - len += scnprintf(buf + len, buf_size - len, "\n"); - - len += scnprintf(buf + len, buf_size - len, "\nPARF registers:\n"); - if (pcie->cfg->has_ext_parf_regs) - len += qcom_pcie_dump_reg_table(pcie->parf, qcom_pcie_ext_parf_dump_regs, - ARRAY_SIZE(qcom_pcie_ext_parf_dump_regs), - buf + len, buf_size - len); - else - len += qcom_pcie_dump_reg_table(pcie->parf, qcom_pcie_parf_dump_regs, - ARRAY_SIZE(qcom_pcie_parf_dump_regs), - buf + len, buf_size - len); - - if (!pcie->mhi) - return len; - - len += scnprintf(buf + len, buf_size - len, "\nMHI registers:\n"); - len += qcom_pcie_dump_reg_table(pcie->mhi, qcom_pcie_mhi_dump_regs, - ARRAY_SIZE(qcom_pcie_mhi_dump_regs), - buf + len, buf_size - len); - - return len; -} - -/* - * qcom_pcie_dump_regs - capture a PCIe register dump on Link Down. - * - * If a storage endpoint is present downstream, print the dump directly to - * dmesg via dev_err() so it is immediately visible even if userspace is not - * available to read a devcoredump after a storage failure. Otherwise hand - * the buffer to the devcoredump framework so it is accessible under - * /sys/class/devcoredump/ for offline analysis. - */ -static void __maybe_unused qcom_pcie_dump_regs(struct qcom_pcie *pcie) -{ - struct device *dev = pcie->pci->dev; - bool storage_ep = qcom_pcie_has_storage_ep(pcie); - char *buf, *line, *pos; - size_t len; - - buf = vmalloc(QCOM_PCIE_DUMP_BUF_SIZE); - if (!buf) - return; - - len = qcom_pcie_fill_dump_buf(pcie, buf, QCOM_PCIE_DUMP_BUF_SIZE); - - if (storage_ep) { - /* - * printk() truncates messages longer than LOG_LINE_MAX, so - * print the dump one line at a time instead of as a single - * dev_err() call. - */ - dev_err(dev, "PCIe Link Down register dump:\n"); - pos = buf; - while ((line = strsep(&pos, "\n"))) - dev_err(dev, "%s\n", line); - vfree(buf); - } else { - dev_coredumpv(dev, buf, len, GFP_KERNEL); - } -} - -static int qcom_pcie_regdump_show(struct seq_file *s, void *data) -{ - struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); - char *buf; - size_t len; - - buf = vmalloc(QCOM_PCIE_DUMP_BUF_SIZE); - if (!buf) - return -ENOMEM; - - len = qcom_pcie_fill_dump_buf(pcie, buf, QCOM_PCIE_DUMP_BUF_SIZE); - seq_write(s, buf, len); - - vfree(buf); - - return 0; -} - static int qcom_pcie_link_transition_count(struct seq_file *s, void *data) { struct qcom_pcie *pcie = (struct qcom_pcie *)dev_get_drvdata(s->private); @@ -2057,11 +1715,8 @@ static void qcom_pcie_init_debugfs(struct qcom_pcie *pcie) return; pcie->debugfs = debugfs_create_dir(name, NULL); - if (pcie->mhi) - debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs, - qcom_pcie_link_transition_count); - debugfs_create_devm_seqfile(dev, "regdump", pcie->debugfs, - qcom_pcie_regdump_show); + debugfs_create_devm_seqfile(dev, "link_transition_count", pcie->debugfs, + qcom_pcie_link_transition_count); } static void qcom_pci_free_msi(void *ptr) @@ -2359,7 +2014,8 @@ static int qcom_pcie_probe(struct platform_device *pdev) qcom_pcie_icc_opp_update(pcie); - qcom_pcie_init_debugfs(pcie); + if (pcie->mhi) + qcom_pcie_init_debugfs(pcie); return 0; @@ -2443,14 +2099,6 @@ static int qcom_pcie_resume_noirq(struct device *dev) return 0; if (pcie->pci->suspended) { - if (pcie->use_pm_opp) { - ret = qcom_pcie_set_max_opp(dev); - if (ret) { - dev_err(dev, "Failed to set max OPP: %d\n", ret); - return ret; - } - } - ret = icc_enable(pcie->icc_cpu); if (ret) { dev_err(dev, "Failed to enable CPU-PCIe interconnect path: %d\n", ret); diff --git a/drivers/remoteproc/qcom_q6v5_pas.c b/drivers/remoteproc/qcom_q6v5_pas.c index ec56e6638a442..d0c3d041bf4d6 100644 --- a/drivers/remoteproc/qcom_q6v5_pas.c +++ b/drivers/remoteproc/qcom_q6v5_pas.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include #include @@ -119,7 +118,6 @@ struct qcom_pas { struct qcom_rproc_pdm pdm_subdev; struct qcom_rproc_ssr ssr_subdev; struct qcom_sysmon *sysmon; - struct platform_device *bam_dmux; struct qcom_scm_pas_context *pas_ctx; struct qcom_scm_pas_context *dtb_pas_ctx; @@ -801,7 +799,6 @@ static int qcom_pas_probe(struct platform_device *pdev) const struct qcom_pas_data *desc; struct qcom_pas *pas; struct rproc *rproc; - struct device_node *node; const char *fw_name, *dtb_fw_name = NULL; const struct rproc_ops *ops = &qcom_pas_ops; int ret; @@ -906,10 +903,6 @@ static int qcom_pas_probe(struct platform_device *pdev) if (ret) goto remove_ssr_sysmon; - node = of_get_compatible_child(pdev->dev.of_node, "qcom,bam-dmux"); - pas->bam_dmux = of_platform_device_create(node, NULL, &pdev->dev); - of_node_put(node); - return 0; remove_ssr_sysmon: @@ -934,9 +927,6 @@ static void qcom_pas_remove(struct platform_device *pdev) { struct qcom_pas *pas = platform_get_drvdata(pdev); - if (pas->bam_dmux) - of_platform_device_destroy(&pas->bam_dmux->dev, NULL); - rproc_del(pas->rproc); qcom_q6v5_deinit(&pas->q6v5); diff --git a/drivers/rpmsg/qcom_glink_native.c b/drivers/rpmsg/qcom_glink_native.c index 7605fde9e6789..833ff9cb8afe6 100644 --- a/drivers/rpmsg/qcom_glink_native.c +++ b/drivers/rpmsg/qcom_glink_native.c @@ -1395,28 +1395,26 @@ static int qcom_glink_announce_create(struct rpmsg_device *rpdev) return 0; } -static void qcom_glink_remove_rpmsg_device(struct qcom_glink *glink, struct glink_channel *channel) +static void qcom_glink_destroy_ept(struct rpmsg_endpoint *ept) { + struct glink_channel *channel = to_glink_channel(ept); + struct qcom_glink *glink = channel->glink; struct rpmsg_channel_info chinfo; + unsigned long flags; + + spin_lock_irqsave(&channel->recv_lock, flags); + channel->ept.cb = NULL; + spin_unlock_irqrestore(&channel->recv_lock, flags); + /* Decouple the potential rpdev from the channel */ if (channel->rpdev) { strscpy_pad(chinfo.name, channel->name, sizeof(chinfo.name)); chinfo.src = RPMSG_ADDR_ANY; chinfo.dst = RPMSG_ADDR_ANY; + rpmsg_unregister_device(glink->dev, &chinfo); } channel->rpdev = NULL; -} - -static void qcom_glink_destroy_ept(struct rpmsg_endpoint *ept) -{ - struct glink_channel *channel = to_glink_channel(ept); - struct qcom_glink *glink = channel->glink; - unsigned long flags; - - spin_lock_irqsave(&channel->recv_lock, flags); - channel->ept.cb = NULL; - spin_unlock_irqrestore(&channel->recv_lock, flags); qcom_glink_send_close_req(glink, channel); } @@ -1706,6 +1704,7 @@ static int qcom_glink_rx_open(struct qcom_glink *glink, unsigned int rcid, static void qcom_glink_rx_close(struct qcom_glink *glink, unsigned int rcid) { + struct rpmsg_channel_info chinfo; struct glink_channel *channel; unsigned long flags; @@ -1721,7 +1720,14 @@ static void qcom_glink_rx_close(struct qcom_glink *glink, unsigned int rcid) /* cancel pending rx_done work */ cancel_work_sync(&channel->intent_work); - qcom_glink_remove_rpmsg_device(glink, channel); + if (channel->rpdev) { + strscpy_pad(chinfo.name, channel->name, sizeof(chinfo.name)); + chinfo.src = RPMSG_ADDR_ANY; + chinfo.dst = RPMSG_ADDR_ANY; + + rpmsg_unregister_device(glink->dev, &chinfo); + } + channel->rpdev = NULL; qcom_glink_send_close_ack(glink, channel); @@ -1735,6 +1741,7 @@ static void qcom_glink_rx_close(struct qcom_glink *glink, unsigned int rcid) static void qcom_glink_rx_close_ack(struct qcom_glink *glink, unsigned int lcid) { + struct rpmsg_channel_info chinfo; struct glink_channel *channel; unsigned long flags; @@ -1756,7 +1763,14 @@ static void qcom_glink_rx_close_ack(struct qcom_glink *glink, unsigned int lcid) spin_unlock_irqrestore(&glink->idr_lock, flags); /* Decouple the potential rpdev from the channel */ - qcom_glink_remove_rpmsg_device(glink, channel); + if (channel->rpdev) { + strscpy(chinfo.name, channel->name, sizeof(chinfo.name)); + chinfo.src = RPMSG_ADDR_ANY; + chinfo.dst = RPMSG_ADDR_ANY; + + rpmsg_unregister_device(glink->dev, &chinfo); + } + channel->rpdev = NULL; kref_put(&channel->refcount, qcom_glink_channel_release); } diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c index 7e2b1cc9c152c..80397fbeaf0dd 100644 --- a/drivers/soc/qcom/qcom-geni-se.c +++ b/drivers/soc/qcom/qcom-geni-se.c @@ -7,11 +7,6 @@ /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ #define __DISABLE_TRACE_MMIO__ -#define CREATE_TRACE_POINTS -#include - -EXPORT_TRACEPOINT_SYMBOL_GPL(geni_se_regs); - #include #include #include @@ -24,8 +19,6 @@ EXPORT_TRACEPOINT_SYMBOL_GPL(geni_se_regs); #include #include #include -#include -#include #include /** @@ -285,12 +278,6 @@ struct se_fw_hdr { #define geni_setbits32(_addr, _v) writel(readl(_addr) | (_v), _addr) #define geni_clrbits32(_addr, _v) writel(readl(_addr) & ~(_v), _addr) -enum domain_idx { - DOMAIN_IDX_POWER, - DOMAIN_IDX_PERF, - DOMAIN_IDX_MAX -}; - /** * geni_se_get_qup_hw_version() - Read the QUP wrapper Hardware version * @se: Pointer to the corresponding serial engine. @@ -593,7 +580,6 @@ static void geni_se_clks_off(struct geni_se *se) clk_disable_unprepare(se->clk); clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks); - clk_disable_unprepare(se->core_clk); } /** @@ -637,18 +623,7 @@ static int geni_se_clks_on(struct geni_se *se) ret = clk_prepare_enable(se->clk); if (ret) - goto err_bulk_clks; - - ret = clk_prepare_enable(se->core_clk); - if (ret) - goto err_se_clk; - - return 0; - -err_se_clk: - clk_disable_unprepare(se->clk); -err_bulk_clks: - clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks); + clk_bulk_disable_unprepare(wrapper->num_clks, wrapper->clks); return ret; } @@ -929,32 +904,30 @@ EXPORT_SYMBOL_GPL(geni_se_rx_dma_unprep); int geni_icc_get(struct geni_se *se, const char *icc_ddr) { - struct geni_icc_path *icc_paths = se->icc_paths; + int i, err; + const char *icc_names[] = {"qup-core", "qup-config", icc_ddr}; if (has_acpi_companion(se->dev)) return 0; - icc_paths[GENI_TO_CORE].path = devm_of_icc_get(se->dev, "qup-core"); - if (IS_ERR(icc_paths[GENI_TO_CORE].path)) - return dev_err_probe(se->dev, PTR_ERR(icc_paths[GENI_TO_CORE].path), - "Failed to get 'qup-core' ICC path\n"); - - icc_paths[CPU_TO_GENI].path = devm_of_icc_get(se->dev, "qup-config"); - if (IS_ERR(icc_paths[CPU_TO_GENI].path)) - return dev_err_probe(se->dev, PTR_ERR(icc_paths[CPU_TO_GENI].path), - "Failed to get 'qup-config' ICC path\n"); - - /* The DDR path is optional, depending on protocol and hw capabilities */ - icc_paths[GENI_TO_DDR].path = devm_of_icc_get(se->dev, "qup-memory"); - if (IS_ERR(icc_paths[GENI_TO_DDR].path)) { - if (PTR_ERR(icc_paths[GENI_TO_DDR].path) == -ENODATA) - icc_paths[GENI_TO_DDR].path = NULL; - else - return dev_err_probe(se->dev, PTR_ERR(icc_paths[GENI_TO_DDR].path), - "Failed to get 'qup-memory' ICC path\n"); + for (i = 0; i < ARRAY_SIZE(se->icc_paths); i++) { + if (!icc_names[i]) + continue; + + se->icc_paths[i].path = devm_of_icc_get(se->dev, icc_names[i]); + if (IS_ERR(se->icc_paths[i].path)) + goto err; } return 0; + +err: + err = PTR_ERR(se->icc_paths[i].path); + if (err != -EPROBE_DEFER) + dev_err_ratelimited(se->dev, "Failed to get ICC path '%s': %d\n", + icc_names[i], err); + return err; + } EXPORT_SYMBOL_GPL(geni_icc_get); @@ -976,28 +949,6 @@ int geni_icc_set_bw(struct geni_se *se) } EXPORT_SYMBOL_GPL(geni_icc_set_bw); -/** - * geni_icc_set_bw_ab() - Set average bandwidth for all ICC paths and apply - * @se: Pointer to the concerned serial engine. - * @core_ab: Average bandwidth in kBps for GENI_TO_CORE path. - * @cfg_ab: Average bandwidth in kBps for CPU_TO_GENI path. - * @ddr_ab: Average bandwidth in kBps for GENI_TO_DDR path. - * - * Sets bandwidth values for all ICC paths and applies them. DDR path is - * optional and only set if it exists. - * - * Return: 0 on success, negative error code on failure. - */ -int geni_icc_set_bw_ab(struct geni_se *se, u32 core_ab, u32 cfg_ab, u32 ddr_ab) -{ - se->icc_paths[GENI_TO_CORE].avg_bw = core_ab; - se->icc_paths[CPU_TO_GENI].avg_bw = cfg_ab; - se->icc_paths[GENI_TO_DDR].avg_bw = ddr_ab; - - return geni_icc_set_bw(se); -} -EXPORT_SYMBOL_GPL(geni_icc_set_bw_ab); - void geni_icc_set_tag(struct geni_se *se, u32 tag) { int i; @@ -1042,196 +993,6 @@ int geni_icc_disable(struct geni_se *se) } EXPORT_SYMBOL_GPL(geni_icc_disable); -/** - * geni_se_resources_deactivate() - Deactivate GENI SE device resources - * @se: Pointer to the geni_se structure - * - * Deactivates device resources for power saving: OPP rate to 0, pin control - * to sleep state, turns off clocks, and disables interconnect. Skips ACPI devices. - * - * Return: 0 on success, negative error code on failure - */ -int geni_se_resources_deactivate(struct geni_se *se) -{ - int ret; - - if (has_acpi_companion(se->dev)) - return 0; - - if (se->has_opp) - dev_pm_opp_set_rate(se->dev, 0); - - ret = pinctrl_pm_select_sleep_state(se->dev); - if (ret) - return ret; - - geni_se_clks_off(se); - - return geni_icc_disable(se); -} -EXPORT_SYMBOL_GPL(geni_se_resources_deactivate); - -/** - * geni_se_resources_activate() - Activate GENI SE device resources - * @se: Pointer to the geni_se structure - * - * Activates device resources for operation: enables interconnect, prepares clocks, - * and sets pin control to default state. Includes error cleanup. Skips ACPI devices. - * - * Unlike geni_se_resources_deactivate(), this function doesn't alter the - * connected genpds' performance states, which must be additionally handled. - * - * Return: 0 on success, negative error code on failure - */ -int geni_se_resources_activate(struct geni_se *se) -{ - int ret; - - if (has_acpi_companion(se->dev)) - return 0; - - ret = geni_icc_enable(se); - if (ret) - return ret; - - ret = geni_se_clks_on(se); - if (ret) - goto out_icc_disable; - - ret = pinctrl_pm_select_default_state(se->dev); - if (ret) { - geni_se_clks_off(se); - goto out_icc_disable; - } - - return 0; - -out_icc_disable: - geni_icc_disable(se); - return ret; -} -EXPORT_SYMBOL_GPL(geni_se_resources_activate); - -/** - * geni_se_set_perf_level() - Set performance level for GENI SE. - * @se: Pointer to the struct geni_se instance. - * @level: The desired performance level. - * - * Sets the performance level by directly calling dev_pm_opp_set_level - * on the performance device associated with the SE. - * - * Return: 0 on success, or a negative error code on failure. - */ -int geni_se_set_perf_level(struct geni_se *se, unsigned long level) -{ - return dev_pm_opp_set_level(se->pd_list->pd_devs[DOMAIN_IDX_PERF], level); -} -EXPORT_SYMBOL_GPL(geni_se_set_perf_level); - -/** - * geni_se_set_perf_opp() - Set performance OPP for GENI SE by frequency. - * @se: Pointer to the struct geni_se instance. - * @clk_freq: The requested clock frequency. - * - * Finds the nearest operating performance point (OPP) for the given - * clock frequency and applies it to the SE's performance device. - * - * Return: 0 on success, or a negative error code on failure. - */ -int geni_se_set_perf_opp(struct geni_se *se, unsigned long clk_freq) -{ - struct device *perf_dev = se->pd_list->pd_devs[DOMAIN_IDX_PERF]; - struct dev_pm_opp *opp; - int ret; - - opp = dev_pm_opp_find_freq_floor(perf_dev, &clk_freq); - if (IS_ERR(opp)) { - dev_err(se->dev, "failed to find opp for freq %lu\n", clk_freq); - return PTR_ERR(opp); - } - - ret = dev_pm_opp_set_opp(perf_dev, opp); - dev_pm_opp_put(opp); - return ret; -} -EXPORT_SYMBOL_GPL(geni_se_set_perf_opp); - -/** - * geni_se_domain_attach() - Attach power domains to a GENI SE device. - * @se: Pointer to the geni_se structure representing the GENI SE device. - * - * This function attaches the power domains ("power" and "perf") required - * in the SCMI auto-VM environment to the GENI Serial Engine device. It - * initializes se->pd_list with the attached domains. - * - * Return: 0 on success, or a negative error code on failure. - */ -int geni_se_domain_attach(struct geni_se *se) -{ - struct dev_pm_domain_attach_data pd_data = { - .pd_flags = PD_FLAG_DEV_LINK_ON, - .pd_names = (const char*[]) { "power", "perf" }, - .num_pd_names = 2, - }; - int ret; - - ret = devm_pm_domain_attach_list(se->dev, - &pd_data, &se->pd_list); - if (ret == 0) - return -ENODEV; - else if (ret < 0) - return ret; - - return 0; -} -EXPORT_SYMBOL_GPL(geni_se_domain_attach); - -/** - * geni_se_resources_init() - Initialize resources for a GENI SE device. - * @se: Pointer to the geni_se structure representing the GENI SE device. - * - * This function initializes various resources required by the GENI Serial Engine - * (SE) device, including clock resources (core and SE clocks), interconnect - * paths for communication. - * It retrieves optional and mandatory clock resources, adds an OF-based - * operating performance point (OPP) table, and sets up interconnect paths - * with default bandwidths. The function also sets a flag (`has_opp`) to - * indicate whether OPP support is available for the device. - * - * Return: 0 on success, or a negative errno on failure. - */ -int geni_se_resources_init(struct geni_se *se) -{ - int ret; - - se->core_clk = devm_clk_get_optional(se->dev, "core"); - if (IS_ERR(se->core_clk)) - return dev_err_probe(se->dev, PTR_ERR(se->core_clk), - "Failed to get optional core clk\n"); - - se->clk = devm_clk_get(se->dev, "se"); - if (IS_ERR(se->clk) && !has_acpi_companion(se->dev)) - return dev_err_probe(se->dev, PTR_ERR(se->clk), - "Failed to get SE clk\n"); - - ret = devm_pm_opp_set_clkname(se->dev, "se"); - if (ret) - return ret; - - ret = devm_pm_opp_of_add_table(se->dev); - if (ret && ret != -ENODEV) - return dev_err_probe(se->dev, ret, "Failed to add OPP table\n"); - - se->has_opp = (ret == 0); - - ret = geni_icc_get(se, "qup-memory"); - if (ret) - return ret; - - return geni_icc_set_bw_ab(se, GENI_DEFAULT_BW, GENI_DEFAULT_BW, GENI_DEFAULT_BW); -} -EXPORT_SYMBOL_GPL(geni_se_resources_init); - /** * geni_find_protocol_fw() - Locate and validate SE firmware for a protocol. * @se: Pointer to the serial engine structure. diff --git a/include/linux/scatterlist.h b/include/linux/scatterlist.h index 6de1a24342990..29f6ceb98d74b 100644 --- a/include/linux/scatterlist.h +++ b/include/linux/scatterlist.h @@ -441,8 +441,6 @@ static inline void sg_init_marker(struct scatterlist *sgl, int sg_nents(struct scatterlist *sg); int sg_nents_for_len(struct scatterlist *sg, u64 len); -int sg_nents_for_dma(struct scatterlist *sgl, unsigned int sglen, size_t len); - struct scatterlist *sg_last(struct scatterlist *s, unsigned int); void sg_init_table(struct scatterlist *, unsigned int); void sg_init_one(struct scatterlist *, const void *, unsigned int); diff --git a/include/linux/soc/qcom/geni-se.h b/include/linux/soc/qcom/geni-se.h index 0fcf154ec6e80..3e812c1b40da3 100644 --- a/include/linux/soc/qcom/geni-se.h +++ b/include/linux/soc/qcom/geni-se.h @@ -60,39 +60,30 @@ struct geni_icc_path { * @dev: Pointer to the Serial Engine device * @wrapper: Pointer to the parent QUP Wrapper core * @clk: Handle to the core serial engine clock - * @core_clk: Auxiliary clock, which may be required by a protocol * @num_clk_levels: Number of valid clock levels in clk_perf_tbl * @clk_perf_tbl: Table of clock frequency input to serial engine clock * @icc_paths: Array of ICC paths for SE * @multi_owner: True if SE is shared between multiprocessors. - * @pd_list: Power domain list for managing power domains - * @has_opp: Indicates if OPP is supported */ struct geni_se { void __iomem *base; struct device *dev; struct geni_wrapper *wrapper; struct clk *clk; - struct clk *core_clk; unsigned int num_clk_levels; unsigned long *clk_perf_tbl; struct geni_icc_path icc_paths[3]; bool multi_owner; - struct dev_pm_domain_list *pd_list; - bool has_opp; }; /* Common SE registers */ -#define GENI_GENERAL_CFG 0x10 #define GENI_FORCE_DEFAULT_REG 0x20 #define GENI_OUTPUT_CTRL 0x24 #define SE_GENI_STATUS 0x40 #define GENI_SER_M_CLK_CFG 0x48 #define GENI_SER_S_CLK_CFG 0x4c -#define GENI_CLK_CTRL_RO 0x60 #define GENI_IF_DISABLE_RO 0x64 #define GENI_FW_REVISION_RO 0x68 -#define GENI_FW_MULTILOCK_MSA_RO 0x74 #define SE_GENI_CLK_SEL 0x7c #define SE_GENI_CFG_SEQ_START 0x84 #define SE_GENI_DMA_MODE_EN 0x258 @@ -103,8 +94,6 @@ struct geni_se { #define SE_GENI_M_IRQ_CLEAR 0x618 #define SE_GENI_M_IRQ_EN_SET 0x61c #define SE_GENI_M_IRQ_EN_CLEAR 0x620 -#define M_CMD_ERR_STATUS 0x624 -#define M_FW_ERR_STATUS 0x628 #define SE_GENI_S_CMD0 0x630 #define SE_GENI_S_CMD_CTRL_REG 0x634 #define SE_GENI_S_IRQ_STATUS 0x640 @@ -122,43 +111,16 @@ struct geni_se { #define SE_GENI_IOS 0x908 #define SE_GENI_M_GP_LENGTH 0x910 #define SE_GENI_S_GP_LENGTH 0x914 -/* TX DMA registers */ -#define SE_DMA_TX_PTR_L 0xc30 -#define SE_DMA_TX_PTR_H 0xc34 -#define SE_DMA_TX_ATTR 0xc38 -#define SE_DMA_TX_LEN 0xc3c #define SE_DMA_TX_IRQ_STAT 0xc40 #define SE_DMA_TX_IRQ_CLR 0xc44 -#define SE_DMA_TX_IRQ_EN 0xc48 -#define SE_DMA_TX_IRQ_EN_SET 0xc4c -#define SE_DMA_TX_IRQ_EN_CLR 0xc50 -#define SE_DMA_TX_LEN_IN 0xc54 #define SE_DMA_TX_FSM_RST 0xc58 -#define SE_DMA_TX_MAX_BURST 0xc5c -/* RX DMA registers */ -#define SE_DMA_RX_PTR_L 0xd30 -#define SE_DMA_RX_PTR_H 0xd34 -#define SE_DMA_RX_ATTR 0xd38 -#define SE_DMA_RX_LEN 0xd3c #define SE_DMA_RX_IRQ_STAT 0xd40 #define SE_DMA_RX_IRQ_CLR 0xd44 -#define SE_DMA_RX_IRQ_EN 0xd48 -#define SE_DMA_RX_IRQ_EN_SET 0xd4c -#define SE_DMA_RX_IRQ_EN_CLR 0xd50 #define SE_DMA_RX_LEN_IN 0xd54 #define SE_DMA_RX_FSM_RST 0xd58 -#define SE_DMA_RX_MAX_BURST 0xd5c -/* DMA general / debug registers */ -#define SE_GSI_EVENT_EN 0xe18 -#define SE_IRQ_EN 0xe1c -#define DMA_IF_EN_RO 0xe20 #define SE_HW_PARAM_0 0xe24 #define SE_HW_PARAM_1 0xe28 #define SE_HW_PARAM_2 0xe2c -#define DMA_GENERAL_CFG 0xe30 -#define SE_DMA_QSB_TRANS_CFG 0xe38 -#define SE_DMA_DEBUG_REG0 0xe40 -#define SE_DMA_IF_EN 0x2004 /* GENI_FORCE_DEFAULT_REG fields */ #define FORCE_DEFAULT BIT(0) @@ -304,12 +266,6 @@ struct geni_se { #define RX_GENI_GP_IRQ_EXT GENMASK(13, 12) #define RX_GENI_CANCEL_IRQ BIT(14) -/* SE_DMA_DEBUG_REG0 fields */ -#define DMA_TX_ACTIVE BIT(0) -#define DMA_RX_ACTIVE BIT(1) -#define DMA_TX_STATE GENMASK(7, 4) -#define DMA_RX_STATE GENMASK(11, 8) - /* SE_HW_PARAM_0 fields */ #define TX_FIFO_WIDTH_MSK GENMASK(29, 24) #define TX_FIFO_WIDTH_SHFT 24 @@ -578,25 +534,12 @@ void geni_se_rx_dma_unprep(struct geni_se *se, dma_addr_t iova, size_t len); int geni_icc_get(struct geni_se *se, const char *icc_ddr); int geni_icc_set_bw(struct geni_se *se); -int geni_icc_set_bw_ab(struct geni_se *se, u32 core_ab, u32 cfg_ab, u32 ddr_ab); void geni_icc_set_tag(struct geni_se *se, u32 tag); int geni_icc_enable(struct geni_se *se); int geni_icc_disable(struct geni_se *se); -int geni_se_resources_init(struct geni_se *se); - -int geni_se_resources_activate(struct geni_se *se); - -int geni_se_resources_deactivate(struct geni_se *se); - int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol); - -int geni_se_domain_attach(struct geni_se *se); - -int geni_se_set_perf_level(struct geni_se *se, unsigned long level); - -int geni_se_set_perf_opp(struct geni_se *se, unsigned long clk_freq); #endif #endif diff --git a/include/trace/events/qcom_geni_se.h b/include/trace/events/qcom_geni_se.h deleted file mode 100644 index 4a6e1ba2d1476..0000000000000 --- a/include/trace/events/qcom_geni_se.h +++ /dev/null @@ -1,157 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ -/* - * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. - */ -#undef TRACE_SYSTEM -#define TRACE_SYSTEM qcom_geni_se - -#if !defined(_TRACE_QCOM_GENI_SE_H) || defined(TRACE_HEADER_MULTI_READ) -#define _TRACE_QCOM_GENI_SE_H - -#include -#include -#include - -TRACE_EVENT(geni_se_regs, - TP_PROTO(struct geni_se *se), - - TP_ARGS(se), - - TP_STRUCT__entry(__string(geni_se_name, dev_name(se->dev)) - __field(u32, geni_se_m_cmd0) - __field(u32, geni_se_m_irq_status) - __field(u32, geni_se_s_cmd0) - __field(u32, geni_se_s_irq_status) - __field(u32, geni_se_status) - __field(u32, geni_se_ios) - __field(u32, geni_se_m_cmd_ctrl) - __field(u32, geni_se_m_cmd_err) - __field(u32, geni_se_m_fw_err) - __field(u32, geni_se_tx_fifo_status) - __field(u32, geni_se_rx_fifo_status) - __field(u32, geni_se_tx_watermark) - __field(u32, geni_se_rx_watermark) - __field(u32, geni_se_rx_watermark_rfr) - __field(u32, geni_se_m_gp_length) - __field(u32, geni_se_s_gp_length) - __field(u32, geni_se_dma_tx_irq) - __field(u32, geni_se_dma_rx_irq) - __field(u32, geni_se_dma_tx_irq_en) - __field(u32, geni_se_dma_rx_irq_en) - __field(u32, geni_se_dma_rx_len) - __field(u32, geni_se_dma_rx_len_in) - __field(u32, geni_se_dma_tx_len) - __field(u32, geni_se_dma_tx_len_in) - __field(u32, geni_se_dma_tx_ptr_l) - __field(u32, geni_se_dma_tx_ptr_h) - __field(u32, geni_se_dma_rx_ptr_l) - __field(u32, geni_se_dma_rx_ptr_h) - __field(u32, geni_se_dma_tx_attr) - __field(u32, geni_se_dma_tx_max_burst) - __field(u32, geni_se_dma_rx_attr) - __field(u32, geni_se_dma_rx_max_burst) - __field(u32, geni_se_dma_if_en) - __field(u32, geni_se_dma_if_en_ro) - __field(u32, geni_se_dma_general_cfg) - __field(u32, geni_se_dma_qsb_trans_cfg) - __field(u32, geni_se_dma_dbg) - __field(u32, geni_se_m_irq_en) - __field(u32, geni_se_s_irq_en) - __field(u32, geni_se_gsi_event_en) - __field(u32, geni_se_irq_en) - __field(u32, geni_se_ser_m_clk_cfg) - __field(u32, geni_se_ser_s_clk_cfg) - __field(u32, geni_se_general_cfg) - __field(u32, geni_se_output_ctrl) - __field(u32, geni_se_clk_ctrl_ro) - __field(u32, geni_se_fifo_if_disable) - __field(u32, geni_se_fw_multilock_msa) - __field(u32, geni_se_clk_sel) - ), - - TP_fast_assign(__assign_str(geni_se_name); - __entry->geni_se_m_cmd0 = readl(se->base + SE_GENI_M_CMD0); - __entry->geni_se_m_irq_status = readl(se->base + SE_GENI_M_IRQ_STATUS); - __entry->geni_se_s_cmd0 = readl(se->base + SE_GENI_S_CMD0); - __entry->geni_se_s_irq_status = readl(se->base + SE_GENI_S_IRQ_STATUS); - __entry->geni_se_status = readl(se->base + SE_GENI_STATUS); - __entry->geni_se_ios = readl(se->base + SE_GENI_IOS); - __entry->geni_se_m_cmd_ctrl = readl(se->base + SE_GENI_M_CMD_CTRL_REG); - __entry->geni_se_m_cmd_err = readl(se->base + M_CMD_ERR_STATUS); - __entry->geni_se_m_fw_err = readl(se->base + M_FW_ERR_STATUS); - __entry->geni_se_tx_fifo_status = readl(se->base + SE_GENI_TX_FIFO_STATUS); - __entry->geni_se_rx_fifo_status = readl(se->base + SE_GENI_RX_FIFO_STATUS); - __entry->geni_se_tx_watermark = readl(se->base + SE_GENI_TX_WATERMARK_REG); - __entry->geni_se_rx_watermark = readl(se->base + SE_GENI_RX_WATERMARK_REG); - __entry->geni_se_rx_watermark_rfr = readl(se->base + SE_GENI_RX_RFR_WATERMARK_REG); - __entry->geni_se_m_gp_length = readl(se->base + SE_GENI_M_GP_LENGTH); - __entry->geni_se_s_gp_length = readl(se->base + SE_GENI_S_GP_LENGTH); - __entry->geni_se_dma_tx_irq = readl(se->base + SE_DMA_TX_IRQ_STAT); - __entry->geni_se_dma_rx_irq = readl(se->base + SE_DMA_RX_IRQ_STAT); - __entry->geni_se_dma_tx_irq_en = readl(se->base + SE_DMA_TX_IRQ_EN); - __entry->geni_se_dma_rx_irq_en = readl(se->base + SE_DMA_RX_IRQ_EN); - __entry->geni_se_dma_rx_len = readl(se->base + SE_DMA_RX_LEN); - __entry->geni_se_dma_rx_len_in = readl(se->base + SE_DMA_RX_LEN_IN); - __entry->geni_se_dma_tx_len = readl(se->base + SE_DMA_TX_LEN); - __entry->geni_se_dma_tx_len_in = readl(se->base + SE_DMA_TX_LEN_IN); - __entry->geni_se_dma_tx_ptr_l = readl(se->base + SE_DMA_TX_PTR_L); - __entry->geni_se_dma_tx_ptr_h = readl(se->base + SE_DMA_TX_PTR_H); - __entry->geni_se_dma_rx_ptr_l = readl(se->base + SE_DMA_RX_PTR_L); - __entry->geni_se_dma_rx_ptr_h = readl(se->base + SE_DMA_RX_PTR_H); - __entry->geni_se_dma_tx_attr = readl(se->base + SE_DMA_TX_ATTR); - __entry->geni_se_dma_tx_max_burst = readl(se->base + SE_DMA_TX_MAX_BURST); - __entry->geni_se_dma_rx_attr = readl(se->base + SE_DMA_RX_ATTR); - __entry->geni_se_dma_rx_max_burst = readl(se->base + SE_DMA_RX_MAX_BURST); - __entry->geni_se_dma_if_en = readl(se->base + SE_DMA_IF_EN); - __entry->geni_se_dma_if_en_ro = readl(se->base + DMA_IF_EN_RO); - __entry->geni_se_dma_general_cfg = readl(se->base + DMA_GENERAL_CFG); - __entry->geni_se_dma_qsb_trans_cfg = readl(se->base + SE_DMA_QSB_TRANS_CFG); - __entry->geni_se_dma_dbg = readl(se->base + SE_DMA_DEBUG_REG0); - __entry->geni_se_m_irq_en = readl(se->base + SE_GENI_M_IRQ_EN); - __entry->geni_se_s_irq_en = readl(se->base + SE_GENI_S_IRQ_EN); - __entry->geni_se_gsi_event_en = readl(se->base + SE_GSI_EVENT_EN); - __entry->geni_se_irq_en = readl(se->base + SE_IRQ_EN); - __entry->geni_se_ser_m_clk_cfg = readl(se->base + GENI_SER_M_CLK_CFG); - __entry->geni_se_ser_s_clk_cfg = readl(se->base + GENI_SER_S_CLK_CFG); - __entry->geni_se_general_cfg = readl(se->base + GENI_GENERAL_CFG); - __entry->geni_se_output_ctrl = readl(se->base + GENI_OUTPUT_CTRL); - __entry->geni_se_clk_ctrl_ro = readl(se->base + GENI_CLK_CTRL_RO); - __entry->geni_se_fifo_if_disable = readl(se->base + GENI_IF_DISABLE_RO); - __entry->geni_se_fw_multilock_msa = readl(se->base + GENI_FW_MULTILOCK_MSA_RO); - __entry->geni_se_clk_sel = readl(se->base + SE_GENI_CLK_SEL); - ), - - TP_printk("%s: m_cmd0=0x%08x m_irq_status=0x%08x s_cmd0=0x%08x s_irq_status=0x%08x geni_status=0x%08x geni_ios=0x%08x m_cmd_ctrl=0x%08x m_cmd_err=0x%08x m_fw_err=0x%08x tx_fifo_sts=0x%08x rx_fifo_sts=0x%08x tx_watermark=0x%08x rx_watermark=0x%08x rx_watermark_rfr=0x%08x m_gp_length=0x%08x s_gp_length=0x%08x dma_tx_irq=0x%08x dma_rx_irq=0x%08x dma_tx_irq_en=0x%08x dma_rx_irq_en=0x%08x dma_rx_len=0x%08x dma_rx_len_in=0x%08x dma_tx_len=0x%08x dma_tx_len_in=0x%08x dma_tx_ptr_l=0x%08x dma_tx_ptr_h=0x%08x dma_rx_ptr_l=0x%08x dma_rx_ptr_h=0x%08x dma_tx_attr=0x%08x dma_tx_max_burst=0x%08x dma_rx_attr=0x%08x dma_rx_max_burst=0x%08x dma_if_en=0x%08x dma_if_en_ro=0x%08x dma_general_cfg=0x%08x dma_qsb_trans_cfg=0x%08x dma_dbg=0x%08x m_irq_en=0x%08x s_irq_en=0x%08x gsi_event_en=0x%08x se_irq_en=0x%08x ser_m_clk_cfg=0x%08x ser_s_clk_cfg=0x%08x general_cfg=0x%08x output_ctrl=0x%08x clk_ctrl_ro=0x%08x fifo_if_dis=0x%08x fw_multilock_msa=0x%08x clk_sel=0x%08x", - __get_str(geni_se_name), - __entry->geni_se_m_cmd0, __entry->geni_se_m_irq_status, - __entry->geni_se_s_cmd0, __entry->geni_se_s_irq_status, - __entry->geni_se_status, __entry->geni_se_ios, - __entry->geni_se_m_cmd_ctrl, - __entry->geni_se_m_cmd_err, __entry->geni_se_m_fw_err, - __entry->geni_se_tx_fifo_status, __entry->geni_se_rx_fifo_status, - __entry->geni_se_tx_watermark, __entry->geni_se_rx_watermark, - __entry->geni_se_rx_watermark_rfr, - __entry->geni_se_m_gp_length, __entry->geni_se_s_gp_length, - __entry->geni_se_dma_tx_irq, __entry->geni_se_dma_rx_irq, - __entry->geni_se_dma_tx_irq_en, __entry->geni_se_dma_rx_irq_en, - __entry->geni_se_dma_rx_len, __entry->geni_se_dma_rx_len_in, - __entry->geni_se_dma_tx_len, __entry->geni_se_dma_tx_len_in, - __entry->geni_se_dma_tx_ptr_l, __entry->geni_se_dma_tx_ptr_h, - __entry->geni_se_dma_rx_ptr_l, __entry->geni_se_dma_rx_ptr_h, - __entry->geni_se_dma_tx_attr, __entry->geni_se_dma_tx_max_burst, - __entry->geni_se_dma_rx_attr, __entry->geni_se_dma_rx_max_burst, - __entry->geni_se_dma_if_en, __entry->geni_se_dma_if_en_ro, - __entry->geni_se_dma_general_cfg, __entry->geni_se_dma_qsb_trans_cfg, - __entry->geni_se_dma_dbg, - __entry->geni_se_m_irq_en, __entry->geni_se_s_irq_en, - __entry->geni_se_gsi_event_en, __entry->geni_se_irq_en, - __entry->geni_se_ser_m_clk_cfg, __entry->geni_se_ser_s_clk_cfg, - __entry->geni_se_general_cfg, __entry->geni_se_output_ctrl, - __entry->geni_se_clk_ctrl_ro, __entry->geni_se_fifo_if_disable, - __entry->geni_se_fw_multilock_msa, __entry->geni_se_clk_sel) -); - -#endif /* _TRACE_QCOM_GENI_SE_H */ - -/* This part must be outside protection */ -#include diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 982ff4b893b2b..1172bda87abff 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -1168,14 +1168,12 @@ #define PCI_SECPCI_LE_CTRL 0x0c /* Lane Equalization Control Register */ /* Physical Layer 16.0 GT/s */ -#define PCI_PL_16GT_STATUS 0x0c /* 16.0 GT/s Status Register */ #define PCI_PL_16GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ #define PCI_PL_16GT_LE_CTRL_DSP_TX_PRESET_MASK 0x0000000F #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_MASK 0x000000F0 #define PCI_PL_16GT_LE_CTRL_USP_TX_PRESET_SHIFT 4 /* Physical Layer 32.0 GT/s */ -#define PCI_PL_32GT_STATUS 0x0c /* 32.0 GT/s Status Register */ #define PCI_PL_32GT_LE_CTRL 0x20 /* Lane Equalization Control Register */ /* Physical Layer 64.0 GT/s */ diff --git a/lib/scatterlist.c b/lib/scatterlist.c index a04cfa7a4533f..91fe08b7e8869 100644 --- a/lib/scatterlist.c +++ b/lib/scatterlist.c @@ -64,32 +64,6 @@ int sg_nents_for_len(struct scatterlist *sg, u64 len) } EXPORT_SYMBOL(sg_nents_for_len); -/** - * sg_nents_for_dma - return the count of DMA-capable entries in scatterlist - * @sgl: The scatterlist - * @sglen: The current number of entries - * @len: The maximum length of DMA-capable block - * - * Description: - * Determines the number of entries in @sgl which would be permitted in - * DMA-capable transfer if list had been split accordingly, taking into - * account chaining as well. - * - * Returns: - * the number of sgl entries needed - * - **/ -int sg_nents_for_dma(struct scatterlist *sgl, unsigned int sglen, size_t len) -{ - struct scatterlist *sg; - int i, nents = 0; - - for_each_sg(sgl, sg, sglen, i) - nents += DIV_ROUND_UP(sg_dma_len(sg), len); - return nents; -} -EXPORT_SYMBOL(sg_nents_for_dma); - /** * sg_last - return the last scatterlist entry in a list * @sgl: First entry in the scatterlist diff --git a/sound/soc/qcom/sc8280xp.c b/sound/soc/qcom/sc8280xp.c index ffa3d9ac05d08..b18996e412276 100644 --- a/sound/soc/qcom/sc8280xp.c +++ b/sound/soc/qcom/sc8280xp.c @@ -382,7 +382,6 @@ static struct snd_soc_common qcs615_priv_data = { .driver_name = "qcs615", .dapm_widgets = sc8280xp_dapm_widgets, .num_dapm_widgets = ARRAY_SIZE(sc8280xp_dapm_widgets), - .codec_sysclk_set = true, }; static struct snd_soc_common qcm6490_priv_data = {