diff --git a/.clang-format b/.clang-format index 1cc151e2adcc5e..6a3de86ab27a4f 100644 --- a/.clang-format +++ b/.clang-format @@ -481,6 +481,7 @@ ForEachMacros: - 'genradix_for_each' - 'genradix_for_each_from' - 'genradix_for_each_reverse' + - 'guard' - 'hash_for_each' - 'hash_for_each_possible' - 'hash_for_each_possible_rcu' @@ -674,6 +675,7 @@ ForEachMacros: - 'rq_list_for_each' - 'rq_list_for_each_safe' - 'sample_read_group__for_each' + - 'scoped_guard' - 'scsi_for_each_prot_sg' - 'scsi_for_each_sg' - 'sctp_for_each_hentry' diff --git a/.gitignore b/.gitignore index 3044b9590f058f..9875120ea7bde0 100644 --- a/.gitignore +++ b/.gitignore @@ -49,6 +49,7 @@ *.s *.so *.so.dbg +*.spdx.json *.su *.symtypes *.tab.[ch] @@ -57,6 +58,7 @@ *.zst Module.symvers dtbs-list +builtin.order modules.order # @@ -68,6 +70,7 @@ modules.order /vmlinux.32 /vmlinux.map /vmlinux.symvers +/vmlinux.thinlto-index /vmlinux.unstripped /vmlinux-gdb.py /vmlinuz @@ -186,5 +189,8 @@ sphinx_*/ # Rust analyzer configuration /rust-project.json +# rustc error message long types +*.long-type-*.txt + # bc language scripts (not LLVM bitcode) !kernel/time/timeconst.bc diff --git a/.mailmap b/.mailmap index a009f73d7ea51e..12f3acdebd7226 100644 --- a/.mailmap +++ b/.mailmap @@ -36,13 +36,14 @@ Alexander Lobakin Alexander Mikhalitsyn Alexander Mikhalitsyn Alexander Mikhalitsyn -Alexander Sverdlin -Alexander Sverdlin -Alexander Sverdlin -Alexander Sverdlin -Alexander Sverdlin -Alexander Sverdlin -Alexander Sverdlin +Alexander Sverdlin +Alexander Sverdlin +Alexander Sverdlin +Alexander Sverdlin +Alexander Sverdlin +Alexander Sverdlin +Alexander Sverdlin +Alexander Sverdlin Alexandre Belloni Alexandre Ghiti Alexei Avshalom Lazar @@ -117,6 +118,7 @@ Asutosh Das Atish Patra Atish Patra Avaneesh Kumar Dwivedi +Avri Altman Axel Dyks Axel Lin Balakrishna Godavarthi @@ -126,6 +128,7 @@ Baolin Wang Baolin Wang Baolin Wang Baolin Wang +Baoquan He Barry Song <21cnbao@gmail.com> Barry Song Barry Song @@ -201,9 +204,9 @@ Christophe Ricard Christopher Obbard Christoph Hellwig Christoph Manszewski -Chuck Lever -Chuck Lever -Chuck Lever +Chuck Lever +Chuck Lever +Chuck Lever Claudiu Beznea Colin Ian King Corey Minyard @@ -370,6 +373,7 @@ Jarkko Sakkinen Jason Gunthorpe Jason Gunthorpe Jason Gunthorpe +Jason Wang Jason Xing Javi Merino @@ -401,6 +405,7 @@ Jesper Dangaard Brouer Jesper Dangaard Brouer Jesper Dangaard Brouer Jesper Dangaard Brouer +Jesse Brandeburg Jessica Zhang Jessica Zhang Jessica Zhang @@ -435,6 +440,7 @@ John Stultz Jonas Gorski Jonathan Cameron Jordan Crouse +Jorge Ramirez-Ortiz @@ -448,6 +454,7 @@ Juha Yrjola Juha Yrjola Julien Thierry Justin Iurman +Ira Weiny Iskren Chernev Kalle Valo Kalle Valo @@ -524,7 +531,8 @@ Luca Ceresoli Luca Weiss Lucas De Marchi Lukasz Luba -Luo Jie +Luo Jie +Luo Jie Lance Yang Lance Yang Maciej W. Rozycki @@ -634,7 +642,6 @@ Nicholas Piggin Nicholas Piggin Nicholas Piggin Nicholas Piggin -Nick Desaulniers Nicolas Ferre Nicolas Pitre Nicolas Pitre @@ -701,6 +708,10 @@ Qi Zheng Quentin Monnet Quentin Monnet Quentin Perret +Radu Rendec +Radu Rendec +Radu Rendec +Radu Rendec Rae Moar Rafael J. Wysocki Rajeev Nandan diff --git a/CREDITS b/CREDITS index 17962bdd6dbdda..84793a967a0b2d 100644 --- a/CREDITS +++ b/CREDITS @@ -197,6 +197,9 @@ S: Hauptstrasse 19 S: 79837 St. Blasien S: Germany +N: Ferenc Bakonyi +D: Hercules graphics adapter framebuffer driver + N: Krishna Balasubramanian E: balasub@cis.ohio-state.edu D: Wrote SYS V IPC (part of standard kernel since 0.99.10) @@ -2241,6 +2244,7 @@ S: Canada N: Krzysztof Kozlowski E: krzk@kernel.org D: NFC network subsystem and drivers maintainer +D: Samsung S2M/S5M Multifunction PMIC device drivers for Exynos platforms N: Christian Krafft D: PowerPC Cell support @@ -2804,6 +2808,7 @@ D: Some of PAS 16 mixer & PCM support, inet6-apps N: William (Bill) Metzenthen E: billm@suburbia.net +E: billm@melbpc.org.au D: Author of the FPU emulator. D: Minor kernel hacker for other lost causes (Hercules mono, etc). S: 22 Parker Street @@ -3368,6 +3373,10 @@ N: Anil Ravindranath E: anil_ravindranath@pmc-sierra.com D: PMC-Sierra MaxRAID driver +N: Dwaipayan Ray +E: dwaipayanray1@gmail.com +D: checkpatch improvements + N: Eric S. Raymond E: esr@thyrsus.com W: http://www.tuxedo.org/~esr/ @@ -3668,7 +3677,17 @@ D: Macintosh IDE Driver N: Peter De Schrijver E: stud11@cc4.kuleuven.ac.be +E: p2@mind.be +E: peter.de-schrijver@nokia.com +E: pdeschrijver@nvidia.com +E: p2@psychaos.be +D: Apollo Domain workstations +D: Ariadne and Hydra Amiga Ethernet drivers +D: IBM PS/2, Microchannel, and Token Ring support D: Mitsumi CD-ROM driver patches March version +D: TWL4030 power management and audio codec driver +D: OMAP power management +D: NVIDIA Tegra clock and BPMP drivers, among many other things S: Molenbaan 29 S: B2240 Zandhoven S: Belgium diff --git a/Documentation/ABI/obsolete/sysfs-driver-ivpu b/Documentation/ABI/obsolete/sysfs-driver-ivpu new file mode 100644 index 00000000000000..b906e714972930 --- /dev/null +++ b/Documentation/ABI/obsolete/sysfs-driver-ivpu @@ -0,0 +1,30 @@ +What: /sys/bus/pci/drivers/intel_vpu/.../sched_mode +Date: October 2024 +KernelVersion: 6.12 +Contact: dri-devel@lists.freedesktop.org +Description: Current NPU scheduling mode. Returns one of the following strings: + - "HW" - Hardware Scheduler mode + - "OS" - Operating System Scheduler mode + Read-only. + Deprecated since the "OS" scheduling mode is not usable + and will be removed from future versions of the driver. + Will be removed in 2027 + +What: /sys/bus/pci/drivers/intel_vpu/.../npu_max_frequency_mhz +Date: April 2025 +KernelVersion: 6.15 +Contact: dri-devel@lists.freedesktop.org +Description: Legacy alias for /sys/bus/pci/drivers/intel_vpu/.../freq/hw_max_freq. + Shows maximum frequency in MHz of the NPU's data processing unit. + Read-only. + Will be removed in 2027 + +What: /sys/bus/pci/drivers/intel_vpu/.../npu_current_frequency_mhz +Date: April 2025 +KernelVersion: 6.15 +Contact: dri-devel@lists.freedesktop.org +Description: Legacy alias for /sys/bus/pci/drivers/intel_vpu/.../freq/current_freq. + Shows current frequency in MHz of the NPU's data processing unit. + The value is read only when the device is active; otherwise it returns 0. + Read-only. + Will be removed in 2027 diff --git a/Documentation/ABI/stable/sysfs-class-infiniband b/Documentation/ABI/stable/sysfs-class-infiniband index 694f23a03a2871..7ba1161034291c 100644 --- a/Documentation/ABI/stable/sysfs-class-infiniband +++ b/Documentation/ABI/stable/sysfs-class-infiniband @@ -148,17 +148,17 @@ Description: **Data info**: port_xmit_data: (RO) Total number of data octets, divided by 4 - (lanes), transmitted on all VLs. This is 64 bit counter + (lanes), transmitted on all VLs. This is a 64-bit counter port_rcv_data: (RO) Total number of data octets, divided by 4 - (lanes), received on all VLs. This is 64 bit counter. + (lanes), received on all VLs. This is a 64-bit counter. port_xmit_packets: (RO) Total number of packets transmitted on all VLs from this port. This may include packets with errors. - This is 64 bit counter. + This is a 64-bit counter. port_rcv_packets: (RO) Total number of packets (this may include - packets containing Errors. This is 64 bit counter. + packets containing Errors). This is a 64-bit counter. link_downed: (RO) Total number of times the Port Training state machine has failed the link error recovery process and downed diff --git a/Documentation/ABI/testing/configfs-thunderbolt_stream b/Documentation/ABI/testing/configfs-thunderbolt_stream new file mode 100644 index 00000000000000..7abc6b73a1e4c0 --- /dev/null +++ b/Documentation/ABI/testing/configfs-thunderbolt_stream @@ -0,0 +1,83 @@ +What: /sys/kernel/config/thunderbolt/stream/. +Date: Sep 2026 +KernelVersion: v7.2 +Contact: Mika Westerberg +Description: + Configuration group for a stream Thunderbolt/USB4 + service. It is possible to create groups even if there + is no connection yet to the other host. Once a + connection established and there is stream service on + the remote side that matches, this configuration is + applied to it. + + To find the service name you can run tblist from tbtools [1]: + + # tblist -A + ... + Domain 0 Route 3 Index 0: stream + + [1] https://github.com/intel/tbtools + +What: /sys/kernel/config/thunderbolt/stream/./$name +Date: Sep 2026 +KernelVersion: v7.2 +Contact: Mika Westerberg +Description: + Creates new stream with $name and fills it with the + default values. If there is an advertised remote stream + with the same name, uses its values as the default. + +What: /sys/kernel/config/thunderbolt/stream/./$name/index +Date: Sep 2026 +KernelVersion: v7.2 +Contact: Mika Westerberg +Description: + This matches the X in /dev/tbstreamX and allows userspace + to map the configfs directory to the corresponding character + device. + +What: /sys/kernel/config/thunderbolt/stream/./$name/in_hopid +Date: Sep 2026 +KernelVersion: v7.2 +Contact: Mika Westerberg +Description: + In HopID used with the read path of the tunnel. Available HopIDs + for tunneling start from 8. You can pass also -1 for automatic + allocation. The allocated value can be read here. Writing 0 will + de-allocate if the stream is not in use. + + To figure out the maximum HopID you can run tbget from + tbtools for the lane adapter. For example below we check + for lane adapter number 1 (first USB4 port): + + # tbget -r 0 -a 1 -D ADP_CS_5.Max\ Input\ HopID + 19 + + This allows to use anything between 8 and 19 inclusive. + +What: /sys/kernel/config/thunderbolt/stream/./$name/out_hopid +Date: Sep 2026 +KernelVersion: v7.2 +Contact: Mika Westerberg +Description: + Out HopID used with the write path of the tunnel. Available HopIDs + for tunneling start from 8. You can pass also -1 for automatic + allocation. The allocated value can be read here. Writing 0 will + de-allocate if the stream is not in use. See @in_hopid + for how to figure out the maximum HopID. + +What: /sys/kernel/config/thunderbolt/stream/./$name/ring_size +Date: Sep 2026 +KernelVersion: v7.2 +Contact: Mika Westerberg +Description: + Size of the TX/RX rings. Can be adjusted between 32 and + 4096. The default is 256. + +What: /sys/kernel/config/thunderbolt/stream/./$name/throttling +Date: Sep 2026 +KernelVersion: v7.2 +Contact: Mika Westerberg +Description: + Interrupt throttling rate in ns. Lower values can give + better latency. The default is 8192 ns. diff --git a/Documentation/ABI/testing/debugfs-vfio b/Documentation/ABI/testing/debugfs-vfio index 70ec2d45468629..ed2f29c3a9b415 100644 --- a/Documentation/ABI/testing/debugfs-vfio +++ b/Documentation/ABI/testing/debugfs-vfio @@ -29,3 +29,29 @@ Date: Oct 2025 KernelVersion: 6.18 Contact: Cédric Le Goater Description: Read the migration features of the vfio device. + +What: /sys/kernel/debug/vfio//pci +Date: June 2026 +KernelVersion: 7.2 +Contact: Alex Williamson +Description: This debugfs file directory is used for debugging + VFIO PCI devices. + +What: /sys/kernel/debug/vfio//pci/nointxmask +Date: June 2026 +KernelVersion: 7.2 +Contact: Alex Williamson +Description: Read the nointxmask policy latched for this device. This + policy governs whether the device may use PCI 2.3 style + INTx masking when supported, reporting a value of "N", or + requires APIC level INTx masking, reporting a value of "Y". + +What: /sys/kernel/debug/vfio//pci/disable_idle_d3 +Date: June 2026 +KernelVersion: 7.2 +Contact: Alex Williamson +Description: Read the disable_idle_d3 policy latched for this device. This + policy governs whether the device PM runtime usage count is + kept elevated while the device is bound to the driver and + unused, reporting a value of "Y", or decremented to allow the + device to enter a low power state, reporting a value of "N". diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/testing/sysfs-bus-iio index 4fc9f6bd428121..d8d6d85235b01d 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -764,10 +764,13 @@ Contact: linux-iio@vger.kernel.org Description: Specifies the output powerdown mode. DAC output stage is disconnected from the amplifier and + 500ohm_to_gnd: connected to ground via a 500Ohm resistor, 1kohm_to_gnd: connected to ground via an 1kOhm resistor, 2.5kohm_to_gnd: connected to ground via a 2.5kOhm resistor, + 3.85kohm_to_gnd: connected to ground via a 3.85kOhm resistor, 6kohm_to_gnd: connected to ground via a 6kOhm resistor, 7.7kohm_to_gnd: connected to ground via a 7.7kOhm resistor, + 16kohm_to_gnd: connected to ground via a 16kOhm resistor, 20kohm_to_gnd: connected to ground via a 20kOhm resistor, 32kohm_to_gnd: connected to ground via a 32kOhm resistor, 42kohm_to_gnd: connected to ground via a 42kOhm resistor, @@ -1510,21 +1513,24 @@ Contact: linux-iio@vger.kernel.org Description: Description of the scan element data storage within the buffer and hence the form in which it is read from user-space. - Form is [be|le]:[s|u]bits/storagebits[>>shift]. - be or le specifies big or little endian. s or u specifies if - signed (2's complement) or unsigned. bits is the number of bits - of data and storagebits is the space (after padding) that it - occupies in the buffer. shift if specified, is the shift that - needs to be applied prior to masking out unused bits. Some - devices put their data in the middle of the transferred elements - with additional information on both sides. Note that some - devices will have additional information in the unused bits - so to get a clean value, the bits value must be used to mask - the buffer output value appropriately. The storagebits value - also specifies the data alignment. So s48/64>>2 will be a - signed 48 bit integer stored in a 64 bit location aligned to - a 64 bit boundary. To obtain the clean value, shift right 2 - and apply a mask to zero the top 16 bits of the result. + Form is [be|le]:[f|s|u]bits/storagebits[>>shift]. + be or le specifies big or little endian. f means floating-point + (IEEE 754 binary format), s means signed (2's complement), u means + unsigned. bits is the number of bits of data and storagebits is the + space (after padding) that it occupies in the buffer; when using a + floating-point format, bits must be one of the width values defined + in the IEEE 754 standard for binary interchange formats (e.g. 16 + indicates the binary16 format for half-precision numbers). shift, + if specified, is the shift that needs to be applied prior to + masking out unused bits. Some devices put their data in the middle + of the transferred elements with additional information on both + sides. Note that some devices will have additional information in + the unused bits, so to get a clean value the bits value must be + used to mask the buffer output value appropriately. The storagebits + value also specifies the data alignment. So s48/64>>2 will be a + signed 48 bit integer stored in a 64 bit location aligned to a 64 + bit boundary. To obtain the clean value, shift right 2 and apply a + mask to zero the top 16 bits of the result. For other storage combinations this attribute will be extended appropriately. @@ -1752,6 +1758,21 @@ Description: measurement from channel Y. Units after application of scale and offset are milliamps. +What: /sys/bus/iio/devices/iio:deviceX/in_rot_quaternionaxis_raw +KernelVersion: 7.1 +Contact: linux-iio@vger.kernel.org +Description: + Raw value of {x, y, z} components of the quaternion vector. These + components represent the axis about which a rotation occurs, and are + subject to the following constraints: + + - the quaternion vector is normalized, i.e. w^2 + x^2 + y^2 + z^2 = 1 + - the rotation angle is within the [-pi, pi] range, i.e. the w + component (which represents the amount of rotation) is non-negative + + These constraints allow the w value to be calculated from the other + components: w = sqrt(1 - (x^2 + y^2 + z^2)). + What: /sys/.../iio:deviceX/in_energy_en What: /sys/.../iio:deviceX/in_distance_en What: /sys/.../iio:deviceX/in_velocity_sqrt(x^2+y^2+z^2)_en @@ -1959,6 +1980,23 @@ Description: Raw (unscaled no offset etc.) resistance reading. Units after application of scale and offset are ohms. +What: /sys/bus/iio/devices/iio:deviceX/in_coverageY_raw +KernelVersion: 7.2 +Contact: linux-iio@vger.kernel.org +Description: + Raw (unscaled no offset etc.) coverage reading. Used for sensors + that report fractional coverage as a percentage, such as leak + detectors where the value represents what portion of the sensing + element is wetted. Units after application of scale and offset are + percent. + +What: /sys/bus/iio/devices/iio:deviceX/in_coverageY_scale +KernelVersion: 7.2 +Contact: linux-iio@vger.kernel.org +Description: + Scale to be applied to in_coverageY_raw to obtain coverage + in percent. + What: /sys/bus/iio/devices/iio:deviceX/heater_enable KernelVersion: 4.1.0 Contact: linux-iio@vger.kernel.org diff --git a/Documentation/ABI/testing/sysfs-bus-pci-drivers-xhci_hcd b/Documentation/ABI/testing/sysfs-bus-pci-drivers-xhci_hcd index d10e6de3adb25a..991765d84201e1 100644 --- a/Documentation/ABI/testing/sysfs-bus-pci-drivers-xhci_hcd +++ b/Documentation/ABI/testing/sysfs-bus-pci-drivers-xhci_hcd @@ -22,7 +22,7 @@ Description: Reading this attribute gives the state of the DbC. It can be one of the following states: disabled, enabled, - initialized, connected, configured and stalled. + initialized, connected, configured or suspended. What: /sys/bus/pci/drivers/xhci_hcd/.../dbc_idVendor Date: March 2023 diff --git a/Documentation/ABI/testing/sysfs-class-hwmon b/Documentation/ABI/testing/sysfs-class-hwmon index cfd0d0bab48398..b185bdfc7186a7 100644 --- a/Documentation/ABI/testing/sysfs-class-hwmon +++ b/Documentation/ABI/testing/sysfs-class-hwmon @@ -27,6 +27,20 @@ Description: Some devices have a variable update rate or interval. This attribute can be used to change it to the desired value. +What: /sys/class/hwmon/hwmonX/update_interval_us +Description: + The interval at which the chip will update readings, + expressed in microseconds. + Unit: microsecond + + RW + + Some devices have a variable update rate or interval and + require finer-than-millisecond control. + This attribute can be used to change it to the desired value. + Drivers implementing this attribute should also implement + update_interval for millisecond-based userspace interfaces. + What: /sys/class/hwmon/hwmonX/inY_min Description: Voltage min value. diff --git a/Documentation/ABI/testing/sysfs-class-ieee80211-rtw89 b/Documentation/ABI/testing/sysfs-class-ieee80211-rtw89 new file mode 100644 index 00000000000000..7dfdce08a42f3f --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-ieee80211-rtw89 @@ -0,0 +1,24 @@ +What: /sys/class/ieee80211/phyX/rtw89_usb/serial_number +Date: May 2026 +Contact: Johnson Tsai , linux-wireless@vger.kernel.org +Description: (Read) Serial number burned into EFUSE of the RTL8852CU-based + USB Wi-Fi adapter. Only present on devices that set the + RTW89_QUIRK_HW_INFO_SYSFS quirk (currently VID 0x28de / + PID 0x2432). + + Format: %10phN (5 raw bytes printed as 10 lowercase hex + digits, no separators). + + Example: 3642000123 + +What: /sys/class/ieee80211/phyX/rtw89_usb/uuid +Date: May 2026 +Contact: Johnson Tsai , linux-wireless@vger.kernel.org +Description: (Read) UUID burned into EFUSE of the RTL8852CU-based USB Wi-Fi + adapter. Only present on devices that set the + RTW89_QUIRK_HW_INFO_SYSFS quirk (currently VID 0x28de / + PID 0x2432). + + Format: %pUb (RFC 4122 UUID in lowercase with hyphens). + + Example: aaec2b7c-0a55-4727-8de0-b30febccbbaa diff --git a/Documentation/ABI/testing/sysfs-class-led b/Documentation/ABI/testing/sysfs-class-led index 0313b82644f244..d4c918cc11a127 100644 --- a/Documentation/ABI/testing/sysfs-class-led +++ b/Documentation/ABI/testing/sysfs-class-led @@ -22,8 +22,8 @@ Description: For additional details please refer to Documentation/leds/leds-class-multicolor.rst. - The value is between 0 and - /sys/class/leds//max_brightness. + The value is between 0 and /sys/class/leds//max_brightness + and is represented by as a decimal. Writing 0 to this file clears active trigger. diff --git a/Documentation/ABI/testing/sysfs-class-led-multicolor b/Documentation/ABI/testing/sysfs-class-led-multicolor index 16fc827b10cb60..62ce58f393d647 100644 --- a/Documentation/ABI/testing/sysfs-class-led-multicolor +++ b/Documentation/ABI/testing/sysfs-class-led-multicolor @@ -16,9 +16,22 @@ Date: March 2020 KernelVersion: 5.9 Contact: Dan Murphy Description: read/write - This file contains array of integers. Order of components is - described by the multi_index array. The maximum intensity should - not exceed /sys/class/leds//max_brightness. + This file contains an array of integers. The order of components + is described by the multi_index array. The maximum intensity value + supported by each color component is described by the multi_max_intensity + file. Writing intensity values larger than the maximum value of a + given color component will result in those values being clamped. + + For additional details please refer to + Documentation/leds/leds-class-multicolor.rst. + +What: /sys/class/leds//multi_max_intensity +Date: May 2026 +KernelVersion: 7.2 +Contact: Armin Wolf +Description: read + This file contains an array of integers describing the maximum + intensity value for each intensity component. For additional details please refer to Documentation/leds/leds-class-multicolor.rst. diff --git a/Documentation/ABI/testing/sysfs-class-power-bd71828 b/Documentation/ABI/testing/sysfs-class-power-bd71828 new file mode 100644 index 00000000000000..2d451e1c833664 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-power-bd71828 @@ -0,0 +1,12 @@ +What: /sys/class/power_supply/bd71828_ac/auto_dcin_limit +Description: + Enable/Disable automatic management of input current limit + (ILIM_DCIN_EN bit). + + Possible values are: + + ============ =========================================== + 1 automatic adjustment of input current limit + 0 no adjustment of input current limit. This + helps for more unusual power sources like + solar modules. diff --git a/Documentation/ABI/testing/sysfs-class-reboot-mode-reboot_modes b/Documentation/ABI/testing/sysfs-class-reboot-mode-reboot_modes index a16c54ab841bb4..4306966b7fcc33 100644 --- a/Documentation/ABI/testing/sysfs-class-reboot-mode-reboot_modes +++ b/Documentation/ABI/testing/sysfs-class-reboot-mode-reboot_modes @@ -2,33 +2,36 @@ What: /sys/class/reboot-mode//reboot_modes Date: March 2026(TBD) KernelVersion: TBD Contact: linux-pm@vger.kernel.org - Description: +Description: This interface exposes the reboot-mode arguments registered with the reboot-mode framework. It is a read-only interface and provides a space separated list of reboot-mode arguments supported on the current platform. Example: + recovery fastboot bootloader The exact sysfs path may vary depending on the name of the driver that registers the arguments. - Example: + Example:: + /sys/class/reboot-mode/nvmem-reboot-mode/reboot_modes /sys/class/reboot-mode/syscon-reboot-mode/reboot_modes /sys/class/reboot-mode/qcom-pon/reboot_modes The supported arguments can be used by userspace to invoke device reset using the standard reboot() system - call interface, with the "argument" as string to "*arg" - parameter along with LINUX_REBOOT_CMD_RESTART2. + call interface, with the "argument" as string to ``*arg`` + parameter along with ``LINUX_REBOOT_CMD_RESTART2``. A driver can expose the supported arguments by registering them with the reboot-mode framework using the property names that follow the mode- format. Example: - mode-bootloader, mode-recovery. + + mode-bootloader, mode-recovery This attribute is useful for scripts or initramfs logic that need to programmatically determine diff --git a/Documentation/ABI/testing/sysfs-devices-faux-tdx-host b/Documentation/ABI/testing/sysfs-devices-faux-tdx-host new file mode 100644 index 00000000000000..c9cb273abf3203 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-devices-faux-tdx-host @@ -0,0 +1,26 @@ +What: /sys/devices/faux/tdx_host/version +Contact: linux-coco@lists.linux.dev +Description: (RO) Report the version of the loaded TDX module. + Formatted as "major.minor.update". Used by TDX module + update tooling. Example: "1.2.03". + +What: /sys/devices/faux/tdx_host/seamldr_version +Contact: linux-coco@lists.linux.dev +Description: (RO) Report the version of the loaded P-SEAMLDR. + Formatted as a TDX module version. Used by TDX module + update tooling. + +What: /sys/devices/faux/tdx_host/num_remaining_updates +Contact: linux-coco@lists.linux.dev +Description: (RO) Report the number of remaining updates. TDX maintains a + log about each TDX module that has been loaded. This log has + a finite size, which limits the number of TDX module updates + that can be performed. + + After each successful update, the number reduces by one. Once it + reaches zero, further updates will fail until next reboot. The + number is always zero if the P-SEAMLDR doesn't support updates. + + See Intel Trust Domain Extensions - SEAM Loader (SEAMLDR) + Interface Specification, Chapter "SEAMLDR_INFO" and Chapter + "SEAMLDR.INSTALL" for more information. diff --git a/Documentation/ABI/testing/sysfs-driver-dell-dw5826e-reset b/Documentation/ABI/testing/sysfs-driver-dell-dw5826e-reset new file mode 100644 index 00000000000000..a665e265633ff2 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-dell-dw5826e-reset @@ -0,0 +1,9 @@ +What: /sys/bus/platform/devices//wwan_reset +Date: April 2026 +KernelVersion: 7.2 +Contact: Jackbb Wu +Description: + Writing to this file triggers a Platform Level Device Reset + (PLDR) of the Dell DW5826e WWAN module via an ACPI _DSM + method. This can be used to recover the modem when it is in + a frozen state and unable to respond to USB commands. diff --git a/Documentation/ABI/testing/sysfs-driver-ivpu b/Documentation/ABI/testing/sysfs-driver-ivpu new file mode 100644 index 00000000000000..91685774edfccf --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-ivpu @@ -0,0 +1,65 @@ +What: /sys/bus/pci/drivers/intel_vpu/.../npu_busy_time_us +Date: May 2024 +KernelVersion: 6.11 +Contact: dri-devel@lists.freedesktop.org +Description: Time in microseconds that the device spent executing jobs. The time is + counted when and only when there are jobs submitted to firmware. This time + can be used to measure the utilization of NPU, either by calculating the + difference between two timepoints or monitoring utilization percentage by + reading periodically. Recommended read period is 1 second to avoid impact + on job submission performance. Read-only. + +What: /sys/bus/pci/drivers/intel_vpu/.../npu_memory_utilization +Date: Jan 2025 +KernelVersion: 6.15 +Contact: dri-devel@lists.freedesktop.org +Description: Current NPU memory utilization in bytes. Reports the total size of all + resident buffer objects allocated for NPU use. Read-only. + +What: /sys/bus/pci/drivers/intel_vpu/.../freq/hw_min_freq +Date: April 2026 +KernelVersion: 7.2 +Contact: dri-devel@lists.freedesktop.org +Description: Minimum frequency in MHz supported by the NPU hardware. This is a + hardware capability and cannot be changed. Read-only. + +What: /sys/bus/pci/drivers/intel_vpu/.../freq/hw_efficient_freq +Date: April 2026 +KernelVersion: 7.2 +Contact: dri-devel@lists.freedesktop.org +Description: Most efficient operating frequency in MHz for the NPU. This represents + the frequency at which the NPU operates most efficiently in terms of power + and performance. Read-only. + +What: /sys/bus/pci/drivers/intel_vpu/.../freq/hw_max_freq +Date: April 2026 +KernelVersion: 7.2 +Contact: dri-devel@lists.freedesktop.org +Description: Maximum frequency in MHz supported by the NPU hardware. This is a + hardware capability and cannot be changed. Read-only. + +What: /sys/bus/pci/drivers/intel_vpu/.../freq/current_freq +Date: April 2026 +KernelVersion: 7.2 +Contact: dri-devel@lists.freedesktop.org +Description: Current operating frequency in MHz of the NPU. The value is valid only + when the device is active; returns 0 when idle. The actual frequency may + be lower than the requested range due to power or thermal constraints. + Read-only. + +What: /sys/bus/pci/drivers/intel_vpu/.../freq/set_min_freq +Date: April 2026 +KernelVersion: 7.2 +Contact: dri-devel@lists.freedesktop.org +Description: Configured minimum operating frequency in MHz (50XX devices and newer). + Values written are clamped to hardware limits (hw_min_freq to hw_max_freq). + If set_min_freq exceeds set_max_freq, the driver clamps set_min_freq to + set_max_freq when selecting the operating frequency. Read-write. + +What: /sys/bus/pci/drivers/intel_vpu/.../freq/set_max_freq +Date: April 2026 +KernelVersion: 7.2 +Contact: dri-devel@lists.freedesktop.org +Description: Configured maximum operating frequency in MHz (50XX devices and newer). + Values written are clamped to hardware limits (hw_min_freq to hw_max_freq). + Read-write. diff --git a/Documentation/ABI/testing/sysfs-driver-qat_kpt b/Documentation/ABI/testing/sysfs-driver-qat_kpt new file mode 100644 index 00000000000000..c6480ea1fa4f8b --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-qat_kpt @@ -0,0 +1,97 @@ +What: /sys/bus/pci/devices//qat_kpt/ +Date: August 2026 +KernelVersion: 7.2 +Contact: qat-linux@intel.com +Description: + Directory containing attributes related to the QAT Key Protection + Technology (KPT) feature. KPT allows cryptographic keys to be used + by the accelerator without being exposed in plaintext to the host. + +What: /sys/bus/pci/devices//qat_kpt/enable +Date: August 2026 +KernelVersion: 7.2 +Contact: qat-linux@intel.com +Description: + (RW) Enables or disables Key Protection Technology (KPT). + + Write 1 to enable KPT, or 0 to disable it. + + Example usage:: + + # cat /sys/bus/pci/devices//qat_kpt/enable + 0 + # echo 1 > /sys/bus/pci/devices//qat_kpt/enable + + This attribute is only available on devices that support KPT. + +What: /sys/bus/pci/devices//qat_kpt/swk_cnt_per_fn +Date: August 2026 +KernelVersion: 7.2 +Contact: qat-linux@intel.com +Description: + (RW) Configures the maximum number of KPT symmetric wrapping keys + (SWKs) that a Virtual Function (VF) may be associated with. + + Valid values range from 0 to 128. A value of 0 indicates no limit. + + Example usage:: + + # cat /sys/bus/pci/devices//qat_kpt/swk_cnt_per_fn + 128 + # echo 128 > /sys/bus/pci/devices//qat_kpt/swk_cnt_per_fn + + This attribute is only available on devices that support KPT. + +What: /sys/bus/pci/devices//qat_kpt/swk_cnt_per_pasid +Date: August 2026 +KernelVersion: 7.2 +Contact: qat-linux@intel.com +Description: + (RW) Configures the maximum number of KPT symmetric wrapping keys + (SWKs) per Process Address Space ID (PASID). + + Valid values range from 0 to 128. A value of 0 indicates no limit. + + Example usage:: + + # cat /sys/bus/pci/devices//qat_kpt/swk_cnt_per_pasid + 128 + # echo 128 > /sys/bus/pci/devices//qat_kpt/swk_cnt_per_pasid + + This attribute is only available on devices that support KPT. + +What: /sys/bus/pci/devices//qat_kpt/swk_max_ttl +Date: August 2026 +KernelVersion: 7.2 +Contact: qat-linux@intel.com +Description: + (RW) Configures the maximum Time To Live (TTL) for KPT symmetric + wrapping keys (SWK). + + Valid values range from 0 to 31536000 seconds. A value of 0 + indicates that the SWK TTL is unlimited. + + Example usage:: + + # cat /sys/bus/pci/devices//qat_kpt/swk_max_ttl + 1000 + # echo 1000 > /sys/bus/pci/devices//qat_kpt/swk_max_ttl + + This attribute is only available on devices that support KPT. + +What: /sys/bus/pci/devices//qat_kpt/swk_shared +Date: August 2026 +KernelVersion: 7.2 +Contact: qat-linux@intel.com +Description: + (RW) Controls shared mode for KPT symmetric wrapping keys (SWK). + + Write 1 to enable shared mode, or 0 to disable it (non-shared mode). + + Example usage:: + + # cat /sys/bus/pci/devices//qat_kpt/swk_shared + 0 + # echo 1 > /sys/bus/pci/devices//qat_kpt/swk_shared + + This attribute is only available on devices that support KPT. diff --git a/Documentation/ABI/testing/sysfs-driver-qat_rl b/Documentation/ABI/testing/sysfs-driver-qat_rl index d534f89b497195..422333a0eb6917 100644 --- a/Documentation/ABI/testing/sysfs-driver-qat_rl +++ b/Documentation/ABI/testing/sysfs-driver-qat_rl @@ -209,7 +209,7 @@ Date: January 2024 KernelVersion: 6.7 Contact: qat-linux@intel.com Description: - (RW) This file will return the remaining capability for a + (RW) This file will return the remaining capacity for a particular service/sla. This is the remaining value that a new SLA can be set to or a current SLA can be increased with. diff --git a/Documentation/ABI/testing/sysfs-driver-tegra-fuse b/Documentation/ABI/testing/sysfs-driver-tegra-fuse index b8936fad2ccfc8..47d5513100f66a 100644 --- a/Documentation/ABI/testing/sysfs-driver-tegra-fuse +++ b/Documentation/ABI/testing/sysfs-driver-tegra-fuse @@ -1,6 +1,6 @@ What: /sys/devices/*//fuse Date: February 2014 -Contact: Peter De Schrijver +Contact: Thierry Reding Description: read-only access to the efuses on Tegra20, Tegra30, Tegra114 and Tegra124 SoC's from NVIDIA. The efuses contain write once data programmed at the factory. The data is laid out in 32bit diff --git a/Documentation/ABI/testing/sysfs-fs-f2fs b/Documentation/ABI/testing/sysfs-fs-f2fs index 423ec40e2e4e2d..1b58c029abd0df 100644 --- a/Documentation/ABI/testing/sysfs-fs-f2fs +++ b/Documentation/ABI/testing/sysfs-fs-f2fs @@ -270,7 +270,8 @@ Description: Shows all enabled kernel features. inode_checksum, flexible_inline_xattr, quota_ino, inode_crtime, lost_found, verity, sb_checksum, casefold, readonly, compression, test_dummy_encryption_v2, - atomic_write, pin_file, encrypted_casefold, linear_lookup. + atomic_write, pin_file, encrypted_casefold, linear_lookup, + fserror. What: /sys/fs/f2fs//inject_rate Date: May 2016 @@ -1000,4 +1001,4 @@ Contact: "Chao Yu" Description: It can be used to tune priority of f2fs critical task, e.g. f2fs_ckpt, f2fs_gc threads, limitation as below: - it requires user has CAP_SYS_NICE capability. - - the range is [100, 139], by default the value is 100. + - the range is [100, 139], by default the value is 120. diff --git a/Documentation/ABI/testing/sysfs-kernel-mm-damon b/Documentation/ABI/testing/sysfs-kernel-mm-damon index 2424237ebb105c..b73e6bc28ea5fc 100644 --- a/Documentation/ABI/testing/sysfs-kernel-mm-damon +++ b/Documentation/ABI/testing/sysfs-kernel-mm-damon @@ -84,6 +84,13 @@ Description: Writing an integer to this file sets the 'address unit' parameter of the given operations set of the context. Reading the file returns the last-written 'address unit' value. +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//pause +Date: Mar 2026 +Contact: SeongJae Park +Description: Writing a boolean keyword to this file sets the 'pause' request + parameter for the context. Reading the file returns the + last-written 'pause' value. + What: /sys/kernel/mm/damon/admin/kdamonds//contexts//monitoring_attrs/intervals/sample_us Date: Mar 2022 Contact: SeongJae Park @@ -322,6 +329,18 @@ Contact: SeongJae Park Description: Writing to and reading from this file sets and gets the goal-based effective quota auto-tuning algorithm to use. +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//quotas/fail_charge_num +Date: Mar 2026 +Contact: SeongJae Park +Description: Writing to and reading from this file sets and gets the + action-failed memory quota charging ratio numerator. + +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//quotas/fail_charge_denom +Date: Mar 2026 +Contact: SeongJae Park +Description: Writing to and reading from this file sets and gets the + action-failed memory quota charging ratio denominator. + What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//quotas/weights/sz_permil Date: Mar 2022 Contact: SeongJae Park @@ -377,15 +396,20 @@ Contact: SeongJae Park Description: Writing to and reading from this file sets and gets the low watermark of the scheme in permil. -What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//filters/nr_filters -Date: Dec 2022 +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//core_filters +Date: Feb 2025 +Contact: SeongJae Park +Description: Directory for DAMON core layer-handled DAMOS filters. + +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//core_filters/nr_filters +Date: Feb 2025 Contact: SeongJae Park Description: Writing a number 'N' to this file creates the number of directories for setting filters of the scheme named '0' to - 'N-1' under the filters/ directory. + 'N-1' under the core_filters/ directory. -What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//filters//type -Date: Dec 2022 +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//core_filters//type +Date: Feb 2025 Contact: SeongJae Park Description: Writing to and reading from this file sets and gets the type of the memory of the interest. 'anon' for anonymous pages, @@ -393,77 +417,78 @@ Description: Writing to and reading from this file sets and gets the type of 'addr' for address range (an open-ended interval), or 'target' for DAMON monitoring target can be written and read. -What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//filters//memcg_path -Date: Dec 2022 +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//core_filters//memcg_path +Date: Feb 2025 Contact: SeongJae Park Description: If 'memcg' is written to the 'type' file, writing to and reading from this file sets and gets the path to the memory cgroup of the interest. -What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//filters//addr_start -Date: Jul 2023 +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//core_filters//addr_start +Date: Feb 2025 Contact: SeongJae Park Description: If 'addr' is written to the 'type' file, writing to or reading from this file sets or gets the start address of the address range for the filter. -What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//filters//addr_end -Date: Jul 2023 +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//core_filters//addr_end +Date: Feb 2025 Contact: SeongJae Park Description: If 'addr' is written to the 'type' file, writing to or reading from this file sets or gets the end address of the address range for the filter. -What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//filters//min +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//core_filters//min Date: Feb 2025 Contact: SeongJae Park Description: If 'hugepage_size' is written to the 'type' file, writing to or reading from this file sets or gets the minimum size of the hugepage for the filter. -What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//filters//max +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//core_filters//max Date: Feb 2025 Contact: SeongJae Park Description: If 'hugepage_size' is written to the 'type' file, writing to or reading from this file sets or gets the maximum size of the hugepage for the filter. -What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//filters//target_idx -Date: Dec 2022 +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//core_filters//damon_target_idx +Date: Feb 2025 Contact: SeongJae Park Description: If 'target' is written to the 'type' file, writing to or reading from this file sets or gets the index of the DAMON monitoring target of the interest. -What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//filters//matching -Date: Dec 2022 +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//core_filters//matching +Date: Feb 2025 Contact: SeongJae Park Description: Writing 'Y' or 'N' to this file sets whether the filter is for the memory of the 'type', or all except the 'type'. -What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//filters//allow -Date: Jan 2025 +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//core_filters//allow +Date: Feb 2025 Contact: SeongJae Park Description: Writing 'Y' or 'N' to this file sets whether to allow or reject applying the scheme's action to the memory that satisfies the 'type' and the 'matching' of the directory. -What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//core_filters -Date: Feb 2025 -Contact: SeongJae Park -Description: Directory for DAMON core layer-handled DAMOS filters. Files - under this directory works same to those of - /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//filters - directory. - What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//ops_filters Date: Feb 2025 Contact: SeongJae Park Description: Directory for DAMON operations set layer-handled DAMOS filters. Files under this directory works same to those of - /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//filters + /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//core_filters directory. +What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//filters +Date: Dec 2022 +Contact: SeongJae Park +Description: Directory for DAMOS filters. Files under this directory works + same to those of + /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//{core,ops}_filters + directory. This is deprecated. Use the core_filters and + ops_filters instead. + What: /sys/kernel/mm/damon/admin/kdamonds//contexts//schemes//dests/nr_dests Date: Jul 2025 Contact: SeongJae Park diff --git a/Documentation/ABI/testing/sysfs-platform-asus-wmi b/Documentation/ABI/testing/sysfs-platform-asus-wmi index 89acb6638df8a5..f9825c6150b5c0 100644 --- a/Documentation/ABI/testing/sysfs-platform-asus-wmi +++ b/Documentation/ABI/testing/sysfs-platform-asus-wmi @@ -58,6 +58,15 @@ Description: * 1 - overboost, * 2 - silent +What: /sys/devices/platform//keystone +Date: Jun 2026 +KernelVersion: 7.2 +Contact: "Dariusz Figzał" +Description: + Reports the Keystone dongle insert state (read-only): + * 0 - not inserted + * 1 - inserted + What: /sys/devices/platform//gpu_mux_mode Date: Aug 2022 KernelVersion: 6.1 diff --git a/Documentation/PCI/pci.rst b/Documentation/PCI/pci.rst index f4d2662871ab1c..be35e9a1ee75f7 100644 --- a/Documentation/PCI/pci.rst +++ b/Documentation/PCI/pci.rst @@ -338,7 +338,7 @@ the PCI_IRQ_MSI and PCI_IRQ_MSIX flags will fail, so try to always specify PCI_IRQ_INTX as well. Drivers that have different interrupt handlers for MSI/MSI-X and -legacy INTx should chose the right one based on the msi_enabled +legacy INTx should choose the right one based on the msi_enabled and msix_enabled flags in the pci_dev structure after calling pci_alloc_irq_vectors. diff --git a/Documentation/PCI/pciebus-howto.rst b/Documentation/PCI/pciebus-howto.rst index 375d9ce171f623..9cc133ccdeeceb 100644 --- a/Documentation/PCI/pciebus-howto.rst +++ b/Documentation/PCI/pciebus-howto.rst @@ -97,7 +97,7 @@ register its service with the PCI Express Port Bus driver (see section 5.2.1 & 5.2.2). It is important that a service driver initializes the pcie_port_service_driver data structure, included in header file /include/linux/pcieport_if.h, before calling these APIs. -Failure to do so will result an identity mismatch, which prevents +Failure to do so will result in an identity mismatch, which prevents the PCI Express Port Bus driver from loading a service driver. pcie_port_service_register diff --git a/Documentation/RCU/Design/Requirements/Requirements.rst b/Documentation/RCU/Design/Requirements/Requirements.rst index 4d886e7c7a9564..8a216e4a46a7df 100644 --- a/Documentation/RCU/Design/Requirements/Requirements.rst +++ b/Documentation/RCU/Design/Requirements/Requirements.rst @@ -206,7 +206,7 @@ non-\ ``NULL``, locklessly accessing the ``->a`` and ``->b`` fields. 1 bool add_gp_buggy(int a, int b) 2 { - 3 p = kmalloc(sizeof(*p), GFP_KERNEL); + 3 p = kmalloc_obj(*p); 4 if (!p) 5 return -ENOMEM; 6 spin_lock(&gp_lock); @@ -228,7 +228,7 @@ their rights to reorder this code as follows: 1 bool add_gp_buggy_optimized(int a, int b) 2 { - 3 p = kmalloc(sizeof(*p), GFP_KERNEL); + 3 p = kmalloc_obj(*p); 4 if (!p) 5 return -ENOMEM; 6 spin_lock(&gp_lock); @@ -264,7 +264,7 @@ shows an example of insertion: 1 bool add_gp(int a, int b) 2 { - 3 p = kmalloc(sizeof(*p), GFP_KERNEL); + 3 p = kmalloc_obj(*p); 4 if (!p) 5 return -ENOMEM; 6 spin_lock(&gp_lock); diff --git a/Documentation/RCU/listRCU.rst b/Documentation/RCU/listRCU.rst index d8bb98623c124e..48c7272a4cccb0 100644 --- a/Documentation/RCU/listRCU.rst +++ b/Documentation/RCU/listRCU.rst @@ -276,7 +276,7 @@ The RCU version of audit_upd_rule() is as follows:: list_for_each_entry(e, list, list) { if (!audit_compare_rule(rule, &e->rule)) { - ne = kmalloc(sizeof(*entry), GFP_ATOMIC); + ne = kmalloc_obj(*entry, GFP_ATOMIC); if (ne == NULL) return -ENOMEM; audit_copy_rule(&ne->rule, &e->rule); diff --git a/Documentation/RCU/whatisRCU.rst b/Documentation/RCU/whatisRCU.rst index a1582bd653d115..e6767baff2d34d 100644 --- a/Documentation/RCU/whatisRCU.rst +++ b/Documentation/RCU/whatisRCU.rst @@ -468,7 +468,7 @@ uses of RCU may be found in listRCU.rst and NMI-RCU.rst. struct foo *new_fp; struct foo *old_fp; - new_fp = kmalloc(sizeof(*new_fp), GFP_KERNEL); + new_fp = kmalloc_obj(*new_fp); spin_lock(&foo_mutex); old_fp = rcu_dereference_protected(gbl_foo, lockdep_is_held(&foo_mutex)); *new_fp = *old_fp; @@ -570,7 +570,7 @@ The foo_update_a() function might then be written as follows:: struct foo *new_fp; struct foo *old_fp; - new_fp = kmalloc(sizeof(*new_fp), GFP_KERNEL); + new_fp = kmalloc_obj(*new_fp); spin_lock(&foo_mutex); old_fp = rcu_dereference_protected(gbl_foo, lockdep_is_held(&foo_mutex)); *new_fp = *old_fp; diff --git a/Documentation/accel/amdxdna/amdnpu.rst b/Documentation/accel/amdxdna/amdnpu.rst index 42e54904f9a87c..064973bf489391 100644 --- a/Documentation/accel/amdxdna/amdnpu.rst +++ b/Documentation/accel/amdxdna/amdnpu.rst @@ -270,6 +270,31 @@ MERT can report various kinds of telemetry information like the following: * Deep Sleep counter * etc. +.. _amdxdna-usage-stats: + +Amdxdna DRM client usage stats implementation +============================================= + +The amdxdna driver implements the DRM client usage stats specification as +documented in :ref:`drm-client-usage-stats`. + +Example of the output showing the implemented key value pairs: + +:: + + pos: 0 + flags: 0100002 + mnt_id: 29 + ino: 939 + drm-driver: amdxdna_accel_driver + drm-client-id: 3219 + drm-pdev: 0000:c5:00.1 + amdxdna_accel_driver-heap-alloc: 60 KiB + amdxdna_accel_driver-internal-alloc: 67588 KiB + amdxdna_accel_driver-external-alloc: 0 + drm-total-memory: 67632 KiB + drm-shared-memory: 0 + References ========== diff --git a/Documentation/admin-guide/LSM/landlock.rst b/Documentation/admin-guide/LSM/landlock.rst index 9923874e215627..314052bbeb0a96 100644 --- a/Documentation/admin-guide/LSM/landlock.rst +++ b/Documentation/admin-guide/LSM/landlock.rst @@ -6,7 +6,7 @@ Landlock: system-wide management ================================ :Author: Mickaël Salaün -:Date: January 2026 +:Date: June 2026 Landlock can leverage the audit framework to log events. @@ -19,8 +19,10 @@ Audit Denied access requests are logged by default for a sandboxed program if `audit` is enabled. This default behavior can be changed with the sys_landlock_restrict_self() flags (cf. -Documentation/userspace-api/landlock.rst). Landlock logs can also be masked -thanks to audit rules. Landlock can generate 2 audit record types. +Documentation/userspace-api/landlock.rst), or suppressed on a per-object +basis by using ``LANDLOCK_ADD_RULE_QUIET`` (ABI 10+). Landlock logs can +also be masked thanks to audit rules. Landlock can generate 2 audit +record types. Record types ------------ @@ -54,6 +56,8 @@ AUDIT_LANDLOCK_ACCESS **net.*** - Network access rights (ABI 4+): - net.bind_tcp - TCP port binding was denied - net.connect_tcp - TCP connection was denied + - net.bind_udp - UDP port binding was denied + - net.connect_send_udp - UDP connection and send was denied **scope.*** - IPC scoping restrictions (ABI 6+): - scope.abstract_unix_socket - Abstract UNIX socket connection denied @@ -172,7 +176,8 @@ If you get spammed with audit logs related to Landlock, this is either an attack attempt or a bug in the security policy. We can put in place some filters to limit noise with two complementary ways: -- with sys_landlock_restrict_self()'s flags if we can fix the sandboxed +- with sys_landlock_restrict_self()'s flags, or + ``LANDLOCK_ADD_RULE_QUIET`` (ABI 10+) if we can fix the sandboxed programs, - or with audit rules (see :manpage:`auditctl(8)`). diff --git a/Documentation/admin-guide/binfmt-misc.rst b/Documentation/admin-guide/binfmt-misc.rst index 59cd902e354974..c0a34fbf8022b5 100644 --- a/Documentation/admin-guide/binfmt-misc.rst +++ b/Documentation/admin-guide/binfmt-misc.rst @@ -68,10 +68,10 @@ Here is what the fields mean: Legacy behavior of binfmt_misc is to pass the full path of the binary to the interpreter as an argument. When this flag is included, binfmt_misc will open the file for reading and pass its - descriptor as an argument, instead of the full path, thus allowing - the interpreter to execute non-readable binaries. This feature - should be used with care - the interpreter has to be trusted not to - emit the contents of the non-readable binary. + descriptor into the auxilary vector with the key "AT_EXECFD", thus + allowing the interpreter to execute non-readable binaries. This + feature should be used with care - the interpreter has to be trusted + not to emit the contents of the non-readable binary. ``C`` - credentials Currently, the behavior of binfmt_misc is to calculate the credentials and security token of the new process according to diff --git a/Documentation/admin-guide/bug-hunting.rst b/Documentation/admin-guide/bug-hunting.rst index 3901b43c96df19..642bf84747269b 100644 --- a/Documentation/admin-guide/bug-hunting.rst +++ b/Documentation/admin-guide/bug-hunting.rst @@ -63,8 +63,8 @@ Documentation/admin-guide/tainted-kernels.rst, "being loaded" is annotated with "+", and "being unloaded" is annotated with "-". -Where is the Oops message is located? -------------------------------------- +Where is the Oops message located? +---------------------------------- Normally the Oops text is read from the kernel buffers by klogd and handed to ``syslogd`` which writes it to a syslog file, typically diff --git a/Documentation/admin-guide/cgroup-v1/cgroups.rst b/Documentation/admin-guide/cgroup-v1/cgroups.rst index 463f984533230a..e501f45ea93f3e 100644 --- a/Documentation/admin-guide/cgroup-v1/cgroups.rst +++ b/Documentation/admin-guide/cgroup-v1/cgroups.rst @@ -525,7 +525,7 @@ cgroup. It may also be taken to prevent cgroups from being modified, but more specific locks may be more appropriate in that situation. -See kernel/cgroup.c for more details. +See kernel/cgroup/cgroup.c for more details. Subsystems can take/release the cgroup_mutex via the functions cgroup_lock()/cgroup_unlock(). diff --git a/Documentation/admin-guide/cgroup-v1/memcg_test.rst b/Documentation/admin-guide/cgroup-v1/memcg_test.rst index 7c7cd457cf6952..ebedbc3c3f9cc9 100644 --- a/Documentation/admin-guide/cgroup-v1/memcg_test.rst +++ b/Documentation/admin-guide/cgroup-v1/memcg_test.rst @@ -321,7 +321,7 @@ Under below explanation, we assume CONFIG_SWAP=y. ---------------------- Memory controller implements memory thresholds using cgroups notification - API. You can use tools/cgroup/cgroup_event_listener.c to test it. + API. You can use samples/cgroup/cgroup_event_listener.c to test it. (Shell-A) Create cgroup and run event listener:: diff --git a/Documentation/admin-guide/cgroup-v2.rst b/Documentation/admin-guide/cgroup-v2.rst index 6efd0095ed995b..993446ab66d0fb 100644 --- a/Documentation/admin-guide/cgroup-v2.rst +++ b/Documentation/admin-guide/cgroup-v2.rst @@ -2785,6 +2785,59 @@ RDMA Interface Files mlx4_0 hca_handle=1 hca_object=20 ocrdma1 hca_handle=1 hca_object=23 + rdma.peak + A read-only nested-keyed file that exists for all the cgroups + except root. It shows the historical high watermark of + resource usage per device since the cgroup was created. + + An example for mlx4 and ocrdma device follows:: + + mlx4_0 hca_handle=1 hca_object=20 + ocrdma1 hca_handle=0 hca_object=23 + + rdma.events + A read-only nested-keyed file which exists on non-root + cgroups. The following nested keys are defined. + + max + The number of times a process in this cgroup or its + descendants attempted an RDMA resource allocation that + was rejected because a rdma.max limit in the subtree + was reached. This is a hierarchical counter: the event + is propagated upward to all ancestor cgroups. A value + change in this file generates a file modified event. + + alloc_fail + The number of RDMA resource allocation attempts that + originated in this cgroup or its descendants and failed + due to a rdma.max limit being reached. This is a + hierarchical counter propagated upward. + + An example for mlx4 device follows:: + + mlx4_0 hca_handle.max=5 hca_handle.alloc_fail=3 hca_object.max=0 hca_object.alloc_fail=0 + + rdma.events.local + Similar to rdma.events but the fields in the file are local + to the cgroup i.e. not hierarchical. The file modified event + generated on this file reflects only the local events. + + The following nested keys are defined. + + max + The number of times a process in this cgroup or its + descendants attempted an RDMA resource allocation that + was rejected because this cgroup's own rdma.max limit + was reached. + alloc_fail + The number of RDMA resource allocation attempts + originating from this cgroup that failed due to this + cgroup's or an ancestor's rdma.max limit. + + An example for mlx4 device follows:: + + mlx4_0 hca_handle.max=5 hca_handle.alloc_fail=0 hca_object.max=0 hca_object.alloc_fail=0 + DMEM ---- diff --git a/Documentation/admin-guide/device-mapper/dm-inlinecrypt.rst b/Documentation/admin-guide/device-mapper/dm-inlinecrypt.rst new file mode 100644 index 00000000000000..76b3aae21eb4cd --- /dev/null +++ b/Documentation/admin-guide/device-mapper/dm-inlinecrypt.rst @@ -0,0 +1,129 @@ +============== +dm-inlinecrypt +============== + +Device-Mapper's "inlinecrypt" target provides transparent encryption of block devices +using the inline encryption hardware. + +For a more detailed description of inline encryption, see: +https://docs.kernel.org/block/inline-encryption.html + +Parameters:: + + \ + [<#opt_params> ] + + + Encryption cipher type. + + The cipher specifications format is:: + + cipher + + Examples:: + + aes-xts-plain64 + + The cipher type corresponds to the encryption modes supported by + inline crypto in the block layer. Currently, only + BLK_ENCRYPTION_MODE_AES_256_XTS (i.e. aes-xts-plain64) is supported. + + + Key used for encryption. It is encoded either as a hexadecimal number + or it can be passed as prefixed with single colon + character (':') for keys residing in kernel keyring service. + You can only use key sizes that are valid for the selected cipher. + Note that the size in bytes of a valid key must be in bellow range. + + [BLK_CRYPTO_KEY_TYPE_RAW, BLK_CRYPTO_KEY_TYPE_HW_WRAPPED] + + + The kernel keyring key is identified by string in following format: + ::. + + + The encryption key size in bytes. The kernel key payload size must match + the value passed in . + + + The type of the key inside the kernel keyring. It can be either 'logon', + or 'trusted' kernel key type. + + + The kernel keyring key description inlinecrypt target should look for + when loading key of . + + + The IV offset is a sector count that is added to the sector number + before creating the IV. + + + This is the device that is going to be used as backend and contains the + encrypted data. You can specify it as a path like /dev/xxx or a device + number :. + + + Starting sector within the device where the encrypted data begins. + +<#opt_params> + Number of optional parameters. If there are no optional parameters, + the optional parameters section can be skipped or #opt_params can be zero. + Otherwise #opt_params is the number of following arguments. + + Example of optional parameters section: + keytype:raw allow_discards sector_size:4096 iv_large_sectors + + + The type of the key as seen by the block layer, either standard or + hardware-wrapped. The string is supplied in the table as + or . + +allow_discards + Block discard requests (a.k.a. TRIM) are passed through the inlinecrypt + device. The default is to ignore discard requests. + + WARNING: Assess the specific security risks carefully before enabling this + option. For example, allowing discards on encrypted devices may lead to + the leak of information about the ciphertext device (filesystem type, + used space etc.) if the discarded blocks can be located easily on the + device later. + +sector_size: + Use as the encryption unit instead of 512 bytes sectors. + This option can be in range 512 - 4096 bytes and must be power of two. + Virtual device will announce this size as a minimal IO and logical sector. + +iv_large_sectors + Use -based sector numbers for IV generation instead of + 512-byte sectors. + + For dm-inlinecrypt, this flag must be specified when + is larger than 512 bytes. The legacy 512-byte-based IV behavior is + not supported. + + When specified, if is 4096 bytes, plain64 IV for the + second sector will be 1, and must be a multiple of + (in 512-byte units). + +Example scripts +=============== +Currently, dm-inlinecrypt devices must be set up directly using dmsetup. +There is no userspace support yet to integrate dm-inlinecrypt with LUKS +or cryptsetup. In particular, cryptsetup currently only supports +dm-crypt, and cannot be used to create dm-inlinecrypt mappings. + +The following examples demonstrate how to create dm-inlinecrypt devices +using dmsetup + +:: + + #!/bin/sh + # Create a inlinecrypt device using dmsetup + dmsetup create inlinecrypt1 --table "0 `blockdev --getsz $1` inlinecrypt aes-xts-plain64 babebabebabebabebabebabebabebabebabebabebabebabebabebabebabebabe 0 0 $1 0 1 keytype:raw" + +:: + + #!/bin/sh + # Create a inlinecrypt device using dmsetup when encryption key is stored in keyring service + dmsetup create inlinecrypt2 --table "0 `blockdev --getsz $1` inlinecrypt aes-xts-plain64 :64:logon:fde:dminlinecrypt_test_key 0 0 $1 0 1 keytype:raw" + diff --git a/Documentation/admin-guide/device-mapper/index.rst b/Documentation/admin-guide/device-mapper/index.rst index 030d854628ac21..73c1f200213434 100644 --- a/Documentation/admin-guide/device-mapper/index.rst +++ b/Documentation/admin-guide/device-mapper/index.rst @@ -15,6 +15,7 @@ Device Mapper dm-flakey dm-ima dm-init + dm-inlinecrypt dm-integrity dm-io dm-log diff --git a/Documentation/admin-guide/devices.txt b/Documentation/admin-guide/devices.txt index 440633642fea76..f544399675fa3c 100644 --- a/Documentation/admin-guide/devices.txt +++ b/Documentation/admin-guide/devices.txt @@ -291,7 +291,6 @@ 154 = /dev/pmu Macintosh PowerBook power manager 155 = 156 = /dev/lcd Front panel LCD display - 157 = /dev/ac Applicom Intl Profibus card 158 = /dev/nwbutton Netwinder external button 159 = /dev/nwdebug Netwinder debug interface 160 = /dev/nwflash Netwinder flash memory diff --git a/Documentation/admin-guide/dynamic-debug-howto.rst b/Documentation/admin-guide/dynamic-debug-howto.rst index 095a63892257e4..9c2f096ed1d81b 100644 --- a/Documentation/admin-guide/dynamic-debug-howto.rst +++ b/Documentation/admin-guide/dynamic-debug-howto.rst @@ -38,12 +38,12 @@ You can view the currently configured behaviour in the *prdbg* catalog:: :#> head -n7 /proc/dynamic_debug/control # filename:lineno [module]function flags format - init/main.c:1179 [main]initcall_blacklist =_ "blacklisting initcall %s\012 - init/main.c:1218 [main]initcall_blacklisted =_ "initcall %s blacklisted\012" - init/main.c:1424 [main]run_init_process =_ " with arguments:\012" - init/main.c:1426 [main]run_init_process =_ " %s\012" - init/main.c:1427 [main]run_init_process =_ " with environment:\012" - init/main.c:1429 [main]run_init_process =_ " %s\012" + init/main.c:1179 [main]initcall_blacklist =_ "blacklisting initcall %s\n" + init/main.c:1218 [main]initcall_blacklisted =_ "initcall %s blacklisted\n" + init/main.c:1424 [main]run_init_process =_ " with arguments:\n" + init/main.c:1426 [main]run_init_process =_ " %s\n" + init/main.c:1427 [main]run_init_process =_ " with environment:\n" + init/main.c:1429 [main]run_init_process =_ " %s\n" The 3rd space-delimited column shows the current flags, preceded by a ``=`` for easy use with grep/cut. ``=p`` shows enabled callsites. @@ -59,10 +59,10 @@ query/commands to the control file. Example:: :#> ddcmd '-p; module main func run* +p' :#> grep =p /proc/dynamic_debug/control - init/main.c:1424 [main]run_init_process =p " with arguments:\012" - init/main.c:1426 [main]run_init_process =p " %s\012" - init/main.c:1427 [main]run_init_process =p " with environment:\012" - init/main.c:1429 [main]run_init_process =p " %s\012" + init/main.c:1424 [main]run_init_process =p " with arguments:\n" + init/main.c:1426 [main]run_init_process =p " %s\n" + init/main.c:1427 [main]run_init_process =p " with environment:\n" + init/main.c:1429 [main]run_init_process =p " %s\n" Error messages go to console/syslog:: @@ -109,10 +109,19 @@ The match-spec's select *prdbgs* from the catalog, upon which to apply the flags-spec, all constraints are ANDed together. An absent keyword is the same as keyword "*". +Note that since the match-spec can be empty, the flags are checked 1st, +then the pairs of keyword and value. Flag errs will hide keyword errs:: -A match specification is a keyword, which selects the attribute of -the callsite to be compared, and a value to compare against. Possible -keywords are::: + bash-5.2# ddcmd mod bar +foo + dyndbg: read 13 bytes from userspace + dyndbg: query 0: "mod bar +foo" mod:* + dyndbg: unknown flag 'o' + dyndbg: flags parse failed + dyndbg: processed 1 queries, with 0 matches, 1 errs + +So a match-spec is a keyword, which selects the attribute of the +callsite to be compared, and a value to compare against. Possible +keywords are:: match-spec ::= 'func' string | 'file' string | diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 97007f4f69d4e8..b5493a7f8f2281 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -24,7 +24,6 @@ IP_PNP IP DHCP, BOOTP, or RARP is enabled. IPV6 IPv6 support is enabled. ISAPNP ISA PnP code is enabled. - ISDN Appropriate ISDN support is enabled. ISOL CPU Isolation is enabled. JOY Appropriate joystick support is enabled. KGDB Kernel debugger support is enabled. @@ -36,7 +35,6 @@ M68k M68k architecture is enabled. These options have more detailed description inside of Documentation/arch/m68k/kernel-options.rst. - MDA MDA console support is enabled. MIPS MIPS architecture is enabled. MOUSE Appropriate mouse support is enabled. MSI Message Signaled Interrupts (PCI). @@ -558,9 +556,6 @@ Kernel parameters 1 -- enable. Default value is set via kernel config option. - arcrimi= [HW,NET] ARCnet - "RIM I" (entirely mem-mapped) cards - Format: ,, - arm64.no32bit_el0 [ARM64] Unconditionally disable the execution of 32 bit applications. @@ -877,6 +872,10 @@ Kernel parameters contiguous memory allocations. It will reserve CMA area for the specified node. + If it is setup together with upper 'cmd_pernuma=' + (unlikely), its size setting takes priority for the + specified numa nodes. + With numa CMA enabled, DMA users on node nid will first try to allocate buffer from the numa area which is located in node nid, if the allocation fails, @@ -893,17 +892,6 @@ Kernel parameters Sets the size of memory pool for coherent, atomic dma allocations, by default set to 256K. - com20020= [HW,NET] ARCnet - COM20020 chipset - Format: - [,[,[,[,[,]]]]] - - com90io= [HW,NET] ARCnet - COM90xx chipset (IO-mapped buffers) - Format: [,] - - com90xx= [HW,NET] - ARCnet - COM90xx chipset (memory-mapped buffers) - Format: [,[,]] - condev= [HW,S390] console device conmode= @@ -1228,8 +1216,9 @@ Kernel parameters deferred probe to give up waiting on dependencies to probe. Only specific dependencies (subsystems or drivers) that have opted in will be ignored. A timeout - of 0 will timeout at the end of initcalls. If the time - out hasn't expired, it'll be restarted by each + of 0 will timeout at the end of initcalls; a negative + value is treated as an infinite timeout value. If the + timeout hasn't expired, it'll be restarted by each successful driver registration. This option will also dump out devices still on the deferred probe list after retrying. @@ -1651,10 +1640,6 @@ Kernel parameters very early in the boot process. For early debugging via a serial port see kgdboc_earlycon instead. - elanfreq= [X86-32] - See comment before function elanfreq_setup() in - arch/x86/kernel/cpu/cpufreq/elanfreq.c. - elfcorehdr=[size[KMG]@]offset[KMG] [PPC,SH,X86,S390,EARLY] Specifies physical address of start of kernel core image elf header and optionally the size. Generally @@ -2082,6 +2067,10 @@ Kernel parameters Format: nn[KMGTPE] or (node format) :nn[KMGTPE][,:nn[KMGTPE]] + The size must be a multiple of the gigantic page size. + When using node format, this applies to each per-node size. + Missaligned values are dropped with a warning. + Reserve a CMA area of given size and allocate gigantic hugepages using the CMA allocator. If enabled, the boot-time allocation of gigantic hugepages is skipped. @@ -2227,9 +2216,6 @@ Kernel parameters syscalls, essentially overriding IA32_EMULATION_DEFAULT_DISABLED at boot time. When false, unconditionally disables IA32 emulation. - icn= [HW,ISDN] - Format: [,[,[,]]] - idle= [X86,EARLY] Format: idle=poll, idle=halt, idle=nomwait @@ -2325,6 +2311,12 @@ Kernel parameters Use the canonical format for the binary runtime measurements, instead of host native format. + ima_flush_htable [IMA] + Flush the IMA hash table when deleting all the + staged measurement records, to achieve maximum + memory saving at the cost of having duplicate + records across the staged measurement lists. + ima_hash= [IMA] Format: { md5 | sha1 | rmd160 | sha256 | sha384 | sha512 | ... } @@ -2566,23 +2558,41 @@ Kernel parameters Don't force hardware IOMMU usage when it is not needed. (default). + merge + Do scatter-gather (SG) merging. Implies "force" + (experimental). + + nomerge + Don't do scatter-gather (SG) merging. + biomerge + Do scatter-gather (SG) merging. Implies "force" + (experimental). [same as "merge"] + panic + Always panic when IOMMU overflows. + nopanic - merge - nomerge + Don't panic on IOMMU overflows. + + pt + Use passththrough mode by default + (Equivalent to iommu.passthrough=1) + + nopt + Use translated mode for DMA by default + (Equivalent to iommu.passthrough=0) soft Use software bounce buffering (SWIOTLB) (default for Intel machines). This can be used to prevent the usage of an available hardware IOMMU. - pt - nopt - nobypass [PPC/POWERNV] - Disable IOMMU bypass, using IOMMU for PCI devices. + usedac + Use the DAC on VIA PCI bridge + (default: disable the VIA PCI bridge DAC) - AMD Gart HW IOMMU-specific options: + AMD Gart HW IOMMU-specific options: (CONFIG_GART_IOMMU) Set the size of the remapping area in bytes. @@ -2590,6 +2600,9 @@ Kernel parameters allowed Overwrite iommu off workarounds for specific chipsets + force + Overwrite iommu off workarounds for specific chipsets + fullflush Flush IOMMU on each allocation (default). @@ -2600,21 +2613,16 @@ Kernel parameters Allocate an own aperture over RAM with size 32MB<,,, isolcpus= [KNL,SMP,ISOL] Isolate a given set of CPUs from disturbance. - [Deprecated - use cpusets instead] Format: [flag-list,] Specify one or more CPUs to isolate from disturbances @@ -2762,11 +2769,10 @@ Kernel parameters Isolate from the general SMP balancing and scheduling algorithms. Note that performing domain isolation this way is irreversible: it's not possible to bring back a CPU to - the domains once isolated through isolcpus. It's strongly - advised to use cpusets instead to disable scheduler load - balancing through the "cpuset.sched_load_balance" file. - It offers a much more flexible interface where CPUs can - move in and out of an isolated set anytime. + the domains once isolated through this boot time + configuration. Use cpusets for a dynamic configuration + which can be altered at runtime. For details see + Documentation/admin-guide/cpu-isolation.rst. You can move a process onto or off an "isolated" CPU via the CPU affinity syscalls or cpuset. @@ -3798,10 +3804,6 @@ Kernel parameters md= [HW] RAID subsystems devices and level See Documentation/admin-guide/md.rst. - mdacon= [MDA] - Format: , - Specifies range of consoles to be captured by the MDA. - mds= [X86,INTEL,EARLY] Control mitigation for the Micro-architectural Data Sampling (MDS) vulnerability. @@ -4248,12 +4250,8 @@ Kernel parameters n2= [NET] SDL Inc. RISCom/N2 synchronous serial card - netdev= [NET] Network devices parameters + netdev= [NET] NE2000 ISA network devices parameters Format: ,,,, - Note that mem_start is often overloaded to mean - something different and driver-specific. - This usage is only documented in each driver source - file if at all. netpoll.carrier_timeout= [NET] Specifies amount of time (in seconds) that @@ -4290,13 +4288,6 @@ Kernel parameters Only applies if the softerr mount option is enabled, and the specified value is >= 0. - nfs.enable_ino64= - [NFS] enable 64-bit inode numbers. - If zero, the NFS client will fake up a 32-bit inode - number for the readdir() and stat() syscalls instead - of returning the full 64-bit number. - The default is to return 64-bit inode numbers. - nfs.idmap_cache_timeout= [NFS] set the maximum lifetime for idmapper cache entries. @@ -4419,10 +4410,6 @@ Kernel parameters These settings can be accessed at runtime via the nmi_watchdog and hardlockup_panic sysctls. - no387 [BUGS=X86-32] Tells the kernel to use the 387 maths - emulation library even if a 387 maths coprocessor - is present. - no4lvl [RISCV,EARLY] Disable 4-level and 5-level paging modes. Forces kernel to use 3-level paging instead. @@ -4626,7 +4613,7 @@ Kernel parameters nosmt [KNL,MIPS,PPC,EARLY] Disable symmetric multithreading (SMT). Equivalent to smt=1. - [KNL,LOONGARCH,X86,PPC,S390] Disable symmetric multithreading (SMT). + [KNL,LOONGARCH,X86,ARM64,PPC,S390] Disable symmetric multithreading (SMT). nosmt=force: Force disable SMT, cannot be undone via the sysfs control file. @@ -5019,8 +5006,6 @@ Kernel parameters the specified number of seconds. This is to be used if your oopses keep scrolling off the screen. - pcbit= [HW,ISDN] - pci=option[,option...] [PCI,EARLY] various PCI subsystem options. Some options herein operate on a specific device @@ -5844,13 +5829,13 @@ Kernel parameters use a call_rcu[_hurry]() path. Please note, this is for a normal grace period. - How to enable it: + How to disable it: - echo 1 > /sys/module/rcutree/parameters/rcu_normal_wake_from_gp - or pass a boot parameter "rcutree.rcu_normal_wake_from_gp=1" + echo 0 > /sys/module/rcutree/parameters/rcu_normal_wake_from_gp + or pass a boot parameter "rcutree.rcu_normal_wake_from_gp=0" - Default is 1 if num_possible_cpus() <= 16 and it is not explicitly - disabled by the boot parameter passing 0. + Default is 1 if it is not explicitly disabled by the boot parameter + passing 0. rcuscale.gp_async= [KNL] Measure performance of asynchronous @@ -6760,8 +6745,6 @@ Kernel parameters restrictions other than those given by hardware at the cost of significant additional memory use for tables. - sa1100ir [NET] - See drivers/net/irda/sa1100_ir.c. sched_proxy_exec= [KNL] Enables or disables "proxy execution" style @@ -7218,6 +7201,18 @@ Kernel parameters Not specifying this option is equivalent to spec_store_bypass_disable=auto. + split_llc= + [X86,EARLY] Split the LLC N-ways + + When set, the LLC is split this many ways by matching + 'core_id % n'. This is setup before SMP bringup and + used during SMP bringup before it knows the full + topology. If your core count doesn't nicely divide by + the number given, you get to keep the pieces. + + This is mostly a debug feature to emulate multiple LLCs + on hardware that only have a single LLC. + split_lock_detect= [X86] Enable split lock detection or bus lock detection @@ -7396,10 +7391,10 @@ Kernel parameters Set the STI (builtin display/keyboard on the HP-PARISC machines) console (graphic card) which should be used as the initial boot-console. - See also comment in drivers/video/console/sticore.c. + See also comment in drivers/video/sticore.c. sti_font= [HW] - See comment in drivers/video/console/sticore.c. + See comment in drivers/video/sticore.c. stifb= [HW] Format: bpp:[:[:...]] @@ -7870,6 +7865,22 @@ Kernel parameters first trust source as a backend which is initialized successfully during iteration. + trusted.debug= [KEYS] + Format: + Enable trusted keys debug traces at runtime when + CONFIG_TRUSTED_KEYS_DEBUG=y. + + To make the traces visible after enabling the option, + use trusted.dyndbg='+p' as needed. By convention, + the subsystem uses pr_debug() for these traces. + + SAFETY: The traces can leak sensitive data, so be + cautious before enabling this. They remain inactive + unless this parameter is set this option to a true + value. + + Default: false + trusted.rng= [KEYS] Format: The RNG used to generate key material for trusted keys. diff --git a/Documentation/admin-guide/laptops/sonypi.rst b/Documentation/admin-guide/laptops/sonypi.rst index 7541f56e0007a8..fb8f4a30ddceba 100644 --- a/Documentation/admin-guide/laptops/sonypi.rst +++ b/Documentation/admin-guide/laptops/sonypi.rst @@ -89,7 +89,7 @@ statically linked into the kernel). Those options are: set to 0xffffffff, meaning that all possible events will be tried. You can use the following bits to construct your own event mask (from - drivers/char/sonypi.h):: + include/linux/sonypi.h):: SONYPI_JOGGER_MASK 0x0001 SONYPI_CAPTURE_MASK 0x0002 diff --git a/Documentation/admin-guide/laptops/uniwill-laptop.rst b/Documentation/admin-guide/laptops/uniwill-laptop.rst index 1f3ca84c7d88bb..24b41dbab886b8 100644 --- a/Documentation/admin-guide/laptops/uniwill-laptop.rst +++ b/Documentation/admin-guide/laptops/uniwill-laptop.rst @@ -46,11 +46,20 @@ Battery Charging Control .. warning:: Some devices do not properly implement the charging threshold interface. Forcing the driver to enable access to said interface on such devices might damage the battery [1]_. Because of this the driver will not enable said feature even when - using the ``force`` module parameter. - -The ``uniwill-laptop`` driver supports controlling the battery charge limit. This happens over -the standard ``charge_control_end_threshold`` power supply sysfs attribute. All values -between 1 and 100 percent are supported. + using the ``force`` module parameter. The charging profile interface will be + available instead. + +The ``uniwill-laptop`` driver supports controlling the battery charge limit. This either happens +over the standard ``charge_control_end_threshold`` or ``charge_types`` power supply sysfs attribute, +depending on the device. When using the ``charge_control_end_threshold`` sysfs attribute, all values +between 1 and 100 percent are supported. When using the ``charge_types`` sysfs attribute, the driver +supports switching between the ``Standard``, ``Trickle`` and ``Long Life`` profiles. + +Keep in mind that when using the ``charge_types`` sysfs attribute, the EC firmware will hide the +true charging status of the battery from the operating system, potentially misleading users into +thinking that the charging profile does not work. Checking the ``current_now`` sysfs attribute +tells you the true charging status of the battery even when using the ``charge_types`` sysfs +attribute (0 means that the battery is currently not charging). Additionally the driver signals the presence of battery charging issues through the standard ``health`` power supply sysfs attribute. diff --git a/Documentation/admin-guide/md.rst b/Documentation/admin-guide/md.rst index dc7eab191caaa6..003fd34f73bcf2 100644 --- a/Documentation/admin-guide/md.rst +++ b/Documentation/admin-guide/md.rst @@ -734,7 +734,7 @@ also have They should be scaled by the bitmap_chunksize. sync_speed_min, sync_speed_max - This are similar to ``/proc/sys/dev/raid/speed_limit_{min,max}`` + These are similar to ``/proc/sys/dev/raid/speed_limit_{min,max}`` however they only apply to the particular array. If no value has been written to these, or if the word ``system`` diff --git a/Documentation/admin-guide/media/amdisp4-1.rst b/Documentation/admin-guide/media/amdisp4-1.rst new file mode 100644 index 00000000000000..878141154f962f --- /dev/null +++ b/Documentation/admin-guide/media/amdisp4-1.rst @@ -0,0 +1,63 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. include:: + +==================================== +AMD Image Signal Processor (amdisp4) +==================================== + +Introduction +============ + +This file documents the driver for the AMD ISP4 that is part of +AMD Ryzen AI Max 300 Series. + +The driver is located under drivers/media/platform/amd/isp4 and uses +the Media-Controller API. + +The driver exposes one video capture device to userspace and provide +web camera like interface. Internally the video device is connected +to the isp4 sub-device responsible for communication with the CCPU FW. + +Topology +======== + +.. _amdisp4_topology_graph: + +.. kernel-figure:: amdisp4.dot + :alt: Diagram of the media pipeline topology + :align: center + + + +The driver has 1 sub-device: Representing isp4 image signal processor. +The driver has 1 video device: Capture device for retrieving images. + +- ISP4 Image Signal Processing Subdevice Node + +--------------------------------------------- + +The isp4 is represented as a single V4L2 subdev, the sub-device does not +provide interface to the user space. The sub-device is connected to one video node +(isp4_capture) with immutable active link. The sub-device represents ISP with +connected sensor similar to smart cameras (sensors with integrated ISP). +sub-device has only one link to the video device for capturing the frames. +The sub-device communicates with CCPU FW for streaming configuration and +buffer management. + + +- isp4_capture - Frames Capture Video Node + +------------------------------------------ + +Isp4_capture is a capture device to capture frames to memory. +The entity is connected to isp4 sub-device. The video device +provides web camera like interface to userspace. It supports +mmap and dma buf types of memory. + +Capturing Video Frames Example +============================== + +.. code-block:: bash + + v4l2-ctl "-d" "/dev/video0" "--set-fmt-video=width=1920,height=1080,pixelformat=NV12" "--stream-mmap" "--stream-count=10" diff --git a/Documentation/admin-guide/media/amdisp4.dot b/Documentation/admin-guide/media/amdisp4.dot new file mode 100644 index 00000000000000..978f30c1a31a4c --- /dev/null +++ b/Documentation/admin-guide/media/amdisp4.dot @@ -0,0 +1,6 @@ +digraph board { + rankdir=TB + n00000001 [label="{{} | amd isp4\n | { 0}}", shape=Mrecord, style=filled, fillcolor=green] + n00000001:port0 -> n00000003 [style=bold] + n00000003 [label="Preview\n/dev/video0", shape=box, style=filled, fillcolor=yellow] +} diff --git a/Documentation/admin-guide/media/rkcif-rk3588-vicap.dot b/Documentation/admin-guide/media/rkcif-rk3588-vicap.dot new file mode 100644 index 00000000000000..f6d3404920b544 --- /dev/null +++ b/Documentation/admin-guide/media/rkcif-rk3588-vicap.dot @@ -0,0 +1,29 @@ +digraph board { + rankdir=TB + n00000007 [label="{{ 0} | rkcif-mipi2\n/dev/v4l-subdev0 | { 1}}", shape=Mrecord, style=filled, fillcolor=green] + n00000007:port1 -> n0000000a + n00000007:port1 -> n00000010 [style=dashed] + n00000007:port1 -> n00000016 [style=dashed] + n00000007:port1 -> n0000001c [style=dashed] + n0000000a [label="rkcif-mipi2-id0\n/dev/video0", shape=box, style=filled, fillcolor=yellow] + n00000010 [label="rkcif-mipi2-id1\n/dev/video1", shape=box, style=filled, fillcolor=yellow] + n00000016 [label="rkcif-mipi2-id2\n/dev/video2", shape=box, style=filled, fillcolor=yellow] + n0000001c [label="rkcif-mipi2-id3\n/dev/video3", shape=box, style=filled, fillcolor=yellow] + n00000025 [label="{{ 0} | rkcif-mipi4\n/dev/v4l-subdev1 | { 1}}", shape=Mrecord, style=filled, fillcolor=green] + n00000025:port1 -> n00000028 + n00000025:port1 -> n0000002e [style=dashed] + n00000025:port1 -> n00000034 [style=dashed] + n00000025:port1 -> n0000003a [style=dashed] + n00000028 [label="rkcif-mipi4-id0\n/dev/video4", shape=box, style=filled, fillcolor=yellow] + n0000002e [label="rkcif-mipi4-id1\n/dev/video5", shape=box, style=filled, fillcolor=yellow] + n00000034 [label="rkcif-mipi4-id2\n/dev/video6", shape=box, style=filled, fillcolor=yellow] + n0000003a [label="rkcif-mipi4-id3\n/dev/video7", shape=box, style=filled, fillcolor=yellow] + n00000043 [label="{{ 0} | dw-mipi-csi2rx fdd30000.csi\n/dev/v4l-subdev2 | { 1}}", shape=Mrecord, style=filled, fillcolor=green] + n00000043:port1 -> n00000007:port0 + n00000048 [label="{{ 0} | dw-mipi-csi2rx fdd50000.csi\n/dev/v4l-subdev3 | { 1}}", shape=Mrecord, style=filled, fillcolor=green] + n00000048:port1 -> n00000025:port0 + n0000004d [label="{{} | imx415 3-001a\n/dev/v4l-subdev4 | { 0}}", shape=Mrecord, style=filled, fillcolor=green] + n0000004d:port0 -> n00000043:port0 + n00000051 [label="{{} | imx415 4-001a\n/dev/v4l-subdev5 | { 0}}", shape=Mrecord, style=filled, fillcolor=green] + n00000051:port0 -> n00000048:port0 +} diff --git a/Documentation/admin-guide/media/rkcif.rst b/Documentation/admin-guide/media/rkcif.rst index 2558c121abc466..313a0ea45d16fe 100644 --- a/Documentation/admin-guide/media/rkcif.rst +++ b/Documentation/admin-guide/media/rkcif.rst @@ -77,3 +77,35 @@ and the following video devices: .. kernel-figure:: rkcif-rk3568-vicap.dot :alt: Topology of the RK3568 Video Capture (VICAP) unit :align: center + +Rockchip RK3588 Video Capture (VICAP) +------------------------------------- + +The RK3588 Video Capture (VICAP) unit features a digital video port and six +MIPI CSI-2 capture interfaces that can receive video data independently. +The DVP accepts parallel video data, BT.656 and BT.1120. +Since the BT.1120 protocol may feature more than one stream, the RK3588 VICAP +DVP features four DMA engines that can capture different streams. +Similarly, the RK3588 VICAP MIPI CSI-2 receivers feature four DMA engines each +to handle different Virtual Channels (VCs). + +The rkcif driver represents this hardware variant by exposing the following +V4L2 subdevices: + +* dw-mipi-csi2rx fdd30000.csi: MIPI CSI-2 receiver connected to MIPI DPHY0 +* dw-mipi-csi2rx fdd50000.csi: MIPI CSI-2 receiver connected to MIPI DPHY1 +* rkcif-mipi2: INTERFACE/CROP block for the MIPI CSI-2 receiver connected to + MIPI DPHY0 +* rkcif-mipi4: INTERFACE/CROP block for the MIPI CSI-2 receiver connected to + MIPI DPHY1 + +and the following video devices: + +* rkcif-mipi2-id{0,1,2,3}: The DMA engines connected to the rkcif-mipi2 + INTERFACE/CROP block. +* rkcif-mipi4-id{0,1,2,3}: The DMA engines connected to the rkcif-mipi4 + INTERFACE/CROP block. + +.. kernel-figure:: rkcif-rk3588-vicap.dot + :alt: Topology of the RK3588 Video Capture (VICAP) unit + :align: center diff --git a/Documentation/admin-guide/media/v4l-drivers.rst b/Documentation/admin-guide/media/v4l-drivers.rst index d31da8e0a54f27..4621eae9fa1edf 100644 --- a/Documentation/admin-guide/media/v4l-drivers.rst +++ b/Documentation/admin-guide/media/v4l-drivers.rst @@ -9,6 +9,7 @@ Video4Linux (V4L) driver-specific documentation .. toctree:: :maxdepth: 2 + amdisp4-1 bttv c3-isp cafe_ccic diff --git a/Documentation/admin-guide/mm/damon/lru_sort.rst b/Documentation/admin-guide/mm/damon/lru_sort.rst index 14cc6b2db8973d..b93ca9b0853d24 100644 --- a/Documentation/admin-guide/mm/damon/lru_sort.rst +++ b/Documentation/admin-guide/mm/damon/lru_sort.rst @@ -75,7 +75,7 @@ Make DAMON_LRU_SORT reads the input parameters again, except ``enabled``. Input parameters that updated while DAMON_LRU_SORT is running are not applied by default. Once this parameter is set as ``Y``, DAMON_LRU_SORT reads values -of parametrs except ``enabled`` again. Once the re-reading is done, this +of parameters except ``enabled`` again. Once the re-reading is done, this parameter is set as ``N``. If invalid parameters are found while the re-reading, DAMON_LRU_SORT will be disabled. @@ -246,7 +246,8 @@ monitor_region_start Start of target memory region in physical address. The start physical address of memory region that DAMON_LRU_SORT will do work -against. By default, biggest System RAM is used as the region. +against. By default, the system's entire physical memory is used as the +region. monitor_region_end ------------------ @@ -254,7 +255,8 @@ monitor_region_end End of target memory region in physical address. The end physical address of memory region that DAMON_LRU_SORT will do work -against. By default, biggest System RAM is used as the region. +against. By default, the system's entire physical memory is used as the +region. addr_unit --------- diff --git a/Documentation/admin-guide/mm/damon/reclaim.rst b/Documentation/admin-guide/mm/damon/reclaim.rst index d7a0225b495087..ec7e3e32b4ac6d 100644 --- a/Documentation/admin-guide/mm/damon/reclaim.rst +++ b/Documentation/admin-guide/mm/damon/reclaim.rst @@ -67,7 +67,7 @@ Make DAMON_RECLAIM reads the input parameters again, except ``enabled``. Input parameters that updated while DAMON_RECLAIM is running are not applied by default. Once this parameter is set as ``Y``, DAMON_RECLAIM reads values -of parametrs except ``enabled`` again. Once the re-reading is done, this +of parameters except ``enabled`` again. Once the re-reading is done, this parameter is set as ``N``. If invalid parameters are found while the re-reading, DAMON_RECLAIM will be disabled. @@ -85,6 +85,17 @@ identifies the region as cold, and reclaims it. 120 seconds by default. +autotune_monitoring_intervals +----------------------------- + +If this parameter is set as ``Y``, DAMON_RECLAIM automatically tunes DAMON's +sampling and aggregation intervals. The auto-tuning aims to capture meaningful +amount of access events in each DAMON-snapshot, while keeping the sampling +interval 5 milliseconds in minimum, and 10 seconds in maximum. Setting this as +``N`` disables the auto-tuning. + +Disabled by default. + quota_ms -------- @@ -229,7 +240,8 @@ Start of target memory region in physical address. The start physical address of memory region that DAMON_RECLAIM will do work against. That is, DAMON_RECLAIM will find cold memory regions in this region -and reclaims. By default, biggest System RAM is used as the region. +and reclaims. By default, the system's entire physical memory is used as the +region. monitor_region_end ------------------ @@ -238,7 +250,8 @@ End of target memory region in physical address. The end physical address of memory region that DAMON_RECLAIM will do work against. That is, DAMON_RECLAIM will find cold memory regions in this region -and reclaims. By default, biggest System RAM is used as the region. +and reclaims. By default, the system's entire physical memory is used as the +region. addr_unit --------- diff --git a/Documentation/admin-guide/mm/damon/stat.rst b/Documentation/admin-guide/mm/damon/stat.rst index c4b14daeb2dd6f..46c5dd96aa2ede 100644 --- a/Documentation/admin-guide/mm/damon/stat.rst +++ b/Documentation/admin-guide/mm/damon/stat.rst @@ -89,3 +89,10 @@ percentiles of the idle time values via this read-only parameter. Reading the parameter returns 101 idle time values in milliseconds, separated by comma. Each value represents 0-th, 1st, 2nd, 3rd, ..., 99th and 100th percentile idle times. + +kdamond_pid +----------- + +PID of the DAMON thread. + +If DAMON_STAT is enabled, this becomes the PID of the worker thread. Else, -1. diff --git a/Documentation/admin-guide/mm/damon/usage.rst b/Documentation/admin-guide/mm/damon/usage.rst index 534e1199cf0917..011296f1e7c219 100644 --- a/Documentation/admin-guide/mm/damon/usage.rst +++ b/Documentation/admin-guide/mm/damon/usage.rst @@ -66,11 +66,17 @@ comma (","). │ :ref:`kdamonds `/nr_kdamonds │ │ :ref:`0 `/state,pid,refresh_ms │ │ │ :ref:`contexts `/nr_contexts - │ │ │ │ :ref:`0 `/avail_operations,operations,addr_unit + │ │ │ │ :ref:`0 `/avail_operations,operations,addr_unit, + │ │ │ │ pause │ │ │ │ │ :ref:`monitoring_attrs `/ │ │ │ │ │ │ intervals/sample_us,aggr_us,update_us │ │ │ │ │ │ │ intervals_goal/access_bp,aggrs,min_sample_us,max_sample_us │ │ │ │ │ │ nr_regions/min,max + │ │ │ │ │ │ :ref:`probes `/nr_probes + │ │ │ │ │ │ │ 0/filters/nr_filters + │ │ │ │ │ │ │ │ 0/type,matching,allow,path + │ │ │ │ │ │ │ │ ... + │ │ │ │ │ │ │ ... │ │ │ │ │ :ref:`targets `/nr_targets │ │ │ │ │ │ :ref:`0 `/pid_target,obsolete_target │ │ │ │ │ │ │ :ref:`regions `/nr_regions @@ -83,18 +89,23 @@ comma (","). │ │ │ │ │ │ │ │ sz/min,max │ │ │ │ │ │ │ │ nr_accesses/min,max │ │ │ │ │ │ │ │ age/min,max - │ │ │ │ │ │ │ :ref:`quotas `/ms,bytes,reset_interval_ms,effective_bytes,goal_tuner + │ │ │ │ │ │ │ :ref:`quotas `/ms,bytes,reset_interval_ms, + │ │ │ │ │ │ │ effective_bytes,goal_tuner, + │ │ │ │ │ │ │ fail_charge_num,fail_charge_denom │ │ │ │ │ │ │ │ weights/sz_permil,nr_accesses_permil,age_permil │ │ │ │ │ │ │ │ :ref:`goals `/nr_goals │ │ │ │ │ │ │ │ │ 0/target_metric,target_value,current_value,nid,path │ │ │ │ │ │ │ :ref:`watermarks `/metric,interval_us,high,mid,low │ │ │ │ │ │ │ :ref:`{core_,ops_,}filters `/nr_filters - │ │ │ │ │ │ │ │ 0/type,matching,allow,memcg_path,addr_start,addr_end,target_idx,min,max + │ │ │ │ │ │ │ │ 0/type,matching,allow,memcg_path,addr_start,addr_end,damon_target_idx,min,max │ │ │ │ │ │ │ :ref:`dests `/nr_dests │ │ │ │ │ │ │ │ 0/id,weight │ │ │ │ │ │ │ :ref:`stats `/nr_tried,sz_tried,nr_applied,sz_applied,sz_ops_filter_passed,qt_exceeds,nr_snapshots,max_nr_snapshots │ │ │ │ │ │ │ :ref:`tried_regions `/total_bytes │ │ │ │ │ │ │ │ 0/start,end,nr_accesses,age,sz_filter_passed + │ │ │ │ │ │ │ │ │ probes + │ │ │ │ │ │ │ │ │ │ 0/hits + │ │ │ │ │ │ │ │ │ │ ... │ │ │ │ │ │ │ │ ... │ │ │ │ │ │ ... │ │ │ │ ... @@ -194,9 +205,9 @@ details). At the moment, only one context per kdamond is supported, so only contexts// ------------- -In each context directory, three files (``avail_operations``, ``operations`` -and ``addr_unit``) and three directories (``monitoring_attrs``, ``targets``, -and ``schemes``) exist. +In each context directory, four files (``avail_operations``, ``operations``, +``addr_unit`` and ``pause``) and three directories (``monitoring_attrs``, +``targets``, and ``schemes``) exist. DAMON supports multiple types of :ref:`monitoring operations `, including those for virtual address @@ -214,6 +225,9 @@ reading from the ``operations`` file. ``addr_unit`` file is for setting and getting the :ref:`address unit ` parameter of the operations set. +``pause`` file is for setting and getting the :ref:`pause request +` parameter of the context. + .. _sysfs_monitoring_attrs: contexts//monitoring_attrs/ @@ -221,8 +235,8 @@ contexts//monitoring_attrs/ Files for specifying attributes of the monitoring including required quality and efficiency of the monitoring are in ``monitoring_attrs`` directory. -Specifically, two directories, ``intervals`` and ``nr_regions`` exist in this -directory. +Specifically, three directories, ``intervals``, ``nr_regions`` and ``probes`` +exist in this directory. Under ``intervals`` directory, three files for DAMON's sampling interval (``sample_us``), aggregation interval (``aggr_us``), and update interval @@ -256,6 +270,29 @@ tuning-applied current values of the two intervals can be read from the ``sample_us`` and ``aggr_us`` files after writing ``update_tuned_intervals`` to the ``state`` file. +.. _damon_usage_sysfs_probes: + +contexts//monitoring_attrs/probes/ +------------------------------------- + +A directory for registering :ref:`data attributes monitoring +` probes. + +In the beginning, this directory has only one file, ``nr_probes``. Writing a +number (``N``) to the file creates the number of child directories named ``0`` +to ``N-1``. Each directory represents each monitoring probe. + +In each probe directory, one directory, ``filters`` exists. The directory +contains files for installing filters for the probe, that is used to determine +the data attribute for the probe. + +In the beginning, ``filters`` directory has only one file, ``nr_filters``. +Writing a number (``N``) to the file creates the number of child directories +named ``0`` to ``N-1``. Each directory represents each filter and works in a +way similar to that for :ref:`DAMOS filter `. When the filter +``type`` is ``memcg``, ``path`` file acts as ``memcg_path`` for :ref:`DAMOS +filter `. + .. _sysfs_targets: contexts//targets/ @@ -337,7 +374,7 @@ to ``N-1``. Each directory represents each DAMON-based operation scheme. schemes// ------------ -In each scheme directory, eight directories (``access_pattern``, ``quotas``, +In each scheme directory, nine directories (``access_pattern``, ``quotas``, ``watermarks``, ``core_filters``, ``ops_filters``, ``filters``, ``dests``, ``stats``, and ``tried_regions``) and three files (``action``, ``target_nid`` and ``apply_interval``) exist. @@ -377,9 +414,10 @@ schemes//quotas/ The directory for the :ref:`quotas ` of the given DAMON-based operation scheme. -Under ``quotas`` directory, five files (``ms``, ``bytes``, -``reset_interval_ms``, ``effective_bytes`` and ``goal_tuner``) and two -directories (``weights`` and ``goals``) exist. +Under ``quotas`` directory, seven files (``ms``, ``bytes``, +``reset_interval_ms``, ``effective_bytes``, ``goal_tuner``, ``fail_charge_num`` +and ``fail_charge_denom``) and two directories (``weights`` and ``goals``) +exist. You can set the ``time quota`` in milliseconds, ``size quota`` in bytes, and ``reset interval`` in milliseconds by writing the values to the three files, @@ -398,6 +436,13 @@ the background design of the feature and the name of the selectable algorithms. Refer to :ref:`goals directory ` for the goals setup. +You can set the action-failed memory quota charging ratio by writing the +numerator and the denominator for the ratio to ``fail_charge_num`` and +``fail_charge_denom`` files, respectively. Reading those files will return the +current set values. Refer to :ref:`design +` for more details of +the ratio feature. + The time quota is internally transformed to a size quota. Between the transformed size quota and user-specified size quota, smaller one is applied. Based on the user-specified :ref:`goal `, the @@ -429,10 +474,12 @@ to ``N-1``. Each directory represents each goal and current achievement. Among the multiple feedback, the best one is used. Each goal directory contains five files, namely ``target_metric``, -``target_value``, ``current_value`` ``nid`` and ``path``. Users can set and +``target_value``, ``current_value``, ``nid``, and ``path``. Users can set and get the five parameters for the quota auto-tuning goals that specified on the :ref:`design doc ` by writing to and -reading from each of the files. Note that users should further write +reading from each of the files. Because the kernel does not update +``current_value``, reading it only makes sense when ``target_metric`` is +``user_input``. Note that users should further write ``commit_schemes_quota_goals`` to the ``state`` file of the :ref:`kdamond directory ` to pass the feedback to DAMON. @@ -447,7 +494,7 @@ given DAMON-based operation scheme. Under the watermarks directory, five files (``metric``, ``interval_us``, ``high``, ``mid``, and ``low``) for setting the metric, the time interval between check of the metric, and the three watermarks exist. You can set and -get the five values by writing to the files, respectively. +get the five values by writing to and reading from the files, respectively. Keywords and meanings of those that can be written to the ``metric`` file are as below. @@ -455,7 +502,7 @@ as below. - none: Ignore the watermarks - free_mem_rate: System's free memory rate (per thousand) -The ``interval`` should written in microseconds unit. +The ``interval_us`` should be written in microseconds unit. .. _sysfs_filters: @@ -471,10 +518,10 @@ directory can be used for installing filters regardless of their handled layers. Filters that requested by ``core_filters`` and ``ops_filters`` will be installed before those of ``filters``. All three directories have same files. -Use of ``filters`` directory can make expecting evaluation orders of given -filters with the files under directory bit confusing. Users are hence -recommended to use ``core_filters`` and ``ops_filters`` directories. The -``filters`` directory could be deprecated in future. +Use of ``filters`` directory can make filters evaluation orders confusing to +expect. For this reason, ``filters`` directory is deprecated. It is still +functioning, but is scheduled for removal in the near future. Users should use +``core_filters`` and ``ops_filters`` directories instead. In the beginning, the directory has only one file, ``nr_filters``. Writing a number (``N``) to the file creates the number of child directories named ``0`` @@ -483,9 +530,9 @@ in the numeric order. Each filter directory contains nine files, namely ``type``, ``matching``, ``allow``, ``memcg_path``, ``addr_start``, ``addr_end``, ``min``, ``max`` -and ``target_idx``. To ``type`` file, you can write the type of the filter. -Refer to :ref:`the design doc ` for available type -names, their meaning and on what layer those are handled. +and ``damon_target_idx``. To ``type`` file, you can write the type of the +filter. Refer to :ref:`the design doc ` for +available type names, their meaning and on what layer those are handled. For ``memcg`` type, you can specify the memory cgroup of the interest by writing the path of the memory cgroup from the cgroups mount point to @@ -495,7 +542,7 @@ files, respectively. For ``hugepage_size`` type, you can specify the minimum and maximum size of the range (closed interval) to ``min`` and ``max`` files, respectively. For ``target`` type, you can specify the index of the target between the list of the DAMON context's monitoring targets list to -``target_idx`` file. +``damon_target_idx`` file. You can write ``Y`` or ``N`` to ``matching`` file to specify whether the filter is for memory that matches the ``type``. You can write ``Y`` or ``N`` to @@ -601,10 +648,19 @@ tried_regions// ------------------ In each region directory, you will find five files (``start``, ``end``, -``nr_accesses``, ``age``, and ``sz_filter_passed``). Reading the files will +``nr_accesses``, ``age`` and ``sz_filter_passed``). Reading the files will show the properties of the region that corresponding DAMON-based operation scheme ``action`` has tried to be applied. +tried_regions//probes/ +------------------------- + +In each region directory, one directory (``probes``) also exists. In the +directory, subdirectories named ``0`` to ``N-1`` exists. ``N`` is the number +of installed probes. In each number-named directory, a file (``hits``) exist. +Reading the file shows the number of data attributes monitoring probe-hit +positive samples of the region. + Example ~~~~~~~ @@ -677,7 +733,7 @@ show results using tracepoint supporting tools like ``perf``. For example:: Each line of the perf script output represents each monitoring region. The first five fields are as usual other tracepoint outputs. The sixth field -(``target_id=X``) shows the ide of the monitoring target of the region. The +(``target_id=X``) shows the id of the monitoring target of the region. The seventh field (``nr_regions=X``) shows the total number of monitoring regions for the target. The eighth field (``X-Y:``) shows the start (``X``) and end (``Y``) addresses of the region in bytes. The ninth field (``X``) shows the diff --git a/Documentation/admin-guide/mm/hugetlbpage.rst b/Documentation/admin-guide/mm/hugetlbpage.rst index 67a941903fd223..3cc15d800be11d 100644 --- a/Documentation/admin-guide/mm/hugetlbpage.rst +++ b/Documentation/admin-guide/mm/hugetlbpage.rst @@ -455,7 +455,7 @@ used to change the file attributes on hugetlbfs. Also, it is important to note that no such mount command is required if applications are going to use only shmat/shmget system calls or mmap with MAP_HUGETLB. For an example of how to use mmap with MAP_HUGETLB see -:ref:`map_hugetlb ` below. +:ref:`examples ` below. Users who wish to use hugetlb memory via shared memory segment should be members of a supplementary group and system admin needs to configure that gid @@ -473,16 +473,13 @@ a hugetlb page and the length is smaller than the hugepage size. Examples ======== -.. _map_hugetlb: +.. _examples: -``map_hugetlb`` - see tools/testing/selftests/mm/map_hugetlb.c +``hugetlb-shm`` + see tools/testing/selftests/mm/hugetlb-shm.c -``hugepage-shm`` - see tools/testing/selftests/mm/hugepage-shm.c - -``hugepage-mmap`` - see tools/testing/selftests/mm/hugepage-mmap.c +``hugetlb-mmap`` + see tools/testing/selftests/mm/hugetlb-mmap.c The `libhugetlbfs`_ library provides a wide range of userspace tools to help with huge page usability, environment setup, and control. diff --git a/Documentation/admin-guide/mm/transhuge.rst b/Documentation/admin-guide/mm/transhuge.rst index 5fbc3d89bb0731..23f8d13c2629d6 100644 --- a/Documentation/admin-guide/mm/transhuge.rst +++ b/Documentation/admin-guide/mm/transhuge.rst @@ -57,13 +57,14 @@ prominent because the size of each page isn't as huge as the PMD-sized variant and there is less memory to clear in each page fault. Some architectures also employ TLB compression mechanisms to squeeze more entries in when a set of PTEs are virtually and physically contiguous -and approporiately aligned. In this case, TLB misses will occur less +and appropriately aligned. In this case, TLB misses will occur less often. THP can be enabled system wide or restricted to certain tasks or even memory ranges inside task's address space. Unless THP is completely disabled, there is ``khugepaged`` daemon that scans memory and -collapses sequences of basic pages into PMD-sized huge pages. +collapses sequences of basic pages into huge pages of either PMD size +or mTHP sizes, if the system is configured to do so. The THP behaviour is controlled via :ref:`sysfs ` interface and using madvise(2) and prctl(2) system calls. @@ -210,7 +211,7 @@ PMD-mappable transparent hugepage:: cat /sys/kernel/mm/transparent_hugepage/hpage_pmd_size All THPs at fault and collapse time will be added to _deferred_list, -and will therefore be split under memory presure if they are considered +and will therefore be split under memory pressure if they are considered "underused". A THP is underused if the number of zero-filled pages in the THP is above max_ptes_none (see below). It is possible to disable this behaviour by writing 0 to shrink_underused, and enable it by writing @@ -219,10 +220,10 @@ this behaviour by writing 0 to shrink_underused, and enable it by writing echo 0 > /sys/kernel/mm/transparent_hugepage/shrink_underused echo 1 > /sys/kernel/mm/transparent_hugepage/shrink_underused -khugepaged will be automatically started when PMD-sized THP is enabled +khugepaged will be automatically started when any THP size is enabled (either of the per-size anon control or the top-level control are set to "always" or "madvise"), and it'll be automatically shutdown when -PMD-sized THP is disabled (when both the per-size anon control and the +all THP sizes are disabled (when both the per-size anon control and the top-level control are "never") process THP controls @@ -265,8 +266,8 @@ Khugepaged controls ------------------- .. note:: - khugepaged currently only searches for opportunities to collapse to - PMD-sized THP and no attempt is made to collapse to other THP + khugepaged currently only searches for opportunities to collapse file/shmem + to PMD-sized THP. Only anonymous memory will attempt to collapse to other THP sizes. khugepaged runs usually at low frequency so while one may not want to @@ -296,11 +297,11 @@ allocation failure to throttle the next allocation attempt:: The khugepaged progress can be seen in the number of pages collapsed (note that this counter may not be an exact count of the number of pages collapsed, since "collapsed" could mean multiple things: (1) A PTE mapping -being replaced by a PMD mapping, or (2) All 4K physical pages replaced by -one 2M hugepage. Each may happen independently, or together, depending on -the type of memory and the failures that occur. As such, this value should -be interpreted roughly as a sign of progress, and counters in /proc/vmstat -consulted for more accurate accounting):: +being replaced by a PMD mapping, or (2) physical pages replaced by one +hugepage of various sizes (PMD-sized or mTHP). Each may happen independently, +or together, depending on the type of memory and the failures that occur. +As such, this value should be interpreted roughly as a sign of progress, +and counters in /proc/vmstat consulted for more accurate accounting):: /sys/kernel/mm/transparent_hugepage/khugepaged/pages_collapsed @@ -308,16 +309,21 @@ for each pass:: /sys/kernel/mm/transparent_hugepage/khugepaged/full_scans -``max_ptes_none`` specifies how many extra small pages (that are -not already mapped) can be allocated when collapsing a group -of small pages into one large page:: +``max_ptes_none`` specifies how many empty (none/zero) pages are allowed +when collapsing a group of small pages into one large page:: /sys/kernel/mm/transparent_hugepage/khugepaged/max_ptes_none -A higher value leads to use additional memory for programs. -A lower value leads to gain less thp performance. Value of -max_ptes_none can waste cpu time very little, you can -ignore it. +For PMD-sized THP collapse, this directly limits the number of empty pages +allowed in the 2MB region. + +For mTHP collapse, only 0 or (HPAGE_PMD_NR - 1) are supported. At +HPAGE_PMD_NR - 1, we collapse to the highest possible order. Any intermediate +value will emit a warning and mTHP collapse will default to max_ptes_none=0. + +A higher value allows more empty pages, potentially leading to more memory +usage but better THP performance. A lower value is more conservative and +may result in fewer THP collapses. ``max_ptes_swap`` specifies how many pages can be brought in from swap when collapsing a group of pages into a transparent huge page:: @@ -337,6 +343,15 @@ that THP is shared. Exceeding the number would block the collapse:: A higher value may increase memory footprint for some workloads. +.. note:: + For mTHP collapse, khugepaged does not support collapsing regions that + contain shared or swapped out pages, as this could lead to continuous + promotion to higher orders. The collapse will fail if any shared or + swapped PTEs are encountered during the scan. + + Currently, madvise_collapse only supports collapsing to PMD-sized THPs + and does not attempt mTHP collapses. + Boot parameters =============== @@ -639,6 +654,14 @@ anon_fault_fallback_charge instead falls back to using huge pages with lower orders or small pages even though the allocation was successful. +collapse_alloc + is incremented every time a huge page is successfully allocated for a + khugepaged collapse. + +collapse_alloc_failed + is incremented every time a huge page allocation fails during a + khugepaged collapse. + zswpout is incremented every time a huge page is swapped out to zswap in one piece without splitting. @@ -706,6 +729,20 @@ nr_anon_partially_mapped an anonymous THP as "partially mapped" and count it here, even though it is not actually partially mapped anymore. +collapse_exceed_none_pte + The number of collapse attempts that failed due to exceeding the + max_ptes_none threshold. + +collapse_exceed_swap_pte + The number of collapse attempts that failed due to exceeding the + max_ptes_swap threshold. For non-PMD orders this occurs if a mTHP range + contains at least one swap PTE. + +collapse_exceed_shared_pte + The number of collapse attempts that failed due to exceeding the + max_ptes_shared threshold. For non-PMD orders this occurs if a mTHP range + contains at least one shared PTE. + As the system ages, allocating huge pages may be expensive as the system uses memory compaction to copy data around memory to free a huge page for use. There are some counters in ``/proc/vmstat`` to help diff --git a/Documentation/admin-guide/pm/cpufreq.rst b/Documentation/admin-guide/pm/cpufreq.rst index dbe6d23a5d671d..8831cface58552 100644 --- a/Documentation/admin-guide/pm/cpufreq.rst +++ b/Documentation/admin-guide/pm/cpufreq.rst @@ -516,7 +516,7 @@ This governor exposes the following tunables: of those tasks above 0 and set this attribute to 1. ``sampling_down_factor`` - Temporary multiplier, between 1 (default) and 100 inclusive, to apply to + Temporary multiplier, between 1 (default) and 100000 inclusive, to apply to the ``sampling_rate`` value if the CPU load goes above ``up_threshold``. This causes the next execution of the governor's worker routine (after @@ -586,8 +586,8 @@ This governor exposes the following tunables: 100 (5 by default). This is how much the frequency is allowed to change in one go. Setting - it to 0 will cause the default frequency step (5 percent) to be used - and setting it to 100 effectively causes the governor to periodically + it to 0 disables frequency changes by the governor entirely and setting + it to 100 effectively causes the governor to periodically switch the frequency between the ``scaling_min_freq`` and ``scaling_max_freq`` policy limits. diff --git a/Documentation/admin-guide/pm/intel_uncore_frequency_scaling.rst b/Documentation/admin-guide/pm/intel_uncore_frequency_scaling.rst index d367ba4d744af4..b43ad4d5e333b2 100644 --- a/Documentation/admin-guide/pm/intel_uncore_frequency_scaling.rst +++ b/Documentation/admin-guide/pm/intel_uncore_frequency_scaling.rst @@ -88,8 +88,15 @@ and "fabric_cluster_id" in the directory. Attributes in each directory: +``instance_id`` + This attribute is used to get die indices in userspace mapped MMIO + blocks. Indices are local to a single TPMI partition. Needed for direct + TPMI register access. + ``domain_id`` This attribute is used to get the power domain id of this instance. + Indices are unique in all TPMI partitions on a given CPU package. Can be + used to map compute dies to corresponding CPUs. ``die_id`` This attribute is used to get the Linux die id of this instance. diff --git a/Documentation/admin-guide/quickly-build-trimmed-linux.rst b/Documentation/admin-guide/quickly-build-trimmed-linux.rst index cb178e0a620848..3432dc8e1a8598 100644 --- a/Documentation/admin-guide/quickly-build-trimmed-linux.rst +++ b/Documentation/admin-guide/quickly-build-trimmed-linux.rst @@ -217,7 +217,7 @@ again. There is a catch: 'localmodconfig' is likely to disable kernel features you did not use since you booted your Linux -- like drivers for currently - disconnected peripherals or a virtualization software not haven't used yet. + disconnected peripherals or virtualization software not currently in use. You can reduce or nearly eliminate that risk with tricks the reference section outlines; but when building a kernel just for quick testing purposes it is often negligible if such features are missing. But you should keep that diff --git a/Documentation/admin-guide/reporting-issues.rst b/Documentation/admin-guide/reporting-issues.rst index 16a66a1f1975f0..87dd874fffcf25 100644 --- a/Documentation/admin-guide/reporting-issues.rst +++ b/Documentation/admin-guide/reporting-issues.rst @@ -129,7 +129,7 @@ After these preparations you'll now enter the main part: situations; during the merge window that actually might be even the best approach, but in that development phase it can be an even better idea to suspend your efforts for a few days anyway. Whatever version you choose, - ideally use a 'vanilla' build. Ignoring these advices will dramatically + ideally use a 'vanilla' build. Ignoring all of this advice will dramatically increase the risk your report will be rejected or ignored. * Ensure the kernel you just installed does not 'taint' itself when @@ -795,7 +795,7 @@ Install a fresh kernel for testing situations; during the merge window that actually might be even the best approach, but in that development phase it can be an even better idea to suspend your efforts for a few days anyway. Whatever version you choose, - ideally use a 'vanilla' built. Ignoring these advices will dramatically + ideally use a 'vanilla' built. Ignoring all of this advice will dramatically increase the risk your report will be rejected or ignored.* As mentioned in the detailed explanation for the first step already: Like most diff --git a/Documentation/admin-guide/sysctl/net.rst b/Documentation/admin-guide/sysctl/net.rst index 0724a793798f3d..e586e17fc7a582 100644 --- a/Documentation/admin-guide/sysctl/net.rst +++ b/Documentation/admin-guide/sysctl/net.rst @@ -36,12 +36,11 @@ Table : Subdirectories in /proc/sys/net ========= =================== = ========== =================== 802 E802 protocol mptcp Multipath TCP appletalk Appletalk protocol netfilter Network Filter - ax25 AX25 netrom NET/ROM - bridge Bridging rose X.25 PLP layer - core General parameter tipc TIPC - ethernet Ethernet protocol unix Unix domain sockets - ipv4 IP version 4 vsock VSOCK sockets - ipv6 IP version 6 x25 X.25 protocol + bridge Bridging tipc TIPC + core General parameter unix Unix domain sockets + ethernet Ethernet protocol vsock VSOCK sockets + ipv4 IP version 4 x25 X.25 protocol + ipv6 IP version 6 ========= =================== = ========== =================== 1. /proc/sys/net/core - Network core options @@ -475,51 +474,7 @@ Please see: Documentation/networking/ip-sysctl.rst and Documentation/admin-guide/sysctl/net.rst for descriptions of these entries. -4. Appletalk ------------- - -The /proc/sys/net/appletalk directory holds the Appletalk configuration data -when Appletalk is loaded. The configurable parameters are: - -aarp-expiry-time ----------------- - -The amount of time we keep an ARP entry before expiring it. Used to age out -old hosts. - -aarp-resolve-time ------------------ - -The amount of time we will spend trying to resolve an Appletalk address. - -aarp-retransmit-limit ---------------------- - -The number of times we will retransmit a query before giving up. - -aarp-tick-time --------------- - -Controls the rate at which expires are checked. - -The directory /proc/net/appletalk holds the list of active Appletalk sockets -on a machine. - -The fields indicate the DDP type, the local address (in network:node format) -the remote address, the size of the transmit pending queue, the size of the -received queue (bytes waiting for applications to read) the state and the uid -owning the socket. - -/proc/net/atalk_iface lists all the interfaces configured for appletalk.It -shows the name of the interface, its Appletalk address, the network range on -that address (or network number for phase 1 networks), and the status of the -interface. - -/proc/net/atalk_route lists each known network route. It lists the target -(network) that the route leads to, the router (may be directly connected), the -route flags, and the device the route is using. - -5. TIPC +4. TIPC ------- tipc_rmem diff --git a/Documentation/admin-guide/sysctl/vm.rst b/Documentation/admin-guide/sysctl/vm.rst index 97e12359775c92..b9b0c218bfb440 100644 --- a/Documentation/admin-guide/sysctl/vm.rst +++ b/Documentation/admin-guide/sysctl/vm.rst @@ -1034,6 +1034,8 @@ min(3% of current process size, user_reserve_kbytes) of free memory. This is intended to prevent a user from starting a single memory hogging process, such that they cannot recover (kill the hog). +This setting has no effect when overcommit_memory is set to 0 or 1. + user_reserve_kbytes defaults to min(3% of the current process size, 128MB). If this is reduced to zero, then the user will be allowed to allocate diff --git a/Documentation/admin-guide/thunderbolt.rst b/Documentation/admin-guide/thunderbolt.rst index 89df26553aa037..91a6cb10998891 100644 --- a/Documentation/admin-guide/thunderbolt.rst +++ b/Documentation/admin-guide/thunderbolt.rst @@ -373,6 +373,67 @@ port which are named like ``thunderbolt0`` and so on. From this point you can either use standard userspace tools like ``ip`` to configure the interface or let your GUI handle it automatically. +Streaming data directly over Thunderbolt cable +---------------------------------------------- +In addition to Thunderbolt networking (aka. USB4NET) Linux supports +streaming data directly over a cable as well (aka. USB4STREAM). This is +possible through ``thunderbolt-stream`` driver. + +Similarly to ``thunderbolt-net`` you load the driver first on one end:: + + host1 # modprobe thunderbolt-stream + +Then you configure it via ``ConfigFS``:: + + host1 # cd /sys/kernel/config/thunderbolt/stream + host1 # mkdir -p 0-1.0/data + host1 # cd 0-1.0 + host1 # echo -1 > data/in_hopid + host1 # echo -1 > data/out_hopid + +This information is automatically announced to the other side via +XDomain properties so if you have cable connected the other side knows +that there is a stream named ``data`` available and can configure it for +you automatically:: + + host2 # cd /sys/kernel/config/thunderbolt/stream + host2 # mkdir -p 0-3.0/data + +Here we used auto-configuration but you can configure it manually too. +In that case you need to fill ``in_hopid`` and ``out_hopid`` accordingly. +If you set them to ``-1`` the next available HopID is used which is +typically what we want. + +Once they are configured you can use ``/dev/tbstreamX`` on both sides to +transfer data:: + + host2 # cat /dev/tbstream0 + host1 # dmesg > /dev/tbstream0 + +Once you are done with the stream you can remove them:: + + host2 # cd /sys/kernel/config/thunderbolt/stream + host2 # rmdir -p 0-1.0/data + host1 # cd /sys/kernel/config/thunderbolt/stream + host1 # rmdir -p 0-3.0/data + +Since streams are essentially files you can use any existing application +that supports ``read(2)`` and ``write(2)`` in some form. + +It is possible to have more than one stream and you can have both stream +and ``thunderbolt-net`` in use simultaneously. For example we can create +two streams with name ``control`` and ``data`` like this:: + + host1 # cd /sys/kernel/config/thunderbolt/stream + host1 # mkdir 0-1.0 + host1 # cd 0-1.0 + host1 # mkdir control + host1 # mkdir data + +Then you have ``/dev/tbstream0`` for ``control`` and ``/dev/tbstream1`` +for ``data``. Before you can use them you need to configure them as +shown above for the one stream case. + Forcing power ------------- Many OEMs include a method that can be used to force the power of a diff --git a/Documentation/admin-guide/workload-tracing.rst b/Documentation/admin-guide/workload-tracing.rst index 35963491b9f196..314e5f03474e6f 100644 --- a/Documentation/admin-guide/workload-tracing.rst +++ b/Documentation/admin-guide/workload-tracing.rst @@ -202,6 +202,15 @@ database. To get out of this mode press ctrl+d. -p option is used to specify the number of file path components to display. -p10 is optimal for browsing kernel sources. +Alternatively, the kernel build system can generate the cscope database:: + + make cscope + +To exclude directories from the generated database, pass IGNORE_DIRS to +the cscope target. For example, to exclude Documentation/, run:: + + make IGNORE_DIRS="Documentation" cscope + What is perf and how do we use it? ================================== @@ -243,13 +252,21 @@ which can help mitigate performance regressions. It also acts as a common benchmarking framework, enabling developers to easily create test cases, integrate transparently, and use performance-rich tooling. -"perf bench all" command runs the following benchmarks: +"perf bench all" runs all available benchmarks in the perf bench +framework. The exact set of benchmarks depends on the perf version and on +the features enabled when perf was built. + +To list the benchmark collections available on the current system, run:: + + perf bench + +To list benchmarks in a collection, run:: + + perf bench + +For example, to list the benchmarks in the mem collection, run:: - * sched/messaging - * sched/pipe - * syscall/basic - * mem/memcpy - * mem/memset + perf bench mem What is stress-ng and how do we use it? ======================================= @@ -271,17 +288,17 @@ exercised: The following command runs the stressor:: - stress-ng --netdev 1 -t 60 --metrics command. + stress-ng --netdev 1 -t 60 --metrics We can use the perf record command to record the events and information associated with a process. This command records the profiling data in the perf.data file in the same directory. Using the following commands you can record the events associated with the -netdev stressor, view the generated report perf.data and annotate the to -view the statistics of each instruction of the program:: +netdev stressor, view the generated report perf.data and annotate the output +to view the statistics of each instruction of the program:: - perf record stress-ng --netdev 1 -t 60 --metrics command. + perf record -- stress-ng --netdev 1 -t 60 --metrics perf report perf annotate @@ -349,13 +366,13 @@ times each system call is invoked, and the corresponding Linux subsystem. +-------------------+-----------+-----------------+-------------------------+ | geteuid | 1 | Process Mgmt. | sys_geteuid() | +-------------------+-----------+-----------------+-------------------------+ -| getegid | 1 | Process Mgmt. | sys_getegid | +| getegid | 1 | Process Mgmt. | sys_getegid() | +-------------------+-----------+-----------------+-------------------------+ | close | 49951 | Filesystem | sys_close() | +-------------------+-----------+-----------------+-------------------------+ | pipe | 604 | Filesystem | sys_pipe() | +-------------------+-----------+-----------------+-------------------------+ -| openat | 48560 | Filesystem | sys_opennat() | +| openat | 48560 | Filesystem | sys_openat() | +-------------------+-----------+-----------------+-------------------------+ | fstat | 8338 | Filesystem | sys_fstat() | +-------------------+-----------+-----------------+-------------------------+ diff --git a/Documentation/arch/arc/arc.rst b/Documentation/arch/arc/arc.rst index 6c4d978f3f4e8f..5923dee37a984d 100644 --- a/Documentation/arch/arc/arc.rst +++ b/Documentation/arch/arc/arc.rst @@ -36,7 +36,7 @@ Important note on ARC processors configurability ARC processors are highly configurable and several configurable options are supported in Linux. Some options are transparent to software -(i.e cache geometries, some can be detected at runtime and configured +(e.g., cache geometries), some can be detected at runtime and configured and used accordingly, while some need to be explicitly selected or configured in the kernel's configuration utility (AKA "make menuconfig"). diff --git a/Documentation/arch/arm/index.rst b/Documentation/arch/arm/index.rst index afe17db294c4ab..b15621093f7a22 100644 --- a/Documentation/arch/arm/index.rst +++ b/Documentation/arch/arm/index.rst @@ -75,3 +75,5 @@ SoC-specific documents sti/overview vfp/release-notes + + zte/index diff --git a/Documentation/arch/arm/kernel_mode_neon.rst b/Documentation/arch/arm/kernel_mode_neon.rst index 9bfb71a2a9b961..1efb6d35b7bd0c 100644 --- a/Documentation/arch/arm/kernel_mode_neon.rst +++ b/Documentation/arch/arm/kernel_mode_neon.rst @@ -121,4 +121,6 @@ observe the following in addition to the rules above: * Compile the unit containing the NEON intrinsics with '-ffreestanding' so GCC uses its builtin version of (this is a C99 header which the kernel does not supply); -* Include last, or at least after +* Do not include directly: instead, include , + which tweaks some macro definitions so that system headers can be included + safely. diff --git a/Documentation/arch/arm/omap/dss.rst b/Documentation/arch/arm/omap/dss.rst index a40c4d9c717a74..9d39679235a337 100644 --- a/Documentation/arch/arm/omap/dss.rst +++ b/Documentation/arch/arm/omap/dss.rst @@ -314,7 +314,7 @@ Kernel boot arguments omapfb.mode=:[,...] - Default video mode for specified displays. For example, - "dvi:800x400MR-24@60". See drivers/video/modedb.c. + "dvi:800x400MR-24@60". See drivers/video/fbdev/core/modedb.c. There are also two special modes: "pal" and "ntsc" that can be used to tv out. diff --git a/Documentation/arch/arm/samsung/clksrc-change-registers.awk b/Documentation/arch/arm/samsung/clksrc-change-registers.awk index 7be1b8aa7cd9a7..48464397088c6d 100755 --- a/Documentation/arch/arm/samsung/clksrc-change-registers.awk +++ b/Documentation/arch/arm/samsung/clksrc-change-registers.awk @@ -163,4 +163,4 @@ BEGIN { } } -// && ! /clksrc_clk.*=.*{/ { print $0 } +// && ! /clksrc_clk.*=.*{/ { print $0 }} diff --git a/Documentation/arch/arm/vlocks.rst b/Documentation/arch/arm/vlocks.rst index 737aa8661a211a..b0ac3326308687 100644 --- a/Documentation/arch/arm/vlocks.rst +++ b/Documentation/arch/arm/vlocks.rst @@ -102,10 +102,10 @@ Features and limitations if (I_won) { /* we won the town election, let's go for the state */ my_state = states[(this_cpu >> 8) & 0xf]; - I_won = vlock_lock(my_state, this_cpu & 0xf)); + I_won = vlock_lock(my_state, this_cpu & 0xf); if (I_won) { /* and so on */ - I_won = vlock_lock(the_whole_country, this_cpu & 0xf]; + I_won = vlock_lock(the_whole_country, this_cpu & 0xf); if (I_won) { /* ... */ } diff --git a/Documentation/arch/arm/zte/index.rst b/Documentation/arch/arm/zte/index.rst new file mode 100644 index 00000000000000..0ed80b60b7463b --- /dev/null +++ b/Documentation/arch/arm/zte/index.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +======= +ZTE SoC +======= + +.. toctree:: + :maxdepth: 1 + + zx297520v3 diff --git a/Documentation/arch/arm/zte/zx297520v3.rst b/Documentation/arch/arm/zte/zx297520v3.rst new file mode 100644 index 00000000000000..d33f454bc895c8 --- /dev/null +++ b/Documentation/arch/arm/zte/zx297520v3.rst @@ -0,0 +1,166 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +==================================== +Booting Linux on ZTE zx297520v3 SoCs +==================================== + +Author: Stefan Dösinger + +Date : 27 Jan 2026 + +1. Hardware description +--------------------------- +Zx297520v3 SoCs use a 64-bit capable Cortex-A53 CPU and GICv3, although they +run in arm32 mode only. The CPU has support EL3, but no hypervisor (EL2) and +it seems to lack VFP and NEON. + +The SoC is used in a number of cheap LTE to WiFi routers, both battery powered +MiFis and stationary CPEs. In addition to the CPU these devices usually have +64 MB Ram (although some is shared with the LTE chip), 128 MB NAND flash, an +SDIO connected RTL8192-type Wifi chip limited to 2.4 ghz operation, USB 2, +and buttons. Devices with as low as 32 MB or as high as 128 MB ram exist, as +do devices with 8 or 16 MB of NOR flash. + +Some devices, especially the stationary ones, have 100 mbit Ethernet and an +Ethernet switch. + +Usually the devices have LEDs for status indication, although some have SPI or +I2C connected displays. + +Some have an SD card slot. If it exists, it is a better choice for the root +file system because it easily outperforms the built-in NAND. + +The LTE interface runs on a separate DSP called ZSP880. It is probably derived +from LSI ZSPs and has an undocumented instruction set. The ZSP communicates +with the main CPU via SRAM and DRAM and a mailbox hardware that can generate +IRQs on either ends. + +There is also a Cortex M0 CPU, which is responsible for early HW initialization +and starting the Cortex A53 CPU. It does not have any essential purpose once +U-Boot is started. An SRAM-based handover protocol exists to run custom code on +this CPU. + +2. Booting via USB +--------------------------- + +The Boot ROM has support for booting custom code via USB. This mode can be +entered by connecting a Boot PIN to GND or by modifying the third byte on NAND +(set it to anything other than 0x5A aka 'Z'). A free software tool to start +custom U-Boot and kernels can be found here: + +https://github.com/zx297520v3-mainline/zx297520v3-loader + +If USB download mode is entered but no boot commands are sent through USB, the +device will proceed to boot normally after a few seconds. It is therefore +possible to enable USB boot permanently and still leave the default boot files +in place. + +https://github.com/zx297520v3-mainline/u-boot-mainline + +Contains an U-Boot version that can be used with the USB loader and sets up the +CPU and interrupt controller to comply with Linux's booting requirements. + +3. Building for built-in U-Boot +------------------------------- +The devices come with an ancient U-Boot that loads legacy uImages from NAND and +boots them without a chance for the user to interrupt. The images are stored in +files ap_cpuap.bin and ap_recovery.bin on a jffs2 partition named imagefs, +usually mtd4. A file named "fotaflag" switches between the two modes. + +In addition to the uImage header, those files have a 384-byte signature header, +which is used for authenticating the images on some devices. Most devices have +this authentication disabled and it is enough to pad the uImage files with 384 +zero bytes. + +Builtin U-Boot also poorly sets up the CPU. Read the next section for details +on this. It has no support for loading DTBs, so CONFIG_ARM_APPENDED_DTB is +needed. + +So to build an image that boots from NAND the following steps are necessary: + +1) Patch the assembly code from section 3 into arch/arm/kernel/head.S. +2) make zx29_defconfig +3) make [-j x] +4) cat arch/arm/boot/zImage arch/arm/boot/dts/zte/[device].dtb > kernel+dtb +5) mkimage -A arm -O linux -T kernel -C none -a 0x20008000 -d kernel+dtb uimg +6) dd if=/dev/zero bs=1 count=384 of=ap_recovery.bin +7) cat uimg >> ap_recovery.bin +8) Place this file onto imagefs on the device. Delete ap_cpuap.bin if the + free space is not enough. +9) Create the file fotaflag: echo -n FOTA-RECOVERY > fotaflag + +For development, booting ap_recovery.bin is recommended because the normal boot +mode arms the watchdog before starting the kernel. + +4. CPU and GIC Setup +--------------------------- + +Generally CPU and GICv3 need to be set up according to the requirements spelled +out in Documentation/arch/arm64/booting.rst. For zx297520v3 this means: + +1. GICD_CTLR.DS=1 to disable GIC security +2. Enable access to ICC_SRE +3. Disable trapping IRQs into monitor mode +4. Configure EL2 and below to run in insecure mode. +5. Configure timer PPIs to active-low. + +The kernel sources provided by ZTE do not boot either (interrupts do not work +at all). They are incomplete in other aspects too, so it is assumed that there +is some workaround similar to the one described in this document somewhere in +the binary blobs. + +The assembly code below is given as an example of how to achieve this: + +:: + + #include + #include + #include + + @ Detect sane bootloaders and skip the hack + ldr r3, =0xf2000000 + ldr r3, [r3] + ldr r4, =(GICD_CTLR_ARE_NS | GICD_CTLR_DS) + cmp r3, r4 + beq skip_zx_hack + @ This allows EL1 to handle ints hat are normally handled by EL2/3. + ldr r3, =0xf2000000 + str r4, [r3] + + cps #MON_MODE + + @ Work in non-secure physical address space: SCR_EL3.NS = 1. At least the UART + @ seems to respond only to non-secure addresses. I have taken insipiration from + @ Raspberry pi's armstub7.S here. + mov r3, #0x131 @ non-secure, Make F, A bits in CPSR writeable + @ Allow hypervisor call. + mcr p15, 0, r3, c1, c1, 0 + + @ AP_PPI_MODE_REG: Configure timer PPIs (10, 11, 13, 14) to active-low. + ldr r3, =0xF22020a8 + ldr r4, =0x50 + str r4, [r3] + ldr r3, =0xF22020ac + ldr r4, =0x14 + str r4, [r3] + + @ Enable EL2 access to ICC_SRE (bit 3, ICC_SRE_EL3.Enable). Enable system reg + @ access to GICv3 registers (bit 0, ICC_SRE_EL3.SRE) for EL1 and EL3. + mrc p15, 6, r3, c12, c12, 5 @ ICC_SRE_EL3 + orr r3, #0x9 @ FIXME: No defines for SRE_EL3 values? + mcr p15, 6, r3, c12, c12, 5 + mrc p15, 0, r3, c12, c12, 5 @ ICC_SRE_EL1 + orr r3, #(ICC_SRE_EL1_SRE) + mcr p15, 0, r3, c12, c12, 5 + + @ Like ICC_SRE_EL3, enable EL1 access to ICC_SRE and system register access + @ for EL2. + mrc p15, 4, r3, c12, c9, 5 @ ICC_SRE_EL2 aka ICC_HSRE + orr r3, r3, #(ICC_SRE_EL2_ENABLE | ICC_SRE_EL2_SRE) + mcr p15, 4, r3, c12, c9, 5 + isb + + @ Back to SVC mode + cps #SVC_MODE + skip_zx_hack: + diff --git a/Documentation/arch/arm64/cpu-hotplug.rst b/Documentation/arch/arm64/cpu-hotplug.rst index 8fb438bf778162..7c3379b704aaf6 100644 --- a/Documentation/arch/arm64/cpu-hotplug.rst +++ b/Documentation/arch/arm64/cpu-hotplug.rst @@ -47,11 +47,12 @@ ever have can be described at boot. There are no power-domain considerations as such devices are emulated. CPU Hotplug on virtual systems is supported. It is distinct from physical -CPU Hotplug as all resources are described as ``present``, but CPUs may be -marked as disabled by firmware. Only the CPU's online/offline behaviour is -influenced by firmware. An example is where a virtual machine boots with a -single CPU, and additional CPUs are added once a cloud orchestrator deploys -the workload. +CPU Hotplug as all vCPU resources are statically described in the firmware +configuration tables (e.g. MADT), meaning their maximum possible count is +known at boot. However, vCPUs that are not enabled at boot are not marked +as ``present`` by the kernel until they are hotplugged. An example is where +a virtual machine boots with a single CPU, and additional CPUs are added +once a cloud orchestrator deploys the workload. For a virtual machine, the VMM (e.g. Qemu) plays the part of firmware. @@ -60,16 +61,19 @@ brought online. Firmware can enforce its policy via PSCI's return codes. e.g. ``DENIED``. The ACPI tables must describe all the resources of the virtual machine. CPUs -that firmware wishes to disable either from boot (or later) should not be -``enabled`` in the MADT GICC structures, but should have the ``online capable`` -bit set, to indicate they can be enabled later. The boot CPU must be marked as -``enabled``. The 'always on' GICR structure must be used to describe the -redistributors. +that are hot-pluggable must have the ``online capable`` bit set and the +``enabled`` bit cleared in the MADT GICC structures to indicate they can be +enabled later. The boot CPU must be marked as ``enabled`` with its +``online capable`` bit cleared. The 'always on' GICR structure must be used +to describe the redistributors. CPUs described as ``online capable`` but not ``enabled`` can be set to enabled by the DSDT's Processor object's _STA method. On virtual systems the _STA method -must always report the CPU as ``present``. Changes to the firmware policy can -be notified to the OS via device-check or eject-request. +must always set the ``ACPI_STA_DEVICE_PRESENT`` bit, while toggling the +``ACPI_STA_DEVICE_ENABLED`` bit to reflect its plug status. The kernel will +then dynamically mark the vCPU as ``present`` within the OS when the +``ACPI_STA_DEVICE_ENABLED`` bit becomes set during hot-add. Changes to the +firmware policy can be notified to the OS via device-check or eject-request. CPUs described as ``enabled`` in the static table, should not have their _STA modified dynamically by firmware. Soft-restart features such as kexec will diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst index 97315ae6c0daee..f60ca5612daa43 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -451,6 +451,33 @@ HWCAP3_LS64 of CPU. User should only use ld64b/st64b on supported target (device) memory location, otherwise fallback to the non-atomic alternatives. +HWCAP3_SVE_B16MM + Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and + ID_AA64ZFR0_EL1.B16B16 == 0b0011 + +HWCAP3_SVE2P3 + Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and + ID_AA64ZFR0_EL1.SVEver == 0b0100 + +HWCAP3_SME_LUT6 + Functionality implied by ID_AA64SMFR0_EL1.LUT6 == 0b1 + +HWCAP3_SME2P3 + Functionality implied by ID_AA64SMFR0_EL1.SMEver == 0b0100 + +HWCAP3_F16MM + Functionality implied by ID_AA64FPFR0_EL1.F16MM2 == 0b1 + +HWCAP3_F16F32DOT + Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0010 + +HWCAP3_F16F32MM + Functionality implied by ID_AA64ISAR0_EL1.FHM == 0b0011 + +HWCAP3_SVE_LUT6 + Functionality implied by ID_AA64PFR0_EL1.SVE == 0b0001 and + ID_AA64ISAR2_EL1.LUT == 0b0010. + 4. Unused AT_HWCAP bits ----------------------- diff --git a/Documentation/arch/arm64/memory-tagging-extension.rst b/Documentation/arch/arm64/memory-tagging-extension.rst index 679725030731d0..e6fe428f0e2a4a 100644 --- a/Documentation/arch/arm64/memory-tagging-extension.rst +++ b/Documentation/arch/arm64/memory-tagging-extension.rst @@ -222,7 +222,7 @@ programs should not retry in case of a non-zero system call return. address ABI control and MTE configuration of a process as per the ``prctl()`` options described in Documentation/arch/arm64/tagged-address-abi.rst and above. The corresponding -``regset`` is 1 element of 8 bytes (``sizeof(long))``). +``regset`` is 1 element of 8 bytes (``sizeof(long)``). Core dump support ----------------- diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index 211119ce7adc7c..014aa1c215a16a 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -116,7 +116,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 | +----------------+-----------------+-----------------+-----------------------------+ -| ARM | Cortex-A76 | #1188873,1418040| ARM64_ERRATUM_1418040 | +| ARM | Cortex-A76 | #1188873, | ARM64_ERRATUM_1418040 | +| | | #1418040 | | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A76 | #1165522 | ARM64_ERRATUM_1165522 | +----------------+-----------------+-----------------+-----------------------------+ @@ -128,15 +129,28 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A76 | #3324349 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A76 | #4193800 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A76AE | #4193801 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A77 | #1491015 | N/A | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A77 | #3324348 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A77 | #4193798 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A78 | #3324344 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ -| ARM | Cortex-A78C | #3324346,3324347| ARM64_ERRATUM_3194386 | +| ARM | Cortex-A78 | #4193791 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A78AE | #4193793 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A78C | #3324346, | ARM64_ERRATUM_3194386 | +| | | #3324347 | | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A78C | #4193794 | ARM64_ERRATUM_4118414 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 | +----------------+-----------------+-----------------+-----------------------------+ @@ -146,6 +160,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A710 | #3324338 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-A710 | #4193788 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A715 | #2645198 | ARM64_ERRATUM_2645198 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-A715 | #3456084 | ARM64_ERRATUM_3194386 | @@ -158,30 +174,44 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1 | #3324344 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-X1 | #4193791 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X1C | #3324346 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-X1C | #4193792 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X2 | #3324338 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-X2 | #4193788 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X3 | #3324335 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-X3 | #4193786 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Cortex-X4 | #4118414 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Cortex-X925 | #3324334 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ -| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 | +| ARM | Cortex-X925 | #4193781 | ARM64_ERRATUM_4118414 | +----------------+-----------------+-----------------+-----------------------------+ -| ARM | Neoverse-N1 | #1349291 | N/A | +| ARM | Neoverse-N1 | #1188873, | ARM64_ERRATUM_1418040 | +| | | #1418040 | | +----------------+-----------------+-----------------+-----------------------------+ -| ARM | Neoverse-N1 | #1490853 | N/A | +| ARM | Neoverse-N1 | #1349291, | N/A | +| | | #1490853 | | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N1 | #1542419 | ARM64_ERRATUM_1542419 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N1 | #3324349 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-N1 | #4193800 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 | @@ -190,24 +220,41 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N2 | #3324339 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-N2 | #4193789 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-N3 | #3456111 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-V1 | #1619801 | N/A | +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-V1 | #4193790 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-V2 | #4193787 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-V3 | #4193784 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-V3AE | #3312417 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-V3AE | #4193784 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | C1-Premium | #4193780 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | C1-Pro | #4193714 | ARM64_ERRATUM_4193714 | +----------------+-----------------+-----------------+-----------------------------+ -| ARM | MMU-500 | #841119,826419 | ARM_SMMU_MMU_500_CPRE_ERRATA| -| | | #562869,1047329 | | +| ARM | C1-Ultra | #4193780 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ +| ARM | MMU-500 | #562869, | ARM_SMMU_MMU_500_CPRE_ERRATA| +| | | #841119, | | +| | | #826419, | | +| | | #1047329 | | +----------------+-----------------+-----------------+-----------------------------+ -| ARM | MMU-600 | #1076982,1209401| N/A | +| ARM | MMU-600 | #1076982, | N/A | +| | | #1209401 | | +----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-700 | #2133013, | N/A | | | | #2268618, | | @@ -230,11 +277,13 @@ stable kernels. | Broadcom | Brahma-B53 | N/A | ARM64_ERRATUM_843419 | +----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ -| Cavium | ThunderX ITS | #22375,24313 | CAVIUM_ERRATUM_22375 | +| Cavium | ThunderX ITS | #22375, | CAVIUM_ERRATUM_22375 | +| | | #24313 | | +----------------+-----------------+-----------------+-----------------------------+ | Cavium | ThunderX ITS | #23144 | CAVIUM_ERRATUM_23144 | +----------------+-----------------+-----------------+-----------------------------+ -| Cavium | ThunderX GICv3 | #23154,38545 | CAVIUM_ERRATUM_23154 | +| Cavium | ThunderX GICv3 | #23154, | CAVIUM_ERRATUM_23154 | +| | | #38545 | | +----------------+-----------------+-----------------+-----------------------------+ | Cavium | ThunderX GICv3 | #38539 | N/A | +----------------+-----------------+-----------------+-----------------------------+ @@ -244,9 +293,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Cavium | ThunderX SMMUv2 | #27704 | N/A | +----------------+-----------------+-----------------+-----------------------------+ -| Cavium | ThunderX2 SMMUv3| #74 | N/A | -+----------------+-----------------+-----------------+-----------------------------+ -| Cavium | ThunderX2 SMMUv3| #126 | N/A | +| Cavium | ThunderX2 SMMUv3| #74, | N/A | +| | | #126 | | +----------------+-----------------+-----------------+-----------------------------+ | Cavium | ThunderX2 Core | #219 | CAVIUM_TX2_ERRATUM_219 | +----------------+-----------------+-----------------+-----------------------------+ @@ -256,13 +304,13 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | NVIDIA | Carmel Core | N/A | NVIDIA_CARMEL_CNP_ERRATUM | +----------------+-----------------+-----------------+-----------------------------+ -| NVIDIA | T241 GICv3/4.x | T241-FABRIC-4 | N/A | -+----------------+-----------------+-----------------+-----------------------------+ -| NVIDIA | T241 MPAM | T241-MPAM-1 | N/A | +| NVIDIA | Olympus core | T410-OLY-1029 | ARM64_ERRATUM_4118414 | +----------------+-----------------+-----------------+-----------------------------+ -| NVIDIA | T241 MPAM | T241-MPAM-4 | N/A | +| NVIDIA | T241 GICv3/4.x | T241-FABRIC-4 | N/A | +----------------+-----------------+-----------------+-----------------------------+ -| NVIDIA | T241 MPAM | T241-MPAM-6 | N/A | +| NVIDIA | T241 MPAM | T241-MPAM-1, | N/A | +| | | T241-MPAM-4, | | +| | | T241-MPAM-6 | | +----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ | Freescale/NXP | LS2080A/LS1043A | A-008585 | FSL_ERRATUM_A008585 | @@ -270,9 +318,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 | +----------------+-----------------+-----------------+-----------------------------+ -| Hisilicon | Hip0{6,7} | #161010701 | N/A | -+----------------+-----------------+-----------------+-----------------------------+ -| Hisilicon | Hip0{6,7} | #161010803 | N/A | +| Hisilicon | Hip0{6,7} | #161010701, | N/A | +| | | #161010803 | | +----------------+-----------------+-----------------+-----------------------------+ | Hisilicon | Hip07 | #161600802 | HISILICON_ERRATUM_161600802 | +----------------+-----------------+-----------------+-----------------------------+ @@ -284,6 +331,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Hisilicon | Hip09 | #162100801 | HISILICON_ERRATUM_162100801 | +----------------+-----------------+-----------------+-----------------------------+ +| Hisilicon | Hip09 | #162100125 | HISILICON_ERRATUM_162100125 | ++----------------+-----------------+-----------------+-----------------------------+ +----------------+-----------------+-----------------+-----------------------------+ | Qualcomm Tech. | Kryo/Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 | +----------------+-----------------+-----------------+-----------------------------+ @@ -323,3 +372,5 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | Microsoft | Azure Cobalt 100| #3324339 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| Microsoft | Azure Cobalt 100| #4193789 | ARM64_ERRATUM_4118414 | ++----------------+-----------------+-----------------+-----------------------------+ diff --git a/Documentation/arch/loongarch/irq-chip-model.rst b/Documentation/arch/loongarch/irq-chip-model.rst index 8f5c3345109e6a..774d40dc6a7eeb 100644 --- a/Documentation/arch/loongarch/irq-chip-model.rst +++ b/Documentation/arch/loongarch/irq-chip-model.rst @@ -181,6 +181,41 @@ go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and then go to CPUINTC directly:: | Devices | +---------+ +Advanced Extended IRQ model (with redirection) +============================================== + +In this model, IPI (Inter-Processor Interrupt) and CPU Local Timer interrupt go +to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, PCH-MSI interrupts go +to REDIRECT for remapping it to AVECINTC, and then go to CPUINTC directly, while +all other devices interrupts go to PCH-PIC/PCH-LPC and gathered by EIOINTC, and +then go to CPUINTC directly:: + + +-----+ +-----------------------+ +-------+ + | IPI | --> | CPUINTC | <-- | Timer | + +-----+ +-----------------------+ +-------+ + ^ ^ ^ + | | | + | +----------+ | + +---------+ | AVECINTC | +---------+ +-------+ + | EIOINTC | +----------+ | LIOINTC | <-- | UARTs | + +---------+ | REDIRECT | +---------+ +-------+ + ^ +----------+ + | ^ + | | + +---------+ +---------+ + | PCH-PIC | | PCH-MSI | + +---------+ +---------+ + ^ ^ ^ + | | | + +---------+ +---------+ +---------+ + | Devices | | PCH-LPC | | Devices | + +---------+ +---------+ +---------+ + ^ + | + +---------+ + | Devices | + +---------+ + ACPI-related definitions ======================== diff --git a/Documentation/arch/m68k/kernel-options.rst b/Documentation/arch/m68k/kernel-options.rst index 2008a20b43295b..c59e7aaed44ec5 100644 --- a/Documentation/arch/m68k/kernel-options.rst +++ b/Documentation/arch/m68k/kernel-options.rst @@ -244,23 +244,7 @@ drive (with "root="). 3) General Device Options (Amiga and Atari) =========================================== -3.1) ether= ------------ - -:Syntax: ether=[[,[,[,]]]], - - is the name of a net driver, as specified in -drivers/net/Space.c in the Linux source. Most prominent are eth0, ... -eth3, sl0, ... sl3, ppp0, ..., ppp3, dummy, and lo. - -The non-ethernet drivers (sl, ppp, dummy, lo) obviously ignore the -settings by this options. Also, the existing ethernet drivers for -Linux/m68k (ariadne, a2065, hydra) don't use them because Zorro boards -are really Plug-'n-Play, so the "ether=" option is useless altogether -for Linux/m68k. - - -3.2) hd= +3.1) hd= -------- :Syntax: hd=,, @@ -273,7 +257,7 @@ itself. It exists just for the case that this fails for one of your disks. -3.3) max_scsi_luns= +3.2) max_scsi_luns= ------------------- :Syntax: max_scsi_luns= @@ -284,7 +268,7 @@ be scanned. Valid values for are between 1 and 8. Default is 8 if configuration, else 1. -3.4) st= +3.3) st= -------- :Syntax: st=,[,[]] @@ -297,7 +281,7 @@ total number of buffers. limits the total number of buffers allocated for all tape devices. -3.5) dmasound= +3.4) dmasound= -------------- :Syntax: dmasound=[,[,]] diff --git a/Documentation/arch/powerpc/vas-api.rst b/Documentation/arch/powerpc/vas-api.rst index a9625a2fa0c634..1d0d055356e3cc 100644 --- a/Documentation/arch/powerpc/vas-api.rst +++ b/Documentation/arch/powerpc/vas-api.rst @@ -293,7 +293,7 @@ Simple example //Format CRB request with compression or //uncompression // Refer tests for vas_copy/vas_paste - vas_copy((&crb, 0, 1); + vas_copy(&crb, 0, 1); vas_paste(addr, 0, 1); // Poll on csb.flags with timeout // csb address is listed in CRB diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index c420a8349bc681..d9928641deb993 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -82,121 +82,121 @@ The following keys are defined: version 1.0 of the RISC-V Vector extension manual. * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is - supported, as defined in version 1.0 of the Bit-Manipulation ISA - extensions. + supported, as defined in version 1.0 of the Bit-Manipulation ISA + extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined - in version 1.0 of the Bit-Manipulation ISA extensions. + in version 1.0 of the Bit-Manipulation ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined - in version 1.0 of the Bit-Manipulation ISA extensions. + in version 1.0 of the Bit-Manipulation ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as - ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. * :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined - in version 1.0 of the Bit-Manipulation ISA extensions. + in version 1.0 of the Bit-Manipulation ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as - defined in version 1.0 of the Scalar Crypto ISA extensions. + defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as - defined in version 1.0 of the Scalar Crypto ISA extensions. + defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as - defined in version 1.0 of the Scalar Crypto ISA extensions. + defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as - defined in version 1.0 of the Scalar Crypto ISA extensions. + defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as - defined in version 1.0 of the Scalar Crypto ISA extensions. + defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as - defined in version 1.0 of the Scalar Crypto ISA extensions. + defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as - defined in version 1.0 of the Scalar Crypto ISA extensions. + defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as - defined in version 1.0 of the Scalar Crypto ISA extensions. + defined in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined - in version 1.0 of the Scalar Crypto ISA extensions. + in version 1.0 of the Scalar Crypto ISA extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as - defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as - defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as - defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as - defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as - defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as - defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as - defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as - defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as - defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as - defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. + defined in version 1.0 of the RISC-V Cryptography Extensions Volume II. * :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported - as defined in the RISC-V ISA manual. + as defined in the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is - supported as defined in the RISC-V ISA manual. + supported as defined in the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0 - is supported as defined in the RISC-V ISA manual. + is supported as defined in the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as - defined in the RISC-V Vector manual starting from commit e2ccd0548d6c - ("Remove draft warnings from Zvfh[min]"). + defined in the RISC-V Vector manual starting from commit e2ccd0548d6c + ("Remove draft warnings from Zvfh[min]"). * :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as - defined in the RISC-V Vector manual starting from commit e2ccd0548d6c - ("Remove draft warnings from Zvfh[min]"). + defined in the RISC-V Vector manual starting from commit e2ccd0548d6c + ("Remove draft warnings from Zvfh[min]"). * :c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as - defined in the RISC-V ISA manual starting from commit 056b6ff467c7 - ("Zfa is ratified"). + defined in the RISC-V ISA manual starting from commit 056b6ff467c7 + ("Zfa is ratified"). * :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as - defined in the RISC-V ISA manual starting from commit 5618fb5a216b - ("Ztso is now ratified.") + defined in the RISC-V ISA manual starting from commit 5618fb5a216b + ("Ztso is now ratified.") * :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as - defined in the Atomic Compare-and-Swap (CAS) instructions manual starting - from commit 5059e0ca641c ("update to ratified"). + defined in the Atomic Compare-and-Swap (CAS) instructions manual starting + from commit 5059e0ca641c ("update to ratified"). * :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0 - is supported as defined in the RISC-V ISA manual. + is supported as defined in the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as - defined in the RISC-V Integer Conditional (Zicond) operations extension - manual starting from commit 95cf1f9 ("Add changes requested by Ved - during signoff") + defined in the RISC-V Integer Conditional (Zicond) operations extension + manual starting from commit 95cf1f9 ("Add changes requested by Ved + during signoff") * :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is - supported as defined in the RISC-V ISA manual starting from commit - d8ab5c78c207 ("Zihintpause is ratified"). + supported as defined in the RISC-V ISA manual starting from commit + d8ab5c78c207 ("Zihintpause is ratified"). * :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0 - is supported as defined in the RISC-V ISA manual. + is supported as defined in the RISC-V ISA manual. * :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is supported, as defined by version 1.0 of the RISC-V Vector extension manual. @@ -214,84 +214,89 @@ The following keys are defined: supported, as defined by version 1.0 of the RISC-V Vector extension manual. * :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is - supported as defined in the RISC-V ISA manual starting from commit - 58220614a5f ("Zimop is ratified/1.0"). + supported as defined in the RISC-V ISA manual starting from commit + 58220614a5f ("Zimop is ratified/1.0"). * :c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard - extensions for code size reduction, as ratified in commit 8be3419c1c0 - ("Zcf doesn't exist on RV64 as it contains no instructions") of - riscv-code-size-reduction. + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. * :c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard - extensions for code size reduction, as ratified in commit 8be3419c1c0 - ("Zcf doesn't exist on RV64 as it contains no instructions") of - riscv-code-size-reduction. + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. * :c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard - extensions for code size reduction, as ratified in commit 8be3419c1c0 - ("Zcf doesn't exist on RV64 as it contains no instructions") of - riscv-code-size-reduction. + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. * :c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard - extensions for code size reduction, as ratified in commit 8be3419c1c0 - ("Zcf doesn't exist on RV64 as it contains no instructions") of - riscv-code-size-reduction. + extensions for code size reduction, as ratified in commit 8be3419c1c0 + ("Zcf doesn't exist on RV64 as it contains no instructions") of + riscv-code-size-reduction. * :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is - supported as defined in the RISC-V ISA manual starting from commit - c732a4f39a4 ("Zcmop is ratified/1.0"). + supported as defined in the RISC-V ISA manual starting from commit + c732a4f39a4 ("Zcmop is ratified/1.0"). * :c:macro:`RISCV_HWPROBE_EXT_ZAWRS`: The Zawrs extension is supported as - ratified in commit 98918c844281 ("Merge pull request #1217 from - riscv/zawrs") of riscv-isa-manual. + ratified in commit 98918c844281 ("Merge pull request #1217 from + riscv/zawrs") of riscv-isa-manual. * :c:macro:`RISCV_HWPROBE_EXT_ZAAMO`: The Zaamo extension is supported as - defined in the in the RISC-V ISA manual starting from commit e87412e621f1 - ("integrate Zaamo and Zalrsc text (#1304)"). + defined in the in the RISC-V ISA manual starting from commit e87412e621f1 + ("integrate Zaamo and Zalrsc text (#1304)"). * :c:macro:`RISCV_HWPROBE_EXT_ZALASR`: The Zalasr extension is supported as - frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr. + frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr. * :c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as - defined in the in the RISC-V ISA manual starting from commit e87412e621f1 - ("integrate Zaamo and Zalrsc text (#1304)"). + defined in the in the RISC-V ISA manual starting from commit e87412e621f1 + ("integrate Zaamo and Zalrsc text (#1304)"). * :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as - defined in version 1.0 of the RISC-V Pointer Masking extensions. + defined in version 1.0 of the RISC-V Pointer Masking extensions. * :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as - defined in the RISC-V ISA manual starting from commit 4dc23d6229de - ("Added Chapter title to BF16"). + defined in the RISC-V ISA manual starting from commit 4dc23d6229de + ("Added Chapter title to BF16"). * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as - defined in the RISC-V ISA manual starting from commit 4dc23d6229de - ("Added Chapter title to BF16"). + defined in the RISC-V ISA manual starting from commit 4dc23d6229de + ("Added Chapter title to BF16"). * :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as - defined in the RISC-V ISA manual starting from commit 4dc23d6229de - ("Added Chapter title to BF16"). + defined in the RISC-V ISA manual starting from commit 4dc23d6229de + ("Added Chapter title to BF16"). * :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as - ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. * :c:macro:`RISCV_HWPROBE_EXT_ZABHA`: The Zabha extension is supported as - ratified in commit 49f49c842ff9 ("Update to Rafified state") of - riscv-zabha. + ratified in commit 49f49c842ff9 ("Update to Rafified state") of + riscv-zabha. * :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as - ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. * :c:macro:`RISCV_HWPROBE_EXT_ZILSD`: The Zilsd extension is supported as - defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating - load/store pair for RV32 with the main manual") of the riscv-isa-manual. + defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating + load/store pair for RV32 with the main manual") of the riscv-isa-manual. * :c:macro:`RISCV_HWPROBE_EXT_ZCLSD`: The Zclsd extension is supported as - defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating - load/store pair for RV32 with the main manual") of the riscv-isa-manual. + defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating + load/store pair for RV32 with the main manual") of the riscv-isa-manual. + + * :c:macro:`RISCV_HWPROBE_EXT_ZICFILP`: The Zicfilp extension is supported, + as defined in version 1.0 of the RISC-V Control-flow Integrity (CFI) + extensions specification, ratified in commit 302a2d45c243 + ("Update build-pdf.yml") of riscv-cfi. * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to - :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was - mistakenly classified as a bitmask rather than a value. + :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was + mistakenly classified as a bitmask rather than a value. * :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing the performance of misaligned scalar native word accesses on the selected set @@ -326,7 +331,7 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`. * :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value describing the - performance of misaligned vector accesses on the selected set of processors. + performance of misaligned vector accesses on the selected set of processors. * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned vector accesses is unknown. @@ -348,7 +353,7 @@ The following keys are defined: * MIPS * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl vendor - extension is supported in the MIPS ISA extensions spec. + extension is supported in the MIPS ISA extensions spec. * :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the thead vendor extensions that are compatible with the @@ -357,8 +362,8 @@ The following keys are defined: * T-HEAD * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor - extension is supported in the T-Head ISA extensions spec starting from - commit a18c801634 ("Add T-Head VECTOR vendor extension. "). + extension is supported in the T-Head ISA extensions spec starting from + commit a18c801634 ("Add T-Head VECTOR vendor extension. "). * :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which represents the size of the Zicbom block in bytes. @@ -370,20 +375,20 @@ The following keys are defined: * SIFIVE * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor - extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication - Extensions Specification. + extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication + Extensions Specification. * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor - extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication - Instruction Extensions Specification. + extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication + Instruction Extensions Specification. * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf - vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged - Clip Instructions Extensions Specification. + vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged + Clip Instructions Extensions Specification. * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq - vendor extension is supported in version 1.0 of Matrix Multiply Accumulate - Instruction Extensions Specification. + vendor extension is supported in version 1.0 of Matrix Multiply Accumulate + Instruction Extensions Specification. * :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which represents the size of the Zicbop block in bytes. @@ -391,3 +396,8 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. + + * :c:macro:`RISCV_HWPROBE_EXT_ZICFISS`: The Zicfiss extension is supported, + as defined in version 1.0 of the RISC-V Control-flow Integrity (CFI) + extensions specification, ratified in commit 302a2d45c243 + ("Update build-pdf.yml") of riscv-cfi. diff --git a/Documentation/arch/s390/s390dbf.rst b/Documentation/arch/s390/s390dbf.rst index aad6d88974fe58..034374c88dbaf4 100644 --- a/Documentation/arch/s390/s390dbf.rst +++ b/Documentation/arch/s390/s390dbf.rst @@ -106,6 +106,36 @@ the ``debug_stoppable`` sysctl. If you set ``debug_stoppable`` to 0 the debug feature cannot be stopped. If the debug feature is already stopped, it will stay deactivated. +Kernel parameters +----------------- +The size and log levels of debug logs can be configured early during boot using +the ``s390dbf`` kernel parameter. The parameter accepts a debug log name, a log +level, and a log size, separated by colon characters (``:``). To configure only +a single attribute, either the log level or the log size may be omitted. + +To configure multiple debug logs, the parameter may be specified multiple times, +or multiple parameter sets may be provided in a single instance, separated by +commas. + +Parameter format:: + + s390dbf=:[|-]:[][,...] + +where: + +- ``name`` specifies either an exact debug log name or a shell-style wildcard + pattern +- ``level`` specifies the log level, or ``-`` to completely deactivate the log +- ``pages`` specifies the debug area size in pages + +Example:: + + s390dbf=cio*:6:128,sclp_err::2 + +This example sets the log level to 6 and the log size to 128 pages for all debug +logs whose names start with ``cio``. It also sets the log level of the +``sclp_err`` debug log to 2. + Kernel Interfaces: ------------------ diff --git a/Documentation/arch/sparc/oradax/dax-hv-api.txt b/Documentation/arch/sparc/oradax/dax-hv-api.txt index ef1a4c2bf08bfe..49be62a9ce86e1 100644 --- a/Documentation/arch/sparc/oradax/dax-hv-api.txt +++ b/Documentation/arch/sparc/oradax/dax-hv-api.txt @@ -457,7 +457,7 @@ bits set, and terminate at a CCB that has the Conditional bit set, but not the P Offset Size Field Description Bits Field Description [15:14] Secondary Input Element Size (see Section 36.2.1.1.4, - “Secondary Input Element Size” + “Secondary Input Element Size”) [13:10] Output Format (see Section 36.2.1.1.6, “Output Format”) [9] Padding Direction selector: A value of 1 causes padding bytes to be added to the left side of output elements. A value of 0 @@ -656,7 +656,7 @@ Offset Size Field Description [18:16] Secondary Input Starting Offset (see Section 36.2.1.1.5, “Input Element Offsets”) [15:14] Secondary Input Element Size (see Section 36.2.1.1.4, - “Secondary Input Element Size” + “Secondary Input Element Size”) [13:10] Output Format (see Section 36.2.1.1.6, “Output Format”) [9:5] Operand size for first scan criteria value. In a scan value operation, this is one of two potential exact match values. @@ -793,13 +793,13 @@ Offset Size Field Description [18:16] Secondary Input Starting Offset (see Section 36.2.1.1.5, “Input Element Offsets”) [15:14] Secondary Input Element Size (see Section 36.2.1.1.4, - “Secondary Input Element Size” + “Secondary Input Element Size”) [13:10] Output Format (see Section 36.2.1.1.6, “Output Format”) [9] Reserved [8:0] Test value used for comparison against the most significant bits in the input values, when using 2 or 3 byte input elements. -8 8 Completion (same fields as Section 36.2.1.2, “Extract command” -16 8 Primary Input (same fields as Section 36.2.1.2, “Extract command” +8 8 Completion (same fields as Section 36.2.1.2, “Extract command”) +16 8 Primary Input (same fields as Section 36.2.1.2, “Extract command”) 24 8 Data Access Control (same fields as Section 36.2.1.2, “Extract command”, except Primary Input Length Format may not use the 0x0 value) 32 8 Secondary Input, if used by Primary Input Format. Same fields as Primary @@ -880,7 +880,7 @@ Offset Size Field Description [18:16] Secondary Input Starting Offset (see Section 36.2.1.1.5, “Input Element Offsets”) [15:14] Secondary Input Element Size (see Section 36.2.1.1.4, - “Secondary Input Element Size” + “Secondary Input Element Size”) 524 @@ -895,8 +895,8 @@ Offset Size Field Description causes padding bytes to be added to the right side of output elements. [8:0] Reserved - 8 8 Completion (same fields as Section 36.2.1.2, “Extract command” - 16 8 Primary Input (same fields as Section 36.2.1.2, “Extract command” + 8 8 Completion (same fields as Section 36.2.1.2, “Extract command”) + 16 8 Primary Input (same fields as Section 36.2.1.2, “Extract command”) 24 8 Data Access Control (same fields as Section 36.2.1.2, “Extract command”) 32 8 Secondary Bit Vector Input. Same fields as Primary Input. 40 8 Reserved @@ -949,7 +949,7 @@ Offset Size Field Description [31] If set, this CCB functions as a Sync command. If clear, this CCB functions as a No-op command. [30:0] Reserved - 8 8 Completion (same fields as Section 36.2.1.2, “Extract command” + 8 8 Completion (same fields as Section 36.2.1.2, “Extract command”) 16 46 Reserved 36.2.2. CCB Completion Area diff --git a/Documentation/arch/sparc/oradax/oracle-dax.rst b/Documentation/arch/sparc/oradax/oracle-dax.rst index d1e14d572918ca..a5d53f240dc882 100644 --- a/Documentation/arch/sparc/oradax/oracle-dax.rst +++ b/Documentation/arch/sparc/oradax/oracle-dax.rst @@ -438,7 +438,7 @@ that in user land:: The output bitmap is ready for consumption immediately after the completion status indicates success. -Excer[t from UltraSPARC Virtual Machine Specification +Excerpt from UltraSPARC Virtual Machine Specification ===================================================== .. include:: dax-hv-api.txt diff --git a/Documentation/arch/x86/tdx.rst b/Documentation/arch/x86/tdx.rst index ff6b110291bc67..3303499ad4c6f8 100644 --- a/Documentation/arch/x86/tdx.rst +++ b/Documentation/arch/x86/tdx.rst @@ -73,6 +73,133 @@ initialize:: [..] virt/tdx: TDX-Module initialization failed ... +TDX module Runtime Update +------------------------- + +Similar to microcode, the BIOS generally has a copy of the TDX module +in flash. It loads this module image in to RAM at boot. However, just +like microcode, the BIOS-loaded TDX module might be out of date either +because the BIOS is old or the system has been up a long time. The +kernel can replace the BIOS version in RAM and load a different TDX +module. Kernel-loaded TDX modules do not affect the BIOS flash and do +not survive reboots. + +The TDX module is normally the only piece of software running in SEAM +mode with which the kernel interacts. But there is a second piece of +software which is used to load or update the TDX module: a persistent +SEAM loader (P-SEAMLDR). It runs in SEAM mode separately from the TDX +module. The kernel communicates with the P-SEAMLDR to perform TDX +module runtime updates. + +How to update the TDX module +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Updating the TDX module is a complex process. Much of the logic and +policy is left to userspace. End users should use existing update +infrastructure provided by their distro. The Intel TDX Module Binaries +repository has a reference implementation of this logic: + + https://github.com/intel/confidential-computing.tdx.tdx-module.binaries/blob/main/version_select_and_load.py + +This section will now lay out roughly what is needed to implement a +userspace-driven TDX module update. Detailed documentation on the +tdx_host ABIs is available here:: + + Documentation/ABI/testing/sysfs-devices-faux-tdx-host + +and is not duplicated in this document. + +1. Check whether runtime update is supported at all + + Verify that the TDX module firmware upload interface is available:: + + /sys/class/firmware/tdx_module + + Note that this is the generic kernel firmware update ABI. It is + separate from the "tdx_host" device ABI itself. + +2. Check whether additional updates are possible. Verify that:: + + /sys/devices/faux/tdx_host/num_remaining_updates + + has a value greater than 0. If it is 0, the TDX update log might be + full. Reboot to reset this to a nonzero value. + +3. Choose a compatible TDX module image + + Choosing a compatible TDX module image is not trivial. There are both + hard compatibility requirements and policy choices to make. + + Hard compatibility requirements: + + - The update must be compatible with the kernel. + + The update must not change any TDX ABIs in any non-backward-compatible + way. It can introduce new features but must not require that the kernel + use new ABIs for existing features. It must ensure that the rest of the + system is not affected in any way. Software on the system must never + notice any behavioral changes. Attestation results should be identical + except for version changes. + + - The update must be compatible with the CPU. + + The set of supported CPU FMS values (family, model, stepping) is + encoded in the module image itself. In practice, module version series + are platform-specific. For example, the 1.5.x series runs on Sapphire + Rapids but not Granite Rapids, which needs 2.0.x. + + - The update must be compatible with the P-SEAMLDR. + + This information is provided in a metadata file, typically + mapping_file.json, released with the module image. Each module image + specifies the minimum required P-SEAMLDR version, and the update is + compatible only if the running P-SEAMLDR meets that requirement. + + The current version of the P-SEAMLDR can be read here:: + + /sys/devices/faux/tdx_host/seamldr_version + + - The update must be compatible with the running TDX module. + + Like P-SEAMLDR, each module image also specifies a minimum required + TDX module version. The running module must satisfy that requirement. + + The update software can read the current TDX module version here:: + + /sys/devices/faux/tdx_host/version + + Policy choices: + + - The update software chooses how to optimize its update. For instance, + it can optimize for fewer updates or for smaller version steps, + for example, 1.2.3 => 1.2.5 versus 1.2.3 => 1.2.4 => 1.2.5. + +4. Perform the update + + Run:: + + echo 1 > /sys/class/firmware/tdx_module/loading + cat > /sys/class/firmware/tdx_module/data + echo 0 > /sys/class/firmware/tdx_module/loading + + The files /sys/class/firmware/tdx_module/status and + /sys/class/firmware/tdx_module/error report update progress and error + information. + + After the update completes, the new module version is visible in + /sys/devices/faux/tdx_host/version. + +Impact on running TDs +~~~~~~~~~~~~~~~~~~~~~ + +TDX module runtime updates must have virtually no visible impact on running +TDs. Any TD visible impact is a TDX module bug. + +The main exception is the TEE_TCB_SVN_2 field in TD quotes, which +reflects the TCB of the currently running TDX module and therefore +changes after an update. By contrast, TEE_TCB_SVN reflects the TCB at TD +launch time and is not affected. + TDX Interaction to Other Kernel Components ------------------------------------------ @@ -138,13 +265,6 @@ If the platform has such erratum, the kernel prints additional message in machine check handler to tell user the machine check may be caused by kernel bug on TDX private memory. -Kexec -~~~~~~~ - -Currently kexec doesn't work on the TDX platforms with the aforementioned -erratum. It fails when loading the kexec kernel image. Otherwise it -works normally. - Interaction vs S3 and deeper states ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/Documentation/arch/x86/x86_64/fsgs.rst b/Documentation/arch/x86/x86_64/fsgs.rst index 6bda4d16d3f747..f8d483a7fb06e8 100644 --- a/Documentation/arch/x86/x86_64/fsgs.rst +++ b/Documentation/arch/x86/x86_64/fsgs.rst @@ -182,8 +182,8 @@ address spaces via an attribute based mechanism in Clang 2.6 and newer versions: ==================================== ===================================== - __attribute__((address_space(256)) Variable is addressed relative to GS - __attribute__((address_space(257)) Variable is addressed relative to FS + __attribute__(address_space(256)) Variable is addressed relative to GS + __attribute__(address_space(257)) Variable is addressed relative to FS ==================================== ===================================== FS/GS based addressing with inline assembly diff --git a/Documentation/block/data-integrity.rst b/Documentation/block/data-integrity.rst index 99905e880a0e56..b7b10c8abbcc26 100644 --- a/Documentation/block/data-integrity.rst +++ b/Documentation/block/data-integrity.rst @@ -154,7 +154,7 @@ bio_free() will automatically free the bip. ---------------- Block devices can set up the integrity information in the integrity -sub-struture of the queue_limits structure. +sub-structure of the queue_limits structure. Layered block devices will need to pick a profile that's appropriate for all subdevices. queue_limits_stack_integrity() can help with that. DM diff --git a/Documentation/block/error-injection.rst b/Documentation/block/error-injection.rst new file mode 100644 index 00000000000000..81f31af82e65db --- /dev/null +++ b/Documentation/block/error-injection.rst @@ -0,0 +1,59 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================ +Configurable Error Injection +============================ + +Overview +-------- + +Configurable error injection allows injecting specific block layer status codes +for sector ranges of a block device. Errors can be injected unconditionally, or +with a given probability. + +To use configurable error injection, CONFIG_BLK_ERROR_INJECTION must be enabled. + +The only interface is the error_injection debugfs file, which is created for +each registered gendisk. Writes to this file are used to create or delete rules +and reads return a list of the current error injection sites. + +Options +------- + +The following options specify the operations: + +=================== ======================================================= +add add a new rule +removeall remove all existing rules +=================== ======================================================= + +The following options specify the details of the rule for the add operation: + +=================== ======================================================= +op= block layer operation this rule applies to. This uses + the XYZ for each REQ_OP_XYZ operation, e.g. READ, WRITE + or DISCARD. Mandatory. +status= Status to return. This uses XYZ for each BLK_STS_XYZ + code, e.g. IOERR or MEDIUM. Mandatory. +start= First block layer sector the rule applies to. + Optional, defaults to 0. +nr_sectors= Number of sectors this rule applies. + Optional, defaults to the remainder of the device. +chance= Only return a failure with a likelihood of 1/chance. + Optional, defaults to 1 (always). +=================== ======================================================= + +Example +------- + +Return BLK_STS_IOERR for one in 10 reads of sector 0 of /dev/nvme0n1: + + $ echo 'add,op=READ,start=0,status=IOERR,chance=10' > /sys/kernel/debug/block/nvme0n1/error_injection + +Return BLK_STS_MEDIUM for every write to /dev/nvme0n1: + + $ echo 'add,op=WRITE,start=0,status=MEDIUM' > /sys/kernel/debug/block/nvme0n1/error_injection + +Remove all rules for /dev/nvme0n1: + + $ echo 'removeall' > /sys/kernel/debug/block/nvme0n1/error_injection diff --git a/Documentation/block/index.rst b/Documentation/block/index.rst index 9fea696f9daa01..bfa1bbd31ddf31 100644 --- a/Documentation/block/index.rst +++ b/Documentation/block/index.rst @@ -22,3 +22,4 @@ Block switching-sched writeback_cache_control ublk + error-injection diff --git a/Documentation/bpf/btf.rst b/Documentation/bpf/btf.rst index 3b60583f5db239..3f05f17990ade7 100644 --- a/Documentation/bpf/btf.rst +++ b/Documentation/bpf/btf.rst @@ -97,10 +97,8 @@ Each type contains the following common data:: struct btf_type { __u32 name_off; /* "info" bits arrangement - * bits 0-15: vlen (e.g. # of struct's members) - * bits 16-23: unused - * bits 24-28: kind (e.g. int, ptr, array...etc) - * bits 29-30: unused + * bits 0-23: vlen (e.g. # of struct's members) + * bits 24-30: kind (e.g. int, ptr, array...etc) * bit 31: kind_flag, currently used by * struct, union, enum, fwd, enum64, * decl_tag and type_tag diff --git a/Documentation/bpf/kfuncs.rst b/Documentation/bpf/kfuncs.rst index 75e6c078e0e722..4c814ff6061e04 100644 --- a/Documentation/bpf/kfuncs.rst +++ b/Documentation/bpf/kfuncs.rst @@ -207,8 +207,26 @@ Here, the buffer may be NULL. If the buffer is not NULL, it must be at least buffer__szk bytes in size. The kfunc is responsible for checking if the buffer is NULL before using it. -2.3.5 __str Annotation ----------------------------- +2.3.5 __nonown_allowed Annotation +--------------------------------- + +This annotation is used to indicate that the parameter may be a non-owning reference. + +An example is given below:: + + __bpf_kfunc int bpf_list_add(..., struct bpf_list_node + *prev__nonown_allowed, ...) + { + ... + } + +For the ``prev__nonown_allowed`` parameter (resolved as ``KF_ARG_PTR_TO_LIST_NODE``), +suffix ``__nonown_allowed`` retains the usual owning-pointer rules and also +permits a non-owning reference with no ref_obj_id (e.g. the return value of +bpf_list_front() / bpf_list_back()). + +2.3.6 __str Annotation +---------------------- This annotation is used to indicate that the argument is a constant string. An example is given below:: @@ -462,6 +480,20 @@ In order to accommodate such requirements, the verifier will enforce strict PTR_TO_BTF_ID type matching if two types have the exact same name, with one being suffixed with ``___init``. +2.8 Accessing arena memory through kfunc arguments +-------------------------------------------------- + +A read or write at any address inside an arena does not oops the kernel. +Unallocated arena pages are lazily backed by a scratch page and the +access is reported through the program's BPF stream as an error. Only +the BPF program's correctness is affected; the kernel itself remains +intact. + +The arena is followed by a ``GUARD_SZ / 2`` (32 KiB) guard region that +is also covered by this recovery. A kfunc handed an arena pointer may +therefore access up to ``GUARD_SZ / 2`` past it without bounds-checking +against the arena. Larger accesses must verify the range explicitly. + .. _BPF_kfunc_lifecycle_expectations: 3. kfunc lifecycle expectations diff --git a/Documentation/bpf/map_lru_hash_update.dot b/Documentation/bpf/map_lru_hash_update.dot index ab10058f5b79f5..412bc8b3b57e9f 100644 --- a/Documentation/bpf/map_lru_hash_update.dot +++ b/Documentation/bpf/map_lru_hash_update.dot @@ -21,10 +21,18 @@ digraph { // names that initiate the corresponding logic in kernel/bpf/bpf_lru_list.c. // Number suffixes and errno suffixes handle subsections of the corresponding // logic in the function as of the writing of this dot. + // + // All LRU locks are rqspinlock_t. Every acquire can fail (AA self-deadlock + // or contention timeout); on failure the corresponding helper returns NULL + // and the caller propagates -ENOMEM. The "rqspinlock acquire failed" + // terminal below is reached via the dashed arrows from each acquire site. + + rqspinlock_failed [shape=rectangle, + label="Any LRU rqspinlock\nacquire fails\n(AA or timeout)"] // cf. __local_list_pop_free() / bpf_percpu_lru_pop_free() local_freelist_check [shape=diamond,fillcolor=1, - label="Local freelist\nnode available?"]; + label="Local freelist\nnode available?\n(lockless free_llist)"]; use_local_node [shape=rectangle, label="Use node owned\nby this CPU"] @@ -82,6 +90,15 @@ digraph { // fn__local_list_pop_pending() } + // Post-steal: re-acquire local loc_l->lock to insert the stolen node into + // the local pending list. If the acquire fails, the stolen node is published + // to the lockless local free_llist so the next pop on this CPU picks it up + // instead of orphaning it. + post_steal_lock [shape=diamond,fillcolor=1, + label="Acquire local\nloc_l->lock\nto add pending"] + post_steal_to_free_llist [shape=rectangle, + label="Publish stolen node to\nlocal free_llist (lockless)"] + fn_bpf_lru_list_pop_free_to_local2 [shape=rectangle, label="Use node that was\nnot recently referenced"] local_freelist_check4 [shape=rectangle, @@ -97,10 +114,19 @@ digraph { fn_htab_lru_map_update_elem_ENOENT [shape=oval,label="return -ENOENT"] begin -> local_freelist_check + // The initial per-CPU lock (loc_l->lock for common, l->lock for percpu) is + // acquired before the local freelist check; rqspinlock failure here exits + // directly to -ENOMEM (no recovery needed: nothing was removed yet). + local_freelist_check -> rqspinlock_failed [style=dashed, + xlabel="acquire fails"] local_freelist_check -> use_local_node [xlabel="Y"] local_freelist_check -> common_lru_check [xlabel="N"] common_lru_check -> fn_bpf_lru_list_pop_free_to_local [xlabel="Y"] common_lru_check -> fn___bpf_lru_list_shrink_inactive [xlabel="N"] + // Global lru_list lock acquire failure in pop_free_to_local: skip refill, + // fall through to the steal path. Not ENOMEM by itself. + fn_bpf_lru_list_pop_free_to_local -> common_lru_check2 [style=dashed, + xlabel="global lru_lock\nacquire fails"] fn_bpf_lru_list_pop_free_to_local -> fn___bpf_lru_node_move_to_free fn___bpf_lru_node_move_to_free -> fn_bpf_lru_list_pop_free_to_local2 [xlabel="Y"] @@ -120,13 +146,27 @@ digraph { local_freelist_check6 -> local_freelist_check7 local_freelist_check7 -> fn_htab_lru_map_update_elem - fn_htab_lru_map_update_elem -> fn_htab_lru_map_update_elem3 [xlabel = "Y"] + // Steal-loop victim lock failure is silent: treat as "no node found here" + // and continue to next CPU; same edge as the existing "N" path. + local_freelist_check5 -> fn_htab_lru_map_update_elem2 [style=dashed, + xlabel="victim's lock\nfails: skip"] + // After a successful steal, re-acquire the local loc_l->lock. On failure + // the stolen node is published to free_llist (recovered, not orphaned) + // and the update returns -ENOMEM. + fn_htab_lru_map_update_elem -> post_steal_lock [xlabel = "Y"] + post_steal_lock -> fn_htab_lru_map_update_elem3 [xlabel = "OK"] + post_steal_lock -> post_steal_to_free_llist [style=dashed, + xlabel="loc_l->lock\nacquire fails"] + post_steal_to_free_llist -> fn_htab_lru_map_update_elem_ENOMEM fn_htab_lru_map_update_elem -> fn_htab_lru_map_update_elem2 [xlabel = "N"] fn_htab_lru_map_update_elem2 -> fn_htab_lru_map_update_elem_ENOMEM [xlabel = "Y"] fn_htab_lru_map_update_elem2 -> local_freelist_check5 [xlabel = "N"] fn_htab_lru_map_update_elem3 -> fn_htab_lru_map_update_elem4 + // Shared rqspinlock-failure terminal collapses to the same -ENOMEM exit. + rqspinlock_failed -> fn_htab_lru_map_update_elem_ENOMEM + use_local_node -> fn_htab_lru_map_update_elem4 fn_bpf_lru_list_pop_free_to_local2 -> fn_htab_lru_map_update_elem4 local_freelist_check4 -> fn_htab_lru_map_update_elem4 diff --git a/Documentation/core-api/cpu_hotplug.rst b/Documentation/core-api/cpu_hotplug.rst index 9b4afca9fd09c0..6de26d1c6a9ad5 100644 --- a/Documentation/core-api/cpu_hotplug.rst +++ b/Documentation/core-api/cpu_hotplug.rst @@ -45,11 +45,6 @@ Command Line Switches This option is limited to the X86 and S390 architecture. -``cpu0_hotplug`` - Allow to shutdown CPU0. - - This option is limited to the X86 architecture. - CPU maps ======== diff --git a/Documentation/core-api/housekeeping.rst b/Documentation/core-api/housekeeping.rst index 92c6e53cea7551..ccb0a88b9cb365 100644 --- a/Documentation/core-api/housekeeping.rst +++ b/Documentation/core-api/housekeeping.rst @@ -99,7 +99,7 @@ the same RCU read side critical section. A typical layout example would look like this on the update side (``housekeeping_update()``):: - rcu_assign_pointer(housekeeping_cpumasks[type], trial); + rcu_assign_pointer(housekeeping.cpumasks[type], trial); synchronize_rcu(); flush_workqueue(example_workqueue); diff --git a/Documentation/core-api/kernel-api.rst b/Documentation/core-api/kernel-api.rst index e8211c4ca66261..4c4a57c1c0940f 100644 --- a/Documentation/core-api/kernel-api.rst +++ b/Documentation/core-api/kernel-api.rst @@ -307,6 +307,7 @@ Accounting Framework Block Devices ============= +.. kernel-doc:: include/linux/bvec.h .. kernel-doc:: include/linux/bio.h .. kernel-doc:: block/blk-core.c :export: diff --git a/Documentation/core-api/kho/abi.rst b/Documentation/core-api/kho/abi.rst index 799d743105a672..edeb5b3119638c 100644 --- a/Documentation/core-api/kho/abi.rst +++ b/Documentation/core-api/kho/abi.rst @@ -28,6 +28,11 @@ KHO persistent memory tracker ABI .. kernel-doc:: include/linux/kho/abi/kexec_handover.h :doc: KHO persistent memory tracker +KHO serialization block ABI +=========================== + +.. kernel-doc:: include/linux/kho/abi/block.h + See Also ======== diff --git a/Documentation/core-api/kho/index.rst b/Documentation/core-api/kho/index.rst index 0a2dee4f8e7d09..320914a42178e3 100644 --- a/Documentation/core-api/kho/index.rst +++ b/Documentation/core-api/kho/index.rst @@ -83,6 +83,17 @@ Public API .. kernel-doc:: kernel/liveupdate/kexec_handover.c :export: +KHO Serialization Blocks API +============================ + +.. kernel-doc:: kernel/liveupdate/kho_block.c + :doc: KHO Serialization Blocks + +.. kernel-doc:: include/linux/kho_block.h + +.. kernel-doc:: kernel/liveupdate/kho_block.c + :internal: + See Also ======== diff --git a/Documentation/core-api/kref.rst b/Documentation/core-api/kref.rst index 8db9ff03d952e6..233d52d2393db5 100644 --- a/Documentation/core-api/kref.rst +++ b/Documentation/core-api/kref.rst @@ -40,7 +40,7 @@ kref_init as so:: struct my_data *data; - data = kmalloc(sizeof(*data), GFP_KERNEL); + data = kmalloc_obj(*data); if (!data) return -ENOMEM; kref_init(&data->refcount); @@ -100,7 +100,7 @@ thread to process:: int rv = 0; struct my_data *data; struct task_struct *task; - data = kmalloc(sizeof(*data), GFP_KERNEL); + data = kmalloc_obj(*data); if (!data) return -ENOMEM; kref_init(&data->refcount); diff --git a/Documentation/core-api/list.rst b/Documentation/core-api/list.rst index 241464ca054981..479aa91cc39586 100644 --- a/Documentation/core-api/list.rst +++ b/Documentation/core-api/list.rst @@ -112,7 +112,7 @@ list: /* State 1 */ - grock = kzalloc(sizeof(*grock), GFP_KERNEL); + grock = kzalloc_obj(*grock); if (!grock) return -ENOMEM; grock->name = "Grock"; @@ -123,7 +123,7 @@ list: /* State 2 */ - dimitri = kzalloc(sizeof(*dimitri), GFP_KERNEL); + dimitri = kzalloc_obj(*dimitri); if (!dimitri) return -ENOMEM; dimitri->name = "Dimitri"; @@ -752,7 +752,7 @@ This is because list_splice() did not reinitialize the list_head it took entries from, leaving its pointer pointing into what is now a different list. If we want to avoid this situation, list_splice_init() can be used. It does the -same thing as list_splice(), except reinitalizes the donor list_head after the +same thing as list_splice(), except reinitializes the donor list_head after the transplant. Concurrency considerations diff --git a/Documentation/core-api/printk-formats.rst b/Documentation/core-api/printk-formats.rst index c0b1b6089307a3..57e887ff24bc8c 100644 --- a/Documentation/core-api/printk-formats.rst +++ b/Documentation/core-api/printk-formats.rst @@ -322,6 +322,7 @@ MAC/FDDI addresses %pMF 00-01-02-03-04-05 %pm 000102030405 %pmR 050403020100 + %p[mM][FR][U] For printing 6-byte MAC/FDDI addresses in hex notation. The ``M`` and ``m`` specifiers result in a printed address with (M) or without (m) byte @@ -335,6 +336,8 @@ For Bluetooth addresses the ``R`` specifier shall be used after the ``M`` specifier to use reversed byte order suitable for visual interpretation of Bluetooth addresses which are in the little endian order. +When ``U`` is passed, the result is printed in the upper case. + Passed by reference. IPv4 addresses diff --git a/Documentation/core-api/real-time/theory.rst b/Documentation/core-api/real-time/theory.rst index 43d0120737f873..92de5654163dac 100644 --- a/Documentation/core-api/real-time/theory.rst +++ b/Documentation/core-api/real-time/theory.rst @@ -25,7 +25,7 @@ Scheduling ========== The core principles of Linux scheduling and the associated user-space API are -documented in the man page sched(7) +documented in the man page `sched(7) `_. By default, the Linux kernel uses the SCHED_OTHER scheduling policy. Under this policy, a task is preempted when the scheduler determines that it has diff --git a/Documentation/cpu-freq/cpu-drivers.rst b/Documentation/cpu-freq/cpu-drivers.rst index c5635ac3de5474..17c69f83691e2a 100644 --- a/Documentation/cpu-freq/cpu-drivers.rst +++ b/Documentation/cpu-freq/cpu-drivers.rst @@ -114,8 +114,13 @@ Then, the driver must fill in the following values: |policy->cur | The current operating frequency of | | | this CPU (if appropriate) | +-----------------------------------+--------------------------------------+ -|policy->min, | | -|policy->max, | | +|policy->min, | The min/max scaling frequency. | +|policy->max | If set by the driver in ->init(), | +| | used as the lower/upper bound for | +| | policy frequency QoS requests; | +| | otherwise, reflects the min/max | +| | frequency the driver can set | ++-----------------------------------+--------------------------------------+ |policy->policy and, if necessary, | | |policy->governor | must contain the "default policy" for| | | this CPU. A few moments later, | diff --git a/Documentation/crypto/api-samples.rst b/Documentation/crypto/api-samples.rst index e923f17bc2bd54..388bb7d7a460b8 100644 --- a/Documentation/crypto/api-samples.rst +++ b/Documentation/crypto/api-samples.rst @@ -159,7 +159,7 @@ Code Example For Random Number Generator Usage static int get_random_numbers(u8 *buf, unsigned int len) { struct crypto_rng *rng = NULL; - char *drbg = "drbg_nopr_sha256"; /* Hash DRBG with SHA-256, no PR */ + char *drbg = "stdrng"; int ret; if (!buf || !len) { diff --git a/Documentation/crypto/async-tx-api.rst b/Documentation/crypto/async-tx-api.rst index f88a7809385e25..49fcfc66314ac4 100644 --- a/Documentation/crypto/async-tx-api.rst +++ b/Documentation/crypto/async-tx-api.rst @@ -82,9 +82,9 @@ xor_val xor a series of source buffers and set a flag if the pq generate the p+q (raid6 syndrome) from a series of source buffers pq_val validate that a p and or q buffer are in sync with a given series of sources -datap (raid6_datap_recov) recover a raid6 data block and the p block +datap (raid6_recov_datap) recover a raid6 data block and the p block from the given sources -2data (raid6_2data_recov) recover 2 raid6 data blocks from the given +2data (raid6_recov_2data) recover 2 raid6 data blocks from the given sources ======== ==================================================================== diff --git a/Documentation/crypto/userspace-if.rst b/Documentation/crypto/userspace-if.rst index 021759198fe775..ab93300c8e0452 100644 --- a/Documentation/crypto/userspace-if.rst +++ b/Documentation/crypto/userspace-if.rst @@ -4,26 +4,88 @@ User Space Interface Introduction ------------ -The concepts of the kernel crypto API visible to kernel space is fully -applicable to the user space interface as well. Therefore, the kernel -crypto API high level discussion for the in-kernel use cases applies -here as well. - -The major difference, however, is that user space can only act as a -consumer and never as a provider of a transformation or cipher -algorithm. - -The following covers the user space interface exported by the kernel -crypto API. A working example of this description is libkcapi that can -be obtained from [1]. That library can be used by user space -applications that require cryptographic services from the kernel. - -Some details of the in-kernel kernel crypto API aspects do not apply to -user space, however. This includes the difference between synchronous -and asynchronous invocations. The user space API call is fully -synchronous. - -[1] https://www.chronox.de/libkcapi/index.html +AF_ALG provides unprivileged userspace programs access to arbitrary hash, +symmetric cipher, AEAD, and RNG algorithms that are implemented in kernel-mode +code. + +AF_ALG is insecure and is deprecated. Originally added to the kernel in 2010, +most kernel developers now consider it to be a mistake. Support for hardware +accelerators, which was the original purpose of AF_ALG, has been removed. + +AF_ALG continues to be supported only for backwards compatibility. On systems +where no programs using AF_ALG remain, the support for it should be disabled by +disabling ``CONFIG_CRYPTO_USER_API_*``. + +Deprecation +----------- + +AF_ALG was originally intended to provide userspace programs access to crypto +accelerators that they wouldn't otherwise have access to. + +However, that capability turned out to not be useful on very many systems. More +significantly, the actual implementation exposes a vastly greater amount of +functionality than that. It actually provides access to all software algorithms. + +This includes arbitrary compositions of different algorithms created via a +complex template system, as well as algorithms that only make sense as internal +implementation details of other algorithms. In the past, it also included full +zero-copy support, which was difficult for the kernel to implement securely. + +Ultimately, these algorithms are just math computations. They use the same +instructions that userspace programs already have access to, just accessed in a +much more convoluted and less efficient way. + +Indeed, userspace code is nearly always what is being used anyway. These same +algorithms are widely implemented in userspace crypto libraries. + +Even when zero-copy and off-CPU accelerators were supported, AF_ALG was usually +much slower than optimized software cryptography in userspace. This was +especially true for the small message sizes usually seen in performance-critical +workloads. While it was possible to demonstrate performance wins for hashing +large files on embedded devices, it is hard to imagine a situation where this +would be performance-critical. + +Nowadays, AF_ALG no longer supports zero-copy or off-CPU accelerators. +Therefore, it is *always* slower than an optimized userspace implementation, +even for large messages. The only possible advantage left is that it avoids +duplicating code between kernel and userspace. However, userspace +implementations, especially hardware-accelerated ones, do not need to be large. +Just because OpenSSL is huge does not mean that all userspace cryptography +libraries are. + +Meanwhile, AF_ALG hasn't been withstanding modern vulnerability discovery tools +such as syzbot and large language models. It receives a steady stream of CVEs. +Some of the examples include: + +- CVE-2026-31677 +- CVE-2026-31431 (https://copy.fail) +- CVE-2025-38079 +- CVE-2025-37808 +- CVE-2024-26824 +- CVE-2022-48781 +- CVE-2019-8912 +- CVE-2018-14619 +- CVE-2017-18075 +- CVE-2017-17806 +- CVE-2017-17805 +- CVE-2016-10147 +- CVE-2015-8970 +- CVE-2015-3331 +- CVE-2014-9644 +- CVE-2013-7421 +- CVE-2011-4081 + +Hardware accelerator drivers are frequently buggy. To reduce attack surface, +AF_ALG now only provides access to algorithms implemented in software. This +means that AF_ALG no longer fulfills its original purpose. + +It is recommended that, whenever possible, userspace programs be migrated to +userspace crypto code (which again, is what is normally used anyway) and +``CONFIG_CRYPTO_USER_API_*`` be disabled. On systems that use SELinux, SELinux +can also be used to restrict the use of AF_ALG to trusted programs. + +The remainder of this documentation provides the historical documentation for +the deprecated AF_ALG interface. User Space API General Remarks ------------------------------ @@ -297,7 +359,7 @@ follows: struct sockaddr_alg sa = { .salg_family = AF_ALG, .salg_type = "rng", /* this selects the random number generator */ - .salg_name = "drbg_nopr_sha256" /* this is the RNG name */ + .salg_name = "stdrng" /* this is the RNG name */ }; @@ -327,33 +389,10 @@ CRYPTO_USER_API_RNG_CAVP option: Zero-Copy Interface ------------------- -In addition to the send/write/read/recv system call family, the AF_ALG -interface can be accessed with the zero-copy interface of -splice/vmsplice. As the name indicates, the kernel tries to avoid a copy -operation into kernel space. - -The zero-copy operation requires data to be aligned at the page -boundary. Non-aligned data can be used as well, but may require more -operations of the kernel which would defeat the speed gains obtained -from the zero-copy interface. - -The system-inherent limit for the size of one zero-copy operation is 16 -pages. If more data is to be sent to AF_ALG, user space must slice the -input into segments with a maximum size of 16 pages. - -Zero-copy can be used with the following code example (a complete -working example is provided with libkcapi): - -:: - - int pipes[2]; - - pipe(pipes); - /* input data in iov */ - vmsplice(pipes[1], iov, iovlen, SPLICE_F_GIFT); - /* opfd is the file descriptor returned from accept() system call */ - splice(pipes[0], NULL, opfd, NULL, ret, 0); - read(opfd, out, outlen); +AF_ALG used to have zero-copy support, but it was removed due to it being a +frequent source of vulnerabilities. For backwards compatibility the splice() +and sendfile() system calls are still supported, but the kernel will make an +internal copy of the data before passing it to the crypto code. Setsockopt Interface diff --git a/Documentation/dev-tools/autofdo.rst b/Documentation/dev-tools/autofdo.rst index bcf06e7d6ffa75..ae03c4dfedc14b 100644 --- a/Documentation/dev-tools/autofdo.rst +++ b/Documentation/dev-tools/autofdo.rst @@ -61,6 +61,9 @@ process consists of the following steps: the AutoFDO profile via offline tools. The support requires a Clang compiler LLVM 17 or later. +Current supported architectures include x86/x86_64 (via LBR) and +arm64 (via SPE or ETM). + Preparation =========== @@ -141,6 +144,35 @@ Here is an example workflow for AutoFDO kernel: $ perf record --pfm-events RETIRED_TAKEN_BRANCH_INSTRUCTIONS:k -a -N -b -c -o -- + - For arm64 with SPE: + + There are a few kernel features that must be enabled to collect SPE profiles on Arm. + Below is a list of the required features: + + - CONFIG_ARM_SPE_PMU=y + - CONFIG_PID_IN_CONTEXTIDR=y + - kpti=off + + Use the following command to generate SPE perf data file:: + + $ perf record -e ' arm_spe_0/branch_filter=1,load_filter=0,store_filter=0/' -a -c -N --no-switch-events -o -- + + - For arm64 with ETM trace: + + Follow the instructions in `Linaro OpenCSD document + `_ + to record ETM traces for AutoFDO:: + + $ perf record -e cs_etm/@tmc_etr0/k -a -o -- + $ perf inject -i -o --itrace=i500009il + + For ARM platforms running Android, follow the instructions in `Android simpleperf + document `_ + to record ETM traces for AutoFDO:: + + $ simpleperf record -e cs-etm:k -a -o -- + $ simpleperf inject -i -o --symdir + 4) (Optional) Download the raw perf file to the host machine. 5) To generate an AutoFDO profile, two offline tools are available: @@ -162,6 +194,15 @@ Here is an example workflow for AutoFDO kernel: $ llvm-profdata merge -o ... + For arm64 SPE, use the following command:: + + $ create_llvm_prof --binary= --profile= --profiler=perf_spe --format=extbinary --out= + + For arm64 ETM, use the following command:: + + $ create_llvm_prof --binary= --profile= --profiler=text -format=extbinary -out= + + 6) Rebuild the kernel using the AutoFDO profile file with the same config as step 1, (Note CONFIG_AUTOFDO_CLANG needs to be enabled):: diff --git a/Documentation/dev-tools/checkpatch.rst b/Documentation/dev-tools/checkpatch.rst index dccede68698ca4..6139a08c34cd8d 100644 --- a/Documentation/dev-tools/checkpatch.rst +++ b/Documentation/dev-tools/checkpatch.rst @@ -184,6 +184,13 @@ Available options: Override checking of perl version. Runtime errors may be encountered after enabling this flag if the perl version does not meet the minimum specified. + - --spdx-cxx-comments + + Don't force C comments ``/* */`` for SPDX license (required by old + toolchains), allow also C++ comments ``//``. + + NOTE: it should *not* be used for Linux mainline. + - --codespell Use the codespell dictionary for checking spelling errors. @@ -210,6 +217,13 @@ Available options: Display the help text. +Configuration file +================== + +Default configuration options can be stored in ``.checkpatch.conf``, search +path: ``.:$HOME:.scripts`` or in a directory specified by ``$CHECKPATCH_CONFIG_DIR`` +environment variable (falling back to the default search path). + Message Levels ============== diff --git a/Documentation/dev-tools/context-analysis.rst b/Documentation/dev-tools/context-analysis.rst index 54d9ee28de9829..8e71e1e75b5bc3 100644 --- a/Documentation/dev-tools/context-analysis.rst +++ b/Documentation/dev-tools/context-analysis.rst @@ -17,7 +17,7 @@ features. To enable for Clang, configure the kernel with:: CONFIG_WARN_CONTEXT_ANALYSIS=y -The feature requires Clang 22 or later. +The feature requires Clang 23 or later. The analysis is *opt-in by default*, and requires declaring which modules and subsystems should be analyzed in the respective `Makefile`:: diff --git a/Documentation/dev-tools/kcov.rst b/Documentation/dev-tools/kcov.rst index 8127849d40f59e..1a739290c8ecc8 100644 --- a/Documentation/dev-tools/kcov.rst +++ b/Documentation/dev-tools/kcov.rst @@ -237,6 +237,9 @@ Both ``kcov_remote_start`` and ``kcov_remote_stop`` annotations and the collection sections. The way a handle is used depends on the context where the matching code section executes. +A thread can use two separate KCOV instances to collect remote coverage and +normal coverage at the same time. + KCOV supports collecting remote coverage from the following contexts: 1. Global kernel background tasks. These are the tasks that are spawned during @@ -262,6 +265,9 @@ gets saved to the ``kcov_handle`` field in the current ``task_struct`` and needs to be passed to the newly spawned local tasks via custom kernel code modifications. Those tasks should in turn use the passed handle in their ``kcov_remote_start`` and ``kcov_remote_stop`` annotations. +In the kernel, common handles are wrapped in a ``kcov_common_handle_id``, which +consumes no space in builds without ``CONFIG_KCOV``; subsystems that integrate +with this mechanism should not need to use any ``#ifdef CONFIG_KCOV`` or such. KCOV follows a predefined format for both global and common handles. Each handle is a ``u64`` integer. Currently, only the one top and the lower 4 bytes diff --git a/Documentation/dev-tools/kselftest.rst b/Documentation/dev-tools/kselftest.rst index 18c2da67fae424..64c0ec7428a273 100644 --- a/Documentation/dev-tools/kselftest.rst +++ b/Documentation/dev-tools/kselftest.rst @@ -15,11 +15,6 @@ able to run that test on an older kernel. Hence, it is important to keep code that can still test an older kernel and make sure it skips the test gracefully on newer releases. -You can find additional information on Kselftest framework, how to -write new tests using the framework on Kselftest wiki: - -https://kselftest.wiki.kernel.org/ - On some systems, hot-plug tests could hang forever waiting for cpu and memory to be ready to be offlined. A special hot-plug target is created to run the full range of hot-plug tests. In default mode, hot-plug tests run @@ -126,6 +121,18 @@ dedicated skiplist:: See the top-level tools/testing/selftests/Makefile for the list of all possible targets. +Requiring all targets to build successfully +=========================================== + +By default, the build succeeds as long as at least one target builds +without error. Set ``FORCE_TARGETS=1`` to instead require every target to +build successfully; make will abort as soon as any target fails:: + + $ make -C tools/testing/selftests FORCE_TARGETS=1 + +This applies to both the ``all`` and ``install`` targets and is useful in +CI environments where a silent partial build would be misleading. + Running the full range hotplug selftests ======================================== diff --git a/Documentation/dev-tools/kunit/run_wrapper.rst b/Documentation/dev-tools/kunit/run_wrapper.rst index 770bb09a475ae7..cecc110a3399f6 100644 --- a/Documentation/dev-tools/kunit/run_wrapper.rst +++ b/Documentation/dev-tools/kunit/run_wrapper.rst @@ -324,6 +324,9 @@ command line arguments: - ``--json``: If set, stores the test results in a JSON format and prints to `stdout` or saves to a file if a filename is specified. +- ``--junit``: If set, stores the test results in JUnit XML format and prints to `stdout` or + saves to a file if a filename is specified. + - ``--filter``: Specifies filters on test attributes, for example, ``speed!=slow``. Multiple filters can be used by wrapping input in quotes and separating filters by commas. Example: ``--filter "speed>slow, module=example"``. diff --git a/Documentation/dev-tools/kunit/usage.rst b/Documentation/dev-tools/kunit/usage.rst index ebd06f5ea4550a..1c78dfff94e8a8 100644 --- a/Documentation/dev-tools/kunit/usage.rst +++ b/Documentation/dev-tools/kunit/usage.rst @@ -157,6 +157,50 @@ Alternatively, one can take full control over the error message by using if (some_setup_function()) KUNIT_FAIL(test, "Failed to setup thing for testing"); +Suppressing warning backtraces +------------------------------ + +Some unit tests trigger warning backtraces either intentionally or as a side +effect. Such backtraces are normally undesirable since they distract from +the actual test and may result in the impression that there is a problem. + +Backtraces can be suppressed with **task-scoped suppression**: while +suppression is active on the current task, the backtrace and stack dump from +``WARN*()``, ``WARN_ON*()``, and related macros on that task are suppressed. +Two API forms are available. + +- Scoped suppression is the simplest form. Wrap the code that triggers + warnings in a ``kunit_warning_suppress()`` block: + +.. code-block:: c + + static void some_test(struct kunit *test) + { + kunit_warning_suppress(test) { + trigger_backtrace(); + KUNIT_EXPECT_SUPPRESSED_WARNING_COUNT(test, 1); + } + } + +.. note:: + The warning count must be checked inside the block; the suppression handle + is not accessible after the block exits. + +- Direct functions return an explicit handle pointer. Use them when the handle + needs to be retained or passed across helper functions: + +.. code-block:: c + + static void some_test(struct kunit *test) + { + struct kunit_suppressed_warning *w; + + w = kunit_start_suppress_warning(test); + trigger_backtrace(); + kunit_end_suppress_warning(test, w); + + KUNIT_EXPECT_EQ(test, kunit_suppressed_warning_count(w), 1); + } Test Suites ~~~~~~~~~~~ @@ -1211,4 +1255,4 @@ For example: dev_managed_string = devm_kstrdup(fake_device, "Hello, World!"); // Everything is cleaned up automatically when the test ends. - } \ No newline at end of file + } diff --git a/Documentation/dev-tools/propeller.rst b/Documentation/dev-tools/propeller.rst index 92195958e3dbca..e927319941c955 100644 --- a/Documentation/dev-tools/propeller.rst +++ b/Documentation/dev-tools/propeller.rst @@ -28,8 +28,10 @@ A few important notes about adopting Propeller optimization: and the linker(ld.lld). #. In addition to LLVM toolchain, Propeller requires a profiling - conversion tool: https://github.com/google/autofdo with a release - after v0.30.1: https://github.com/google/autofdo/releases/tag/v0.30.1. + conversion tool: https://github.com/google/llvm-propeller. + +Current supported architectures include x86/X86_64 (via LBR), +and arm64 (via SPE). The Propeller optimization process involves the following steps: @@ -124,17 +126,30 @@ Here is an example workflow for building an AutoFDO+Propeller kernel: $ perf record --pfm-event RETIRED_TAKEN_BRANCH_INSTRUCTIONS:k -a -N -b -c -o -- - Note you can repeat the above steps to collect multiple s. + - For arm64 with SPE:: + There are a few kernel features that must be enabled to collect SPE profiles on Arm. + Below is a list of the required features: + + - CONFIG_ARM_SPE_PMU=y + - CONFIG_PID_IN_CONTEXTIDR=y + - kpti=off + + Use the following command to generate SPE perf data file:: + + $ perf record -e 'arm_spe_0/branch_filter=1,load_filter=0,store_filter=0/' -a -N -c --no-switch-events -o -- + + Note you can repeat the above steps to collect multiple s. 4) (Optional) Download the raw perf file(s) to the host machine. -5) Use the create_llvm_prof tool (https://github.com/google/autofdo) to +5) Use the generate_propeller_profiles tool (https://github.com/google/llvm-propeller) to generate Propeller profile. :: - $ create_llvm_prof --binary= --profile= - --format=propeller --propeller_output_module_name - --out=_cc_profile.txt - --propeller_symorder=_ld_profile.txt + $ generate_propeller_profiles \ + --binary= --profile= \ + --format=propeller --propeller_output_module_name \ + --out=_cc_profile.txt \ + --propeller_symorder=_ld_profile.txt "" can be something like "/home/user/dir/any_string". @@ -146,10 +161,20 @@ Here is an example workflow for building an AutoFDO+Propeller kernel: you can create a temp list file "" with each line containing one perf file name and run:: - $ create_llvm_prof --binary= --profile=@ - --format=propeller --propeller_output_module_name - --out=_cc_profile.txt - --propeller_symorder=_ld_profile.txt + $ generate_propeller_profiles \ + --binary= --profile=@ \ + --format=propeller --propeller_output_module_name \ + --out=_cc_profile.txt \ + --propeller_symorder=_ld_profile.txt + + For arm64 SPE, add the option '--profiler=perf_spe', like:: + + $ generate_propeller_profiles \ + --binary= --profile= \ + --profiler=perf_spe \ + --format=propeller --propeller_output_module_name \ + --out=_cc_profile.txt \ + --propeller_symorder=_ld_profile.txt 6) Rebuild the kernel using the AutoFDO and Propeller profiles. :: diff --git a/Documentation/devicetree/bindings/Makefile b/Documentation/devicetree/bindings/Makefile index 7b668f7fd4007f..00149e8242611f 100644 --- a/Documentation/devicetree/bindings/Makefile +++ b/Documentation/devicetree/bindings/Makefile @@ -46,6 +46,18 @@ quiet_cmd_chk_bindings = CHKDT $(src) xargs -n200 -P$$(nproc) $(DT_DOC_CHECKER) -u $(src)) \ && touch $@ || true +DT_CHK_STYLE = $(srctree)/scripts/dtc/dt-check-style + +# Feed the file list to the checker via @argfile in a single Python +# process so the ruamel.yaml import is paid once. scripts/jobserver-exec +# claims slots from the GNU make jobserver and exposes the count via +# $PARALLELISM, which dt-check-style picks up to size its worker pool. +quiet_cmd_chk_style = STYLE $(src) + cmd_chk_style = f=$$(mktemp) && $(find_cmd) > $$f && \ + $(PYTHON3) $(srctree)/scripts/jobserver-exec \ + $(PYTHON3) $(DT_CHK_STYLE) @$$f \ + && touch $@ || true; rm -f $$f + quiet_cmd_mk_schema = SCHEMA $@ cmd_mk_schema = f=$$(mktemp) ; \ $(find_all_cmd) > $$f ; \ @@ -62,13 +74,16 @@ override DTC_FLAGS := \ $(obj)/processed-schema.json: $(DT_DOCS) check_dtschema_version FORCE $(call if_changed,mk_schema) -targets += .dt-binding.checked .yamllint.checked +targets += .dt-binding.checked .yamllint.checked .dt-style.checked $(obj)/.yamllint.checked: $(DT_DOCS) $(src)/.yamllint FORCE $(if $(DT_SCHEMA_LINT),$(call if_changed,yamllint),) $(obj)/.dt-binding.checked: $(DT_DOCS) FORCE $(call if_changed,chk_bindings) +$(obj)/.dt-style.checked: $(DT_DOCS) FORCE + $(call if_changed,chk_style) + always-y += processed-schema.json targets += $(patsubst $(obj)/%,%, $(CHK_DT_EXAMPLES)) targets += $(patsubst $(obj)/%.dtb,%.dts, $(CHK_DT_EXAMPLES)) @@ -82,7 +97,7 @@ dt_compatible_check: $(obj)/processed-schema.json $(Q)$(srctree)/scripts/dtc/dt-extract-compatibles $(srctree) | xargs dt-check-compatible -v -s $< PHONY += dt_binding_check_one -dt_binding_check_one: $(obj)/.dt-binding.checked $(obj)/.yamllint.checked +dt_binding_check_one: $(obj)/.dt-binding.checked $(obj)/.yamllint.checked $(obj)/.dt-style.checked PHONY += dt_binding_check dt_binding_check: dt_binding_check_one $(CHK_DT_EXAMPLES) diff --git a/Documentation/devicetree/bindings/arm/altera.yaml b/Documentation/devicetree/bindings/arm/altera.yaml index 206686f3eebceb..0b418d9d60dbd8 100644 --- a/Documentation/devicetree/bindings/arm/altera.yaml +++ b/Documentation/devicetree/bindings/arm/altera.yaml @@ -111,10 +111,17 @@ properties: - enum: - intel,socfpga-agilex5-socdk - intel,socfpga-agilex5-socdk-013b + - intel,socfpga-agilex5-socdk-debug - intel,socfpga-agilex5-socdk-modular - intel,socfpga-agilex5-socdk-nand - const: intel,socfpga-agilex5 + - description: Agilex7m boards + items: + - enum: + - altr,socfpga-agilex7m-socdk + - const: altr,socfpga-agilex7m + - description: SoCFPGA VT items: - const: altr,socfpga-vt diff --git a/Documentation/devicetree/bindings/arm/amlogic.yaml b/Documentation/devicetree/bindings/arm/amlogic.yaml index a885278bc4e2e4..9f73a0054fb21b 100644 --- a/Documentation/devicetree/bindings/arm/amlogic.yaml +++ b/Documentation/devicetree/bindings/arm/amlogic.yaml @@ -234,6 +234,12 @@ properties: - amlogic,av400 - const: amlogic,a5 + - description: Boards with the Amlogic A9 A311Y3 SoC + items: + - enum: + - amlogic,by401 + - const: amlogic,a9 + - description: Boards with the Amlogic C3 C302X/C308L SoC items: - enum: diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index 5c2629ec3d4cbc..e49403c73f9d2e 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -96,6 +96,13 @@ description: | - MacBook Pro (13-inch, M2, 2022) - Mac mini (M2, 2023) + Devices based on the "M3" SoC: + + - MacBook Air (13-inch, M3, 2024) + - MacBook Air (15-inch, M3, 2024) + - MacBook Pro (14-inch, M3, 2023) + - iMac (24-inch, M3, 2023) + Devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: - MacBook Pro (14-inch, M1 Pro, 2021) @@ -297,6 +304,17 @@ properties: - const: apple,t8112 - const: apple,arm-platform + - description: Apple M3 SoC based platforms + items: + - enum: + - apple,j433 # iMac (24-inch, 2x USB-C, M3, 2023) + - apple,j434 # iMac (24-inch, 4x USB-C, M3, 2023) + - apple,j504 # MacBook Pro (14-inch, M3, 2023) + - apple,j613 # MacBook Air (13-inch, M3, 2024) + - apple,j615 # MacBook Air (15-inch, M3, 2024) + - const: apple,t8122 + - const: apple,arm-platform + - description: Apple M1 Pro SoC based platforms items: - enum: diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml index b88f41a225a385..c67b67ba065afa 100644 --- a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -36,7 +36,9 @@ properties: - const: syscon - const: simple-mfd - items: - - const: apple,t6020-pmgr + - enum: + - apple,t6020-pmgr + - apple,t8122-pmgr - const: apple,t8103-pmgr - const: syscon - const: simple-mfd diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 8ec7a3e74a21d2..dd7996960de3e8 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -95,6 +95,8 @@ properties: - facebook,greatlakes-bmc - facebook,harma-bmc - facebook,minerva-cmc + - facebook,rainiera6-bmc + - facebook,sanmiguel-bmc - facebook,santabarbara-bmc - facebook,yosemite4-bmc - facebook,yosemite5-bmc @@ -117,4 +119,10 @@ properties: - ufispace,ncplite-bmc - const: aspeed,ast2600 + - description: AST2700 based boards + items: + - enum: + - aspeed,ast2700-evb + - const: aspeed,ast2700 + additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 5f5ff5e51e519e..5be89c5840262d 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -223,6 +223,7 @@ properties: - qcom,oryon-1-2 - qcom,oryon-1-3 - qcom,oryon-1-4 + - qcom,oryon-1-5 - qcom,oryon-2-1 - qcom,oryon-2-2 - qcom,oryon-2-3 diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index 0023cd12680758..86876311ec59a3 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -688,7 +688,7 @@ properties: - const: phytec,imx6ul-pcl063 # PHYTEC phyCORE-i.MX 6UL - const: fsl,imx6ul - - description: i.MX6UL Variscite VAR-SOM-MX6 Boards + - description: i.MX6UL Variscite VAR-SOM-6UL Boards items: - const: variscite,mx6ulconcerto - const: variscite,var-som-imx6ul @@ -797,6 +797,12 @@ properties: - const: phytec,imx6ull-pcl063 # PHYTEC phyCORE-i.MX 6ULL - const: fsl,imx6ull + - description: i.MX6ULL Variscite VAR-SOM-6UL Boards + items: + - const: variscite,mx6ullconcerto # Variscite VAR-SOM-6UL dev kit board + - const: variscite,var-som-imx6ull # Variscite VAR-SOM-6UL SoM (6ULL variant) + - const: fsl,imx6ull + - description: i.MX6ULL Boards with Toradex Colibri iMX6ULL Modules items: - enum: @@ -1025,6 +1031,7 @@ properties: - toradex,verdin-imx8mm-nonwifi-ivy # Verdin iMX8M Mini Module on Ivy - toradex,verdin-imx8mm-nonwifi-mallow # Verdin iMX8M Mini Module on Mallow - toradex,verdin-imx8mm-nonwifi-yavia # Verdin iMX8M Mini Module on Yavia + - toradex,verdin-imx8mm-nonwifi-zinnia # Verdin iMX8M Mini Module on Zinnia - const: toradex,verdin-imx8mm-nonwifi # Verdin iMX8M Mini Module without Wi-Fi / BT - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module - const: fsl,imx8mm @@ -1037,6 +1044,7 @@ properties: - toradex,verdin-imx8mm-wifi-ivy # Verdin iMX8M Mini Wi-Fi / BT Module on Ivy - toradex,verdin-imx8mm-wifi-mallow # Verdin iMX8M Mini Wi-Fi / BT Module on Mallow - toradex,verdin-imx8mm-wifi-yavia # Verdin iMX8M Mini Wi-Fi / BT Module on Yavia + - toradex,verdin-imx8mm-wifi-zinnia # Verdin iMX8M Mini Wi-Fi / BT Module on Zinnia - const: toradex,verdin-imx8mm-wifi # Verdin iMX8M Mini Wi-Fi / BT Module - const: toradex,verdin-imx8mm # Verdin iMX8M Mini Module - const: fsl,imx8mm @@ -1271,6 +1279,7 @@ properties: - toradex,verdin-imx8mp-nonwifi-ivy # Verdin iMX8M Plus Module on Ivy - toradex,verdin-imx8mp-nonwifi-mallow # Verdin iMX8M Plus Module on Mallow - toradex,verdin-imx8mp-nonwifi-yavia # Verdin iMX8M Plus Module on Yavia + - toradex,verdin-imx8mp-nonwifi-zinnia # Verdin iMX8M Plus Module on Zinnia - const: toradex,verdin-imx8mp-nonwifi # Verdin iMX8M Plus Module without Wi-Fi / BT - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module - const: fsl,imx8mp @@ -1283,6 +1292,7 @@ properties: - toradex,verdin-imx8mp-wifi-ivy # Verdin iMX8M Plus Wi-Fi / BT Module on Ivy - toradex,verdin-imx8mp-wifi-mallow # Verdin iMX8M Plus Wi-Fi / BT Module on Mallow - toradex,verdin-imx8mp-wifi-yavia # Verdin iMX8M Plus Wi-Fi / BT Module on Yavia + - toradex,verdin-imx8mp-wifi-zinnia # Verdin iMX8M Plus Wi-Fi / BT Module on Zinnia - const: toradex,verdin-imx8mp-wifi # Verdin iMX8M Plus Wi-Fi / BT Module - const: toradex,verdin-imx8mp # Verdin iMX8M Plus Module - const: fsl,imx8mp @@ -1394,6 +1404,13 @@ properties: - fsl,imx8dxl-evk # i.MX8DXL EVK Board - const: fsl,imx8dxl + - description: SolidRun i.MX8DXL SoM based boards + items: + - enum: + - solidrun,imx8dxl-hummingboard-telematics # SolidRun i.MX8DXL SoM EVK Board + - const: solidrun,imx8dxl-sr-som + - const: fsl,imx8dxl + - description: i.MX8QXP/i.MX8DX Boards with Toradex Colibri iMX8X Modules items: - enum: @@ -1458,6 +1475,7 @@ properties: - description: i.MX91 based Boards items: - enum: + - fsl,imx91-9x9-qsb # i.MX91 9x9 QSB Board - fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board - fsl,imx91-11x11-frdm # FRDM i.MX91 Development Board - fsl,imx91-11x11-frdm-s # FRDM i.MX91S Development Board @@ -1482,9 +1500,11 @@ properties: - description: i.MX95 based Boards items: - enum: + - fsl,imx95-15x15-ab2 # i.MX95 15x15 Audio Board V2 - fsl,imx95-15x15-evk # i.MX95 15x15 EVK Board - fsl,imx95-15x15-frdm # i.MX95 15x15 FRDM Board - fsl,imx95-19x19-evk # i.MX95 19x19 EVK Board + - fsl,imx95-19x19-frdm-pro # i.MX95 19x19 FRDM PRO Board - toradex,verdin-imx95-19x19-evk # i.MX95 Verdin Evaluation Kit (EVK) - const: fsl,imx95 @@ -1501,6 +1521,14 @@ properties: - const: phytec,imx95-phycore-fpsc # phyCORE-i.MX 95 FPSC - const: fsl,imx95 + - description: Toradex Boards with Aquila iMX95 Modules + items: + - enum: + - toradex,aquila-imx95-clover # Aquila iMX95 Module on Clover Board + - toradex,aquila-imx95-dev # Aquila iMX95 Module on Aquila Development Board + - const: toradex,aquila-imx95 # Aquila iMX95 Module + - const: fsl,imx95 + - description: Toradex Boards with SMARC iMX95 Modules items: - const: toradex,smarc-imx95-dev # Toradex SMARC iMX95 on Toradex SMARC Development Board @@ -1515,6 +1543,7 @@ properties: - toradex,verdin-imx95-nonwifi-ivy # Verdin iMX95 Module on Ivy - toradex,verdin-imx95-nonwifi-mallow # Verdin iMX95 Module on Mallow - toradex,verdin-imx95-nonwifi-yavia # Verdin iMX95 Module on Yavia + - toradex,verdin-imx95-nonwifi-zinnia # Verdin iMX95 Module on Zinnia - const: toradex,verdin-imx95-nonwifi # Verdin iMX95 Module without Wi-Fi / BT - const: toradex,verdin-imx95 # Verdin iMX95 Module - const: fsl,imx95 @@ -1527,6 +1556,7 @@ properties: - toradex,verdin-imx95-wifi-ivy # Verdin iMX95 Wi-Fi / BT Module on Ivy - toradex,verdin-imx95-wifi-mallow # Verdin iMX95 Wi-Fi / BT Module on Mallow - toradex,verdin-imx95-wifi-yavia # Verdin iMX95 Wi-Fi / BT Module on Yavia + - toradex,verdin-imx95-wifi-zinnia # Verdin iMX95 Wi-Fi / BT Module on Zinnia - const: toradex,verdin-imx95-wifi # Verdin iMX95 Wi-Fi / BT Module - const: toradex,verdin-imx95 # Verdin iMX95 Module - const: fsl,imx95 @@ -1614,6 +1644,18 @@ properties: - const: variscite,var-dart-mx91 # Variscite DART-MX91 SOM - const: fsl,imx91 + - description: Variscite VAR-SOM-MX91 based boards + items: + - const: variscite,var-som-mx91-symphony # Variscite VAR-SOM-MX91 on Symphony + - const: variscite,var-som-mx91 # Variscite VAR-SOM-MX91 + - const: fsl,imx91 + + - description: Variscite DART-MX93 based boards + items: + - const: variscite,var-dart-mx93-sonata # Variscite DART-MX93 on Sonata Development Board + - const: variscite,var-dart-mx93 # Variscite DART-MX93 SOM + - const: fsl,imx93 + - description: Variscite VAR-SOM-MX93 based boards items: - const: variscite,var-som-mx93-symphony @@ -1868,6 +1910,7 @@ properties: - enum: - solidrun,clearfog-cx - solidrun,honeycomb + - solidrun,twins-single - const: solidrun,lx2160a-cex7 - const: fsl,lx2160a diff --git a/Documentation/devicetree/bindings/arm/gemini.yaml b/Documentation/devicetree/bindings/arm/gemini.yaml index fc092962ab5653..dfb11244b57eb5 100644 --- a/Documentation/devicetree/bindings/arm/gemini.yaml +++ b/Documentation/devicetree/bindings/arm/gemini.yaml @@ -55,6 +55,11 @@ properties: - const: itian,sq201 - const: cortina,gemini + - description: Raidsonic NAS IB-4210-B + items: + - const: raidsonic,ib-4210-b + - const: cortina,gemini + - description: Raidsonic NAS IB-4220-B items: - const: raidsonic,ib-4220-b @@ -70,6 +75,11 @@ properties: - const: teltonika,rut1xx - const: cortina,gemini + - description: Verbatim S08V1901-D1 NAS + items: + - const: verbatim,s08v1901-d1 + - const: cortina,gemini + - description: Wiligear Wiliboard WBD-111 items: - const: wiligear,wiliboard-wbd111 diff --git a/Documentation/devicetree/bindings/arm/omap/crossbar.txt b/Documentation/devicetree/bindings/arm/omap/crossbar.txt deleted file mode 100644 index a43e4c7aba3dbf..00000000000000 --- a/Documentation/devicetree/bindings/arm/omap/crossbar.txt +++ /dev/null @@ -1,55 +0,0 @@ -Some socs have a large number of interrupts requests to service -the needs of its many peripherals and subsystems. All of the -interrupt lines from the subsystems are not needed at the same -time, so they have to be muxed to the irq-controller appropriately. -In such places a interrupt controllers are preceded by an CROSSBAR -that provides flexibility in muxing the device requests to the controller -inputs. - -Required properties: -- compatible : Should be "ti,irq-crossbar" -- reg: Base address and the size of the crossbar registers. -- interrupt-controller: indicates that this block is an interrupt controller. -- ti,max-irqs: Total number of irqs available at the parent interrupt controller. -- ti,max-crossbar-sources: Maximum number of crossbar sources that can be routed. -- ti,reg-size: Size of a individual register in bytes. Every individual - register is assumed to be of same size. Valid sizes are 1, 2, 4. -- ti,irqs-reserved: List of the reserved irq lines that are not muxed using - crossbar. These interrupt lines are reserved in the soc, - so crossbar bar driver should not consider them as free - lines. - -Optional properties: -- ti,irqs-skip: This is similar to "ti,irqs-reserved", but these are for - SOC-specific hard-wiring of those irqs which unexpectedly bypasses the - crossbar. These irqs have a crossbar register, but still cannot be used. - -- ti,irqs-safe-map: integer which maps to a safe configuration to use - when the interrupt controller irq is unused (when not provided, default is 0) - -Examples: - crossbar_mpu: crossbar@4a002a48 { - compatible = "ti,irq-crossbar"; - reg = <0x4a002a48 0x130>; - ti,max-irqs = <160>; - ti,max-crossbar-sources = <400>; - ti,reg-size = <2>; - ti,irqs-reserved = <0 1 2 3 5 6 131 132>; - ti,irqs-skip = <10 133 139 140>; - }; - -Consumer: -======== -See Documentation/devicetree/bindings/interrupt-controller/interrupts.txt and -Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml for -further details. - -An interrupt consumer on an SoC using crossbar will use: - interrupts = - -Example: - device_x@4a023000 { - /* Crossbar 8 used */ - interrupts = ; - ... - }; diff --git a/Documentation/devicetree/bindings/arm/omap/dmm.txt b/Documentation/devicetree/bindings/arm/omap/dmm.txt deleted file mode 100644 index 8bd6d0a238a88f..00000000000000 --- a/Documentation/devicetree/bindings/arm/omap/dmm.txt +++ /dev/null @@ -1,22 +0,0 @@ -OMAP Dynamic Memory Manager (DMM) bindings - -The dynamic memory manager (DMM) is a module located immediately in front of the -SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of memory -accesses such as priority generation amongst initiators, configuration of SDRAM -interleaving, optimizing transfer of 2D block objects, and provide MMU-like page -translation for initiators which need contiguous dma bus addresses. - -Required properties: -- compatible: Should contain "ti,omap4-dmm" for OMAP4 family - Should contain "ti,omap5-dmm" for OMAP5 and DRA7x family -- reg: Contains DMM register address range (base address and length) -- interrupts: Should contain an interrupt-specifier for DMM_IRQ. -- ti,hwmods: Name of the hwmod associated to DMM, which is typically "dmm" - -Example: - -dmm@4e000000 { - compatible = "ti,omap4-dmm"; - reg = <0x4e000000 0x800>; - ti,hwmods = "dmm"; -}; diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index b4943123d2e425..50cc18a6ec5edd 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -79,6 +79,7 @@ properties: - items: - enum: - fairphone,fp6 + - nothing,asteroids - const: qcom,milos - items: @@ -365,6 +366,11 @@ properties: - qcom,ipq9574-ap-al02-c9 - const: qcom,ipq9574 + - items: + - enum: + - qcom,ipq9650-rdp488 + - const: qcom,ipq9650 + - items: - enum: - qcom,kaanapali-mtp @@ -822,6 +828,14 @@ properties: - const: google,zombie-sku514 - const: qcom,sc7280 + - description: Xiaomi Poco F1 + items: + - enum: + - xiaomi,beryllium-ebbg + - xiaomi,beryllium-tianma + - const: xiaomi,beryllium + - const: qcom,sdm845 + - items: - enum: - lenovo,flex-5g @@ -972,8 +986,6 @@ properties: - sony,akatsuki-row - sony,apollo-row - thundercomm,db845c - - xiaomi,beryllium - - xiaomi,beryllium-ebbg - xiaomi,polaris - const: qcom,sdm845 @@ -1040,6 +1052,7 @@ properties: - items: - enum: + - motorola,dubai - nothing,spacewar - const: qcom,sm7325 @@ -1168,6 +1181,10 @@ properties: - const: microsoft,denali - const: qcom,x1e80100 + - items: + - const: microsoft,surface-pro-12in + - const: qcom,x1p42100 + - items: - enum: - qcom,purwa-iot-evk diff --git a/Documentation/devicetree/bindings/arm/st,nomadik.yaml b/Documentation/devicetree/bindings/arm/st,nomadik.yaml new file mode 100644 index 00000000000000..d2167908ff6003 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/st,nomadik.yaml @@ -0,0 +1,23 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/st,nomadik.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST Nomadik SoC based Boards + +maintainers: + - Linus Walleij + +description: + Boards using the Nomadik SoC platform + +properties: + $nodename: + const: '/' + compatible: + enum: + - st,nomadik-nhk-15 + - calaosystems,usb-s8815 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/ste-nomadik.txt b/Documentation/devicetree/bindings/arm/ste-nomadik.txt deleted file mode 100644 index 2fdff5a806cfb7..00000000000000 --- a/Documentation/devicetree/bindings/arm/ste-nomadik.txt +++ /dev/null @@ -1,38 +0,0 @@ -ST-Ericsson Nomadik Device Tree Bindings - -For various board the "board" node may contain specific properties -that pertain to this particular board, such as board-specific GPIOs. - -Required root node property: src -- Nomadik System and reset controller used for basic chip control, clock - and reset line control. -- compatible: must be "stericsson,nomadik,src" - -Boards with the Nomadik SoC include: - -Nomadik NHK-15 board manufactured by ST Microelectronics: - -Required root node property: - -compatible="st,nomadik-nhk-15"; - -S8815 "MiniKit" manufactured by Calao Systems: - -Required root node property: - -compatible="calaosystems,usb-s8815"; - -Required node: usb-s8815 - -Example: - -usb-s8815 { - ethernet-gpio { - gpios = <&gpio3 19 0x1>; - interrupts = <19 0x1>; - interrupt-parent = <&gpio3>; - }; - mmcsd-gpio { - gpios = <&gpio3 16 0x1>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml index dcd1c53765077f..dd1f637e4175a2 100644 --- a/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml +++ b/Documentation/devicetree/bindings/arm/tegra/nvidia,tegra186-pmc.yaml @@ -16,6 +16,7 @@ properties: - nvidia,tegra186-pmc - nvidia,tegra194-pmc - nvidia,tegra234-pmc + - nvidia,tegra238-pmc - nvidia,tegra264-pmc reg: @@ -76,6 +77,7 @@ allOf: contains: enum: - nvidia,tegra234-pmc + - nvidia,tegra238-pmc - nvidia,tegra264-pmc then: properties: diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index 2a6a9441c23de2..69b5441cbf1a97 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -97,6 +97,13 @@ properties: - const: toradex,verdin-am62 # Verdin AM62 Module - const: ti,am625 + - description: K3 AM625 SoC on TQ-Systems TQMa62xx SoM + items: + - enum: + - tq,am625-tqma6254-mba62xx # MBa62xx base board + - const: tq,am625-tqma6254 + - const: ti,am625 + - description: K3 AM62P5 SoC Toradex Verdin Modules and Carrier Boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/zte.yaml b/Documentation/devicetree/bindings/arm/zte.yaml new file mode 100644 index 00000000000000..f028d2cec7ab21 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/zte.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/zte.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx platforms + +maintainers: + - Stefan Dösinger + +description: | + ARM platforms using SoCs designed by ZTE. Currently this supports devices + based on the zx297520v3 SoC which is found in LTE routers. + +properties: + $nodename: + const: "/" + compatible: + oneOf: + - items: + - enum: + - dlink,dwr932m + - const: zte,zx297520v3 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml index 00bbde203f598a..4808065fc9115f 100644 --- a/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml +++ b/Documentation/devicetree/bindings/bus/fsl,spba-bus.yaml @@ -26,8 +26,10 @@ select: compatible: contains: enum: + - fsl,aipi-bus - fsl,aips - fsl,emi + - fsl,emi-bus - fsl,spba-bus required: - compatible @@ -39,8 +41,10 @@ properties: compatible: items: - enum: + - fsl,aipi-bus - fsl,aips - fsl,emi + - fsl,emi-bus - fsl,spba-bus - const: simple-bus diff --git a/Documentation/devicetree/bindings/cache/l2c2x0.yaml b/Documentation/devicetree/bindings/cache/l2c2x0.yaml index 10c1a900202fc2..ee604117ffb3fe 100644 --- a/Documentation/devicetree/bindings/cache/l2c2x0.yaml +++ b/Documentation/devicetree/bindings/cache/l2c2x0.yaml @@ -66,6 +66,9 @@ properties: reg: maxItems: 1 + power-domains: + maxItems: 1 + arm,data-latency: description: Cycles of latency for Data RAM accesses. Specifies 3 cells of read, write and setup latencies. Minimum valid values are 1. Controllers diff --git a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml index 995d5781578106..34e3a2d7859275 100644 --- a/Documentation/devicetree/bindings/cache/qcom,llcc.yaml +++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml @@ -20,7 +20,9 @@ description: | properties: compatible: enum: + - qcom,eliza-llcc - qcom,glymur-llcc + - qcom,hawi-llcc - qcom,ipq5424-llcc - qcom,kaanapali-llcc - qcom,qcs615-llcc @@ -35,6 +37,7 @@ properties: - qcom,sc8280xp-llcc - qcom,sdm670-llcc - qcom,sdm845-llcc + - qcom,shikra-llcc - qcom,sm6350-llcc - qcom,sm7150-llcc - qcom,sm8150-llcc @@ -57,6 +60,11 @@ properties: interrupts: maxItems: 1 + memory-region: + maxItems: 1 + description: handle to a reserved-memory node used for firmware-populated + SLC/SCT shared memory. + nvmem-cells: items: - description: Reference to an nvmem node for multi channel DDR @@ -206,6 +214,7 @@ allOf: enum: - qcom,sc7280-llcc - qcom,sdm670-llcc + - qcom,shikra-llcc then: properties: reg: @@ -318,6 +327,7 @@ allOf: contains: enum: - qcom,kaanapali-llcc + - qcom,hawi-llcc - qcom,sm8450-llcc - qcom,sm8550-llcc - qcom,sm8650-llcc @@ -340,6 +350,39 @@ allOf: - const: llcc3_base - const: llcc_broadcast_base - const: llcc_broadcast_and_base + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-llcc + then: + required: + - memory-region + else: + properties: + memory-region: false + + - if: + properties: + compatible: + contains: + enum: + - qcom,eliza-llcc + then: + properties: + reg: + items: + - description: LLCC0 base register region + - description: LLCC2 base register region + - description: LLCC broadcast OR register region + - description: LLCC broadcast AND register region + reg-names: + items: + - const: llcc0_base + - const: llcc2_base + - const: llcc_broadcast_base + - const: llcc_broadcast_and_base additionalProperties: false diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml index 55bb73707d58ac..a4b214a941eae3 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-peripherals-clkc.yaml @@ -24,7 +24,7 @@ properties: const: 1 clocks: - minItems: 14 + minItems: 15 items: - description: input oscillator - description: input sys clk @@ -40,12 +40,13 @@ properties: - description: input gp1 pll - description: input mpll1 - description: input mpll2 + - description: input mpll3 - description: external input rmii oscillator (optional) - description: input video pll0 (optional) - description: external pad input for rtc (optional) clock-names: - minItems: 14 + minItems: 15 items: - const: xtal - const: sys @@ -61,6 +62,7 @@ properties: - const: gp1 - const: mpll1 - const: mpll2 + - const: mpll3 - const: ext_rmii - const: vid_pll0 - const: ext_rtc @@ -97,7 +99,8 @@ examples: <&gp0 1>, <&gp1 1>, <&mpll 4>, - <&mpll 6>; + <&mpll 6>, + <&mpll 8>; clock-names = "xtal", "sys", "fix", @@ -111,6 +114,7 @@ examples: "gp0", "gp1", "mpll1", - "mpll2"; + "mpll2", + "mpll3"; }; }; diff --git a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml index 49c61f65deff75..b488d92b798464 100644 --- a/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml +++ b/Documentation/devicetree/bindings/clock/amlogic,t7-pll-clkc.yaml @@ -72,7 +72,7 @@ allOf: contains: enum: - amlogic,t7-gp0-pll - - amlogic,t7-gp1--pll + - amlogic,t7-gp1-pll - amlogic,t7-hifi-pll - amlogic,t7-pcie-pll - amlogic,t7-mpll diff --git a/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml b/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml new file mode 100644 index 00000000000000..34c93cb5db400c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/canaan,k230-clk.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/canaan,k230-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Canaan Kendryte K230 Clock + +maintainers: + - Xukai Wang + +description: + The Canaan K230 clock controller generates various clocks for SoC + peripherals. See include/dt-bindings/clock/canaan,k230-clk.h for + valid clock IDs. + +properties: + compatible: + const: canaan,k230-clk + + reg: + items: + - description: PLL control registers + - description: Sysclk control registers + + clocks: + items: + - description: Main external reference clock + - description: + External clock which used as the pulse input + for the timer to provide timing signals. + + clock-names: + items: + - const: osc24m + - const: timer-pulse-in + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + +additionalProperties: false + +examples: + - | + clock-controller@91102000 { + compatible = "canaan,k230-clk"; + reg = <0x91102000 0x40>, + <0x91100000 0x108>; + clocks = <&osc24m>, <&timerx_pulse_in>; + clock-names = "osc24m", "timer-pulse-in"; + #clock-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml index d416c374e8534f..ceeaa8f9fb08f9 100644 --- a/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml +++ b/Documentation/devicetree/bindings/clock/cirrus,cs2000-cp.yaml @@ -11,14 +11,19 @@ maintainers: description: | The CS2000-CP is an extremely versatile system clocking device that - utilizes a programmable phase lock loop. + utilizes a programmable phase lock loop. CS2500 is a compatible + drop-in replacement for CS2000-CP. Link: https://www.cirrus.com/products/cs2000/ + Link: https://www.cirrus.com/products/cs2500/ properties: compatible: - enum: - - cirrus,cs2000-cp + oneOf: + - items: + - const: cirrus,cs2500 + - const: cirrus,cs2000-cp + - const: cirrus,cs2000-cp clocks: description: diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml index 6f3a8578fe2a68..0db5504013d5e8 100644 --- a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -37,6 +37,9 @@ properties: '#power-domain-cells': const: 1 + '#reset-cells': + const: 1 + required: - compatible - reg @@ -44,16 +47,27 @@ required: additionalProperties: false -if: - not: - properties: - compatible: - contains: - const: marvell,pxa1908-apmu - -then: - properties: - '#power-domain-cells': false +allOf: + - if: + not: + properties: + compatible: + contains: + const: marvell,pxa1908-apmu + then: + properties: + '#power-domain-cells': false + - if: + not: + properties: + compatible: + contains: + enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + then: + properties: + '#reset-cells': false examples: # APMU block: diff --git a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml index ef2b1e2044309a..a177a1934b19f9 100644 --- a/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,dispcc-sm6125.yaml @@ -42,12 +42,6 @@ properties: - const: cfg_ahb_clk - const: gcc_disp_gpll0_div_clk_src - '#clock-cells': - const: 1 - - '#power-domain-cells': - const: 1 - power-domains: description: A phandle and PM domain specifier for the CX power domain. @@ -58,18 +52,16 @@ properties: A phandle to an OPP node describing the power domain's performance point. maxItems: 1 - reg: - maxItems: 1 - required: - compatible - - reg - clocks - clock-names - - '#clock-cells' - '#power-domain-cells' -additionalProperties: false +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false examples: - | @@ -101,6 +93,7 @@ examples: power-domains = <&rpmpd SM6125_VDDCX>; #clock-cells = <1>; + #reset-cells = <1>; #power-domain-cells = <1>; }; ... diff --git a/Documentation/devicetree/bindings/clock/qcom,hawi-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,hawi-gcc.yaml new file mode 100644 index 00000000000000..4f428c0f7286e8 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,hawi-gcc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,hawi-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on Hawi + +maintainers: + - Vivek Aknurwar + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on Hawi. + + See also: include/dt-bindings/clock/qcom,hawi-gcc.h + +properties: + compatible: + const: qcom,hawi-gcc + + clocks: + items: + - description: Board XO source + - description: Board Always On XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source + - description: PCIE 1 Pipe clock source + - description: UFS PHY RX symbol 0 clock + - description: UFS PHY RX symbol 1 clock + - description: UFS PHY TX symbol 0 clock + - description: USB3 PHY wrapper pipe clock + +required: + - compatible + - clocks + - '#power-domain-cells' + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,hawi-gcc"; + reg = <0x00100000 0x1f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&sleep_clk>, + <&pcie0_phy>, + <&pcie1_phy>, + <&ufs_mem_phy 0>, + <&ufs_mem_phy 1>, + <&ufs_mem_phy 2>, + <&usb_1_qmpphy>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml index de338c05190fb1..a4f9af8fa187b2 100644 --- a/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9574-cmn-pll.yaml @@ -8,7 +8,7 @@ title: Qualcomm CMN PLL Clock Controller on IPQ SoC maintainers: - Bjorn Andersson - - Luo Jie + - Luo Jie description: The CMN (or common) PLL clock controller expects a reference @@ -25,6 +25,7 @@ properties: compatible: enum: - qcom,ipq5018-cmn-pll + - qcom,ipq5332-cmn-pll - qcom,ipq5424-cmn-pll - qcom,ipq6018-cmn-pll - qcom,ipq8074-cmn-pll diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml new file mode 100644 index 00000000000000..f33105217a062a --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq9650-gcc.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq9650-gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on IPQ9650 + +maintainers: + - Bjorn Andersson + - Kathiravan Thirumoorthy + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on IPQ9650 + + See also: + include/dt-bindings/clock/qcom,ipq9650-gcc.h + include/dt-bindings/reset/qcom,ipq9650-gcc.h + +properties: + compatible: + const: qcom,ipq9650-gcc + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE30 PHY0 pipe clock source + - description: PCIE30 PHY1 pipe clock source + - description: PCIE30 PHY2 pipe clock source + - description: PCIE30 PHY3 pipe clock source + - description: PCIE30 PHY4 pipe clock source + - description: USB PCIE wrapper pipe clock source + - description: NSS common clock source + + '#power-domain-cells': false + + '#interconnect-cells': + const: 1 + +required: + - compatible + - clocks + +allOf: + - $ref: qcom,gcc.yaml# + +unevaluatedProperties: false + +examples: + - | + clock-controller@1800000 { + compatible = "qcom,ipq9650-gcc"; + reg = <0x01800000 0x40000>; + clocks = <&xo_board_clk>, + <&sleep_clk>, + <&pcie30_phy0_pipe_clk>, + <&pcie30_phy1_pipe_clk>, + <&pcie30_phy2_pipe_clk>, + <&pcie30_phy3_pipe_clk>, + <&pcie30_phy4_pipe_clk>, + <&usb3phy_0_cc_pipe_clk>, + <&nss_cmn_clk>; + #clock-cells = <1>; + #reset-cells = <1>; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml index 466c884aa2bab2..e868963f659b65 100644 --- a/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,kaanapali-gxclkctl.yaml @@ -44,7 +44,7 @@ required: - power-domains - '#power-domain-cells' -unevaluatedProperties: false +additionalProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml index f63149ecf3e1b9..707b25d2c11e60 100644 --- a/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,milos-camcc.yaml @@ -25,6 +25,10 @@ properties: - description: Sleep clock source - description: Camera AHB clock from GCC + interconnects: + items: + - description: Interconnect path to enable the MultiMedia NoC + required: - compatible - clocks @@ -37,12 +41,16 @@ unevaluatedProperties: false examples: - | #include + #include + #include clock-controller@adb0000 { compatible = "qcom,milos-camcc"; reg = <0x0adb0000 0x40000>; clocks = <&bi_tcxo_div2>, <&sleep_clk>, <&gcc GCC_CAMERA_AHB_CLK>; + interconnects = <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mmss_noc SLAVE_MNOC_HF_MEM_NOC QCOM_ICC_TAG_ALWAYS>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; diff --git a/Documentation/devicetree/bindings/clock/qcom,milos-gxclkctl.yaml b/Documentation/devicetree/bindings/clock/qcom,milos-gxclkctl.yaml new file mode 100644 index 00000000000000..fbcb5d3f3e3d10 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,milos-gxclkctl.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,milos-gxclkctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Graphics Power Domain Controller on Milos + +maintainers: + - Luca Weiss + +description: | + Qualcomm GX(graphics) is a clock controller which has PLLs, clocks and + Power domains (GDSC). This module provides the power domains control + of gxclkctl on Qualcomm SoCs which helps the recovery of Graphics subsystem. + + See also: + include/dt-bindings/clock/qcom,kaanapali-gxclkctl.h + +properties: + compatible: + enum: + - qcom,milos-gxclkctl + + reg: + maxItems: 1 + + power-domains: + description: + Power domains required for the clock controller to operate + items: + - description: GFX power domain + - description: GPUCC(CX) power domain + + '#power-domain-cells': + const: 1 + +required: + - compatible + - reg + - power-domains + - '#power-domain-cells' + +additionalProperties: false + +examples: + - | + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + + clock-controller@3d64000 { + compatible = "qcom,milos-gxclkctl"; + reg = <0x0 0x03d64000 0x0 0x6000>; + power-domains = <&rpmhpd RPMHPD_GFX>, + <&gpucc 0>; + #power-domain-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml b/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml index 61473385da2de4..480745349a5d13 100644 --- a/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,qca8k-nsscc.yaml @@ -8,7 +8,7 @@ title: Qualcomm NSS Clock & Reset Controller on QCA8386/QCA8084 maintainers: - Bjorn Andersson - - Luo Jie + - Luo Jie description: | Qualcomm NSS clock control module provides the clocks and resets diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml index a2c404a579812d..d344b338604295 100644 --- a/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,rpmhcc.yaml @@ -19,6 +19,7 @@ properties: enum: - qcom,eliza-rpmh-clk - qcom,glymur-rpmh-clk + - qcom,hawi-rpmh-clk - qcom,kaanapali-rpmh-clk - qcom,milos-rpmh-clk - qcom,nord-rpmh-clk diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml index 7bbf120d928cc5..5d77029bfaf883 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8450-videocc.yaml @@ -20,6 +20,7 @@ description: | include/dt-bindings/clock/qcom,sm8450-videocc.h include/dt-bindings/clock/qcom,sm8650-videocc.h include/dt-bindings/clock/qcom,sm8750-videocc.h + include/dt-bindings/clock/qcom,x1p42100-videocc.h properties: compatible: @@ -32,6 +33,7 @@ properties: - qcom,sm8650-videocc - qcom,sm8750-videocc - qcom,x1e80100-videocc + - qcom,x1p42100-videocc clocks: items: @@ -70,6 +72,7 @@ allOf: - qcom,sm8450-videocc - qcom,sm8550-videocc - qcom,sm8750-videocc + - qcom,x1p42100-videocc then: required: - required-opps diff --git a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml index 1ccdf4b0f5dd39..08824f84897358 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sm8550-tcsr.yaml @@ -17,6 +17,7 @@ description: | See also: - include/dt-bindings/clock/qcom,eliza-tcsr.h - include/dt-bindings/clock/qcom,glymur-tcsr.h + - include/dt-bindings/clock/qcom,hawi-tcsrcc.h - include/dt-bindings/clock/qcom,nord-tcsrcc.h - include/dt-bindings/clock/qcom,sm8550-tcsr.h - include/dt-bindings/clock/qcom,sm8650-tcsr.h @@ -28,6 +29,7 @@ properties: - enum: - qcom,eliza-tcsr - qcom,glymur-tcsr + - qcom,hawi-tcsrcc - qcom,kaanapali-tcsr - qcom,milos-tcsr - qcom,nord-tcsrcc diff --git a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml index 938a2f1ff3fca8..b28614186cc098 100644 --- a/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,x1e80100-camcc.yaml @@ -23,6 +23,7 @@ properties: compatible: enum: - qcom,x1e80100-camcc + - qcom,x1p42100-camcc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml index a0e09b7002f071..703b5bf26717cc 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-clocks.yaml @@ -41,7 +41,7 @@ properties: clock-output-names: minItems: 3 - maxItems: 17 + maxItems: 19 renesas,mode: description: Board-specific settings of the MD_CK* bits on R-Mobile A1 @@ -90,6 +90,8 @@ allOf: - const: zx - const: zs - const: hp + - const: ztr + - const: zt - if: properties: @@ -123,6 +125,8 @@ allOf: - const: zb - const: m3 - const: cp + - const: ztr + - const: zt required: - renesas,mode @@ -240,6 +244,6 @@ examples: #clock-cells = <1>; clock-output-names = "system", "pllc0", "pllc1", "pllc2", "r", "usb24s", "i", "zg", "b", "m1", "hp", "hpp", - "usbp", "s", "zb", "m3", "cp"; + "usbp", "s", "zb", "m3", "cp", "ztr", "zt"; renesas,mode = <0x05>; }; diff --git a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml index 2197c952e21dfa..b6ee8c8efd46da 100644 --- a/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml +++ b/Documentation/devicetree/bindings/clock/renesas,cpg-div6-clock.yaml @@ -60,7 +60,7 @@ examples: clock-output-names = "main", "pll0", "pll1", "pll2", "pll2s", "pll2h", "z", "z2", "i", "m3", "b", "m1", "m2", - "zx", "zs", "hp"; + "zx", "zs", "hp", "ztr", "zt"; }; sdhi2_clk: sdhi2_clk@e615007c { diff --git a/Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml b/Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml new file mode 100644 index 00000000000000..1a3105e86980a1 --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/qcom,shikra-epss.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/qcom,shikra-epss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Shikra SoC EPSS + +maintainers: + - Imran Shaik + - Taniya Das + +description: | + EPSS is a hardware engine used by some Qualcomm SoCs to manage + frequency in hardware. It is capable of controlling frequency for + multiple clusters. + + The Qualcomm Shikra SoC EPSS supports up to 12 frequency lookup table + (LUT) entries. + +properties: + compatible: + enum: + - qcom,shikra-epss + + reg: + items: + - description: Frequency domain 0 register region + - description: Frequency domain 1 register region + + reg-names: + items: + - const: freq-domain0 + - const: freq-domain1 + + clocks: + items: + - description: XO Clock + - description: GPLL0 Clock + + clock-names: + items: + - const: xo + - const: alternate + + interrupts: + items: + - description: IRQ line for DCVSH 0 + - description: IRQ line for DCVSH 1 + + interrupt-names: + items: + - const: dcvsh-irq-0 + - const: dcvsh-irq-1 + + '#freq-domain-cells': + const: 1 + + '#clock-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - interrupt-names + - '#freq-domain-cells' + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + soc { + #address-cells = <1>; + #size-cells = <1>; + + cpufreq@fd91000 { + compatible = "qcom,shikra-epss"; + reg = <0x0fd91000 0x1000>, <0x0fd92000 0x1000>; + reg-names = "freq-domain0", "freq-domain1"; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gpll0>; + clock-names = "xo", "alternate"; + interrupts = , + ; + interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1"; + #freq-domain-cells = <1>; + #clock-cells = <1>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml index ccb6b8dd8e116e..db895c50e2d25e 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml @@ -14,6 +14,7 @@ properties: items: - enum: - qcom,eliza-inline-crypto-engine + - qcom,hawi-inline-crypto-engine - qcom,kaanapali-inline-crypto-engine - qcom,milos-inline-crypto-engine - qcom,qcs8300-inline-crypto-engine diff --git a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml index 41402599e9ab81..dc270c8aedf3a1 100644 --- a/Documentation/devicetree/bindings/crypto/qcom,prng.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom,prng.yaml @@ -17,11 +17,14 @@ properties: - qcom,prng-ee # 8996 and later using EE - items: - enum: + - qcom,glymur-trng + - qcom,hawi-trng - qcom,ipq5332-trng - qcom,ipq5424-trng - qcom,ipq9574-trng - qcom,kaanapali-trng - qcom,milos-trng + - qcom,nord-trng - qcom,qcs615-trng - qcom,qcs8300-trng - qcom,sa8255p-trng diff --git a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml index 79d5be2548bc52..08febd66c22ba8 100644 --- a/Documentation/devicetree/bindings/crypto/qcom-qce.yaml +++ b/Documentation/devicetree/bindings/crypto/qcom-qce.yaml @@ -45,7 +45,11 @@ properties: - items: - enum: + - qcom,eliza-qce + - qcom,glymur-qce - qcom,kaanapali-qce + - qcom,milos-qce + - qcom,nord-qce - qcom,qcs615-qce - qcom,qcs8300-qce - qcom,sa8775p-qce diff --git a/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml b/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml index 9a6e9b25d14a93..7cfe92a8bcd721 100644 --- a/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lontium,lt9211.yaml @@ -36,18 +36,56 @@ properties: properties: port@0: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: Primary MIPI DSI port-1 for MIPI input or LVDS port-1 for LVDS input or DPI input. + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + required: + - data-lanes + port@1: - $ref: /schemas/graph.yaml#/properties/port + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false description: Additional MIPI port-2 for MIPI input or LVDS port-2 for LVDS input. Used in combination with primary port-1 to drive higher resolution displays + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + minItems: 1 + items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + + required: + - data-lanes + port@2: $ref: /schemas/graph.yaml#/properties/port description: @@ -99,6 +137,7 @@ examples: reg = <0>; endpoint { + data-lanes = <1 2 3 4>; remote-endpoint = <&dsi0_out>; }; }; diff --git a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml index 7586d681bcc6ba..3c727e4d1096a5 100644 --- a/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lvds-codec.yaml @@ -34,10 +34,12 @@ properties: - items: - enum: - doestek,dtc34lm85am # For the Doestek DTC34LM85AM Flat Panel Display (FPD) Transmitter + - idt,v103 # For the Triple 10-BIT LVDS Transmitter - onnn,fin3385 # OnSemi FIN3385 - ti,ds90c185 # For the TI DS90C185 FPD-Link Serializer - ti,ds90c187 # For the TI DS90C187 FPD-Link Serializer - ti,sn75lvds83 # For the TI SN75LVDS83 FlatLink transmitter + - ti,sn75lvds93 # For the TI SN75LVDS93 FlatLink transmitter - const: lvds-encoder # Generic LVDS encoder compatible fallback - items: - enum: diff --git a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml index e6808419f62545..7636c24906ba08 100644 --- a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml +++ b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml @@ -30,6 +30,7 @@ properties: - algoltek,ag6311 - asl-tek,cs5263 - dumb-vga-dac + - mstar,tsumu88adt3-lf-1 - parade,ps185hdm - radxa,ra620 - realtek,rtd2171 diff --git a/Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml b/Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml index e2d293d623b8d5..76064549303147 100644 --- a/Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml +++ b/Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml @@ -10,6 +10,7 @@ maintainers: - Svyatoslav Ryhel allOf: + - $ref: /schemas/display/dsi-controller.yaml# - $ref: /schemas/spi/spi-peripheral-props.yaml# properties: @@ -86,7 +87,7 @@ required: - compatible - ports -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml index 3820dd7e11af14..4d34a92192bf08 100644 --- a/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml @@ -10,11 +10,14 @@ maintainers: - Joseph Guo description: - Waveshare bridge board is part of Waveshare panel which converts DSI to DPI. + Waveshare bridge board is part of Waveshare panel which converts DSI to DPI + or LVDS. properties: compatible: - const: waveshare,dsi2dpi + enum: + - waveshare,dsi2dpi + - waveshare,dsi2lvds reg: maxItems: 1 @@ -53,7 +56,7 @@ properties: port@1: $ref: /schemas/graph.yaml#/properties/port description: - Video port for MIPI DPI output panel. + Video port for MIPI DPI or LVDS output to the panel. required: - port@0 diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml index bbcfe7e2958b70..b0c5869771fae2 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx-parallel-display.yaml @@ -42,6 +42,17 @@ properties: unevaluatedProperties: false description: output port connected to a panel + port: + $ref: /schemas/graph.yaml#/properties/port + unevaluatedProperties: false + deprecated: true + description: input port connected to the IPU display interface, see port@0 + + display-timings: + $ref: /schemas/display/panel/display-timings.yaml# + unevaluatedProperties: false + deprecated: true + required: - compatible diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx53-tve.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx53-tve.yaml new file mode 100644 index 00000000000000..2fcf4474591229 --- /dev/null +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx53-tve.yaml @@ -0,0 +1,104 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/imx/fsl,imx53-tve.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX53 Television Encoder (TVE) + +maintainers: + - Frank Li + +description: + The Television Encoder (TVE) is a hardware block in the i.MX53 SoC that + converts digital video data into analog TV signals (NTSC/PAL). + +properties: + compatible: + const: fsl,imx53-tve + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: TVE gate clock + - description: Display interface selector clock + + clock-names: + items: + - const: tve + - const: di_sel + + ddc-i2c-bus: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle to the I2C bus used for DDC (Display Data Channel) communication + to read EDID information from the connected display. + + dac-supply: + description: + Regulator supply for the TVE DAC (Digital-to-Analog Converter). + + fsl,tve-mode: + $ref: /schemas/types.yaml#/definitions/string + description: + TVE output mode selection. + enum: + - ntsc + - pal + - vga + + fsl,hsync-pin: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Pin number for horizontal sync signal in VGA mode. + minimum: 0 + maximum: 8 + + fsl,vsync-pin: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Pin number for vertical sync signal in VGA mode. + minimum: 0 + maximum: 8 + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + Port node with one endpoint connected to the IPU display interface. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - fsl,tve-mode + +additionalProperties: false + +examples: + - | + #include + #include + + tve@63ff0000 { + compatible = "fsl,imx53-tve"; + reg = <0x63ff0000 0x1000>; + interrupts = <92>; + clocks = <&clks IMX5_CLK_TVE_GATE>, + <&clks IMX5_CLK_IPU_DI1_SEL>; + clock-names = "tve", "di_sel"; + fsl,tve-mode = "vga"; + + port { + endpoint { + remote-endpoint = <&ipu_di1_tve>; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml index 27118f4c0d2810..fd095e5742c51e 100644 --- a/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml +++ b/Documentation/devicetree/bindings/display/imx/fsl,imx8qxp-dc-command-sequencer.yaml @@ -41,7 +41,7 @@ properties: - const: sw3 sram: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 description: phandle pointing to the mmio-sram device node required: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml index bacdfe7d08a619..ac0d924a451b48 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl-2l.yaml @@ -45,9 +45,8 @@ properties: - description: OVL-2L Clock iommus: - description: - This property should point to the respective IOMMU block with master port as argument, - see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + minItems: 1 + maxItems: 2 mediatek,gce-client-reg: description: The register of client driver can be configured by gce with diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml index 679f731f0f15f7..4df5c7b410c693 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ovl.yaml @@ -66,9 +66,8 @@ properties: - description: OVL Clock iommus: - description: - This property should point to the respective IOMMU block with master port as argument, - see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + minItems: 1 + maxItems: 2 mediatek,gce-client-reg: description: The register of client driver can be configured by gce with diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml index cb187a95c11ea4..d914c06640dfe4 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,rdma.yaml @@ -65,9 +65,7 @@ properties: - description: RDMA Clock iommus: - description: - This property should point to the respective IOMMU block with master port as argument, - see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + maxItems: 1 mediatek,rdma-fifo-size: description: diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml index 816841a96133db..97d052b0fb6141 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,wdma.yaml @@ -45,9 +45,7 @@ properties: - description: WDMA Clock iommus: - description: - This property should point to the respective IOMMU block with master port as argument, - see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + maxItems: 1 mediatek,gce-client-reg: description: The register of client driver can be configured by gce with diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index a24fcb91441812..dbc0613e427ed6 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -16,6 +16,7 @@ properties: - enum: - qcom,apq8064-dsi-ctrl - qcom,kaanapali-dsi-ctrl + - qcom,milos-dsi-ctrl - qcom,msm8226-dsi-ctrl - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl @@ -339,6 +340,7 @@ allOf: compatible: contains: enum: + - qcom,milos-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,sa8775p-dsi-ctrl - qcom,sar2130p-dsi-ctrl diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 93e5e6e19754eb..8578c2f8122e2c 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -300,6 +300,36 @@ allOf: required: - qcom,qmp + - if: + properties: + compatible: + contains: + const: qcom,adreno-gmu-810.0 + then: + properties: + reg: + items: + - description: Core GMU registers + reg-names: + items: + - const: gmu + clocks: + items: + - description: GPU AHB clock + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GMU HUB clock + clock-names: + items: + - const: ahb + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: hub + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 04b2328903ca19..dbbd8b814189b3 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -84,13 +84,9 @@ properties: maxItems: 64 sram: - $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 maxItems: 4 - items: - maxItems: 1 - description: | - phandles to one or more reserved on-chip SRAM regions. + description: phandle to the On Chip Memory (OCMEM) that's present on some a3xx and a4xx Snapdragon SoCs. See Documentation/devicetree/bindings/sram/qcom,ocmem.yaml @@ -411,6 +407,23 @@ allOf: - clocks - clock-names + - if: + properties: + compatible: + contains: + enum: + - qcom,adreno-44010000 + - qcom,adreno-44070001 + then: + properties: + reg: + minItems: 2 + maxItems: 2 + + reg-names: + minItems: 2 + maxItems: 2 + - if: properties: compatible: @@ -434,6 +447,8 @@ allOf: - qcom,adreno-43050a01 - qcom,adreno-43050c01 - qcom,adreno-43051401 + - qcom,adreno-44010000 + - qcom,adreno-44070001 then: # Starting with A6xx, the clocks are usually defined in the GMU node properties: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,milos-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,milos-mdss.yaml new file mode 100644 index 00000000000000..7010ffa0ae350d --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,milos-mdss.yaml @@ -0,0 +1,286 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,milos-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Milos Display MDSS + +maintainers: + - Luca Weiss + +description: + Milos MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,milos-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,milos-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,milos-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,milos-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,milos-dsi-phy-4nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible = "qcom,milos-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interrupts = ; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &cnoc_main SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; + interconnect-names = "mdp0-mem", + "cpu-cfg"; + + power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,milos-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x3000>; + reg-names = "mdp", + "vbif"; + + interrupts-extended = <&mdss 0>; + + clocks = <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-342000000 { + opp-hz = /bits/ 64 <342000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-402000000 { + opp-hz = /bits/ 64 <402000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-535000000 { + opp-hz = /bits/ 64 <535000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + required-opps = <&rpmhpd_opp_nom_l1>; + }; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000>; + required-opps = <&rpmhpd_opp_turbo>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,milos-dsi-ctrl", "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x1000>; + reg-names = "dsi_ctrl"; + + interrupts-extended = <&mdss 4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, + <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + + power-domains = <&rpmhpd RPMHPD_CX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible = "qcom,milos-dsi-phy-4nm"; + reg = <0x0ae95000 0x200>, + <0x0ae95200 0x300>, + <0x0ae95500 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", + "ref"; + + #clock-cells = <1>; + #phy-cells = <0>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml index e2730a2f25cfb0..6c827cf9692b99 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -200,9 +200,11 @@ examples: <0x0aec2000 0x1c8>; clocks = <&dispcc0 MDSS_DISP_CC_MDSS_DPTX0_AUX_CLK>, - <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>; + <&dispcc0 MDSS_DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_EDP_REF_CLKREF_EN>; clock-names = "aux", - "cfg_ahb"; + "cfg_ahb", + "ref"; #clock-cells = <1>; #phy-cells = <0>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index 134321b5089785..aa0cf0ec5b93f6 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -18,6 +18,7 @@ properties: - qcom,eliza-dpu - qcom,glymur-dpu - qcom,kaanapali-dpu + - qcom,milos-dpu - qcom,sa8775p-dpu - qcom,sm8650-dpu - qcom,sm8750-dpu diff --git a/Documentation/devicetree/bindings/display/panel/chipwealth,ch13726a.yaml b/Documentation/devicetree/bindings/display/panel/chipwealth,ch13726a.yaml new file mode 100644 index 00000000000000..c8d7b61037e622 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/chipwealth,ch13726a.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/chipwealth,ch13726a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Chip Wealth Technology CH13726A AMOLED driver + +maintainers: + - Neil Armstrong + +description: + Chip Wealth Technology CH13726A is a single-chip solution + for AMOLED connected using a MIPI-DSI video interface. + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - const: ayntec,thor-panel-bottom + - const: chipwealth,ch13726a + + reg: + maxItems: 1 + description: DSI virtual channel + + vdd-supply: true + vddio-supply: true + vdd1v2-supply: true + avdd-supply: true + + port: true + reset-gpios: true + rotation: true + +required: + - compatible + - reg + - vdd-supply + - vddio-supply + - vdd1v2-supply + - avdd-supply + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "ayntec,thor-panel-bottom", "chipwealth,ch13726a"; + reg = <0>; + vdd1v2-supply = <&vreg_l11b_1p2>; + vddio-supply = <&vdd_disp_1v8>; + vdd-supply = <&vreg_l13b_3p0>; + avdd-supply = <&vdd_disp2_2v8>; + reset-gpios = <&tlmm 133 GPIO_ACTIVE_HIGH>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/panel/focaltech,ota7290b.yaml b/Documentation/devicetree/bindings/display/panel/focaltech,ota7290b.yaml new file mode 100644 index 00000000000000..db6775f4d75ca0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/focaltech,ota7290b.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/focaltech,ota7290b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Focaltech OTA7290B DSI panels + +maintainers: + - Dmitry Baryshkov + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: waveshare,8.8-dsi-touch-a + + reg: + maxItems: 1 + + vdd-supply: + description: supply regulator for VDD, usually 3.3V + + vdda-supply: + description: supply regulator for VDDA, 7-10V + + vcc-supply: + description: supply regulator for VCCIO, usually 1.5V + + reset-gpios: true + backlight: true + rotation: true + port: true + +required: + - compatible + - reg + - vdd-supply + - vcc-supply + - reset-gpios + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "waveshare,8.8-dsi-touch-a"; + reg = <0>; + vdd-supply = <&vdd>; + vcc-supply = <&vccio>; + reset-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; + + port { + endpoint { + remote-endpoint = <&mipi_out_panel>; + }; + }; + }; + }; + +... + diff --git a/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml b/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml index 66404b425af35a..7667428bf9a884 100644 --- a/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml +++ b/Documentation/devicetree/bindings/display/panel/himax,hx83102.yaml @@ -30,6 +30,8 @@ properties: - starry,2082109qfh040022-50e # STARRY himax83102-j02 10.51" WUXGA TFT LCD panel - starry,himax83102-j02 + # Waveshare 12.3-DSI-TOUCH-A panel + - waveshare,12.3-dsi-touch-a - const: himax,hx83102 reg: diff --git a/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml b/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml index 84e840e0224f2f..83c343b0283558 100644 --- a/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml +++ b/Documentation/devicetree/bindings/display/panel/himax,hx8394.yaml @@ -23,6 +23,8 @@ properties: - hannstar,hsd060bhw4 - microchip,ac40t08a-mipi-panel - powkiddy,x55-panel + - waveshare,5.0-dsi-touch-a + - waveshare,5.5-dsi-touch-a - const: himax,hx8394 - items: - enum: diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml index d979701a00a8a5..42e35986fbf60d 100644 --- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml @@ -24,6 +24,7 @@ properties: - raspberrypi,dsi-7inch - startek,kd050hdfia020 - tdo,tl050hdv35 + - waveshare,7.0-dsi-touch-a - wanchanglong,w552946aaa - wanchanglong,w552946aba - const: ilitek,ili9881c @@ -34,6 +35,7 @@ properties: backlight: true port: true power-supply: true + iovcc-supply: true reset-gpios: true rotation: true diff --git a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml index e39efb44ed42c0..4eae802de9fd5b 100644 --- a/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml +++ b/Documentation/devicetree/bindings/display/panel/jadard,jd9365da-h3.yaml @@ -24,6 +24,12 @@ properties: - radxa,display-10hd-ad001 - radxa,display-8hd-ad002 - taiguanck,xti05101-01a + - waveshare,3.4-dsi-touch-c + - waveshare,4.0-dsi-touch-c + - waveshare,8.0-dsi-touch-a + - waveshare,9.0-dsi-touch-b + - waveshare,10.1-dsi-touch-a + - waveshare,10.1-dsi-touch-b - const: jadard,jd9365da-h3 reg: diff --git a/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml b/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml new file mode 100644 index 00000000000000..ff6fdad7febfa0 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/novatek,nt35532.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/novatek,nt35532.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Novatek NT35532-based DSI display panels + +maintainers: + - Cristian Cozzolino + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + items: + - enum: + - flipkart,rimob-panel-nt35532-cs + - const: novatek,nt35532 + + reg: + maxItems: 1 + + backlight: true + reset-gpios: true + + avdd-supply: + description: positive boost supply regulator + + avee-supply: + description: negative boost supply regulator + + vci-supply: + description: regulator that supplies the analog voltage + + vddam-supply: + description: power supply for MIPI interface + + vddi-supply: + description: regulator that supplies the I/O voltage + + port: true + +required: + - compatible + - reg + - reset-gpios + - vddi-supply + - port + +additionalProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "flipkart,rimob-panel-nt35532-cs", "novatek,nt35532"; + reg = <0>; + + backlight = <&pmi8950_wled>; + reset-gpios = <&tlmm 61 GPIO_ACTIVE_LOW>; + avdd-supply = <&lab>; + avee-supply = <&ibb>; + vci-supply = <&pm8953_l17>; + vddi-supply = <&pm8953_l6>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml index b31c67babaa866..b89f86bc068375 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml @@ -58,6 +58,10 @@ properties: - hydis,hv070wx2-1e0 # Jenson Display BL-JT60050-01A 7" WSVGA (1024x600) color TFT LCD LVDS panel - jenson,bl-jt60050-01a + # Riverdi RVT101HVLNWC00 10.1" WXGA (1280x800) TFT LCD LVDS panel + - riverdi,rvt101hvlnwc00 + # Riverdi RVT70HSLNWCA0 7.0" WSVGA (1024x600) TFT LCD LVDS panel + - riverdi,rvt70hslnwca0 # Samsung LTN070NL01 7.0" WSVGA (1024x600) TFT LCD LVDS panel - samsung,ltn070nl01 # Samsung LTN101AL03 10.1" WXGA (800x1280) TFT LCD LVDS panel diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml index cc8d795df732c3..6d4133b91e7cc4 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml @@ -63,6 +63,8 @@ properties: - samsung,s6e3fa7-ams559nk06 # Shangai Top Display Optoelectronics 7" TL070WSH30 1024x600 TFT LCD panel - tdo,tl070wsh30 + # Team Source Display Technology 7" TST070WSBE-196C 1024x600 TFT LCD panel + - team-source-display,tst070wsbe-196c reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 3e41ed0ef5d51c..21453f0d7ce226 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -31,6 +31,8 @@ properties: # Ampire AM-1280800N3TZQW-T00H 10.1" WQVGA TFT LCD panel - ampire,am-1280800n3tzqw-t00h + # Ampire AM-1280800W8TZQW-T00H 10.1" WXGA TFT LCD panel + - ampire,am-1280800w8tzqw-t00h # Ampire AM-480272H3TMQW-T01H 4.3" WQVGA TFT LCD panel - ampire,am-480272h3tmqw-t01h # Ampire AM-800480L1TMQW-T00H 5" WVGA TFT LCD panel @@ -97,6 +99,8 @@ properties: - dataimage,fg1001l0dsswmg01 # DataImage, Inc. 7" WVGA (800x480) TFT LCD panel with 24-bit parallel interface. - dataimage,scf0700c48ggu18 + # Displaytech DT050BTFT-PTS 5.0" 800x480 TFT LCD Panel + - displaytech,dt050btft-pts # DLC Display Co. DLC1010GIG 10.1" WXGA TFT LCD Panel - dlc,dlc1010gig # Emerging Display Technology Corp. 3.5" QVGA TFT LCD panel @@ -232,6 +236,8 @@ properties: - nec,nl12880bc20-05 # NEC LCD Technologies,Ltd. WQVGA TFT LCD panel - nec,nl4827hc19-05b + # NEC LCD Technologies,Ltd. VGA TFT LCD panel + - nec,nl6448bc33-70c # Netron-DY E231732 7.0" WSVGA TFT LCD panel - netron-dy,e231732 # Newhaven Display International 480 x 272 TFT LCD panel @@ -304,6 +310,8 @@ properties: - shelly,sca07010-bfn-lnn # Starry KR070PE2T 7" WVGA TFT LCD panel - starry,kr070pe2t + # Startek KD070HDFLD092 7" WSVGA TFT LCD panel + - startek,kd070hdfld092 # Startek KD070WVFPA043-C069A 7" TFT LCD panel - startek,kd070wvfpa # Team Source Display Technology TST043015CMHX 4.3" WQVGA TFT LCD panel @@ -341,10 +349,38 @@ properties: - vivax,tpc9150-panel # VXT 800x480 color TFT LCD panel - vxt,vl050-8048nt-c01 + # Waveshare 10.1" WXGA (1280x800) LCD panel + - waveshare,10.1inch-c-panel + # Waveshare 11.9" (320x1480) LCD panel + - waveshare,11.9inch-panel # Waveshare 13.3" FHD (1920x1080) LCD panel - waveshare,13.3inch-panel + # Waveshare 2.8" VGA (480x640) LCD panel + - waveshare,2.8inch-panel + # Waveshare 3.4" (800x800) LCD panel + - waveshare,3.4inch-c-panel + # Waveshare 4.0" WVGA (480x800) LCD panel + - waveshare,4.0inch-panel + # Waveshare 4.0" (720x720) LCD panel + - waveshare,4.0inch-c-panel + # Waveshare 5.0" WSVGA (1024x600) LCD panel + - waveshare,5.0inch-c-panel + # Waveshare 5.0" HD 720p (720x1280) LCD panel + - waveshare,5.0inch-d-panel + # Waveshare 6.25" (720x1560) LCD panel + - waveshare,6.25inch-panel # Waveshare 7.0" WSVGA (1024x600) LCD panel - waveshare,7.0inch-c-panel + # Waveshare 7.0" WXGA (1280x800) LCD panel + - waveshare,7.0inch-e-panel + # Waveshare 7.0" HD 720p (720x1280) LCD panel + - waveshare,7.0inch-h-panel + # Waveshare 7.9" (400x1280) LCD panel + - waveshare,7.9inch-panel + # Waveshare 8.0" WXGA (1280x800) LCD panel + - waveshare,8.0inch-c-panel + # Waveshare 8.8" (480x1920) LCD panel + - waveshare,8.8inch-panel # Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel - winstar,wf35ltiacd # Yes Optoelectronics YTC700TLAG-05-201C 7" TFT LCD panel diff --git a/Documentation/devicetree/bindings/display/panel/samsung,sofef01-m.yaml b/Documentation/devicetree/bindings/display/panel/samsung,sofef01-m.yaml new file mode 100644 index 00000000000000..bccc667aa072e8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/samsung,sofef01-m.yaml @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,sofef01-m.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung SOFEF01-M DDI for 1080x2520@60Hz 6.0"/6.1" OLED DSI panels + +maintainers: + - Marijn Suijten + +description: | + Samsung SOFEF01-M Display-Driver-IC found in multiple Sony smartphones, paired with + the following panel: + - Sony Xperia 5 (kumano bahamut): amb609tc01 + - Sony Xperia 10 II (seine pdx201): ams597ut01 + - Sony Xperia 10 III (lena pdx213): ams597ut04 + - Sony Xperia 10 IV (murray pdx225): ams597ut05 + - Sony Xperia 10 V (zambezi pdx235): ams605dk01 + - Sony Xperia 10 VI (columbia pdx246): ams605dk01 + + The assembly features a Samsung touchscreen compatible with + samsung,s6sy761. + +properties: + compatible: + enum: + - samsung,sofef01-m-amb609tc01 # 6.1" + - samsung,sofef01-m-ams597ut01 # 6.0" + - samsung,sofef01-m-ams597ut04 # 6.0" + - samsung,sofef01-m-ams597ut05 # 6.0" + - samsung,sofef01-m-ams605dk01 # 6.1" + + port: true + + reg: + maxItems: 1 + description: DSI virtual channel + + reset-gpios: true + + vci-supply: + description: DisplayIC Operation supply (3.0V) + + vddio-supply: + description: I/O voltage supply (1.8V) + +required: + - compatible + - port + - reg + - reset-gpios + - vddio-supply + +allOf: + - $ref: panel-common.yaml# + - if: + properties: + compatible: + contains: + const: samsung,sofef01-m-amb609tc01 + then: + required: + - vci-supply + else: + properties: + vci-supply: false + +unevaluatedProperties: false + +examples: + - | + #include + + dsi { + #address-cells = <1>; + #size-cells = <0>; + panel@0 { + compatible = "samsung,sofef01-m-amb609tc01"; + reg = <0>; + + reset-gpios = <&tlmm 6 GPIO_ACTIVE_LOW>; + + vci-supply = <&vreg_l17a_3p0>; + vddio-supply = <&vreg_l14a_1p8>; + + port { + endpoint { + remote-endpoint = <&dsi0_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml index 2cc66dcef870a1..7c84a9ecc7a703 100644 --- a/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml +++ b/Documentation/devicetree/bindings/display/renesas,rzg2l-du.yaml @@ -21,6 +21,7 @@ properties: - renesas,r9a07g043u-du # RZ/G2UL - renesas,r9a07g044-du # RZ/G2{L,LC} - renesas,r9a09g057-du # RZ/V2H(P) + - renesas,r9a09g077-du # RZ/T2H - items: - enum: - renesas,r9a07g054-du # RZ/V2L @@ -28,6 +29,9 @@ properties: - items: - const: renesas,r9a09g056-du # RZ/V2N - const: renesas,r9a09g057-du # RZ/V2H(P) fallback + - items: + - const: renesas,r9a09g087-du # RZ/N2H + - const: renesas,r9a09g077-du # RZ/T2H fallback reg: maxItems: 1 @@ -83,7 +87,6 @@ required: - interrupts - clocks - clock-names - - resets - power-domains - ports - renesas,vsps @@ -95,13 +98,16 @@ allOf: properties: compatible: contains: - const: renesas,r9a07g043u-du + enum: + - renesas,r9a07g043u-du + - renesas,r9a09g077-du then: properties: ports: properties: port@0: description: DPI + port@1: false required: - port@0 @@ -137,6 +143,17 @@ allOf: required: - port@0 + - if: + properties: + compatible: + contains: + const: renesas,r9a09g077-du + then: + properties: + resets: false + else: + required: + - resets examples: # RZ/G2L DU diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml index 1a33128e77f580..195f665970bf99 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3399-cdn-dp.yaml @@ -41,7 +41,9 @@ properties: minItems: 1 items: - description: Extcon device providing the cable state for DP PHY device 0 + maxItems: 1 - description: Extcon device providing the cable state for DP PHY device 1 + maxItems: 1 description: List of phandle to the extcon device providing the cable state for the DP PHY. diff --git a/Documentation/devicetree/bindings/dma/fsl,edma.yaml b/Documentation/devicetree/bindings/dma/fsl,edma.yaml index fa4248e2f1b9ce..f609038e35ae18 100644 --- a/Documentation/devicetree/bindings/dma/fsl,edma.yaml +++ b/Documentation/devicetree/bindings/dma/fsl,edma.yaml @@ -12,6 +12,9 @@ description: | DMAMUX0 and DMAMUX1, specific DMA request source can only be multiplexed by any channel of certain group, DMAMUX0 or DMAMUX1, but not both. + This binding has an inverted dma-channel-mask definition compared to + the common DMA binding for historical reasons. + maintainers: - Peng Fan @@ -95,6 +98,12 @@ properties: eDMA are implemented in big endian mode, otherwise in little mode. type: boolean + dma-channel-mask: + description: | + Bitmask of available DMA channels (inverted definition). + Bit semantics: 0 means channel available, 1 means channel unavailable + default: 0 + required: - "#dma-cells" - compatible diff --git a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml index 0dabe9bbb219ba..bc093c783d9866 100644 --- a/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml +++ b/Documentation/devicetree/bindings/dma/nvidia,tegra186-gpc-dma.yaml @@ -14,17 +14,16 @@ description: | maintainers: - Jon Hunter - Rajesh Gumasta - -allOf: - - $ref: dma-controller.yaml# + - Akhil R properties: compatible: oneOf: - - const: nvidia,tegra186-gpcdma + - enum: + - nvidia,tegra264-gpcdma + - nvidia,tegra186-gpcdma - items: - enum: - - nvidia,tegra264-gpcdma - nvidia,tegra234-gpcdma - nvidia,tegra194-gpcdma - const: nvidia,tegra186-gpcdma @@ -51,6 +50,14 @@ properties: iommus: maxItems: 1 + iommu-map: + description: + Maps DMA channel numbers to IOMMU stream IDs. A single entry can map all + channels when stream IDs are contiguous. In systems where the channels or + stream IDs are not contiguous, multiple entries may be needed. + minItems: 1 + maxItems: 32 + dma-coherent: true dma-channel-mask: @@ -60,12 +67,23 @@ required: - compatible - reg - interrupts - - resets - - reset-names - "#dma-cells" - iommus - dma-channel-mask +allOf: + - $ref: dma-controller.yaml# + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra186-gpcdma + then: + required: + - resets + - reset-names + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml index 6493a6968bb4b9..0923fb189ada9e 100644 --- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml @@ -23,6 +23,8 @@ properties: - qcom,bam-v1.4.0 # MSM8916, SDM630 - qcom,bam-v1.7.0 + # Kaanapali + - qcom,bam-v2.0.0 - items: - enum: # SDM845, SM6115, SM8150, SM8250 and QCM2290 @@ -118,4 +120,23 @@ examples: #dma-cells = <1>; qcom,ee = <0>; }; + - | + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + dma-controller@1dc4000 { + compatible = "qcom,bam-v2.0.0"; + reg = <0x0 0x01dc4000 0x0 0x22000>; + interrupts = ; + #dma-cells = <1>; + iommus = <&apps_smmu 0xc0 0>, <&apps_smmu 0xc1 0>; + qcom,ee = <0>; + qcom,num-ees = <4>; + num-channels = <20>; + qcom,controlled-remotely; + }; + }; ... diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml index fde1df035ad12b..54dca623223d51 100644 --- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml @@ -24,7 +24,9 @@ properties: - qcom,sm6350-gpi-dma - items: - enum: + - qcom,eliza-gpi-dma - qcom,glymur-gpi-dma + - qcom,hawi-gpi-dma - qcom,kaanapali-gpi-dma - qcom,milos-gpi-dma - qcom,qcm2290-gpi-dma @@ -35,6 +37,7 @@ properties: - qcom,sc7280-gpi-dma - qcom,sc8280xp-gpi-dma - qcom,sdx75-gpi-dma + - qcom,shikra-gpi-dma - qcom,sm6115-gpi-dma - qcom,sm6375-gpi-dma - qcom,sm8350-gpi-dma diff --git a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml index 804514732dbe65..0a30a455b0ee54 100644 --- a/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml +++ b/Documentation/devicetree/bindings/dma/snps,dw-axi-dmac.yaml @@ -21,11 +21,12 @@ properties: - enum: - snps,axi-dma-1.01a - intel,kmb-axi-dma - - sophgo,cv1800b-axi-dma - starfive,jh7110-axi-dma - starfive,jh8100-axi-dma - items: - - const: altr,agilex5-axi-dma + - enum: + - altr,agilex5-axi-dma + - sophgo,cv1800b-axi-dma - const: snps,axi-dma-1.01a reg: diff --git a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml index ec06235baf5ca3..62ce6d81526b44 100644 --- a/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml +++ b/Documentation/devicetree/bindings/dma/spacemit,k1-pdma.yaml @@ -14,7 +14,9 @@ allOf: properties: compatible: - const: spacemit,k1-pdma + enum: + - spacemit,k1-pdma + - spacemit,k3-pdma reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml index 607da11e7baa93..d8f92838f4c9d5 100644 --- a/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml +++ b/Documentation/devicetree/bindings/dma/stericsson,dma40.yaml @@ -136,13 +136,9 @@ properties: maxItems: 1 sram: - $ref: /schemas/types.yaml#/definitions/phandle-array - description: A phandle array with inner size 1 (no arg cells). - First phandle is the LCPA (Logical Channel Parameter Address) memory. - Second phandle is the LCLA (Logical Channel Link base Address) memory. - maxItems: 2 items: - maxItems: 1 + - description: LCPA (Logical Channel Parameter Address) memory. + - description: LCLA (Logical Channel Link base Address) memory. memcpy-channels: $ref: /schemas/types.yaml#/definitions/uint32-array diff --git a/Documentation/devicetree/bindings/embedded-controller/microsoft,surface-rt-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/microsoft,surface-rt-ec.yaml new file mode 100644 index 00000000000000..0fee574a30151f --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/microsoft,surface-rt-ec.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/microsoft,surface-rt-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microsoft Surface RT fuel gauge and charger EC + +maintainers: + - Jonas Schwöbel + - Svyatoslav Ryhel + +description: + An Embedded Controller used in Microsoft Surface RT for monitoring + battery properties and charger status. + +allOf: + - $ref: /schemas/power/supply/power-supply.yaml# + +properties: + compatible: + const: microsoft,surface-rt-ec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + enable-gpios: + maxItems: 1 + + monitored-battery: true + +required: + - compatible + - reg + - interrupts + - enable-gpios + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@a { + compatible = "microsoft,surface-rt-ec"; + reg = <0x0a>; + + interrupt-parent = <&gpio>; + interrupts = <74 IRQ_TYPE_EDGE_RISING>; + + enable-gpios = <&gpio 88 GPIO_ACTIVE_HIGH>; + monitored-battery = <&battery>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml new file mode 100644 index 00000000000000..ac5a08f8f76dfd --- /dev/null +++ b/Documentation/devicetree/bindings/embedded-controller/qcom,hamoa-crd-ec.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/embedded-controller/qcom,hamoa-crd-ec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Hamoa Embedded Controller + +maintainers: + - Sibi Sankar + - Anvesh Jain P + +description: + Qualcomm Snapdragon based Hamoa/Purwa and Glymur reference devices have an + EC running on different MCU chips. The EC handles things like fan control, + temperature sensors, access to EC internal state changes. + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,glymur-crd-ec + - qcom,hamoa-iot-evk-ec + - const: qcom,hamoa-crd-ec + - enum: + - qcom,hamoa-crd-ec + + reg: + const: 0x76 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + i2c { + #address-cells = <1>; + #size-cells = <0>; + + embedded-controller@76 { + compatible = "qcom,hamoa-crd-ec"; + reg = <0x76>; + + interrupts-extended = <&tlmm 66 IRQ_TYPE_LEVEL_HIGH>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/extcon/samsung,s2mu005-muic.yaml b/Documentation/devicetree/bindings/extcon/samsung,s2mu005-muic.yaml new file mode 100644 index 00000000000000..0a320d5e2a352e --- /dev/null +++ b/Documentation/devicetree/bindings/extcon/samsung,s2mu005-muic.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/extcon/samsung,s2mu005-muic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MUIC Device for Samsung S2M series PMICs + +maintainers: + - Kaustabh Chakraborty + +description: | + The Samsung S2M series PMIC MUIC device is a USB port accessory + detector. It reports multiple states depending on the ID-GND + resistance measured by an internal ADC. + + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +properties: + compatible: + enum: + - samsung,s2mu005-muic + + connector: + $ref: /schemas/connector/usb-connector.yaml# + + port: + $ref: /schemas/graph.yaml#/properties/port + description: Port connecting to the USB controller or PHY. + +required: + - compatible + - connector + - port + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index 7918d31f58b4ae..25f62bacbc9195 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -25,6 +25,7 @@ properties: - qcom,scm-apq8084 - qcom,scm-eliza - qcom,scm-glymur + - qcom,scm-hawi - qcom,scm-ipq4019 - qcom,scm-ipq5018 - qcom,scm-ipq5210 @@ -49,6 +50,7 @@ properties: - qcom,scm-msm8994 - qcom,scm-msm8996 - qcom,scm-msm8998 + - qcom,scm-nord - qcom,scm-qcm2290 - qcom,scm-qcs615 - qcom,scm-qcs8300 @@ -208,6 +210,7 @@ allOf: contains: enum: - qcom,scm-eliza + - qcom,scm-hawi - qcom,scm-kaanapali - qcom,scm-milos - qcom,scm-sm8450 diff --git a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt b/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt deleted file mode 100644 index 52a294cf273053..00000000000000 --- a/Documentation/devicetree/bindings/fpga/altera-pr-ip.txt +++ /dev/null @@ -1,12 +0,0 @@ -Altera Arria10 Partial Reconfiguration IP - -Required properties: -- compatible : should contain "altr,a10-pr-ip" -- reg : base address and size for memory mapped io. - -Example: - - fpga_mgr: fpga-mgr@ff20c000 { - compatible = "altr,a10-pr-ip"; - reg = <0xff20c000 0x10>; - }; diff --git a/Documentation/devicetree/bindings/fpga/altera-socfpga-fpga-mgr.txt b/Documentation/devicetree/bindings/fpga/altera-socfpga-fpga-mgr.txt deleted file mode 100644 index d52f3340414d05..00000000000000 --- a/Documentation/devicetree/bindings/fpga/altera-socfpga-fpga-mgr.txt +++ /dev/null @@ -1,17 +0,0 @@ -Altera SOCFPGA FPGA Manager - -Required properties: -- compatible : should contain "altr,socfpga-fpga-mgr" -- reg : base address and size for memory mapped io. - - The first index is for FPGA manager register access. - - The second index is for writing FPGA configuration data. -- interrupts : interrupt for the FPGA Manager device. - -Example: - - hps_0_fpgamgr: fpgamgr@ff706000 { - compatible = "altr,socfpga-fpga-mgr"; - reg = <0xFF706000 0x1000 - 0xFFB90000 0x1000>; - interrupts = <0 175 4>; - }; diff --git a/Documentation/devicetree/bindings/fpga/altr,a10-pr-ip.yaml b/Documentation/devicetree/bindings/fpga/altr,a10-pr-ip.yaml new file mode 100644 index 00000000000000..1f4df40308bd0d --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altr,a10-pr-ip.yaml @@ -0,0 +1,34 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/altr,a10-pr-ip.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera Arria10 Partial Reconfiguration IP + +maintainers: + - Matthew Gerlach + +description: + The Altera Arria 10 Partial Reconfiguration IP core allows the host + processor to perform partial reconfiguration of the FPGA fabric. + +properties: + compatible: + const: altr,a10-pr-ip + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + fpga-mgr@ff20c000 { + compatible = "altr,a10-pr-ip"; + reg = <0xff20c000 0x10>; + }; diff --git a/Documentation/devicetree/bindings/fpga/altr,socfpga-fpga-mgr.yaml b/Documentation/devicetree/bindings/fpga/altr,socfpga-fpga-mgr.yaml new file mode 100644 index 00000000000000..9bcc1200d61d01 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/altr,socfpga-fpga-mgr.yaml @@ -0,0 +1,38 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/altr,socfpga-fpga-mgr.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Altera SOCFPGA FPGA Manager + +maintainers: + - Steffen Trumtrar + +properties: + compatible: + const: altr,socfpga-fpga-mgr + + reg: + items: + - description: FPGA manager register access + - description: Writing FPGA configuration data + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + fpgamgr@ff706000 { + compatible = "altr,socfpga-fpga-mgr"; + reg = <0xff706000 0x1000>, + <0xffb90000 0x1000>; + interrupts = <0 175 4>; + }; diff --git a/Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml b/Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml new file mode 100644 index 00000000000000..7c7444ff9c3ad4 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/efinix,trion-config.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/efinix,trion-config.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Efinix SPI FPGA Manager + +maintainers: + - Ian Dannapel + +description: | + Efinix FPGAs (Trion, Topaz, and Titanium families) support loading bitstreams + through "SPI Passive Mode". + Additional pin hogs for bus width configuration should be set + elsewhere, if necessary. + + References: + - https://www.efinixinc.com/docs/an006-configuring-trion-fpgas-v6.3.pdf + - https://www.efinixinc.com/docs/an033-configuring-titanium-fpgas-v2.8.pdf + - https://www.efinixinc.com/docs/an061-configuring-topaz-fpgas-v1.1.pdf + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - efinix,titanium-config + - efinix,topaz-config + - const: efinix,trion-config + - const: efinix,trion-config + + spi-cpha: true + + spi-cpol: true + + spi-max-frequency: + maximum: 25000000 + + reg: + maxItems: 1 + + reset-gpios: + description: + reset and re-configuration trigger pin (low active) + maxItems: 1 + + cdone-gpios: + description: + optional configuration done status pin (high active) + maxItems: 1 + +required: + - compatible + - reg + - reset-gpios + - spi-cpha + - spi-cpol + +unevaluatedProperties: false + +examples: + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + fpga-mgr@0 { + compatible = "efinix,trion-config"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-cpha; + spi-cpol; + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + fpga-mgr@0 { + compatible = "efinix,titanium-config", "efinix,trion-config"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-cpha; + spi-cpol; + reset-gpios = <&gpio4 17 GPIO_ACTIVE_LOW>; + cdone-gpios = <&gpio0 9 GPIO_ACTIVE_HIGH>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/fpga/technologic,ts7300-fpga.yaml b/Documentation/devicetree/bindings/fpga/technologic,ts7300-fpga.yaml new file mode 100644 index 00000000000000..c93e3a1a135bb8 --- /dev/null +++ b/Documentation/devicetree/bindings/fpga/technologic,ts7300-fpga.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fpga/technologic,ts7300-fpga.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Technologic Systems TS-7300 FPGA Manager + +maintainers: + - Florian Fainelli + +description: + FPGA manager for the Altera Cyclone II FPGA on Technologic Systems + TS-7300 board. The FPGA is programmed via the memory-mapped interface + implemented in the CPLD. + +properties: + compatible: + const: technologic,ts7300-fpga + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + fpga-mgr@13c00000 { + compatible = "technologic,ts7300-fpga"; + reg = <0x13c00000 0x2>; + }; +... diff --git a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml index 23410aeca30000..451538df63f728 100644 --- a/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml +++ b/Documentation/devicetree/bindings/gpio/fairchild,74hc595.yaml @@ -45,6 +45,18 @@ properties: $ref: /schemas/types.yaml#/definitions/uint32 description: Number of daisy-chained shift registers + lines-initial-states: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bitmask that specifies the initial state of each output line, written + by the driver before the gpiochip is registered. Bit N corresponds to + GPIO line N, following the convention already documented for + nxp,pcf8575. Because the 74HC595/74LVC594 family is push-pull output + only, a bit set to zero drives the line low and a bit set to one + drives it high. The bitmask covers up to 32 lines (four cascaded + registers); outputs beyond that come up zeroed. When the property is + absent all outputs come up low, preserving the previous behaviour. + enable-gpios: description: GPIO connected to the OE (Output Enable) pin. maxItems: 1 @@ -79,6 +91,7 @@ examples: gpio-controller; #gpio-cells = <2>; registers-number = <4>; + lines-initial-states = <0xffff0000>; spi-max-frequency = <100000>; }; }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml index 5e2496379a3c86..de24bb361e9f64 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-zynq.yaml @@ -12,10 +12,11 @@ maintainers: properties: compatible: enum: + - xlnx,eio-gpio-1.0 + - xlnx,pmc-gpio-1.0 + - xlnx,versal-gpio-1.0 - xlnx,zynq-gpio-1.0 - xlnx,zynqmp-gpio-1.0 - - xlnx,versal-gpio-1.0 - - xlnx,pmc-gpio-1.0 reg: maxItems: 1 @@ -30,7 +31,7 @@ properties: gpio-line-names: description: strings describing the names of each gpio line - minItems: 58 + minItems: 52 maxItems: 174 interrupt-controller: true @@ -89,6 +90,16 @@ allOf: minItems: 116 maxItems: 116 + - if: + properties: + compatible: + enum: + - xlnx,eio-gpio-1.0 + then: + properties: + gpio-line-names: + maxItems: 52 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml index 17748dd1015d70..adeb3b3a2902d8 100644 --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml @@ -85,6 +85,8 @@ properties: - nvidia,tegra194-gpio-aon - nvidia,tegra234-gpio - nvidia,tegra234-gpio-aon + - nvidia,tegra238-gpio + - nvidia,tegra238-gpio-aon - nvidia,tegra256-gpio - nvidia,tegra264-gpio - nvidia,tegra264-gpio-uphy @@ -163,6 +165,7 @@ allOf: - nvidia,tegra186-gpio - nvidia,tegra194-gpio - nvidia,tegra234-gpio + - nvidia,tegra238-gpio - nvidia,tegra256-gpio - nvidia,tegra264-gpio - nvidia,tegra264-gpio-uphy @@ -180,6 +183,7 @@ allOf: - nvidia,tegra186-gpio-aon - nvidia,tegra194-gpio-aon - nvidia,tegra234-gpio-aon + - nvidia,tegra238-gpio-aon - nvidia,tegra264-gpio-aon then: properties: @@ -192,6 +196,8 @@ allOf: compatible: contains: enum: + - nvidia,tegra238-gpio + - nvidia,tegra238-gpio-aon - nvidia,tegra264-gpio - nvidia,tegra264-gpio-uphy - nvidia,tegra264-gpio-aon diff --git a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml index bba6f5b6606fdf..55069533f6d912 100644 --- a/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/snps,dw-apb-gpio.yaml @@ -95,6 +95,12 @@ patternProperties: '#interrupt-cells': const: 2 + patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml b/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml new file mode 100644 index 00000000000000..091e1fffcd4767 --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/waveshare,dsi-touch-gpio.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/waveshare,dsi-touch-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Waveshare GPIO controller on DSI TOUCH panels + +maintainers: + - Dmitry Baryshkov + +description: + Waveshare DSI TOUCH panel kits contain separate GPIO controller for toggling + power supplies and panel / touchscreen resets. + +properties: + compatible: + const: waveshare,dsi-touch-gpio + + reg: + maxItems: 1 + + gpio-controller: true + + '#gpio-cells': + const: 2 + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + wsgpio: gpio@45 { + compatible = "waveshare,dsi-touch-gpio"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + panel_avdd: regulator-panel-avdd { + compatible = "regulator-fixed"; + regulator-name = "panel-avdd"; + gpios = <&wsgpio 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + panel_iovcc: regulator-panel-iovcc { + compatible = "regulator-fixed"; + regulator-name = "panel-iovcc"; + gpios = <&wsgpio 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + panel_vcc: regulator-panel-vcc { + compatible = "regulator-fixed"; + regulator-name = "panel-vcc"; + gpios = <&wsgpio 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; +... diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml index db49b8ff8c7486..9db9f84ad964b8 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-bifrost.yaml @@ -26,6 +26,7 @@ properties: - realtek,rtd1619-mali - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a08g046-mali - renesas,r9a09g047-mali - renesas,r9a09g056-mali - renesas,r9a09g057-mali @@ -150,6 +151,7 @@ allOf: enum: - renesas,r9a07g044-mali - renesas,r9a07g054-mali + - renesas,r9a08g046-mali - renesas,r9a09g047-mali - renesas,r9a09g056-mali - renesas,r9a09g057-mali diff --git a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml index dada28b47ea079..2900224aac743f 100644 --- a/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml +++ b/Documentation/devicetree/bindings/hwinfo/ti,k3-socinfo.yaml @@ -15,6 +15,9 @@ description: | represented by CTRLMMR_xxx_JTAGID register which contains information about SoC id and revision. + On some SoCs like AM62P, the silicon revision is determined by reading + alternative registers via NVMEM cells. + properties: $nodename: pattern: "^chipid@[0-9a-f]+$" @@ -26,6 +29,14 @@ properties: reg: maxItems: 1 + nvmem-cells: + items: + - description: Alternate silicon revision register + + nvmem-cell-names: + items: + - const: gpsw1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml b/Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml new file mode 100644 index 00000000000000..05e2132ad4d862 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/adi,ltc4283.yaml @@ -0,0 +1,272 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/adi,ltc4283.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: LTC4283 Negative Voltage Hot Swap Controller + +maintainers: + - Nuno Sá + +description: | + The LTC4283 negative voltage hot swap controller drives an external N-channel + MOSFET to allow a board to be safely inserted and removed from a live + backplane. + + https://www.analog.com/media/en/technical-documentation/data-sheets/ltc4283.pdf + +properties: + compatible: + enum: + - adi,ltc4283 + + reg: + maxItems: 1 + + adi,rsense-nano-ohms: + description: Value of the sense resistor. + + adi,current-limit-sense-microvolt: + description: + The current limit sense voltage of the chip is adjustable between + 15mV and 30mV in 1mV steps. This effectively limits the current + on the load. + minimum: 15000 + maximum: 30000 + default: 15000 + + adi,current-limit-foldback-factor: + description: + Specifies the foldback factor for the current limit. The current limit + can be reduced (folded back) to one of four preset levels. The value + represents the percentage of the current limit sense voltage to use + during foldback. A value of 100 means no foldback. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [10, 20, 50, 100] + default: 100 + + adi,cooling-delay-ms: + description: + Cooling time to apply after an overcurrent fault, FET bad or + external fault. + enum: [512, 1002, 2005, 4100, 8190, 16400, 32800, 65600] + default: 512 + + adi,fet-bad-timer-delay-ms: + description: + FET bad timer delay. After a FET bad status condition is detected, + this timer is started. If the condition persists for the + specified time, the FET is turned off and a fault is logged. + enum: [256, 512, 1002, 2005] + default: 256 + + adi,power-good-reset-on-fet: + description: + If set, resets the power good status when the MOSFET is turned off. + Otherwise, it resets when a low output voltage is detected. + type: boolean + + adi,fet-turn-off-disable: + description: + If set, the MOSFET is not turned off when a FET fault is detected. + type: boolean + + adi,tmr-pull-down-disable: + description: Disables 2uA pull-down current on the TMR pin. + type: boolean + + adi,dvdt-inrush-control-disable: + description: + Disables dV/dt inrush control during startup. In dV/dt mode, the inrush + current is limited by controlling a constant output voltage ramp rate. + When disabled, the inrush control mechanism is active current limiting. + type: boolean + + adi,fault-log-enable: + description: + If set, enables logging fault registers and ADC data into EEPROM upon a + fault. + type: boolean + + adi,vpower-drns-enable: + description: + If set, enables the attenuated MOSFET drain voltage to be monitored. This + effectively means that the MOSFET power is monitored. If not set, the + attenuated input voltage (and hence input power) is monitored. + type: boolean + + adi,external-fault-fet-off-enable: + description: Turns MOSFET off following an external fault. + type: boolean + + adi,undervoltage-retry-disable: + description: Do not retry to turn on the MOSFET after an undervoltage fault. + type: boolean + + adi,overvoltage-retry-disable: + description: Do not retry to turn on the MOSFET after an overvoltage fault. + type: boolean + + adi,external-fault-retry-enable: + description: Retry to turn on the MOSFET after an external fault. + type: boolean + + adi,overcurrent-retries: + description: Configures auto-retry following an Overcurrent fault. + $ref: /schemas/types.yaml#/definitions/string + enum: [latch-off, "1", "7", unlimited] + default: latch-off + + adi,fet-bad-retries: + description: + Configures auto-retry following a FET bad fault and a consequent MOSFET + turn off. + $ref: /schemas/types.yaml#/definitions/string + enum: [latch-off, "1", "7", unlimited] + default: latch-off + + adi,pgio1-func: + description: Configures the function of the PGIO1 pin. + $ref: /schemas/types.yaml#/definitions/string + enum: [inverted_power_good, power_good, gpio] + default: inverted_power_good + + adi,pgio2-func: + description: Configures the function of the PGIO2 pin. + $ref: /schemas/types.yaml#/definitions/string + enum: [inverted_power_good, power_good, gpio, active_current_limiting] + default: inverted_power_good + + adi,pgio3-func: + description: Configures the function of the PGIO3 pin. + $ref: /schemas/types.yaml#/definitions/string + enum: [inverted_power_good_input, power_good_input, gpio] + default: inverted_power_good_input + + adi,pgio4-func: + description: Configures the function of the PGIO4 pin. + $ref: /schemas/types.yaml#/definitions/string + enum: [inverted_external_fault, external_fault, gpio] + default: inverted_external_fault + + adi,gpio-on-adio1: + description: If set, the ADIO1 pin is used as a GPIO. + type: boolean + + adi,gpio-on-adio2: + description: If set, the ADIO2 pin is used as a GPIO. + type: boolean + + adi,gpio-on-adio3: + description: If set, the ADIO3 pin is used as a GPIO. + type: boolean + + adi,gpio-on-adio4: + description: If set, the ADIO4 pin is used as a GPIO. + type: boolean + + gpio-controller: true + + '#gpio-cells': + const: 2 + +dependencies: + adi,gpio-on-adio1: + - gpio-controller + - '#gpio-cells' + adi,gpio-on-adio2: + - gpio-controller + - '#gpio-cells' + adi,gpio-on-adio3: + - gpio-controller + - '#gpio-cells' + adi,gpio-on-adio4: + - gpio-controller + - '#gpio-cells' + adi,external-fault-retry-enable: + - adi,pgio4-func + adi,external-fault-fet-off-enable: + - adi,pgio4-func + +required: + - compatible + - reg + - adi,rsense-nano-ohms + +allOf: + - if: + properties: + adi,pgio1-func: + const: gpio + required: + - adi,pgio1-func + then: + required: + - gpio-controller + - '#gpio-cells' + + - if: + properties: + adi,pgio2-func: + const: gpio + required: + - adi,pgio2-func + then: + required: + - gpio-controller + - '#gpio-cells' + + - if: + properties: + adi,pgio3-func: + const: gpio + required: + - adi,pgio3-func + then: + required: + - gpio-controller + - '#gpio-cells' + + - if: + properties: + adi,pgio4-func: + const: gpio + required: + - adi,pgio4-func + then: + properties: + adi,external-fault-retry-enable: false + adi,external-fault-fet-off-enable: false + required: + - gpio-controller + - '#gpio-cells' + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + swap-controller@15 { + compatible = "adi,ltc4283"; + reg = <0x15>; + + adi,rsense-nano-ohms = <500>; + adi,current-limit-sense-microvolt = <25000>; + adi,current-limit-foldback-factor = <10>; + adi,cooling-delay-ms = <8190>; + adi,fet-bad-timer-delay-ms = <512>; + + adi,external-fault-fet-off-enable; + adi,pgio4-func = "external_fault"; + + adi,gpio-on-adio1; + adi,pgio1-func = "gpio"; + gpio-controller; + #gpio-cells = <2>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/hwmon/apple,smc-hwmon.yaml b/Documentation/devicetree/bindings/hwmon/apple,smc-hwmon.yaml new file mode 100644 index 00000000000000..64149ef4cc59c5 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/apple,smc-hwmon.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/apple,smc-hwmon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Apple SMC Hardware Monitoring + +description: + Apple's System Management Controller (SMC) exposes a vast array of + hardware monitoring sensors, including temperature probes, current and + voltage sense, power meters, and fan speeds. It also provides endpoints + to manually control the speed of each fan individually. Each Apple + Silicon device exposes a different set of endpoints via SMC keys. This + is true even when two machines share an SoC. The CPU core temperature + sensor keys on an M1 Mac mini are different to those on an M1 MacBook + Pro, for example. + +maintainers: + - James Calligeros + +$defs: + sensor: + type: object + + properties: + apple,key-id: + $ref: /schemas/types.yaml#/definitions/string + pattern: "^[A-Za-z0-9]{4}$" + description: The SMC FourCC key of the desired sensor. + Must match the node's suffix. + + label: + description: Human-readable name for the sensor + + required: + - apple,key-id + +properties: + compatible: + const: apple,smc-hwmon + +patternProperties: + "^current-[A-Za-z0-9]{4}$": + $ref: "#/$defs/sensor" + unevaluatedProperties: false + + "^fan-[A-Za-z0-9]{4}$": + $ref: "#/$defs/sensor" + unevaluatedProperties: false + + properties: + apple,fan-minimum: + $ref: /schemas/types.yaml#/definitions/string + pattern: "^[A-Za-z0-9]{4}$" + description: SMC key containing the fan's minimum speed + + apple,fan-maximum: + $ref: /schemas/types.yaml#/definitions/string + pattern: "^[A-Za-z0-9]{4}$" + description: SMC key containing the fan's maximum speed + + apple,fan-target: + $ref: /schemas/types.yaml#/definitions/string + pattern: "^[A-Za-z0-9]{4}$" + description: Writeable endpoint for setting desired fan speed + + apple,fan-mode: + $ref: /schemas/types.yaml#/definitions/string + pattern: "^[A-Za-z0-9]{4}$" + description: Writeable key to enable/disable manual fan control + + "^power-[A-Za-z0-9]{4}$": + $ref: "#/$defs/sensor" + unevaluatedProperties: false + + "^temperature-[A-Za-z0-9]{4}$": + $ref: "#/$defs/sensor" + unevaluatedProperties: false + + "^voltage-[A-Za-z0-9]{4}$": + $ref: "#/$defs/sensor" + unevaluatedProperties: false + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/hwmon/lm75.yaml b/Documentation/devicetree/bindings/hwmon/lm75.yaml index 0b9fda81e3ec50..b48bf3fd721fe9 100644 --- a/Documentation/devicetree/bindings/hwmon/lm75.yaml +++ b/Documentation/devicetree/bindings/hwmon/lm75.yaml @@ -54,6 +54,13 @@ properties: interrupts: maxItems: 1 + ti,alert-polarity-active-high: + description: Alert pin is asserted based on the value of alert polarity + bit of configuration register. Default value is normal (0 which maps to + active-low). The other value is inverted (1 which maps to active-high). + Specify this property to set the alert polarity to active-high. + $ref: /schemas/types.yaml#/definitions/flag + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/hwmon/microchip,emc1812.yaml b/Documentation/devicetree/bindings/hwmon/microchip,emc1812.yaml new file mode 100644 index 00000000000000..1a273621db826d --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/microchip,emc1812.yaml @@ -0,0 +1,193 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/microchip,emc1812.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip EMC1812/13/14/15/33 multichannel temperature sensor + +maintainers: + - Marius Cristea + +description: | + The Microchip EMC1812/13/14/15/33 is a high-accuracy 2-wire multichannel + low-voltage remote diode temperature monitor. + + The datasheet can be found here: + https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/EMC1812-3-4-5-33-Data-Sheet-DS20005751.pdf + + EMC1812 has one external remote temperature monitoring channel + EMC1813 has two external remote temperature monitoring channels + EMC1814 has three external remote temperature monitoring channels and + channels 2 and 3 support anti parallel diode + EMC1815 has four external remote temperature monitoring channels and + channels 1/2 and 3/4 support anti parallel diode + EMC1833 has two external remote temperature monitoring channels and + channels 1 and 2 support anti parallel diode + +properties: + compatible: + enum: + - microchip,emc1812 + - microchip,emc1813 + - microchip,emc1814 + - microchip,emc1815 + - microchip,emc1833 + + reg: + maxItems: 1 + + interrupts: + items: + - description: alert-therm2 asserts when the ALERT limit is exceeded. + - description: therm-addr asserts when the THERM limit is exceeded. + minItems: 1 + + interrupt-names: + items: + - const: alert-therm2 + - const: therm-addr + minItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + microchip,enable-anti-parallel: + description: + Enable anti-parallel diode mode operation. EMC1814, EMC1815 and EMC1833 + support reading two external diodes in anti-parallel connection on the + same set of pins. Disabling APD functionality to implement substrate + diodes on devices that support APD eliminates the benefit of APD + (two diodes on one channel). + type: boolean + + microchip,parasitic-res-on-channel1-2: + description: + Indicates that the chip and the diodes/transistors are sufficiently + far apart that a parasitic resistance is added to the wires, which can + affect the measurements. Due to the availability of only a single + configuration bit in hardware, channels 1 and 2 are affected together. + If channel 2 is not available in hardware, this setting affects only + channel 1. + type: boolean + + microchip,parasitic-res-on-channel3-4: + description: + Indicates that the chip and the diodes/transistors are sufficiently + far apart that a parasitic resistance is added to the wires, which can + affect the measurements. Due to the availability of only a single + configuration bit in hardware, channels 3 and 4 are affected together. + If channel 4 is not available in hardware, this setting affects only + channel 3. + type: boolean + + vdd-supply: true + +patternProperties: + "^channel@[0-4]$": + description: | + Represents the temperature channels. + 0: Internal sensor + 1-4: External remote diodes + type: object + + properties: + reg: + maxItems: 1 + + label: + description: Unique name to identify which channel this is. + + required: + - reg + + additionalProperties: false + +required: + - compatible + - reg + - vdd-supply + +allOf: + # EMC1812: 1 Internal, 1 External Channels, No APD, + # parasitic-res-on-channel1-2: for channel 1 + - if: + properties: + compatible: + const: microchip,emc1812 + then: + properties: + microchip,enable-anti-parallel: false + microchip,parasitic-res-on-channel3-4: false + patternProperties: + "^channel@[2-4]$": false + + # EMC1813: 1 Internal, 2 External Channels, No APD, + # parasitic-res-on-channel1-2: on both channel 1 & 2 + - if: + properties: + compatible: + const: microchip,emc1813 + then: + properties: + microchip,enable-anti-parallel: false + microchip,parasitic-res-on-channel3-4: false + patternProperties: + "^channel@[3-4]$": false + + # EMC1833: 1 Internal, 2 External Channels, Supports APD, + # parasitic-res-on-channel1-2: on both channel 1 & 2 + - if: + properties: + compatible: + const: microchip,emc1833 + then: + properties: + microchip,parasitic-res-on-channel3-4: false + patternProperties: + "^channel@[3-4]$": false + + # EMC1814: 1 Internal, 3 External Channels, Supports APD, + # parasitic-res-on-channel1-2: on both channel 1 & 2 + # parasitic-res-on-channel3-4: for channel 3 + - if: + properties: + compatible: + const: microchip,emc1814 + then: + properties: + channel@4: false + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@4c { + compatible = "microchip,emc1813"; + reg = <0x4c>; + + #address-cells = <1>; + #size-cells = <0>; + + microchip,parasitic-res-on-channel1-2; + + vdd-supply = <&vdd>; + + channel@1 { + reg = <1>; + label = "External CH1 Temperature"; + }; + + channel@2 { + reg = <2>; + label = "External CH2 Temperature"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml index d3f06ebc19fa27..8c2548539d7fd7 100644 --- a/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml +++ b/Documentation/devicetree/bindings/hwmon/microchip,emc2305.yaml @@ -54,6 +54,12 @@ patternProperties: The fan number used to determine the associated PWM channel. maxItems: 1 + fan-shutdown-percent: + description: + PWM duty cycle in percent applied to the fan during shutdown. + minimum: 0 + maximum: 100 + required: - reg @@ -80,12 +86,14 @@ examples: fan@0 { reg = <0x0>; pwms = <&fan_controller 26000 PWM_POLARITY_INVERTED 1>; + fan-shutdown-percent = <100>; #cooling-cells = <2>; }; fan@1 { reg = <0x1>; pwms = <&fan_controller 26000 0 1>; + fan-shutdown-percent = <50>; #cooling-cells = <2>; }; diff --git a/Documentation/devicetree/bindings/hwmon/nsa320-mcu.txt b/Documentation/devicetree/bindings/hwmon/nsa320-mcu.txt deleted file mode 100644 index 0863e067c85b02..00000000000000 --- a/Documentation/devicetree/bindings/hwmon/nsa320-mcu.txt +++ /dev/null @@ -1,20 +0,0 @@ -Bindings for the fan / temperature monitor microcontroller used on -the Zyxel NSA 320 and several subsequent models. - -Required properties: -- compatible : "zyxel,nsa320-mcu" -- data-gpios : The GPIO pin connected to the data line on the MCU -- clk-gpios : The GPIO pin connected to the clock line on the MCU -- act-gpios : The GPIO pin connected to the active line on the MCU - -Example: - - hwmon { - compatible = "zyxel,nsa320-mcu"; - pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act>; - pinctrl-names = "default"; - - data-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; - clk-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; - act-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; - }; diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml new file mode 100644 index 00000000000000..1625dd59417f1b --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20830.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/pmbus/adi,max20830.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices MAX20830 Step-Down Switching Regulator with PMBus + +maintainers: + - Alexis Czezar Torreno + +description: | + The MAX20830 is a fully integrated step-down DC-DC switching regulator with + PMBus interface. It provides 2.7V to 16V input, 0.4V to 5.8V adjustable + output, and up to 30A output current. It allows monitoring of input/output + voltage, output current and temperature through the PMBus serial interface. + Datasheet: + https://www.analog.com/en/products/max20830.html + +allOf: + - $ref: /schemas/regulator/regulator.yaml# + +properties: + compatible: + const: adi,max20830 + + reg: + maxItems: 1 + + vddh-supply: + description: + Phandle to the regulator that provides the VDDH power supply. + + avdd-supply: + description: + Phandle to the regulator that provides the AVDD power supply. + + ldoin-supply: + description: + Optional 2.5V to 5.5V LDO input supply. + + pwr-good-gpios: + description: + GPIO connected to the power-good status output pin. + maxItems: 1 + +required: + - compatible + - reg + - vddh-supply + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@30 { + compatible = "adi,max20830"; + reg = <0x30>; + vddh-supply = <&vddh>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20860a.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20860a.yaml new file mode 100644 index 00000000000000..dd238265d462b0 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/pmbus/adi,max20860a.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/pmbus/adi,max20860a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices MAX20860A Step-Down Converter + +maintainers: + - Sanman Pradhan + +description: | + The MAX20860A is a fully integrated step-down DC-DC switching regulator + with PMBus interface for monitoring input/output voltage, output current + and temperature. + + Datasheet: https://www.analog.com/en/products/max20860a.html + +allOf: + - $ref: /schemas/regulator/regulator.yaml# + +properties: + compatible: + const: adi,max20860a + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@40 { + compatible = "adi,max20860a"; + reg = <0x40>; + }; + }; diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/infineon,xdp720.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/infineon,xdp720.yaml index 72bc3a5e7139ad..4a949c53f7ae7d 100644 --- a/Documentation/devicetree/bindings/hwmon/pmbus/infineon,xdp720.yaml +++ b/Documentation/devicetree/bindings/hwmon/pmbus/infineon,xdp720.yaml @@ -5,23 +5,31 @@ $id: http://devicetree.org/schemas/hwmon/pmbus/infineon,xdp720.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Infineon XDP720 Digital eFuse Controller +title: Infineon XDP720 / XDP730 Digital eFuse Controllers maintainers: - Ashish Yadav description: | - The XDP720 is an eFuse with integrated current sensor and digital - controller. It provides accurate system telemetry (V, I, P, T) and - reports analog current at the IMON pin for post-processing. + The XDP720 and XDP730 are PMBus-compliant digital eFuse controllers + with an integrated current sensor. They provide accurate system + telemetry (V, I, P, T) and report analog current at the IMON pin for + post-processing. - Datasheet: - https://www.infineon.com/assets/row/public/documents/24/49/infineon-xdp720-001-datasheet-en.pdf + Both parts share the same PMBus register map and direct-format + coefficients; they differ in the GIMON gain step exposed via the + TELEMETRY_AVG register (bit 10) and in the VDD_VIN pin number + (XDP720: pin 9, XDP730: pin 20). + + Datasheets: + - XDP720: https://www.infineon.com/assets/row/public/documents/24/49/infineon-xdp720-001-datasheet-en.pdf + - XDP730: https://www.infineon.com/assets/row/public/documents/24/49/infineon-xdp730-001-datasheet-en.pdf properties: compatible: enum: - infineon,xdp720 + - infineon,xdp730 reg: maxItems: 1 @@ -33,9 +41,9 @@ properties: vdd-vin-supply: description: - Supply for the VDD_VIN pin (pin 9), the IC controller power supply. - Typically connected to the input bus (VIN) through a 100 ohm / 100 nF - RC filter. + Supply for the VDD_VIN pin (XDP720 pin 9, XDP730 pin 20), the IC + controller power supply. Typically connected to the input bus + (VIN) through a 100 ohm / 100 nF RC filter. required: - compatible @@ -50,7 +58,7 @@ examples: #address-cells = <1>; #size-cells = <0>; - hwmon@11 { + efuse@11 { compatible = "infineon,xdp720"; reg = <0x11>; vdd-vin-supply = <&vdd_vin>; diff --git a/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml b/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml index a84cc3a4cfdcaf..6a24851fd80d49 100644 --- a/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml +++ b/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml @@ -63,7 +63,8 @@ properties: description: The PWM that is used to control the fan. maxItems: 1 - "#cooling-cells": true + "#cooling-cells": + const: 2 required: - compatible diff --git a/Documentation/devicetree/bindings/hwmon/zyxel,nsa320-mcu.yaml b/Documentation/devicetree/bindings/hwmon/zyxel,nsa320-mcu.yaml new file mode 100644 index 00000000000000..a111f8125e09e2 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/zyxel,nsa320-mcu.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/zyxel,nsa320-mcu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZyXEL NSA320 MCU + +maintainers: + - Adam Baker + - Guenter Roeck + +description: + The ZyXEL NSA320 uses a dedicated microcontroller to manage system-critical + functions like fan speed and power monitoring. It is connected to the SoC + via a GPIO-based serial protocol. + +properties: + compatible: + const: zyxel,nsa320-mcu + + data-gpios: + maxItems: 1 + description: GPIO pin connected to the data line on the MCU. + + clk-gpios: + maxItems: 1 + description: GPIO pin connected to the clock line on the MCU. + + act-gpios: + maxItems: 1 + description: GPIO pin connected to the active line on the MCU. + +required: + - compatible + - data-gpios + - clk-gpios + - act-gpios + +additionalProperties: false + +examples: + - | + #include + + hwmon { + compatible = "zyxel,nsa320-mcu"; + pinctrl-0 = <&pmx_mcu_data &pmx_mcu_clk &pmx_mcu_act>; + pinctrl-names = "default"; + + data-gpios = <&gpio0 14 GPIO_ACTIVE_HIGH>; + clk-gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; + act-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>; + }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt b/Documentation/devicetree/bindings/i2c/i2c-davinci.txt deleted file mode 100644 index 6590501c53d4e5..00000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-davinci.txt +++ /dev/null @@ -1,43 +0,0 @@ -* Texas Instruments Davinci/Keystone I2C - -This file provides information, what the device node for the -davinci/keystone i2c interface contains. - -Required properties: -- compatible: "ti,davinci-i2c" or "ti,keystone-i2c"; -- reg : Offset and length of the register set for the device -- clocks: I2C functional clock phandle. - For 66AK2G this property should be set per binding, - Documentation/devicetree/bindings/clock/ti,sci-clk.yaml - -SoC-specific Required Properties: - -The following are mandatory properties for Keystone 2 66AK2G SoCs only: - -- power-domains: Should contain a phandle to a PM domain provider node - and an args specifier containing the I2C device id - value. This property is as per the binding, - Documentation/devicetree/bindings/soc/ti/sci-pm-domain.yaml - -Recommended properties : -- interrupts : standard interrupt property. -- clock-frequency : desired I2C bus clock frequency in Hz. -- ti,has-pfunc: boolean; if defined, it indicates that SoC supports PFUNC - registers. PFUNC registers allow to switch I2C pins to function as - GPIOs, so they can be toggled manually. - -Example (enbw_cmc board): - i2c@1c22000 { - compatible = "ti,davinci-i2c"; - reg = <0x22000 0x1000>; - clock-frequency = <100000>; - interrupts = <15>; - interrupt-parent = <&intc>; - #address-cells = <1>; - #size-cells = <0>; - - dtt@48 { - compatible = "national,lm75"; - reg = <0x48>; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.yaml b/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.yaml index 1eaf00b90a77a3..deca72bfc8cf33 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-demux-pinctrl.yaml @@ -40,6 +40,7 @@ properties: i2c-parent: $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 2 items: maxItems: 1 description: diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.yaml b/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.yaml index 4a93d1f78f9328..6e44510aaef626 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-gpio.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: GPIO-based I2C Bus Mux maintainers: - - Wolfram Sang + - Peter Korsgaard description: | This binding describes an I2C bus multiplexer that uses GPIOs to route the I2C signals. diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.yaml b/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.yaml index 2e3d555eb96c19..99812a893476b3 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-pinctrl.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Pinctrl-based I2C Bus Mux maintainers: - - Wolfram Sang + - Thierry Reding description: | This binding describes an I2C bus multiplexer that uses pin multiplexing to route the I2C diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt b/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt deleted file mode 100644 index b9d9755e4172d0..00000000000000 --- a/Documentation/devicetree/bindings/i2c/i2c-mux-reg.txt +++ /dev/null @@ -1,74 +0,0 @@ -Register-based I2C Bus Mux - -This binding describes an I2C bus multiplexer that uses a single register -to route the I2C signals. - -Required properties: -- compatible: i2c-mux-reg -- i2c-parent: The phandle of the I2C bus that this multiplexer's master-side - port is connected to. -* Standard I2C mux properties. See i2c-mux.yaml in this directory. -* I2C child bus nodes. See i2c-mux.yaml in this directory. - -Optional properties: -- reg: this pair of specifies the register to control the mux. - The depends on its parent node. It can be any memory-mapped - address. The size must be either 1, 2, or 4 bytes. If reg is omitted, the - resource of this device will be used. -- little-endian: The existence indicates the register is in little endian. -- big-endian: The existence indicates the register is in big endian. - If both little-endian and big-endian are omitted, the endianness of the - CPU will be used. -- write-only: The existence indicates the register is write-only. -- idle-state: value to set the muxer to when idle. When no value is - given, it defaults to the last value used. - -Whenever an access is made to a device on a child bus, the value set -in the relevant node's reg property will be output to the register. - -If an idle state is defined, using the idle-state (optional) property, -whenever an access is not being made to a device on a child bus, the -register will be set according to the idle value. - -If an idle state is not defined, the most recently used value will be -left programmed into the register. - -Example of a mux on PCIe card, the host is a powerpc SoC (big endian): - - i2c-mux { - /* the depends on the address translation - * of the parent device. If omitted, device resource - * will be used instead. The size is to determine - * whether iowrite32, iowrite16, or iowrite8 will be used. - */ - reg = <0x6028 0x4>; - little-endian; /* little endian register on PCIe */ - compatible = "i2c-mux-reg"; - #address-cells = <1>; - #size-cells = <0>; - i2c-parent = <&i2c1>; - i2c@0 { - reg = <0>; - #address-cells = <1>; - #size-cells = <0>; - - si5338: clock-generator@70 { - compatible = "silabs,si5338"; - reg = <0x70>; - /* other stuff */ - }; - }; - - i2c@1 { - /* data is written using iowrite32 */ - reg = <1>; - #address-cells = <1>; - #size-cells = <0>; - - si5338: clock-generator@70 { - compatible = "silabs,si5338"; - reg = <0x70>; - /* other stuff */ - }; - }; - }; diff --git a/Documentation/devicetree/bindings/i2c/i2c-mux-reg.yaml b/Documentation/devicetree/bindings/i2c/i2c-mux-reg.yaml new file mode 100644 index 00000000000000..01ade0771c60f5 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/i2c-mux-reg.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/i2c-mux-reg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Register-based I2C Bus Mux + +maintainers: + - Peter Rosin + +description: | + This binding describes an I2C bus multiplexer that uses a single + memory-mapped register to route the I2C signals. + + Whenever an access is made to a device on a child bus, the value + set in the relevant node's reg property is output to the register. + + If an idle state is defined via the idle-state property, the + register is set to that value whenever no access is being made. + Otherwise the most recently used value is left programmed. + +allOf: + - $ref: /schemas/i2c/i2c-mux.yaml# + +properties: + compatible: + const: i2c-mux-reg + + reg: + maxItems: 1 + description: | + Offset and size of the register that selects the active child + bus, relative to the parent node's address space. The size + determines the access width and must be 1, 2, or 4 bytes. If + omitted, the platform device's own memory resource is used + instead. + + i2c-parent: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle of the I2C bus that this multiplexer's master-side port + is connected to. + + little-endian: + type: boolean + description: Register is accessed in little-endian byte order. + + big-endian: + type: boolean + description: Register is accessed in big-endian byte order. + + write-only: + type: boolean + description: + Register is write-only; the driver must not read back the + current selection. + + idle-state: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Value to write to the register when no child bus is selected. + +required: + - compatible + - i2c-parent + +unevaluatedProperties: false + +examples: + - | + i2c-mux@6028 { + compatible = "i2c-mux-reg"; + reg = <0x6028 0x4>; + little-endian; + #address-cells = <1>; + #size-cells = <0>; + i2c-parent = <&i2c1>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml b/Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml index 67882ec6e06afc..ee09c6d9c5f0b7 100644 --- a/Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/loongson,ls2x-i2c.yaml @@ -16,6 +16,7 @@ properties: compatible: enum: - loongson,ls2k-i2c + - loongson,ls2k0300-i2c - loongson,ls7a-i2c reg: @@ -24,6 +25,9 @@ properties: interrupts: maxItems: 1 + clocks: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml b/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml index 6ff58b64d49627..bd63c70aac6bc2 100644 --- a/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml +++ b/Documentation/devicetree/bindings/i2c/microchip,corei2c.yaml @@ -37,6 +37,9 @@ properties: modes are supported, possible values are 100000 and 400000. enum: [100000, 400000] + resets: + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml b/Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml index d9ef8672901125..736e9a3eab8a9e 100644 --- a/Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml +++ b/Documentation/devicetree/bindings/i2c/opencores,i2c-ocores.yaml @@ -95,8 +95,8 @@ examples: interrupts = <10>; opencores,ip-clock-frequency = <20000000>; - reg-shift = <0>; /* 8 bit registers */ - reg-io-width = <1>; /* 8 bit read/write */ + reg-shift = <0>; /* 8 bit registers */ + reg-io-width = <1>; /* 8 bit read/write */ }; i2c@b0000000 { @@ -108,7 +108,7 @@ examples: clocks = <&osc>; clock-frequency = <400000>; /* i2c bus frequency 400 KHz */ - reg-shift = <0>; /* 8 bit registers */ - reg-io-width = <1>; /* 8 bit read/write */ + reg-shift = <0>; /* 8 bit registers */ + reg-io-width = <1>; /* 8 bit read/write */ }; ... diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 7c497a358e1dc8..1e8def25ec0ec1 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: + - qcom,glymur-cci - qcom,kaanapali-cci - qcom,milos-cci - qcom,qcm2290-cci @@ -35,6 +36,7 @@ properties: - qcom,sc8280xp-cci - qcom,sdm670-cci - qcom,sdm845-cci + - qcom,shikra-cci - qcom,sm6150-cci - qcom,sm6350-cci - qcom,sm8250-cci @@ -134,9 +136,11 @@ allOf: compatible: contains: enum: + - qcom,glymur-cci - qcom,kaanapali-cci - qcom,qcm2290-cci - qcom,qcs8300-cci + - qcom,shikra-cci - qcom,sm8750-cci then: properties: diff --git a/Documentation/devicetree/bindings/i2c/ti,davinci-i2c.yaml b/Documentation/devicetree/bindings/i2c/ti,davinci-i2c.yaml new file mode 100644 index 00000000000000..b94ac06dce3669 --- /dev/null +++ b/Documentation/devicetree/bindings/i2c/ti,davinci-i2c.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i2c/ti,davinci-i2c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments DaVinci/Keystone I2C + +maintainers: + - Chaitanya Sabnis + +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + - if: + properties: + compatible: + contains: + const: ti,keystone-i2c + then: + required: + - power-domains + +properties: + compatible: + enum: + - ti,davinci-i2c + - ti,keystone-i2c + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + ti,has-pfunc: + description: + Indicates that the SoC supports PFUNC registers, allowing I2C pins + to function as GPIOs for manual toggling. + type: boolean + +required: + - compatible + - reg + - interrupts + - clocks + +unevaluatedProperties: false + +examples: + - | + i2c@1c22000 { + compatible = "ti,davinci-i2c"; + reg = <0x01c22000 0x1000>; + clocks = <&i2c_clk>; + clock-frequency = <100000>; + interrupts = <15>; + #address-cells = <1>; + #size-cells = <0>; + + sensor@48 { + compatible = "national,lm75"; + reg = <0x48>; + }; + }; diff --git a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml b/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml index 39bb1a1784c9bc..d488fb42094567 100644 --- a/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml +++ b/Documentation/devicetree/bindings/i3c/mipi-i3c-hci.yaml @@ -9,9 +9,6 @@ title: MIPI I3C HCI maintainers: - Nicolas Pitre -allOf: - - $ref: /schemas/i3c/i3c.yaml# - description: | MIPI I3C Host Controller Interface @@ -28,9 +25,17 @@ description: | properties: compatible: - const: mipi-i3c-hci + enum: + - mipi-i3c-hci + - microchip,sama7d65-i3c-hci reg: maxItems: 1 + + clocks: + items: + - description: Peripheral bus clock + - description: System Generic clock + interrupts: maxItems: 1 @@ -39,6 +44,20 @@ required: - reg - interrupts +allOf: + - $ref: /schemas/i3c/i3c.yaml# + - if: + properties: + compatible: + contains: + const: microchip,sama7d65-i3c-hci + then: + required: + - clocks + else: + properties: + clocks: false + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml index 79df2696ef2491..4a3f7d3e05c399 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4080.yaml @@ -18,7 +18,11 @@ description: | service a wide variety of precision, wide bandwidth data acquisition applications. + The AD4880 is a dual-channel variant with two independent ADC channels, + each with its own SPI configuration interface. + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4080.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/ad4880.pdf $ref: /schemas/spi/spi-peripheral-props.yaml# @@ -34,9 +38,16 @@ properties: - adi,ad4086 - adi,ad4087 - adi,ad4088 + - adi,ad4880 + - adi,ad4884 reg: - maxItems: 1 + minItems: 1 + maxItems: 2 + description: + SPI chip select(s). For single-channel devices, one chip select. + For multi-channel devices like AD4880, two chip selects are required + as each channel has its own SPI configuration interface. spi-max-frequency: description: Configuration of the SPI bus. @@ -60,7 +71,10 @@ properties: vrefin-supply: true io-backends: - maxItems: 1 + minItems: 1 + items: + - description: Backend for channel A (primary) + - description: Backend for channel B (secondary) adi,lvds-cnv-enable: description: Enable the LVDS signal type on the CNV pin. Default is CMOS. @@ -81,6 +95,27 @@ required: - vdd33-supply - vrefin-supply +allOf: + - if: + properties: + compatible: + contains: + enum: + - adi,ad4880 + - adi,ad4884 + then: + properties: + reg: + minItems: 2 + io-backends: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + io-backends: + maxItems: 1 + additionalProperties: false examples: @@ -101,4 +136,21 @@ examples: io-backends = <&iio_backend>; }; }; + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad4880"; + reg = <0>, <1>; + spi-max-frequency = <10000000>; + vdd33-supply = <&vdd33>; + vddldo-supply = <&vddldo>; + vrefin-supply = <&vrefin>; + clocks = <&cnv>; + clock-names = "cnv"; + io-backends = <&iio_backend_cha>, <&iio_backend_chb>; + }; + }; ... diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml index d00690a8d3fbd9..cc38617bb8295c 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4130.yaml @@ -5,19 +5,30 @@ $id: http://devicetree.org/schemas/iio/adc/adi,ad4130.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Analog Devices AD4130 ADC device driver +title: Analog Devices AD4130 family ADCs maintainers: - Cosmin Tanislav description: | - Bindings for the Analog Devices AD4130 ADC. Datasheet can be found here: + Bindings for the Analog Devices AD4130 family ADCs. + Datasheets can be found here: + https://www.analog.com/media/en/technical-documentation/data-sheets/AD4129-4.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/AD4129-8.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/AD4130-4.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/AD4130-8.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/AD4131-4.pdf + https://www.analog.com/media/en/technical-documentation/data-sheets/AD4131-8.pdf properties: compatible: enum: + - adi,ad4129-4 + - adi,ad4129-8 + - adi,ad4130-4 - adi,ad4130 + - adi,ad4131-4 + - adi,ad4131-8 reg: maxItems: 1 @@ -32,6 +43,10 @@ properties: interrupts: maxItems: 1 + description: | + Data Ready / FIFO interrupt. For devices with FIFO support, the + interrupt polarity specified here is inverted when the device enters + FIFO mode, and normal for data ready. interrupt-names: description: | diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml b/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml new file mode 100644 index 00000000000000..af28a0c1cfa9eb --- /dev/null +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad4691.yaml @@ -0,0 +1,180 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/adc/adi,ad4691.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD4691 Family Multichannel SAR ADCs + +maintainers: + - Radu Sabau + +description: | + The AD4691 family are high-speed, low-power, multichannel successive + approximation register (SAR) analog-to-digital converters (ADCs) with + an SPI-compatible serial interface. The ADC supports CNV Burst Mode, + where an external PWM drives the CNV pin, and Manual Mode, where CNV + is directly tied to the SPI chip-select. + + Datasheets: + * https://www.analog.com/en/products/ad4691.html + * https://www.analog.com/en/products/ad4692.html + * https://www.analog.com/en/products/ad4693.html + * https://www.analog.com/en/products/ad4694.html + +$ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + enum: + - adi,ad4691 + - adi,ad4692 + - adi,ad4693 + - adi,ad4694 + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 40000000 + + spi-cpol: true + spi-cpha: true + + avdd-supply: + description: Analog power supply (4.5V to 5.5V). + + vdd-supply: + description: + External 1.8V digital core supply. When present, the internal LDO is + disabled (LDO_EN = 0). Mutually exclusive with ldo-in-supply. + + ldo-in-supply: + description: + LDO input supply (2.4V to 5.5V). When present and vdd-supply is absent, + the internal LDO generates 1.8V VDD from this input (LDO_EN = 1). + Mutually exclusive with vdd-supply. + + vio-supply: + description: I/O voltage supply (1.71V to 1.89V or VDD). + + ref-supply: + description: External reference voltage supply (2.4V to 5.25V). + + refin-supply: + description: Internal reference buffer input supply. + + reset-gpios: + description: + GPIO line controlling the hardware reset pin (active-low). + maxItems: 1 + + pwms: + description: + PWM connected to the CNV pin. When present, selects CNV Burst Mode where + the PWM drives the conversion rate. When absent, Manual Mode is used + (CNV tied to SPI CS). + maxItems: 1 + + interrupts: + description: + Interrupt lines connected to the ADC GP pins. Each GP pin can be + physically wired to an interrupt-capable input on the SoC. + maxItems: 4 + + interrupt-names: + description: Names of the interrupt lines, matching the GP pin names. + minItems: 1 + maxItems: 4 + items: + enum: + - gp0 + - gp1 + - gp2 + - gp3 + + gpio-controller: true + + '#gpio-cells': + const: 2 + + '#trigger-source-cells': + description: + This node can act as a trigger source. The single cell in a consumer + reference specifies the GP pin number (0-3) used as the trigger output. + const: 1 + +required: + - compatible + - reg + - avdd-supply + - vio-supply + +allOf: + # vdd-supply and ldo-in-supply are mutually exclusive, one is required: + # either an external 1.8V VDD is provided or the internal LDO is fed from + # ldo-in-supply to generate VDD. + - oneOf: + - required: + - vdd-supply + - required: + - ldo-in-supply + # ref-supply and refin-supply are mutually exclusive, one is required + - oneOf: + - required: + - ref-supply + - required: + - refin-supply + +unevaluatedProperties: false + +examples: + - | + #include + /* AD4692 in CNV Burst Mode with SPI offload */ + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad4692"; + reg = <0>; + spi-cpol; + spi-cpha; + spi-max-frequency = <40000000>; + + avdd-supply = <&avdd_supply>; + ldo-in-supply = <&avdd_supply>; + vio-supply = <&vio_supply>; + ref-supply = <&ref_5v>; + + reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + + pwms = <&pwm_gen 0 0>; + + #trigger-source-cells = <1>; + }; + }; + + - | + #include + /* AD4692 in Manual Mode (CNV tied to SPI CS) */ + spi { + #address-cells = <1>; + #size-cells = <0>; + + adc@0 { + compatible = "adi,ad4692"; + reg = <0>; + spi-cpol; + spi-cpha; + spi-max-frequency = <31250000>; + + avdd-supply = <&avdd_supply>; + ldo-in-supply = <&avdd_supply>; + vio-supply = <&vio_supply>; + refin-supply = <&refin_supply>; + + reset-gpios = <&gpio0 15 GPIO_ACTIVE_LOW>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml b/Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml index da605a051b9497..6467800d30e27f 100644 --- a/Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/allwinner,sun20i-d1-gpadc.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - allwinner,sun20i-d1-gpadc + - allwinner,sun55i-a523-gpadc - items: - enum: - allwinner,sun50i-h616-gpadc @@ -29,7 +30,12 @@ properties: const: 0 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + maxItems: 2 interrupts: maxItems: 1 @@ -40,6 +46,30 @@ properties: resets: maxItems: 1 +allOf: + - if: + properties: + compatible: + enum: + - allwinner,sun55i-a523-gpadc + then: + properties: + clocks: + items: + - description: Bus clock + - description: Module clock + clock-names: + items: + - const: bus + - const: mod + required: + - clock-names + else: + properties: + clocks: + maxItems: 1 + clock-names: false + patternProperties: "^channel@[0-9a-f]+$": $ref: adc.yaml diff --git a/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml b/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml index 9c57eb13f89284..1ea60dff98d59d 100644 --- a/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml +++ b/Documentation/devicetree/bindings/iio/adc/avia-hx711.yaml @@ -10,14 +10,9 @@ maintainers: - Andreas Klinger description: | - Bit-banging driver using two GPIOs: - - sck-gpio gives a clock to the sensor with 24 cycles for data retrieval - and up to 3 cycles for selection of the input channel and gain for the - next measurement - - dout-gpio is the sensor data the sensor responds to the clock - - Specifications about the driver can be found at: - http://www.aviaic.com/ENProducts.aspx + The HX711 is a 24-bit ADC with selectable gain (32/64/128) and two + differential input channels. Channel A supports gain 64 and 128; + channel B supports gain 32. properties: compatible: @@ -26,23 +21,23 @@ properties: sck-gpios: description: - Definition of the GPIO for the clock (output). In the datasheet it is - named PD_SCK + GPIO for the clock output (PD_SCK in the datasheet). maxItems: 1 dout-gpios: description: - Definition of the GPIO for the data-out sent by the sensor in - response to the clock (input). - See Documentation/devicetree/bindings/gpio/gpio.txt for information - on how to specify a consumer gpio. + GPIO for the data output from the sensor (DOUT in the datasheet). maxItems: 1 avdd-supply: description: - Definition of the regulator used as analog supply + Analog supply voltage (AVDD). clock-frequency: + description: + Controls the SCK bit-bang timing. The value is used to derive the + delay between SCK edges; keep the SCK high time below 60 us to + avoid triggering chip power-down mode. minimum: 20000 maximum: 2500000 default: 400000 diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml index 5d4ab701f51a1e..9936aa605c7ba5 100644 --- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt6359-auxadc.yaml @@ -18,12 +18,17 @@ description: properties: compatible: - enum: - - mediatek,mt6357-auxadc - - mediatek,mt6358-auxadc - - mediatek,mt6359-auxadc - - mediatek,mt6363-auxadc - - mediatek,mt6373-auxadc + oneOf: + - enum: + - mediatek,mt6357-auxadc + - mediatek,mt6358-auxadc + - mediatek,mt6359-auxadc + - mediatek,mt6363-auxadc + - mediatek,mt6373-auxadc + - items: + - enum: + - mediatek,mt6365-auxadc + - const: mediatek,mt6359-auxadc "#io-channel-cells": const: 1 diff --git a/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml b/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml index c978c3a3e31af2..63aac8de22ad28 100644 --- a/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/qcom,pm8018-adc.yaml @@ -78,6 +78,10 @@ patternProperties: reg: maxItems: 1 + label: + description: | + Unique name to identify which channel this is. + qcom,decimation: $ref: /schemas/types.yaml#/definitions/uint32 description: | @@ -130,36 +134,47 @@ examples: vcoin: adc-channel@0 { reg = <0x00 0x00>; + label = "vcoin"; }; vbat: adc-channel@1 { reg = <0x00 0x01>; + label = "vbat"; }; dcin: adc-channel@2 { reg = <0x00 0x02>; + label = "dcin"; }; ichg: adc-channel@3 { reg = <0x00 0x03>; + label = "ichg"; }; vph_pwr: adc-channel@4 { reg = <0x00 0x04>; + label = "vph_pwr"; }; usb_vbus: adc-channel@a { reg = <0x00 0x0a>; + label = "usb_vbus"; }; die_temp: adc-channel@b { reg = <0x00 0x0b>; + label = "die_temp"; }; ref_625mv: adc-channel@c { reg = <0x00 0x0c>; + label = "ref_625mv"; }; ref_1250mv: adc-channel@d { reg = <0x00 0x0d>; + label = "ref_1250mv"; }; ref_325mv: adc-channel@e { reg = <0x00 0x0e>; + label = "ref_325mv"; }; ref_muxoff: adc-channel@f { reg = <0x00 0x0f>; + label = "ref_muxoff"; }; }; }; diff --git a/Documentation/devicetree/bindings/iio/adc/st,spear600-adc.yaml b/Documentation/devicetree/bindings/iio/adc/st,spear600-adc.yaml index dd9ec303870336..c8b8f28541ce24 100644 --- a/Documentation/devicetree/bindings/iio/adc/st,spear600-adc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/st,spear600-adc.yaml @@ -65,5 +65,5 @@ examples: interrupt-parent = <&vic1>; interrupts = <6>; sampling-frequency = <5000000>; - vref-external = <2500>; /* 2.5V VRef */ + vref-external = <2500>; /* 2.5V VRef */ }; diff --git a/Documentation/devicetree/bindings/iio/chemical/sensirion,scd30.yaml b/Documentation/devicetree/bindings/iio/chemical/sensirion,scd30.yaml index 40d87346ff4cff..a5b0debe85b1a5 100644 --- a/Documentation/devicetree/bindings/iio/chemical/sensirion,scd30.yaml +++ b/Documentation/devicetree/bindings/iio/chemical/sensirion,scd30.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Sensirion SCD30 carbon dioxide sensor maintainers: - - Tomasz Duszynski + - Maxwell Doose description: | Air quality sensor capable of measuring co2 concentration, temperature diff --git a/Documentation/devicetree/bindings/iio/dac/adi,ad5706r.yaml b/Documentation/devicetree/bindings/iio/dac/adi,ad5706r.yaml new file mode 100644 index 00000000000000..19cc744a9f0fc3 --- /dev/null +++ b/Documentation/devicetree/bindings/iio/dac/adi,ad5706r.yaml @@ -0,0 +1,105 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/dac/adi,ad5706r.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AD5706R 4-Channel Current Output DAC + +maintainers: + - Alexis Czezar Torreno + +description: | + The AD5706R is a 4-channel, 16-bit resolution, current output + digital-to-analog converter (DAC) with programmable output current + ranges (50mA, 150mA, 200mA, 300mA), an integrated 2.5V voltage + reference, and load DAC, A/B toggle, and dither functions. + + Datasheet: + https://www.analog.com/en/products/ad5706r.html + +properties: + compatible: + enum: + - adi,ad5706r + + reg: + maxItems: 1 + + avdd-supply: + description: Analog power supply (2.9V to 3.6V). + + iovdd-supply: + description: Logic power supply (1.14V to 1.89V). + + pvdd0-supply: + description: Power supply for IDAC0 channel (1.65V to AVDD). + + pvdd1-supply: + description: Power supply for IDAC1 channel (1.65V to AVDD). + + pvdd2-supply: + description: Power supply for IDAC2 channel (1.65V to AVDD). + + pvdd3-supply: + description: Power supply for IDAC3 channel (1.65V to AVDD). + + vref-supply: + description: + Optional external 2.5V voltage reference. If not provided, the + internal 2.5V reference is used. + + pwms: + maxItems: 1 + description: + Optional PWM connected to the LDAC/TGP/DCK pin for hardware + triggered DAC updates, toggle, or dither clock generation. + + reset-gpios: + maxItems: 1 + description: + GPIO connected to the active low RESET pin. If not provided, + software reset is used. + + enable-gpios: + maxItems: 1 + description: + GPIO connected to the active low OUT_EN pin. Controls whether + the current outputs are enabled or in high-Z/ground state. + +required: + - compatible + - reg + - avdd-supply + - iovdd-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + + spi { + #address-cells = <1>; + #size-cells = <0>; + + dac@0 { + compatible = "adi,ad5706r"; + reg = <0>; + avdd-supply = <&avdd>; + iovdd-supply = <&iovdd>; + pvdd0-supply = <&pvdd>; + pvdd1-supply = <&pvdd>; + pvdd2-supply = <&pvdd>; + pvdd3-supply = <&pvdd>; + vref-supply = <&vref>; + spi-max-frequency = <50000000>; + pwms = <&pwm0 0 1000000 0>; + reset-gpios = <&gpio0 10 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio0 12 GPIO_ACTIVE_LOW>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml b/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml index d2466aa6bda210..d131f136bd1516 100644 --- a/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml +++ b/Documentation/devicetree/bindings/iio/dac/microchip,mcp47feb02.yaml @@ -161,8 +161,8 @@ patternProperties: properties: reg: description: The channel number. - minItems: 1 - maxItems: 8 + minimum: 0 + maximum: 7 label: description: Unique name to identify which channel this is. @@ -280,23 +280,23 @@ examples: #address-cells = <1>; #size-cells = <0>; - dac@0 { - compatible = "microchip,mcp47feb02"; - reg = <0>; - vdd-supply = <&vdac_vdd>; - vref-supply = <&vref_reg>; + dac@60 { + compatible = "microchip,mcp47feb02"; + reg = <0x60>; + vdd-supply = <&vdac_vdd>; + vref-supply = <&vref_reg>; - #address-cells = <1>; - #size-cells = <0>; - channel@0 { - reg = <0>; - label = "Adjustable_voltage_ch0"; - }; + #address-cells = <1>; + #size-cells = <0>; + channel@0 { + reg = <0>; + label = "Adjustable_voltage_ch0"; + }; - channel@1 { - reg = <0x1>; - label = "Adjustable_voltage_ch1"; - }; - }; + channel@1 { + reg = <0x1>; + label = "Adjustable_voltage_ch1"; + }; + }; }; ... diff --git a/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml b/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml index fcbd4b430e48ea..8e094651381c84 100644 --- a/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml +++ b/Documentation/devicetree/bindings/iio/gyroscope/bosch,bmg160.yaml @@ -26,6 +26,9 @@ properties: vdd-supply: true vddio-supply: true + mount-matrix: + description: an optional 3x3 mounting rotation matrix. + spi-max-frequency: maximum: 10000000 @@ -56,6 +59,9 @@ examples: reg = <0x69>; interrupt-parent = <&gpio6>; interrupts = <18 IRQ_TYPE_EDGE_RISING>; + mount-matrix = "0", "1", "0", + "1", "0", "0", + "0", "0", "1"; }; }; ... diff --git a/Documentation/devicetree/bindings/iio/light/brcm,apds9999.yaml b/Documentation/devicetree/bindings/iio/light/brcm,apds9999.yaml new file mode 100644 index 00000000000000..9f5b3b294c2cac --- /dev/null +++ b/Documentation/devicetree/bindings/iio/light/brcm,apds9999.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/light/brcm,apds9999.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# +title: Broadcom APDS-9999 Digital Proximity and RGB Sensor + +maintainers: + - Jose A. Perez de Azpillaga + +description: | + Broadcom APDS-9999 is a digital proximity and RGB sensor with + ambient light sensing (ALS) capability. The device uses individual + R, G, B, and IR channels plus a Vertical Cavity Surface Emitting + Laser (VCSEL) for proximity detection. + + Datasheet: https://docs.broadcom.com/docs/APDS-9999-DS + +properties: + compatible: + enum: + - brcm,apds9999 + + reg: + maxItems: 1 + + vdd-supply: true + + vcsel-supply: + description: VCSEL power supply (VVCSEL pin) + + interrupts: + maxItems: 1 + +additionalProperties: false + +required: + - compatible + - reg + - vdd-supply + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + light-sensor@52 { + compatible = "brcm,apds9999"; + reg = <0x52>; + vdd-supply = <&vdd_reg>; + vcsel-supply = <&vcsel_reg>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/light/tsl2772.yaml b/Documentation/devicetree/bindings/iio/light/tsl2772.yaml index d8122985794442..9921ccaa64a06c 100644 --- a/Documentation/devicetree/bindings/iio/light/tsl2772.yaml +++ b/Documentation/devicetree/bindings/iio/light/tsl2772.yaml @@ -26,6 +26,8 @@ properties: - amstaos,tmd2672 - amstaos,tsl2772 - amstaos,tmd2772 + - avago,apds9900 + - avago,apds9901 - avago,apds9930 reg: diff --git a/Documentation/devicetree/bindings/iio/light/vishay,veml6030.yaml b/Documentation/devicetree/bindings/iio/light/vishay,veml6030.yaml index 4ea69f1fdd63ae..0041e1db68388d 100644 --- a/Documentation/devicetree/bindings/iio/light/vishay,veml6030.yaml +++ b/Documentation/devicetree/bindings/iio/light/vishay,veml6030.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/iio/light/vishay,veml6030.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: VEML3235, VEML6030, VEML6035 and VEML7700 Ambient Light Sensors (ALS) +title: VEML3235, VEML3328, VEML6030, VEML6035 and VEML7700 Ambient Light Sensors (ALS) maintainers: - Rishi Gupta @@ -21,6 +21,7 @@ description: | Specifications about the sensors can be found at: https://www.vishay.com/docs/80131/veml3235.pdf + https://www.vishay.com/docs/84968/veml3328.pdf https://www.vishay.com/docs/84366/veml6030.pdf https://www.vishay.com/docs/84889/veml6035.pdf https://www.vishay.com/docs/84286/veml7700.pdf @@ -29,6 +30,7 @@ properties: compatible: enum: - vishay,veml3235 + - vishay,veml3328 - vishay,veml6030 - vishay,veml6035 - vishay,veml7700 @@ -79,6 +81,7 @@ allOf: compatible: enum: - vishay,veml3235 + - vishay,veml3328 - vishay,veml7700 then: properties: diff --git a/Documentation/devicetree/bindings/iio/magnetometer/memsic,mmc5983.yaml b/Documentation/devicetree/bindings/iio/magnetometer/memsic,mmc5983.yaml new file mode 100644 index 00000000000000..4a4df6bb70fead --- /dev/null +++ b/Documentation/devicetree/bindings/iio/magnetometer/memsic,mmc5983.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iio/magnetometer/memsic,mmc5983.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MEMSIC MMC5983MA 3-axis magnetic sensor + +maintainers: + - Vladislav Kulikov + +properties: + compatible: + const: memsic,mmc5983 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: + description: Regulator that provides power to the sensor + + vddio-supply: + description: Regulator that provides power to the digital interface and INT pin + +required: + - compatible + - reg + - vdd-supply + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@30 { + compatible = "memsic,mmc5983"; + reg = <0x30>; + vdd-supply = <&vdd_3v3_reg>; + vddio-supply = <&vdd_3v3_reg>; + }; + }; + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + magnetometer@0 { + compatible = "memsic,mmc5983"; + reg = <0>; + spi-max-frequency = <10000000>; + vdd-supply = <&vdd_3v3_reg>; + vddio-supply = <&vdd_3v3_reg>; + }; + }; diff --git a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml index a22725f7619b79..13e5f29f058849 100644 --- a/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml +++ b/Documentation/devicetree/bindings/iio/temperature/adi,ltc2983.yaml @@ -4,14 +4,18 @@ $id: http://devicetree.org/schemas/iio/temperature/adi,ltc2983.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Analog Devices LTC2983, LTC2986, LTM2985 Multi-sensor Temperature system +title: Analog Devices LTC2983 and similar Multi-sensor Temperature systems maintainers: - Nuno Sá description: | - Analog Devices LTC2983, LTC2984, LTC2986, LTM2985 Multi-Sensor Digital - Temperature Measurement Systems + Analog Devices Multi-Sensor Digital Temperature Measurement Systems: + - ADT7604 + - LTC2983 + - LTC2984 + - LTC2986 + - LTM2985 https://www.analog.com/media/en/technical-documentation/data-sheets/2983fc.pdf https://www.analog.com/media/en/technical-documentation/data-sheets/2984fb.pdf @@ -43,6 +47,7 @@ properties: compatible: oneOf: - enum: + - adi,adt7604 - adi,ltc2983 - adi,ltc2986 - adi,ltm2985 @@ -436,6 +441,121 @@ patternProperties: required: - adi,custom-temp + '^copper-trace@': + $ref: '#/$defs/sensor-node' + unevaluatedProperties: false + description: | + Copper trace resistance sensor (some parts only). Two variants exist: + sub-ohm (< 1 ohm, no custom table allowed) and standard (> 1 ohm, + required custom table). + + properties: + reg: + minimum: 2 + maximum: 20 + + adi,sensor-type: + description: Sensor type for copper trace sensors. + $ref: /schemas/types.yaml#/definitions/uint32 + const: 32 + + adi,rsense-handle: + description: Associated sense resistor sensor. + $ref: /schemas/types.yaml#/definitions/phandle + + adi,copper-trace-sub-ohm: + description: + Select the sub-ohm (< 1 ohm) copper trace variant. Custom table + and excitation current are not allowed in this mode. + type: boolean + + adi,excitation-current-microamp: + description: + Excitation current applied to the copper trace. Not used in + sub-ohm mode. The datasheet recommends 1mA for copper trace + sensors due to their typically small resistance. + enum: [5, 10, 25, 50, 100, 250, 500, 1000] + default: 1000 + + adi,custom-copper-trace: + description: + Resistance-to-temperature table for copper trace sensors with + resistance > 1 ohm. Required when adi,copper-trace-sub-ohm is not + set. See Page 36 of the datasheet. + $ref: /schemas/types.yaml#/definitions/uint64-matrix + minItems: 3 + maxItems: 64 + items: + items: + - description: Resistance point in uOhms. + - description: Temperature point in uK. + + required: + - adi,rsense-handle + + allOf: + - if: + required: + - adi,copper-trace-sub-ohm + then: + properties: + adi,custom-copper-trace: false + adi,excitation-current-microamp: false + - if: + not: + required: + - adi,copper-trace-sub-ohm + then: + required: + - adi,custom-copper-trace + + '^leak-detector@': + $ref: '#/$defs/sensor-node' + unevaluatedProperties: false + description: | + Leak detector sensor (some parts only). Outputs resistance in ohms and + a coverage percentage via IIO_COVERAGE (raw/1024 = coverage %). + + properties: + reg: + minimum: 2 + maximum: 20 + + adi,sensor-type: + description: Sensor type for leak detector sensors. + $ref: /schemas/types.yaml#/definitions/uint32 + const: 33 + + adi,rsense-handle: + description: Associated sense resistor sensor. + $ref: /schemas/types.yaml#/definitions/phandle + + adi,excitation-current-nanoamp: + description: + Excitation current applied to the leak detector. The correct value + depends on the electrical characteristics of the liquid being sensed. + For example, 10000 (10µA) is recommended for PG25 (see datasheet + Table 39). + enum: [250, 500, 1000, 5000, 10000, 25000, 50000, 100000, 250000, + 500000, 1000000] + + adi,custom-leak-detector: + description: | + Lookup table mapping resistance to coverage percentage. Entries must + be in ascending resistance order. + $ref: /schemas/types.yaml#/definitions/uint64-matrix + minItems: 3 + maxItems: 64 + items: + items: + - description: Resistance point in uOhms. + - description: Coverage data percentage (0 to 100). + + required: + - adi,rsense-handle + - adi,excitation-current-nanoamp + - adi,custom-leak-detector + '^rsense@': $ref: '#/$defs/sensor-node' unevaluatedProperties: false @@ -477,6 +597,32 @@ allOf: patternProperties: '^temp@': false + - if: + properties: + compatible: + contains: + const: adi,adt7604 + then: + patternProperties: + '^thermocouple@': false + '^diode@': false + '^adc@': false + '^temp@': false + '^rtd@': + properties: + adi,sensor-type: + not: + const: 18 + '^thermistor@': + properties: + adi,sensor-type: + not: + const: 27 + else: + patternProperties: + '^copper-trace@': false + '^leak-detector@': false + examples: - | #include @@ -556,4 +702,69 @@ examples: }; }; }; + + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + + temperature-sensor@0 { + compatible = "adi,adt7604"; + reg = <0>; + interrupt-parent = <&gpio>; + interrupts = <25 IRQ_TYPE_EDGE_RISING>; + + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <&supply>; + + trace_rsense: rsense@2 { + reg = <2>; + adi,sensor-type = <29>; + adi,rsense-val-milli-ohms = <100000>; // 100 ohm + }; + + copper-trace@4 { + reg = <4>; + adi,sensor-type = <32>; + adi,rsense-handle = <&trace_rsense>; + adi,copper-trace-sub-ohm; + }; + + r_sense: rsense@12 { + reg = <12>; + adi,sensor-type = <29>; + adi,rsense-val-milli-ohms = <1000000>; // 1 kohm + }; + + leak-detector@14 { + reg = <14>; + adi,sensor-type = <33>; + adi,rsense-handle = <&r_sense>; + adi,excitation-current-nanoamp = <10000>; + adi,custom-leak-detector = + /bits/ 64 < 0 100>, + /bits/ 64 < 202020000 99>, + /bits/ 64 < 285710000 70>, + /bits/ 64 < 333330000 60>, + /bits/ 64 < 400000000 50>, + /bits/ 64 < 500000000 40>, + /bits/ 64 < 666670000 30>, + /bits/ 64 < 1000000000 20>, + /bits/ 64 < 2000000000 10>, + /bits/ 64 <1000000000000 0>; + }; + + rtd@18 { + reg = <18>; + adi,sensor-type = <12>; // PT100 + adi,rsense-handle = <&r_sense>; + adi,number-of-wires = <2>; + adi,rsense-share; + adi,excitation-current-microamp = <500>; + adi,rtd-curve = <0>; + }; + }; + }; ... diff --git a/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml b/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml index 9bf07acea59994..26ea78df27c4c3 100644 --- a/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml +++ b/Documentation/devicetree/bindings/input/atmel,maxtouch.yaml @@ -88,8 +88,7 @@ properties: - 2 # ATMEL_MXT_WAKEUP_GPIO default: 0 - wakeup-source: - type: boolean + wakeup-source: true required: - compatible diff --git a/Documentation/devicetree/bindings/input/imx-keypad.yaml b/Documentation/devicetree/bindings/input/imx-keypad.yaml index b110eb1f3358ae..175256cb1295a3 100644 --- a/Documentation/devicetree/bindings/input/imx-keypad.yaml +++ b/Documentation/devicetree/bindings/input/imx-keypad.yaml @@ -66,20 +66,20 @@ examples: clocks = <&clks 0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_kpp_1>; - linux,keymap = <0x00000067 /* KEY_UP */ - 0x0001006c /* KEY_DOWN */ - 0x00020072 /* KEY_VOLUMEDOWN */ - 0x00030066 /* KEY_HOME */ - 0x0100006a /* KEY_RIGHT */ - 0x01010069 /* KEY_LEFT */ - 0x0102001c /* KEY_ENTER */ - 0x01030073 /* KEY_VOLUMEUP */ - 0x02000040 /* KEY_F6 */ - 0x02010042 /* KEY_F8 */ - 0x02020043 /* KEY_F9 */ - 0x02030044 /* KEY_F10 */ - 0x0300003b /* KEY_F1 */ - 0x0301003c /* KEY_F2 */ - 0x0302003d /* KEY_F3 */ - 0x03030074>; /* KEY_POWER */ + linux,keymap = <0x00000067 /* KEY_UP */ + 0x0001006c /* KEY_DOWN */ + 0x00020072 /* KEY_VOLUMEDOWN */ + 0x00030066 /* KEY_HOME */ + 0x0100006a /* KEY_RIGHT */ + 0x01010069 /* KEY_LEFT */ + 0x0102001c /* KEY_ENTER */ + 0x01030073 /* KEY_VOLUMEUP */ + 0x02000040 /* KEY_F6 */ + 0x02010042 /* KEY_F8 */ + 0x02020043 /* KEY_F9 */ + 0x02030044 /* KEY_F10 */ + 0x0300003b /* KEY_F1 */ + 0x0301003c /* KEY_F2 */ + 0x0302003d /* KEY_F3 */ + 0x03030074>; /* KEY_POWER */ }; diff --git a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml index b95435bd6a9b5f..140a862ecfbeb3 100644 --- a/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml +++ b/Documentation/devicetree/bindings/input/mediatek,pmic-keys.yaml @@ -23,14 +23,19 @@ description: | properties: compatible: - enum: - - mediatek,mt6323-keys - - mediatek,mt6328-keys - - mediatek,mt6331-keys - - mediatek,mt6357-keys - - mediatek,mt6358-keys - - mediatek,mt6359-keys - - mediatek,mt6397-keys + oneOf: + - enum: + - mediatek,mt6323-keys + - mediatek,mt6328-keys + - mediatek,mt6331-keys + - mediatek,mt6357-keys + - mediatek,mt6358-keys + - mediatek,mt6359-keys + - mediatek,mt6397-keys + - items: + - enum: + - mediatek,mt6365-keys + - const: mediatek,mt6359-keys power-off-time-sec: true diff --git a/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml b/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml index 7ade03f1b32b81..2d762193f1c078 100644 --- a/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml +++ b/Documentation/devicetree/bindings/input/microchip,cap11xx.yaml @@ -197,12 +197,12 @@ examples: microchip,sensitivity-delta-sense = <16>; microchip,input-threshold = <21>, <18>, <46>, <46>, <46>, <21>; - linux,keycodes = <103>, /* KEY_UP */ - <106>, /* KEY_RIGHT */ - <108>, /* KEY_DOWN */ - <105>, /* KEY_LEFT */ - <109>, /* KEY_PAGEDOWN */ - <104>; /* KEY_PAGEUP */ + linux,keycodes = <103>, /* KEY_UP */ + <106>, /* KEY_RIGHT */ + <108>, /* KEY_DOWN */ + <105>, /* KEY_LEFT */ + <109>, /* KEY_PAGEDOWN */ + <104>; /* KEY_PAGEUP */ #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml b/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml index 12256ae7df90db..64c4f24ea3dd05 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml @@ -40,6 +40,10 @@ properties: vdd-supply: description: Power supply + reset-gpios: + description: Reset GPIO (active-low) + maxItems: 1 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/input/touchscreen/ti,ads7843.yaml b/Documentation/devicetree/bindings/input/touchscreen/ti,ads7843.yaml index 8f6335d7da1c53..1b58fc263dce8c 100644 --- a/Documentation/devicetree/bindings/input/touchscreen/ti,ads7843.yaml +++ b/Documentation/devicetree/bindings/input/touchscreen/ti,ads7843.yaml @@ -165,9 +165,9 @@ examples: touchscreen@0 { compatible = "ti,tsc2046"; - reg = <0>; /* CS0 */ + reg = <0>; /* CS0 */ interrupt-parent = <&gpio1>; - interrupts = <8 0>; /* BOOT6 / GPIO 8 */ + interrupts = <8 0>; /* BOOT6 / GPIO 8 */ pendown-gpio = <&gpio1 8 0>; spi-max-frequency = <1000000>; vcc-supply = <®_vcc3>; diff --git a/Documentation/devicetree/bindings/input/touchscreen/wacom,w9007a-lt03.yaml b/Documentation/devicetree/bindings/input/touchscreen/wacom,w9007a-lt03.yaml new file mode 100644 index 00000000000000..6d1da6a435d39e --- /dev/null +++ b/Documentation/devicetree/bindings/input/touchscreen/wacom,w9007a-lt03.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/input/touchscreen/wacom,w9007a-lt03.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wacom W9000-series penabled I2C touchscreen + +maintainers: + - Hendrik Noack + +description: | + The W9000-series are penabled touchscreen controllers by Wacom. + + The firmware of controllers in different devices may differ. This can also + affect the controller's behavior. + +allOf: + - $ref: touchscreen.yaml# + +properties: + compatible: + enum: + - wacom,w9002 + - wacom,w9007a-lt03 + - wacom,w9007a-v1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vdd-supply: true + + flash-mode-gpios: + maxItems: 1 + + reset-gpios: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + digitizer@56 { + compatible = "wacom,w9007a-lt03"; + reg = <0x56>; + interrupt-parent = <&gpd1>; + interrupts = <1 IRQ_TYPE_EDGE_RISING>; + + vdd-supply = <&stylus_reg>; + + flash-mode-gpios = <&gpd1 3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpx0 1 GPIO_ACTIVE_LOW>; + + touchscreen-x-mm = <216>; + touchscreen-y-mm = <135>; + touchscreen-inverted-x; + }; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml new file mode 100644 index 00000000000000..49a2dca5db62a5 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,hawi-rpmh.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,hawi-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Hawi + +maintainers: + - Vivek Aknurwar + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,hawi-rpmh.h + +properties: + compatible: + enum: + - qcom,hawi-aggre1-noc + - qcom,hawi-clk-virt + - qcom,hawi-cnoc-main + - qcom,hawi-gem-noc + - qcom,hawi-llclpi-noc + - qcom,hawi-lpass-ag-noc + - qcom,hawi-lpass-lpiaon-noc + - qcom,hawi-lpass-lpicx-noc + - qcom,hawi-mc-virt + - qcom,hawi-mmss-noc + - qcom,hawi-nsp-noc + - qcom,hawi-pcie-anoc + - qcom,hawi-stdst-cfg + - qcom,hawi-stdst-main + - qcom,hawi-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 2 + maxItems: 3 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-clk-virt + - qcom,hawi-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-pcie-anoc + then: + properties: + clocks: + items: + - description: aggre-NOC PCIe AXI clock + - description: cfg-NOC PCIe a-NOC AHB clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-aggre1-noc + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB3 PRIM AXI clock + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,hawi-aggre1-noc + - qcom,hawi-pcie-anoc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + clk_virt: interconnect-0 { + compatible = "qcom,hawi-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre_noc: interconnect@f00000 { + compatible = "qcom,hawi-aggre1-noc"; + reg = <0x0 0xf00000 0x0 0x54400>; + #interconnect-cells = <2>; + clocks = <&gcc_aggre_ufs_phy_axi_clk>, + <&gcc_aggre_usb3_prim_axi_clk>, + <&rpmhcc_ipa_clk>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml index ce79521bb1ef2c..ff64225e828174 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - qcom,glymur-cpu-bwmon + - qcom,hawi-cpu-bwmon - qcom,kaanapali-cpu-bwmon - qcom,qcm2290-cpu-bwmon - qcom,qcs615-cpu-bwmon @@ -45,6 +46,7 @@ properties: - const: qcom,sdm845-bwmon # BWMON v4, unified register space - items: - enum: + - qcom,hawi-llcc-bwmon - qcom,qcs615-llcc-bwmon - qcom,qcs8300-llcc-bwmon - qcom,sa8775p-llcc-bwmon diff --git a/Documentation/devicetree/bindings/interconnect/qcom,nord-rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,nord-rpmh.yaml new file mode 100644 index 00000000000000..3650d3d5b9185f --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,nord-rpmh.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,nord-rpmh.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm RPMh Network-On-Chip Interconnect on Nord + +maintainers: + - Odelu Kukatla + +description: | + RPMh interconnect providers support system bandwidth requirements through + RPMh hardware accelerators known as Bus Clock Manager (BCM). The provider is + able to communicate with the BCM through the Resource State Coordinator (RSC) + associated with each execution environment. Provider nodes must point to at + least one RPMh device child node pertaining to their RSC and each provider + can map to multiple RPMh resources. + + See also: include/dt-bindings/interconnect/qcom,nord-rpmh.h + +properties: + compatible: + enum: + - qcom,nord-aggre1-noc + - qcom,nord-aggre1-noc-tile + - qcom,nord-aggre2-noc + - qcom,nord-aggre2-noc-tile + - qcom,nord-clk-virt + - qcom,nord-cnoc-cfg + - qcom,nord-cnoc-main + - qcom,nord-hpass-ag-noc + - qcom,nord-hscnoc + - qcom,nord-mc-virt + - qcom,nord-mmss-noc + - qcom,nord-nsp-data-noc-0 + - qcom,nord-nsp-data-noc-1 + - qcom,nord-nsp-data-noc-2 + - qcom,nord-nsp-data-noc-3 + - qcom,nord-pcie-cfg + - qcom,nord-pcie-data-inbound + - qcom,nord-pcie-data-outbound + - qcom,nord-system-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + +required: + - compatible + +allOf: + - $ref: qcom,rpmh-common.yaml# + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-clk-virt + - qcom,nord-mc-virt + then: + properties: + reg: false + else: + required: + - reg + + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-aggre1-noc-tile + then: + properties: + clocks: + items: + - description: aggre UFS PHY AXI clock + - description: aggre USB2 AXI clock + - description: aggre USB3 PRIM AXI clock + - description: aggre USB3 SEC AXI clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-aggre2-noc + then: + properties: + clocks: + items: + - description: RPMH CC IPA clock + + - if: + properties: + compatible: + contains: + enum: + - qcom,nord-aggre1-noc-tile + - qcom,nord-aggre2-noc + then: + required: + - clocks + else: + properties: + clocks: false + +unevaluatedProperties: false + +examples: + - | + clk_virt: interconnect-clk-virt { + compatible = "qcom,nord-clk-virt"; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + }; + + aggre1_noc_tile: interconnect@1720000 { + compatible = "qcom,nord-aggre1-noc-tile"; + reg = <0x01720000 0x23400>; + #interconnect-cells = <2>; + qcom,bcm-voters = <&apps_bcm_voter>; + clocks = <&ne_gcc_aggre_noc_ufs_phy_axi_clk>, + <&ne_gcc_aggre_noc_usb2_axi_clk>, + <&ne_gcc_aggre_noc_usb3_prim_axi_clk>, + <&ne_gcc_aggre_noc_usb3_sec_axi_clk>; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml index 8f6bc6399626b6..51428a2b0ce099 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sdm660.yaml @@ -79,6 +79,19 @@ allOf: - const: aggre2_usb3_axi - const: cfg_noc_usb2_axi + - if: + properties: + compatible: + enum: + - qcom,sdm660-bimc + - qcom,sdm660-cnoc + - qcom,sdm660-gnoc + - qcom,sdm660-snoc + then: + properties: + clocks: false + clock-names: false + examples: - | #include diff --git a/Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml b/Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml new file mode 100644 index 00000000000000..a0c26de94ccf70 --- /dev/null +++ b/Documentation/devicetree/bindings/interconnect/qcom,shikra.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,shikra.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Shikra Network-On-Chip interconnect + +maintainers: + - Raviteja Laggyshetty + +description: + The Qualcomm Shikra interconnect providers support adjusting the + bandwidth requirements between the various NoC fabrics. + +properties: + compatible: + enum: + - qcom,shikra-config-noc + - qcom,shikra-mem-noc-core + - qcom,shikra-sys-noc + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 4 + + clock-names: + minItems: 1 + maxItems: 4 + +# Child node's properties +patternProperties: + '^interconnect-[a-z0-9]+$': + type: object + description: + The interconnect providers do not have a separate QoS register space, + but share parent's space. + + $ref: qcom,rpm-common.yaml# + + properties: + compatible: + enum: + - qcom,shikra-clk-virt + - qcom,shikra-mc-virt + - qcom,shikra-mmrt-virt + - qcom,shikra-mmnrt-virt + + required: + - compatible + + unevaluatedProperties: false + +required: + - compatible + - reg + +allOf: + - $ref: qcom,rpm-common.yaml# + - if: + properties: + compatible: + const: qcom,shikra-mem-noc-core + + then: + properties: + clocks: + items: + - description: GPU-NoC AXI clock + + clock-names: + items: + - const: gpu_axi + patternProperties: + '^interconnect-[a-z0-9]+$': false + + - if: + properties: + compatible: + const: qcom,shikra-sys-noc + + then: + properties: + clocks: + items: + - description: EMAC0-NoC AXI clock. + - description: EMAC1-NoC AXI clock. + - description: USB2-NoC AXI clock. + - description: USB3-NoC AXI clock. + + clock-names: + items: + - const: emac0_axi + - const: emac1_axi + - const: usb2_axi + - const: usb3_axi + + - if: + properties: + compatible: + const: qcom,shikra-config-noc + + then: + properties: + clocks: false + clock-names: false + patternProperties: + '^interconnect-[a-z0-9]+$': false + +unevaluatedProperties: false + +examples: + - | + interconnect@1880000 { + compatible = "qcom,shikra-sys-noc"; + reg = <0x01880000 0x6a080>; + #interconnect-cells = <2>; + clocks = <&gcc_emac0_axi_sys_noc_clk>, + <&gcc_emac1_axi_sys_noc_clk>, + <&gcc_sys_noc_usb2_prim_axi_clk>, + <&gcc_sys_noc_usb3_prim_axi_clk>; + clock-names = "emac0_axi", + "emac1_axi", + "usb2_axi", + "usb3_axi"; + + interconnect-clk { + compatible = "qcom,shikra-clk-virt"; + #interconnect-cells = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml b/Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml index 14b1a0b08e736e..cdae0acf3a1da4 100644 --- a/Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml +++ b/Documentation/devicetree/bindings/interconnect/qcom,sm6115.yaml @@ -62,23 +62,33 @@ allOf: - if: properties: compatible: - const: qcom,sm6115-cnoc + const: qcom,sm6115-bimc + then: + properties: + clocks: false + clock-names: false + patternProperties: + '^interconnect-[a-z0-9]+$': false + - if: + properties: + compatible: + const: qcom,sm6115-cnoc then: properties: clocks: items: - description: USB-NoC AXI clock - clock-names: items: - const: usb_axi + patternProperties: + '^interconnect-[a-z0-9]+$': false - if: properties: compatible: const: qcom,sm6115-snoc - then: properties: clocks: @@ -87,7 +97,6 @@ allOf: - description: UFS-NoC AXI clock. - description: USB-NoC AXI clock. - description: IPA clock. - clock-names: items: - const: cpu_axi @@ -95,20 +104,6 @@ allOf: - const: usb_axi - const: ipa - - if: - properties: - compatible: - enum: - - qcom,sm6115-bimc - - qcom,sm6115-clk-virt - - qcom,sm6115-mmrt-virt - - qcom,sm6115-mmnrt-virt - - then: - properties: - clocks: false - clock-names: false - unevaluatedProperties: false examples: @@ -149,4 +144,6 @@ examples: compatible = "qcom,sm6115-cnoc"; reg = <0x01900000 0x8200>; #interconnect-cells = <1>; + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>; + clock-names = "usb_axi"; }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml index d0fad930de9d9b..d26671913e8959 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/amlogic,meson-gpio-intc.yaml @@ -38,6 +38,8 @@ properties: - amlogic,a4-gpio-intc - amlogic,a4-gpio-ao-intc - amlogic,a5-gpio-intc + - amlogic,a9-gpio-intc + - amlogic,a9-gpio-ao-intc - amlogic,c3-gpio-intc - amlogic,s6-gpio-intc - amlogic,s7-gpio-intc @@ -56,7 +58,7 @@ properties: amlogic,channel-interrupts: description: Array with the upstream hwirq numbers minItems: 2 - maxItems: 12 + maxItems: 20 $ref: /schemas/types.yaml#/definitions/uint32-array required: @@ -76,9 +78,20 @@ then: amlogic,channel-interrupts: maxItems: 2 else: - properties: - amlogic,channel-interrupts: - minItems: 8 + if: + properties: + compatible: + contains: + const: amlogic,a9-gpio-ao-intc + then: + properties: + amlogic,channel-interrupts: + minItems: 20 + else: + properties: + amlogic,channel-interrupts: + minItems: 8 + maxItems: 12 additionalProperties: false diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml deleted file mode 100644 index 258d21fe6e359f..00000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-intc.yaml +++ /dev/null @@ -1,90 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-intc.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Aspeed AST2700 Interrupt Controller - -description: - This interrupt controller hardware is second level interrupt controller that - is hooked to a parent interrupt controller. It's useful to combine multiple - interrupt sources into 1 interrupt to parent interrupt controller. - -maintainers: - - Kevin Chen - -properties: - compatible: - enum: - - aspeed,ast2700-intc-ic - - reg: - maxItems: 1 - - interrupt-controller: true - - '#interrupt-cells': - const: 1 - description: - The first cell is the IRQ number, the second cell is the trigger - type as defined in interrupt.txt in this directory. - - interrupts: - minItems: 1 - maxItems: 10 - description: | - Depend to which INTC0 or INTC1 used. - INTC0 and INTC1 are two kinds of interrupt controller with enable and raw - status registers for use. - INTC0 is used to assert GIC if interrupt in INTC1 asserted. - INTC1 is used to assert INTC0 if interrupt of modules asserted. - +-----+ +-------+ +---------+---module0 - | GIC |---| INTC0 |--+--| INTC1_0 |---module2 - | | | | | | |---... - +-----+ +-------+ | +---------+---module31 - | - | +---------+---module0 - +---| INTC1_1 |---module2 - | | |---... - | +---------+---module31 - ... - | +---------+---module0 - +---| INTC1_5 |---module2 - | |---... - +---------+---module31 - -required: - - compatible - - reg - - interrupt-controller - - '#interrupt-cells' - - interrupts - -additionalProperties: false - -examples: - - | - #include - - bus { - #address-cells = <2>; - #size-cells = <2>; - - interrupt-controller@12101b00 { - compatible = "aspeed,ast2700-intc-ic"; - reg = <0 0x12101b00 0 0x10>; - #interrupt-cells = <1>; - interrupt-controller; - interrupts = , - , - , - , - , - , - , - , - , - ; - }; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml new file mode 100644 index 00000000000000..a62f0fd2435ba1 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2700-interrupt.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2700-interrupt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 Interrupt Controllers (INTC0/INTC1) + +description: | + The ASPEED AST2700 SoC integrates two interrupt controller designs: + + - INTC0: Primary controller that routes interrupt sources to upstream, + processor-specific interrupt controllers + + - INTC1: Secondary controller whose interrupt outputs feed into INTC0 + + The SoC contains four processors to which interrupts can be routed: + + - PSP: Primary Service Processor (Cortex-A35) + - SSP: Secondary Service Processor (Cortex-M4) + - TSP: Tertiary Service Processor (Cortex-M4) + - BMCU: Boot MCU (a RISC-V microcontroller) + + The following diagram illustrates the overall architecture of the + ASPEED AST2700 interrupt controllers: + + +-----------+ +-----------+ + | INTC0 | | INTC1(0) | + +-----------+ +-----------+ + | Router | +-----------+ | Router | + | out int | +Peripheral + | out int | + +-----------+ | 0 0 <-+Controllers+ | INTM | +-----------+ + |PSP GIC <-|---+ . . | +-----------+ | . . <-+Peripheral + + +-----------+ | . . | | . . | +Controllers+ + +-----------+ | . . | | . . | +-----------+ + |SSP NVIC <-|---+ . . <----------------+ . . | + +-----------+ | . . | | . . | + +-----------+ | . . <-------- | . . | + |TSP NVIC <-|---+ . . | | ----+ . . | + +-----------+ | . . | | | | O P | + | . . | | | +-----------+ + | . . <---- | -------------------- + | . . | | | +-----------+ | + | M N | | ---------+ INTC1(1) | | + +-----------+ | +-----------+ | + | . | + | +-----------+ | + -------------+ INTC1(N) | | + +-----------+ | + +--------------+ | + + BMCU APLIC <-+--------------------------------------------- + +--------------+ + + INTC0 supports: + - 128 local peripheral interrupt inputs + - Fan-in from up to three INTC1 instances via banked interrupt lines (INTM) + - Local peripheral interrupt outputs + - Merged interrupt outputs + - Software interrupt outputs (SWINT) + - Configurable interrupt routes targeting the PSP, SSP, and TSP + + INTC1 supports: + - 192 local peripheral interrupt inputs + - Banked interrupt outputs (INTM, 5 x 6 banks x 32 interrupts per bank) + - Configurable interrupt routes targeting the PSP, SSP, TSP, and BMCU + + One INTC1 instance is always present, on the SoC's IO die. A further two + instances may be attached to the SoC's one INTC0 instance via LTPI (LVDS + Tunneling Protocol & Interface). + + Interrupt numbering model + ------------------------- + The binding uses a controller-local numbering model. Peripheral device + nodes use the INTCx local interrupt number (hwirq) in their 'interrupts' or + 'interrupts-extended' properties. + + For AST2700, INTC0 exposes the following (inclusive) input ranges: + + - 000..479: Independent interrupts + - 480..489: INTM0-INTM9 + - 490..499: INTM10-INTM19 + - 500..509: INTM20-INTM29 + - 510..519: INTM30-INTM39 + - 520..529: INTM40-INTM49 + + INTC0's (inclusive) output ranges are as follows: + + - 000..127: 1:1 local peripheral interrupt output to PSP + - 144..151: Software interrupts from the SSP output to PSP + - 152..159: Software interrupts from the TSP output to PSP + - 192..201: INTM0-INTM9 banked outputs to PSP + - 208..217: INTM30-INTM39 banked outputs to PSP + - 224..233: INTM40-INTM49 banked outputs to PSP + - 256..383: 1:1 local peripheral interrupt output to SSP + - 384..393: INTM10-INTM19 banked outputs to SSP + - 400..407: Software interrupts from the PSP output to SSP + - 408..415: Software interrupts from the TSP output to SSP + - 426..553: 1:1 local peripheral interrupt output to TSP + - 554..563: INTM20-INTM29 banked outputs to TSP + - 570..577: Software interrupts from the PSP output to TSP + - 578..585: Software interrupts from the SSP output to TSP + + Inputs and outputs for INTC1 instances are context-dependent. However, for the + first instance of INTC1, the (inclusive) output ranges are: + + - 00..05: INTM0-INTM5 + - 10..15: INTM10-INTM15 + - 20..25: INTM20-INTM25 + - 30..35: INTM30-INTM35 + - 40..45: INTM40-INTM45 + - 50..50: BootMCU + +maintainers: + - Ryan Chen + - Andrew Jeffery + +properties: + compatible: + enum: + - aspeed,ast2700-intc0 + - aspeed,ast2700-intc1 + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 1 + description: Single cell encoding the INTC local interrupt number (hwirq). + + aspeed,interrupt-ranges: + description: | + Describes how ranges of controller output pins are routed to a parent + interrupt controller. + + Each range entry is encoded as: + + + + where: + - out: First controller interrupt output index in the range. + - count: Number of consecutive controller interrupt outputs and parent + interrupt inputs in this range. + - phandle: Phandle to the parent interrupt controller node. + - parent-specifier: Interrupt specifier, as defined by the parent + interrupt controller binding. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 3 + items: + description: Range descriptors with a parent interrupt specifier. + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - aspeed,interrupt-ranges + +additionalProperties: false + +examples: + - | + #include + + interrupt-controller@12100000 { + compatible = "aspeed,ast2700-intc0"; + reg = <0x12100000 0x3b00>; + interrupt-parent = <&gic>; + interrupt-controller; + #interrupt-cells = <1>; + + aspeed,interrupt-ranges = + <0 128 &gic GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, + <144 8 &gic GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <152 8 &gic GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <192 10 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, + <208 10 &gic GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, + <224 10 &gic GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>, + <256 128 &ssp_nvic 0 0>, + <384 10 &ssp_nvic 160 0>, + <400 8 &ssp_nvic 144 0>, + <408 8 &ssp_nvic 152 0>, + <426 128 &tsp_nvic 0 0>, + <554 10 &tsp_nvic 160 0>, + <570 8 &tsp_nvic 144 0>, + <578 8 &tsp_nvic 152 0>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml index 5536319c49c31a..44c09785e6bb62 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/econet,en751221-intc.yaml @@ -52,6 +52,25 @@ properties: - description: primary per-CPU IRQ - description: shadow IRQ number + econet,cpu-interrupt-map: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + When running in VEIC mode, the hardware re-routes interrupts from the + CPU interrupt controller core to the "external" interrupt controller + (this device). It then prioritizes them and sends them back to the CPU + along with its own interrupts. The CPU hardware handles interrupts using + a special dispatch table (the normal interrupt handler is not invoked). + In this interrupt controller, the CPU interrupts are renumbered as they + are merged with this controller's own hardware interrupts. + + This is the inverse of an interrupt-map, mapping which interrupts from + this controller must be routed back to the CPU interrupt domain for + correct handling there. + items: + items: + - description: The interrupt number as received in this controller + - description: The interrupt number to be dispatched on the CPU intc + required: - compatible - reg @@ -74,5 +93,6 @@ examples: interrupts = <2>; econet,shadow-interrupts = <7 2>, <8 3>, <13 12>, <30 29>; + econet,cpu-interrupt-map = <7 0>, <8 1>; }; ... diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index b4942881b9c963..8162a49d49a669 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -30,7 +30,9 @@ properties: - qcom,glymur-pdc - qcom,hawi-pdc - qcom,kaanapali-pdc + - qcom,maili-pdc - qcom,milos-pdc + - qcom,nord-pdc - qcom,qcs615-pdc - qcom,qcs8300-pdc - qcom,qdu1000-pdc diff --git a/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml index 78c01d14e76572..a809bc4f75159c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/renesas,r9a09g077-icu.yaml @@ -165,7 +165,7 @@ examples: icu: interrupt-controller@802a0000 { compatible = "renesas,r9a09g077-icu"; reg = <0x802a0000 0x10000>, - <0x812a0000 0x50>; + <0x812a0000 0x10000>; #interrupt-cells = <2>; #address-cells = <0>; interrupt-controller; diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index e0267223887ec2..decc43df3c839c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -73,6 +73,7 @@ properties: - allwinner,sun20i-d1-plic - sophgo,cv1800b-plic - sophgo,cv1812h-plic + - sophgo,sg2000-plic - sophgo,sg2002-plic - sophgo,sg2042-plic - sophgo,sg2044-plic diff --git a/Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml deleted file mode 100644 index ada5788602d65e..00000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/starfive,jh8100-intc.yaml +++ /dev/null @@ -1,61 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/interrupt-controller/starfive,jh8100-intc.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: StarFive External Interrupt Controller - -description: - StarFive SoC JH8100 contain a external interrupt controller. It can be used - to handle high-level input interrupt signals. It also send the output - interrupt signal to RISC-V PLIC. - -maintainers: - - Changhuang Liang - -properties: - compatible: - const: starfive,jh8100-intc - - reg: - maxItems: 1 - - clocks: - description: APB clock for the interrupt controller - maxItems: 1 - - resets: - description: APB reset for the interrupt controller - maxItems: 1 - - interrupts: - maxItems: 1 - - interrupt-controller: true - - "#interrupt-cells": - const: 1 - -required: - - compatible - - reg - - clocks - - resets - - interrupts - - interrupt-controller - - "#interrupt-cells" - -additionalProperties: false - -examples: - - | - interrupt-controller@12260000 { - compatible = "starfive,jh8100-intc"; - reg = <0x12260000 0x10000>; - clocks = <&syscrg_ne 76>; - resets = <&syscrg_ne 13>; - interrupts = <45>; - interrupt-controller; - #interrupt-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml new file mode 100644 index 00000000000000..d8a0a3862ae2c0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/starfive,jhb100-intc.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/starfive,jhb100-intc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive External Interrupt Controller + +description: + StarFive SoC JHB100 contain a external interrupt controller. It can be used + to handle high-level input interrupt signals. It also send the output + interrupt signal to RISC-V PLIC. + +maintainers: + - Changhuang Liang + +properties: + compatible: + const: starfive,jhb100-intc + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 1 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - "#interrupt-cells" + +additionalProperties: false + +examples: + - | + interrupt-controller@12260000 { + compatible = "starfive,jhb100-intc"; + reg = <0x12260000 0x10000>; + interrupts = <45>; + interrupt-controller; + #interrupt-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/ti,irq-crossbar.yaml b/Documentation/devicetree/bindings/interrupt-controller/ti,irq-crossbar.yaml new file mode 100644 index 00000000000000..a919db1d064524 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/ti,irq-crossbar.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/ti,irq-crossbar.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments IRQ Crossbar + +maintainers: + - Sricharan R + +description: + Some socs have a large number of interrupts requests to service the needs of + its many peripherals and subsystems. All of the interrupt lines from the + subsystems are not needed at the same time, so they have to be muxed to the + irq-controller appropriately. In such places a interrupt controllers are + preceded by an CROSSBAR that provides flexibility in muxing the device + requests to the controller inputs. + +properties: + compatible: + const: ti,irq-crossbar + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 3 + + ti,max-irqs: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Total number of irqs available at the parent interrupt controller. + minimum: 1 + + ti,max-crossbar-sources: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum number of crossbar sources that can be routed. + minimum: 1 + + ti,reg-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of a individual register in bytes. Every individual + register is assumed to be of same size. + enum: [1, 2, 4] + + ti,irqs-reserved: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + List of the reserved irq lines that are not muxed using crossbar. These + interrupt lines are reserved in the soc, so crossbar bar driver should not + consider them as free lines. + + ti,irqs-skip: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + Similar to "ti,irqs-reserved", but these are for SOC-specific hard-wiring + of those irqs which unexpectedly bypasses the crossbar. These irqs have a + crossbar register, but still cannot be used. + + ti,irqs-safe-map: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + integer which maps to a safe configuration to use when the interrupt + controller irq is unused. + default: 0 + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - ti,max-irqs + - ti,max-crossbar-sources + - ti,reg-size + - ti,irqs-reserved + +additionalProperties: false + +examples: + - | + crossbar@4a002a48 { + compatible = "ti,irq-crossbar"; + reg = <0x4a002a48 0x130>; + interrupt-controller; + #interrupt-cells = <3>; + ti,max-irqs = <160>; + ti,max-crossbar-sources = <400>; + ti,reg-size = <2>; + ti,irqs-reserved = <0 1 2 3 5 6 131 132>; + ti,irqs-skip = <10 133 139 140>; + }; diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 06fb5c8e7547cb..a701dec2fa0a4a 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -37,8 +37,10 @@ properties: - enum: - qcom,eliza-smmu-500 - qcom,glymur-smmu-500 + - qcom,hawi-smmu-500 - qcom,kaanapali-smmu-500 - qcom,milos-smmu-500 + - qcom,nord-smmu-500 - qcom,qcm2290-smmu-500 - qcom,qcs615-smmu-500 - qcom,qcs8300-smmu-500 @@ -55,6 +57,7 @@ properties: - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 - qcom,sdx75-smmu-500 + - qcom,shikra-smmu-500 - qcom,sm6115-smmu-500 - qcom,sm6125-smmu-500 - qcom,sm6350-smmu-500 @@ -566,7 +569,11 @@ allOf: properties: compatible: items: - - const: qcom,sm8750-smmu-500 + - enum: + - qcom,glymur-smmu-500 + - qcom,hawi-smmu-500 + - qcom,kaanapali-smmu-500 + - qcom,sm8750-smmu-500 - const: qcom,adreno-smmu - const: qcom,smmu-500 - const: arm,mmu-500 @@ -595,6 +602,7 @@ allOf: - qcom,sdm845-smmu-500 - qcom,sdx55-smmu-500 - qcom,sdx65-smmu-500 + - qcom,sdx75-smmu-500 - qcom,sm6350-smmu-500 - qcom,sm6375-smmu-500 then: @@ -602,6 +610,40 @@ allOf: clock-names: false clocks: false + # Disallow clocks for all other platforms where specific compatible is used + # with different fallbacks and only one combination has no clocks + - if: + properties: + compatible: + items: + - enum: + - qcom,eliza-smmu-500 + - qcom,glymur-smmu-500 + - qcom,hawi-smmu-500 + - qcom,kaanapali-smmu-500 + - qcom,milos-smmu-500 + - qcom,nord-smmu-500 + - qcom,qcs615-smmu-500 + - qcom,qcs8300-smmu-500 + - qcom,sa8775p-smmu-500 + - qcom,shikra-smmu-500 + - qcom,sm6115-smmu-500 + - qcom,sm6125-smmu-500 + - qcom,sm8150-smmu-500 + - qcom,sm8250-smmu-500 + - qcom,sm8350-smmu-500 + - qcom,sm8450-smmu-500 + - qcom,sm8550-smmu-500 + - qcom,sm8650-smmu-500 + - qcom,sm8750-smmu-500 + - qcom,x1e80100-smmu-500 + - const: qcom,smmu-500 + - const: arm,mmu-500 + then: + properties: + clock-names: false + clocks: false + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml index d4838c3b3741f0..f83efb3ee00002 100644 --- a/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/riscv,iommu.yaml @@ -32,22 +32,35 @@ properties: # should be specified along with 'reg' property providing MMIO location. compatible: oneOf: - - items: + - description: Platform (non-PCIe) IOMMU implementations + items: - enum: - qemu,riscv-iommu + - tenstorrent,riscv-iommu - const: riscv,iommu - - items: + - description: PCIe IOMMU implementations + items: - enum: - pci1efd,edf1 - const: riscv,pci-iommu reg: - maxItems: 1 - description: - For non-PCI devices this represents base address and size of for the - IOMMU memory mapped registers interface. - For PCI IOMMU hardware implementation this should represent an address - of the IOMMU, as defined in the PCI Bus Binding reference. + minItems: 1 + items: + - description: + For non-PCI devices, base address and size of the IOMMU memory + mapped registers interface. For PCI IOMMU hardware + implementation, an address of the IOMMU, as defined in the PCI + Bus Binding reference. + - description: + Region containing platform specific MMRs for machine-mode + configuration, such as PMA and PMP registers. + + reg-names: + minItems: 1 + items: + - const: base + - const: machine '#iommu-cells': const: 1 @@ -75,6 +88,26 @@ required: additionalProperties: false +allOf: + - if: + properties: + compatible: + contains: + enum: + - tenstorrent,riscv-iommu + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + else: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + examples: - |+ /* Example 1 (IOMMU device with wired interrupts) */ @@ -145,3 +178,13 @@ examples: }; }; }; + + - |+ + /* Example 5 (Tenstorrent IOMMU device with MSIs) */ + iommu5: iommu@d2020000 { + compatible = "tenstorrent,riscv-iommu", "riscv,iommu"; + reg = <0xd2020000 0x10000>, <0xaa000000 0x10000>; + reg-names = "base", "machine"; + msi-parent = <&imsics_smode>; + #iommu-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/iommu/verisilicon,iommu.yaml b/Documentation/devicetree/bindings/iommu/verisilicon,iommu.yaml new file mode 100644 index 00000000000000..d3ce9e603b61d7 --- /dev/null +++ b/Documentation/devicetree/bindings/iommu/verisilicon,iommu.yaml @@ -0,0 +1,71 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/iommu/verisilicon,iommu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Verisilicon IOMMU + +maintainers: + - Benjamin Gaignard + +description: |+ + A Versilicon iommu translates io virtual addresses to physical addresses for + its associated video decoder. + +properties: + compatible: + items: + - const: rockchip,rk3588-av1-iommu + - const: verisilicon,iommu-1.2 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Core clock + - description: Interface clock + + clock-names: + items: + - const: core + - const: iface + + "#iommu-cells": + const: 0 + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#iommu-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + iommu@fdca0000 { + compatible = "rockchip,rk3588-av1-iommu","verisilicon,iommu-1.2"; + reg = <0x0 0xfdca0000 0x0 0x600>; + interrupts = ; + clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>; + clock-names = "core", "iface"; + #iommu-cells = <0>; + }; + }; diff --git a/Documentation/devicetree/bindings/leds/backlight/maxim,max25014.yaml b/Documentation/devicetree/bindings/leds/backlight/maxim,max25014.yaml new file mode 100644 index 00000000000000..d00be2e0819381 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/backlight/maxim,max25014.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/backlight/maxim,max25014.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim max25014 backlight controller + +maintainers: + - Maud Spierings + +properties: + compatible: + enum: + - maxim,max25014 + + reg: + maxItems: 1 + + default-brightness: + minimum: 0 + maximum: 100 + default: 50 + + enable-gpios: + maxItems: 1 + + interrupts: + maxItems: 1 + + power-supply: + description: Regulator which controls the boost converter input rail. + + pwms: + maxItems: 1 + + maxim,iset: + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 15 + default: 11 + description: + Value of the ISET field in the ISET register. This controls the current + scale of the outputs, a higher number means more current. + + maxim,strings: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + A 4-bit bitfield that describes which led strings to turn on. + minItems: 4 + maxItems: 4 + items: + maximum: 1 + default: + [1 1 1 1] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + backlight@6f { + compatible = "maxim,max25014"; + reg = <0x6f>; + default-brightness = <50>; + enable-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + interrupt-parent = <&gpio1>; + interrupts = <2 IRQ_TYPE_EDGE_FALLING>; + power-supply = <®_backlight>; + pwms = <&pwm1>; + maxim,iset = <7>; + maxim,strings = <1 1 1 0>; + }; + }; diff --git a/Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml b/Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml index 72cadebf6e3e35..0297bfbb2750d2 100644 --- a/Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml +++ b/Documentation/devicetree/bindings/leds/irled/ir-spi-led.yaml @@ -25,7 +25,7 @@ properties: duty-cycle: $ref: /schemas/types.yaml#/definitions/uint8 - enum: [50, 60, 70, 75, 80, 90] + enum: [30, 50, 60, 70, 75, 80, 90] description: Percentage of one period in which the signal is active. diff --git a/Documentation/devicetree/bindings/leds/leds-lp55xx.yaml b/Documentation/devicetree/bindings/leds/leds-lp55xx.yaml index fe8aaecf301081..67637efac37838 100644 --- a/Documentation/devicetree/bindings/leds/leds-lp55xx.yaml +++ b/Documentation/devicetree/bindings/leds/leds-lp55xx.yaml @@ -183,7 +183,7 @@ examples: compatible = "ti,lp8501"; reg = <0x32>; clock-mode = /bits/ 8 <2>; - pwr-sel = /bits/ 8 <3>; /* D1~9 connected to VOUT */ + pwr-sel = /bits/ 8 <3>; /* D1~9 connected to VOUT */ ti,charge-pump-mode = ; led@0 { diff --git a/Documentation/devicetree/bindings/leds/samsung,s2mu005-flash.yaml b/Documentation/devicetree/bindings/leds/samsung,s2mu005-flash.yaml new file mode 100644 index 00000000000000..36051ab20509f1 --- /dev/null +++ b/Documentation/devicetree/bindings/leds/samsung,s2mu005-flash.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/samsung,s2mu005-flash.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Flash and Torch LED Controller for Samsung S2M series PMICs + +maintainers: + - Kaustabh Chakraborty + +description: | + The Samsung S2M series PMIC flash LED has two led channels (typically + as back and front camera flashes), with support for both torch and + flash modes. + + This is a part of device tree bindings for S2M and S5M family of Power + Management IC (PMIC). + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +properties: + compatible: + enum: + - samsung,s2mu005-flash + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^led@[0-1]$": + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + reg: + enum: [0, 1] + + required: + - reg + +required: + - compatible + - "#address-cells" + - "#size-cells" + +additionalProperties: false diff --git a/Documentation/devicetree/bindings/leds/ti,lm3560.yaml b/Documentation/devicetree/bindings/leds/ti,lm3560.yaml new file mode 100644 index 00000000000000..6cf8cf91ab2e2a --- /dev/null +++ b/Documentation/devicetree/bindings/leds/ti,lm3560.yaml @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/ti,lm3560.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI LM3560 Synchronous Boost Flash Driver + +maintainers: + - Svyatoslav Ryhel + +description: + The LM3560 is a 2-MHz fixed frequency synchronous boost converter with two + 1000-mA constant current drivers for high-current white LEDs. The dual high- + side current sources allow for grounded cathode LED operation and can be + tied together for providing flash currents at up to 2 A through a single LED. + An adaptive regulation method ensures the current for each LED remains in + regulation and maximizes efficiency. + +properties: + compatible: + enum: + - ti,lm3559 + - ti,lm3560 + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + enable-gpios: + description: GPIO connected to the HWEN pin. + maxItems: 1 + + vin-supply: + description: Supply connected to the IN line. + + flash-max-timeout-us: + minimum: 32000 + maximum: 1024000 + default: 32000 + + ti,peak-current-microamp: + description: + The LM3560 features 4 selectable current limits 1.6A, 2.3A, 3A, and 3.6A + (in case of LM3559 - 1.4A, 2.1A, 2.7A, and 3.2A). When the current limit + is reached, the LM3559/LM3560 stops switching for the remainder of the + switching cycle. + +patternProperties: + '^led@[01]$': + type: object + $ref: /schemas/leds/common.yaml# + description: LED control bank nodes. + unevaluatedProperties: false + + properties: + reg: + description: Control bank selection (0 = bank A, 1 = bank B). + maximum: 1 + + required: + - reg + - flash-max-microamp + - led-max-microamp + +allOf: + - $ref: /schemas/leds/common.yaml# + - if: + properties: + compatible: + contains: + const: ti,lm3559 + then: + properties: + ti,peak-current-microamp: + enum: [1400000, 2100000, 2700000, 3200000] + default: 1400000 + patternProperties: + '^led@[01]$': + properties: + flash-max-microamp: + minimum: 56250 + maximum: 900000 + led-max-microamp: + minimum: 28125 + maximum: 225000 + + - if: + properties: + compatible: + contains: + const: ti,lm3560 + then: + properties: + ti,peak-current-microamp: + enum: [1600000, 2300000, 3000000, 3600000] + default: 1600000 + patternProperties: + '^led@[01]$': + properties: + flash-max-microamp: + minimum: 62500 + maximum: 1000000 + led-max-microamp: + minimum: 31250 + maximum: 250000 + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + led-controller@53 { + compatible = "ti,lm3560"; + reg = <0x53>; + + enable-gpios = <&gpio 28 GPIO_ACTIVE_HIGH>; + vin-supply = <&vdd_3v3_sys>; + + flash-max-timeout-us = <1024000>; + ti,peak-current-microamp = <1600000>; + + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + + function = LED_FUNCTION_FLASH; + color = ; + + flash-max-microamp = <562500>; + led-max-microamp = <156250>; + }; + + led@1 { + reg = <1>; + + function = LED_FUNCTION_FLASH; + color = ; + + flash-max-microamp = <562500>; + led-max-microamp = <156250>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml index f40dc904832729..1b4ef0688ca79f 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml @@ -49,6 +49,7 @@ properties: - qcom,qcs615-apss-shared - qcom,sc7180-apss-shared - qcom,sc8180x-apss-shared + - qcom,shikra-apss-shared - qcom,sm7150-apss-shared - qcom,sm8150-apss-shared - const: qcom,sdm845-apss-shared diff --git a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml index 90bfde66cc4a63..03359479d926a6 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom,cpucp-mbox.yaml @@ -19,7 +19,9 @@ properties: - items: - enum: - qcom,glymur-cpucp-mbox + - qcom,hawi-cpucp-mbox - qcom,kaanapali-cpucp-mbox + - qcom,nord-cpucp-mbox - qcom,sm8750-cpucp-mbox - const: qcom,x1e80100-cpucp-mbox - enum: diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml index f5c584cf2146dd..3839e1f5f9046a 100644 --- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml +++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml @@ -26,7 +26,9 @@ properties: - enum: - qcom,eliza-ipcc - qcom,glymur-ipcc + - qcom,hawi-ipcc - qcom,kaanapali-ipcc + - qcom,maili-ipcc - qcom,milos-ipcc - qcom,qcs8300-ipcc - qcom,qdu1000-ipcc diff --git a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml index 541325f900a1d3..01f2afa023f045 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun4i-a10-video-engine.yaml @@ -63,6 +63,16 @@ properties: CMA pool to use for buffers allocation instead of the default CMA pool. + # FIXME: This should be made required eventually once every SoC will + # have the MBUS declared. + interconnects: + maxItems: 1 + + # FIXME: This should be made required eventually once every SoC will + # have the MBUS declared. + interconnect-names: + const: dma-mem + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml index 1aa5775ba2bcea..978ef2dc0ae781 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-csi.yaml @@ -40,6 +40,12 @@ properties: resets: maxItems: 1 + interconnects: + maxItems: 1 + + interconnect-names: + const: dma-mem + port: $ref: /schemas/graph.yaml#/$defs/port-base description: Parallel input port, connect to a parallel sensor diff --git a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml index 3ea4a4290f23de..c0d7accc7bbebd 100644 --- a/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml +++ b/Documentation/devicetree/bindings/media/allwinner,sun6i-a31-isp.yaml @@ -36,6 +36,12 @@ properties: resets: maxItems: 1 + interconnects: + maxItems: 1 + + interconnect-names: + const: dma-mem + ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/Documentation/devicetree/bindings/media/cnm,wave521c.yaml b/Documentation/devicetree/bindings/media/cnm,wave521c.yaml index 6a11c1d11fb5f9..6cd33dfd095d60 100644 --- a/Documentation/devicetree/bindings/media/cnm,wave521c.yaml +++ b/Documentation/devicetree/bindings/media/cnm,wave521c.yaml @@ -37,7 +37,7 @@ properties: maxItems: 1 sram: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 description: The VPU uses the SRAM to store some of the reference data instead of storing it on DMA memory. It is mainly used for the purpose of reducing diff --git a/Documentation/devicetree/bindings/media/i2c/onnn,mt9m114.yaml b/Documentation/devicetree/bindings/media/i2c/onnn,mt9m114.yaml index e896f4db242147..2b39614f5cbf7d 100644 --- a/Documentation/devicetree/bindings/media/i2c/onnn,mt9m114.yaml +++ b/Documentation/devicetree/bindings/media/i2c/onnn,mt9m114.yaml @@ -15,6 +15,9 @@ description: |- an I2C interface and outputs image data over a 8-bit parallel or 1-lane MIPI CSI-2 connection. +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + properties: compatible: enum: @@ -90,7 +93,7 @@ required: - vaa-supply - port -additionalProperties: false +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml index ebc615584f9216..4505e66876a299 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml @@ -160,7 +160,7 @@ examples: vcodec_enc_vp8: vcodec@19002000 { compatible = "mediatek,mt8173-vcodec-enc-vp8"; - reg = <0x19002000 0x1000>; /* VENC_LT_SYS */ + reg = <0x19002000 0x1000>; /* VENC_LT_SYS */ interrupts = ; iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>, <&iommu M4U_PORT_VENC_REC_FRM_SET2>, diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml index bf8082d87ac035..d1d209cbbd43ae 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-subdev-decoder.yaml @@ -232,7 +232,7 @@ examples: #address-cells = <2>; #size-cells = <2>; ranges = <0 0 0 0x16000000 0 0x40000>; - reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ + reg = <0 0x16000000 0 0x1000>; /* VDEC_SYS */ video-codec@10000 { compatible = "mediatek,mtk-vcodec-lat"; reg = <0 0x10000 0 0x800>; diff --git a/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml b/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml index 18cc6315a82121..6ba668aa633d73 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml @@ -56,10 +56,10 @@ properties: maxItems: 5 # Wrapper and 4 slots sram: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 description: - Optional phandle to a reserved on-chip SRAM regions. The SRAM can - be used for descriptor storage, which may improve bus utilization. + The SRAM can be used for descriptor storage, which may improve bus + utilization. required: - compatible diff --git a/Documentation/devicetree/bindings/media/qcom,msm8939-venus.yaml b/Documentation/devicetree/bindings/media/qcom,msm8939-venus.yaml new file mode 100644 index 00000000000000..10a50a410748a5 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,msm8939-venus.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,msm8939-venus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm MSM8939 Venus video encode and decode accelerators + +maintainers: + - André Apitzsch + - Erikas Bitovtas + +description: + The Venus IP is a video encode and decode accelerator present + on Qualcomm platforms + +allOf: + - $ref: qcom,venus-common.yaml# + +properties: + compatible: + const: qcom,msm8939-venus + + power-domains: + maxItems: 3 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: vcodec1 + + clocks: + maxItems: 5 + + clock-names: + items: + - const: core + - const: iface + - const: bus + - const: vcodec0_core + - const: vcodec1_core + + iommus: + maxItems: 1 + +required: + - compatible + - iommus + - power-domain-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + video-codec@1d00000 { + compatible = "qcom,msm8939-venus"; + reg = <0x01d00000 0xff000>; + interrupts = ; + clocks = <&gcc GCC_VENUS0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_AHB_CLK>, + <&gcc GCC_VENUS0_AXI_CLK>, + <&gcc GCC_VENUS0_CORE0_VCODEC0_CLK>, + <&gcc GCC_VENUS0_CORE1_VCODEC0_CLK>; + clock-names = "core", + "iface", + "bus", + "vcodec0_core", + "vcodec1_core"; + power-domains = <&gcc VENUS_GDSC>, + <&gcc VENUS_CORE0_GDSC>, + <&gcc VENUS_CORE1_GDSC>; + power-domain-names = "venus", "vcodec0", "vcodec1"; + iommus = <&apps_iommu 5>; + memory-region = <&venus_mem>; + }; diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml index 7e6dc410c2d2bd..5977e7d0a71b4f 100644 --- a/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml @@ -18,7 +18,11 @@ allOf: properties: compatible: - const: qcom,qcm2290-venus + oneOf: + - items: + - const: qcom,sm6115-venus + - const: qcom,qcm2290-venus + - const: qcom,qcm2290-venus power-domains: maxItems: 3 diff --git a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml index bfd8b1ad473128..b21bed31484848 100644 --- a/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sc7180-venus.yaml @@ -91,6 +91,21 @@ properties: deprecated: true additionalProperties: false + video-firmware: + type: object + additionalProperties: false + + description: | + Firmware subnode is needed when the platform does not + have TrustZone. + + properties: + iommus: + maxItems: 1 + + required: + - iommus + required: - compatible - power-domain-names diff --git a/Documentation/devicetree/bindings/media/qcom,sc7280-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sc7280-venus.yaml index 413c5b4ee6504b..9725fcb761dc0f 100644 --- a/Documentation/devicetree/bindings/media/qcom,sc7280-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sc7280-venus.yaml @@ -43,8 +43,7 @@ properties: - const: vcodec_bus iommus: - minItems: 1 - maxItems: 2 + maxItems: 1 interconnects: maxItems: 2 @@ -120,12 +119,7 @@ examples: <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; interconnect-names = "cpu-cfg", "video-mem"; - iommus = <&apps_smmu 0x2180 0x20>, - <&apps_smmu 0x2184 0x20>; + iommus = <&apps_smmu 0x2180 0x20>; memory-region = <&video_mem>; - - video-firmware { - iommus = <&apps_smmu 0x21a2 0x0>; - }; }; diff --git a/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml new file mode 100644 index 00000000000000..96974d90d8c431 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm6350-camss.yaml @@ -0,0 +1,471 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm6350-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 Camera Subsystem (CAMSS) + +maintainers: + - Luca Weiss + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sm6350-camss + + reg: + maxItems: 24 + + reg-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite + - const: a5_csr + - const: a5_qgic + - const: a5_sierra + - const: bps + - const: camnoc + - const: core_top_csr_tcsr + - const: cpas_cdm + - const: cpas_top + - const: ipe + - const: jpeg_dma + - const: jpeg_enc + - const: lrme + + clocks: + maxItems: 39 + + clock-names: + items: + - const: cam_axi + - const: soc_ahb + - const: camnoc_axi + - const: core_ahb + - const: cpas_ahb + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: vfe0_axi + - const: vfe0 + - const: vfe0_cphy_rx + - const: vfe0_csid + - const: vfe1_axi + - const: vfe1 + - const: vfe1_cphy_rx + - const: vfe1_csid + - const: vfe2_axi + - const: vfe2 + - const: vfe2_cphy_rx + - const: vfe2_csid + - const: vfe_lite + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + - const: bps + - const: bps_ahb + - const: bps_areg + - const: bps_axi + - const: icp + - const: ipe0 + - const: ipe0_ahb + - const: ipe0_areg + - const: ipe0_axi + - const: jpeg + - const: lrme + + interrupts: + maxItems: 18 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid2 + - const: csid_lite + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: vfe0 + - const: vfe1 + - const: vfe2 + - const: vfe_lite + - const: a5 + - const: cpas + - const: cpas_cdm + - const: jpeg_dma + - const: jpeg_enc + - const: lrme + + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_mnoc + - const: sf_icp_mnoc + + iommus: + maxItems: 14 + + power-domains: + maxItems: 6 + + power-domain-names: + items: + - const: ife0 + - const: ife1 + - const: ife2 + - const: top + - const: bps + - const: ipe + + vdd-csiphy0-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY0. + + vdd-csiphy0-1p25-supply: + description: + Phandle to a 1.25V regulator supply to CSIPHY0. + + vdd-csiphy1-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY1. + + vdd-csiphy1-1p25-supply: + description: + Phandle to a 1.25V regulator supply to CSIPHY1. + + vdd-csiphy2-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY2. + + vdd-csiphy2-1p25-supply: + description: + Phandle to a 1.25V regulator supply to CSIPHY2. + + vdd-csiphy3-0p9-supply: + description: + Phandle to a 0.9V regulator supply to CSIPHY3. + + vdd-csiphy3-1p25-supply: + description: + Phandle to a 1.25V regulator supply to CSIPHY3. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-3]$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data from a CSIPHY. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + bus-type: + enum: + - 1 # MEDIA_BUS_TYPE_CSI2_CPHY + - 4 # MEDIA_BUS_TYPE_CSI2_DPHY + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - ports + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@acb3000 { + compatible = "qcom,sm6350-camss"; + + reg = <0x0 0x0acb3000 0x0 0x1000>, + <0x0 0x0acba000 0x0 0x1000>, + <0x0 0x0acc1000 0x0 0x1000>, + <0x0 0x0acc8000 0x0 0x1000>, + <0x0 0x0ac65000 0x0 0x1000>, + <0x0 0x0ac66000 0x0 0x1000>, + <0x0 0x0ac67000 0x0 0x1000>, + <0x0 0x0ac68000 0x0 0x1000>, + <0x0 0x0acaf000 0x0 0x4000>, + <0x0 0x0acb6000 0x0 0x4000>, + <0x0 0x0acbd000 0x0 0x4000>, + <0x0 0x0acc4000 0x0 0x4000>, + <0x0 0x0ac18000 0x0 0x3000>, + <0x0 0x0ac00000 0x0 0x6000>, + <0x0 0x0ac10000 0x0 0x8000>, + <0x0 0x0ac6f000 0x0 0x8000>, + <0x0 0x0ac42000 0x0 0x4600>, + <0x0 0x01fc0000 0x0 0x40000>, + <0x0 0x0ac48000 0x0 0x1000>, + <0x0 0x0ac40000 0x0 0x1000>, + <0x0 0x0ac87000 0x0 0xa000>, + <0x0 0x0ac52000 0x0 0x4000>, + <0x0 0x0ac4e000 0x0 0x4000>, + <0x0 0x0ac6b000 0x0 0xa00>; + reg-names = "csid0", + "csid1", + "csid2", + "csid_lite", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite", + "a5_csr", + "a5_qgic", + "a5_sierra", + "bps", + "camnoc", + "core_top_csr_tcsr", + "cpas_cdm", + "cpas_top", + "ipe", + "jpeg_dma", + "jpeg_enc", + "lrme"; + + clocks = <&gcc GCC_CAMERA_AXI_CLK>, + <&camcc CAMCC_SOC_AHB_CLK>, + <&camcc CAMCC_CAMNOC_AXI_CLK>, + <&camcc CAMCC_CORE_AHB_CLK>, + <&camcc CAMCC_CPAS_AHB_CLK>, + <&camcc CAMCC_CSIPHY0_CLK>, + <&camcc CAMCC_CSI0PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY1_CLK>, + <&camcc CAMCC_CSI1PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY2_CLK>, + <&camcc CAMCC_CSI2PHYTIMER_CLK>, + <&camcc CAMCC_CSIPHY3_CLK>, + <&camcc CAMCC_CSI3PHYTIMER_CLK>, + <&camcc CAMCC_IFE_0_AXI_CLK>, + <&camcc CAMCC_IFE_0_CLK>, + <&camcc CAMCC_IFE_0_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_0_CSID_CLK>, + <&camcc CAMCC_IFE_1_AXI_CLK>, + <&camcc CAMCC_IFE_1_CLK>, + <&camcc CAMCC_IFE_1_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_1_CSID_CLK>, + <&camcc CAMCC_IFE_2_AXI_CLK>, + <&camcc CAMCC_IFE_2_CLK>, + <&camcc CAMCC_IFE_2_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_2_CSID_CLK>, + <&camcc CAMCC_IFE_LITE_CLK>, + <&camcc CAMCC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAMCC_IFE_LITE_CSID_CLK>, + <&camcc CAMCC_BPS_CLK>, + <&camcc CAMCC_BPS_AHB_CLK>, + <&camcc CAMCC_BPS_AREG_CLK>, + <&camcc CAMCC_BPS_AXI_CLK>, + <&camcc CAMCC_ICP_CLK>, + <&camcc CAMCC_IPE_0_CLK>, + <&camcc CAMCC_IPE_0_AHB_CLK>, + <&camcc CAMCC_IPE_0_AREG_CLK>, + <&camcc CAMCC_IPE_0_AXI_CLK>, + <&camcc CAMCC_JPEG_CLK>, + <&camcc CAMCC_LRME_CLK>; + clock-names = "cam_axi", + "soc_ahb", + "camnoc_axi", + "core_ahb", + "cpas_ahb", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "vfe0_axi", + "vfe0", + "vfe0_cphy_rx", + "vfe0_csid", + "vfe1_axi", + "vfe1", + "vfe1_cphy_rx", + "vfe1_csid", + "vfe2_axi", + "vfe2", + "vfe2_cphy_rx", + "vfe2_csid", + "vfe_lite", + "vfe_lite_cphy_rx", + "vfe_lite_csid", + "bps", + "bps_ahb", + "bps_areg", + "bps_axi", + "icp", + "ipe0", + "ipe0_ahb", + "ipe0_areg", + "ipe0_axi", + "jpeg", + "lrme"; + + interrupts = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names = "csid0", + "csid1", + "csid2", + "csid_lite", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "vfe0", + "vfe1", + "vfe2", + "vfe_lite", + "a5", + "cpas", + "cpas_cdm", + "jpeg_dma", + "jpeg_enc", + "lrme"; + + interconnects = <&gem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>, + <&mmss_noc MASTER_CAMNOC_ICP QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc", + "sf_icp_mnoc"; + + iommus = <&apps_smmu 0x820 0xc0>, + <&apps_smmu 0x840 0x0>, + <&apps_smmu 0x860 0xc0>, + <&apps_smmu 0x880 0x0>, + <&apps_smmu 0xc40 0x20>, + <&apps_smmu 0xc60 0x20>, + <&apps_smmu 0xc80 0x0>, + <&apps_smmu 0xca2 0x0>, + <&apps_smmu 0xcc0 0x20>, + <&apps_smmu 0xce0 0x20>, + <&apps_smmu 0xd00 0x20>, + <&apps_smmu 0xd20 0x20>, + <&apps_smmu 0xd40 0x20>, + <&apps_smmu 0xd60 0x20>; + + power-domains = <&camcc IFE_0_GDSC>, + <&camcc IFE_1_GDSC>, + <&camcc IFE_2_GDSC>, + <&camcc TITAN_TOP_GDSC>, + <&camcc BPS_GDSC>, + <&camcc IPE_0_GDSC>; + power-domain-names = "ife0", + "ife1", + "ife2", + "top", + "bps", + "ipe"; + + vdd-csiphy0-0p9-supply = <&vreg_l18a>; + vdd-csiphy0-1p25-supply = <&vreg_l22a>; + vdd-csiphy1-0p9-supply = <&vreg_l18a>; + vdd-csiphy1-1p25-supply = <&vreg_l22a>; + vdd-csiphy2-0p9-supply = <&vreg_l18a>; + vdd-csiphy2-1p25-supply = <&vreg_l22a>; + vdd-csiphy3-0p9-supply = <&vreg_l18a>; + vdd-csiphy3-1p25-supply = <&vreg_l22a>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + csiphy0_ep: endpoint { + data-lanes = <0 1 2 3>; + bus-type = ; + remote-endpoint = <&sensor_ep>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml b/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml index da54493220c9dc..aca748e42aca2a 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8250-venus.yaml @@ -10,19 +10,25 @@ maintainers: - Stanimir Varbanov description: | - The Venus IP is a video encode and decode accelerator present - on Qualcomm platforms + The Iris v2.xx IP is a video encode and decode accelerator present on + Qualcomm platforms allOf: - $ref: qcom,venus-common.yaml# properties: compatible: - const: qcom,sm8250-venus + oneOf: + - const: qcom,sm8250-venus + - items: + - enum: + - qcom,sc8280xp-iris + - qcom,sm8350-iris + - const: qcom,sm8250-venus power-domains: minItems: 2 - maxItems: 3 + maxItems: 4 power-domain-names: minItems: 2 @@ -30,6 +36,7 @@ properties: - const: venus - const: vcodec0 - const: mx + - const: mmcx clocks: maxItems: 3 @@ -114,8 +121,12 @@ examples: interrupts = ; power-domains = <&videocc MVS0C_GDSC>, <&videocc MVS0_GDSC>, - <&rpmhpd RPMHPD_MX>; - power-domain-names = "venus", "vcodec0", "mx"; + <&rpmhpd RPMHPD_MX>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", + "vcodec0", + "mx", + "mmcx"; clocks = <&gcc GCC_VIDEO_AXI0_CLK>, <&videocc VIDEO_CC_MVS0C_CLK>, diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index 9c4b760508b502..0400ca1bff05dc 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -26,6 +26,7 @@ properties: - qcom,qcs8300-iris - qcom,sm8550-iris - qcom,sm8650-iris + - qcom,x1p42100-iris reg: maxItems: 1 @@ -41,13 +42,16 @@ properties: - const: mmcx clocks: - maxItems: 3 + minItems: 3 + maxItems: 4 clock-names: + minItems: 3 items: - const: iface - const: core - const: vcodec0_core + - const: vcodec0_bse firmware-name: maxItems: 1 @@ -115,6 +119,23 @@ allOf: maxItems: 1 reset-names: maxItems: 1 + - if: + properties: + compatible: + enum: + - qcom,x1p42100-iris + then: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + else: + properties: + clocks: + maxItems: 3 + clock-names: + maxItems: 3 unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/media/qcom,venus-common.yaml b/Documentation/devicetree/bindings/media/qcom,venus-common.yaml index 3153d91f9d18a3..59a3fde846d219 100644 --- a/Documentation/devicetree/bindings/media/qcom,venus-common.yaml +++ b/Documentation/devicetree/bindings/media/qcom,venus-common.yaml @@ -47,21 +47,6 @@ properties: minItems: 1 maxItems: 4 - video-firmware: - type: object - additionalProperties: false - - description: | - Firmware subnode is needed when the platform does not - have TrustZone. - - properties: - iommus: - maxItems: 1 - - required: - - iommus - required: - reg - clocks diff --git a/Documentation/devicetree/bindings/media/renesas,fcp.yaml b/Documentation/devicetree/bindings/media/renesas,fcp.yaml index b5eff6fec8a98a..5e11ae0ee45644 100644 --- a/Documentation/devicetree/bindings/media/renesas,fcp.yaml +++ b/Documentation/devicetree/bindings/media/renesas,fcp.yaml @@ -30,6 +30,8 @@ properties: - renesas,r9a07g043u-fcpvd # RZ/G2UL - renesas,r9a07g044-fcpvd # RZ/G2{L,LC} - renesas,r9a07g054-fcpvd # RZ/V2L + - renesas,r9a08g046-fcpvd # RZ/G3L + - renesas,r9a09g047-fcpvd # RZ/G3E - renesas,r9a09g056-fcpvd # RZ/V2N - renesas,r9a09g057-fcpvd # RZ/V2H(P) - const: renesas,fcpv # Generic FCP for VSP fallback @@ -77,6 +79,8 @@ allOf: - renesas,r9a07g043u-fcpvd - renesas,r9a07g044-fcpvd - renesas,r9a07g054-fcpvd + - renesas,r9a08g046-fcpvd + - renesas,r9a09g047-fcpvd - renesas,r9a09g056-fcpvd - renesas,r9a09g057-fcpvd then: diff --git a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml index 07a97dd87a5bcc..803358780f01b9 100644 --- a/Documentation/devicetree/bindings/media/renesas,vsp1.yaml +++ b/Documentation/devicetree/bindings/media/renesas,vsp1.yaml @@ -25,6 +25,8 @@ properties: - enum: - renesas,r9a07g043u-vsp2 # RZ/G2UL - renesas,r9a07g054-vsp2 # RZ/V2L + - renesas,r9a08g046-vsp2 # RZ/G3L + - renesas,r9a09g047-vsp2 # RZ/G3E - renesas,r9a09g056-vsp2 # RZ/V2N - renesas,r9a09g057-vsp2 # RZ/V2H(P) - const: renesas,r9a07g044-vsp2 # RZ/G2L fallback diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml index 4ac4a3b6f40640..8bfad0fca3b7df 100644 --- a/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-mipi-csi2.yaml @@ -16,9 +16,15 @@ description: properties: compatible: - enum: - - fsl,imx93-mipi-csi2 - - rockchip,rk3568-mipi-csi2 + oneOf: + - enum: + - fsl,imx93-mipi-csi2 + - fsl,imx95-mipi-csi2 + - rockchip,rk3568-mipi-csi2 + - items: + - enum: + - rockchip,rk3588-mipi-csi2 + - const: rockchip,rk3568-mipi-csi2 reg: maxItems: 1 @@ -135,6 +141,21 @@ allOf: clock-names: minItems: 2 + - if: + properties: + compatible: + contains: + const: fsl,imx95-mipi-csi2 + then: + properties: + interrupts: + maxItems: 1 + interrupt-names: false + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + examples: - | #include diff --git a/Documentation/devicetree/bindings/media/rockchip,rk3568-vicap.yaml b/Documentation/devicetree/bindings/media/rockchip,rk3568-vicap.yaml index 18cd0a5a531817..080b64503b1bc4 100644 --- a/Documentation/devicetree/bindings/media/rockchip,rk3568-vicap.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,rk3568-vicap.yaml @@ -15,9 +15,15 @@ description: the data from camera sensors, video decoders, or other companion ICs and transfers it into system main memory by AXI bus. + The Rockchip RK3588 Video Capture (VICAP) is similar to its RK3568 + counterpart, but features six MIPI CSI-2 ports and additional connections + to the image signal processor (ISP) blocks. + properties: compatible: - const: rockchip,rk3568-vicap + enum: + - rockchip,rk3568-vicap + - rockchip,rk3588-vicap reg: maxItems: 1 @@ -26,11 +32,8 @@ properties: maxItems: 1 clocks: - items: - - description: ACLK - - description: HCLK - - description: DCLK - - description: ICLK + minItems: 4 + maxItems: 5 clock-names: items: @@ -38,25 +41,19 @@ properties: - const: hclk - const: dclk - const: iclk + - const: iclk1 + minItems: 4 iommus: maxItems: 1 resets: - items: - - description: ARST - - description: HRST - - description: DRST - - description: PRST - - description: IRST + minItems: 5 + maxItems: 9 reset-names: - items: - - const: arst - - const: hrst - - const: drst - - const: prst - - const: irst + minItems: 5 + maxItems: 9 rockchip,grf: $ref: /schemas/types.yaml#/definitions/phandle @@ -67,8 +64,15 @@ properties: ports: $ref: /schemas/graph.yaml#/properties/ports + additionalProperties: false properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + port@0: $ref: /schemas/graph.yaml#/$defs/port-base unevaluatedProperties: false @@ -100,13 +104,75 @@ properties: port@1: $ref: /schemas/graph.yaml#/properties/port - description: Port connected to the MIPI CSI-2 receiver output. + description: Port connected to the MIPI CSI-2 receiver 0 output. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + port@2: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the MIPI CSI-2 receiver 1 output. properties: endpoint: $ref: video-interfaces.yaml# unevaluatedProperties: false + port@3: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the MIPI CSI-2 receiver 2 output. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + port@4: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the MIPI CSI-2 receiver 3 output. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + port@5: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the MIPI CSI-2 receiver 4 output. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + port@6: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the MIPI CSI-2 receiver 5 output. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + port@10: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the ISP0 input. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + port@11: + $ref: /schemas/graph.yaml#/properties/port + description: Port connected to the ISP1 input. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false required: - compatible - reg @@ -114,6 +180,75 @@ required: - clocks - ports +allOf: + - if: + properties: + compatible: + contains: + const: rockchip,rk3568-vicap + then: + properties: + clocks: + maxItems: 4 + + clock-names: + maxItems: 4 + + resets: + maxItems: 5 + + reset-names: + items: + - const: arst + - const: hrst + - const: drst + - const: prst + - const: irst + + ports: + properties: + port@2: false + + port@3: false + + port@4: false + + port@5: false + + port@6: false + + port@10: false + + port@11: false + + - if: + properties: + compatible: + contains: + const: rockchip,rk3588-vicap + then: + properties: + clocks: + minItems: 5 + + clock-names: + minItems: 5 + + resets: + minItems: 9 + + reset-names: + items: + - const: arst + - const: hrst + - const: drst + - const: irst0 + - const: irst1 + - const: irst2 + - const: irst3 + - const: irst4 + - const: irst5 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml index 42022401d0ffa6..4f38a0ef29d842 100644 --- a/Documentation/devicetree/bindings/media/rockchip,vdec.yaml +++ b/Documentation/devicetree/bindings/media/rockchip,vdec.yaml @@ -91,9 +91,8 @@ properties: maxItems: 1 sram: - $ref: /schemas/types.yaml#/definitions/phandle - description: | - phandle to a reserved on-chip SRAM regions. + maxItems: 1 + description: Some SoCs, like rk3588 provide on-chip SRAM to store temporary buffers during decoding. diff --git a/Documentation/devicetree/bindings/media/rockchip-rga.yaml b/Documentation/devicetree/bindings/media/rockchip-rga.yaml index ac17cda65191be..7bd92f73366649 100644 --- a/Documentation/devicetree/bindings/media/rockchip-rga.yaml +++ b/Documentation/devicetree/bindings/media/rockchip-rga.yaml @@ -9,7 +9,11 @@ title: Rockchip 2D raster graphic acceleration controller (RGA) description: RGA is a standalone 2D raster graphic acceleration unit. It accelerates 2D graphics operations, such as point/line drawing, image scaling, rotation, - BitBLT, alpha blending and image blur/sharpness. + BitBLT, alpha blending and image blur/sharpness. There exist many versions + of this unit that differ in the supported inputs/output formats, + the attached IOMMU and the supported operations on the input. As some SoCs + include multiple RGA units with different versions, a more specific + compatible name to differentiate the concrete unit is used for them. maintainers: - Jacob Chen @@ -20,6 +24,7 @@ properties: oneOf: - const: rockchip,rk3288-rga - const: rockchip,rk3399-rga + - const: rockchip,rk3588-rga3 - items: - enum: - rockchip,rk3228-rga @@ -45,6 +50,9 @@ properties: power-domains: maxItems: 1 + iommus: + maxItems: 1 + resets: maxItems: 3 diff --git a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml index d9fbb90b0977d8..7c2ddd27780f61 100644 --- a/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml +++ b/Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml @@ -47,10 +47,10 @@ properties: maxItems: 1 sram: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 description: - phandle to a reserved SRAM region which is used as temporary - storage memory between DMA and MDMA engines. + SRAM region which is used as temporary storage memory between DMA and + MDMA engines. port: $ref: /schemas/graph.yaml#/$defs/port-base diff --git a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml index b9f033f2f3ce46..bf62998b0445a3 100644 --- a/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml +++ b/Documentation/devicetree/bindings/media/ti,j721e-csi2rx-shim.yaml @@ -20,11 +20,44 @@ properties: const: ti,j721e-csi2rx-shim dmas: - maxItems: 1 + minItems: 1 + maxItems: 32 dma-names: + minItems: 1 items: - const: rx0 + - const: rx1 + - const: rx2 + - const: rx3 + - const: rx4 + - const: rx5 + - const: rx6 + - const: rx7 + - const: rx8 + - const: rx9 + - const: rx10 + - const: rx11 + - const: rx12 + - const: rx13 + - const: rx14 + - const: rx15 + - const: rx16 + - const: rx17 + - const: rx18 + - const: rx19 + - const: rx20 + - const: rx21 + - const: rx22 + - const: rx23 + - const: rx24 + - const: rx25 + - const: rx26 + - const: rx27 + - const: rx28 + - const: rx29 + - const: rx30 + - const: rx31 reg: maxItems: 1 @@ -62,8 +95,8 @@ examples: ti_csi2rx0: ticsi2rx@4500000 { compatible = "ti,j721e-csi2rx-shim"; - dmas = <&main_udmap 0x4940>; - dma-names = "rx0"; + dmas = <&main_udmap 0x4940>, <&main_udmap 0x4941>; + dma-names = "rx0", "rx1"; reg = <0x4500000 0x1000>; power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; #address-cells = <1>; diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml index f5f03bf364137c..9398aae4909333 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-emc.yaml @@ -16,7 +16,9 @@ description: | properties: compatible: - const: nvidia,tegra124-emc + enum: + - nvidia,tegra114-emc + - nvidia,tegra124-emc reg: maxItems: 1 @@ -29,6 +31,9 @@ properties: items: - const: emc + interrupts: + maxItems: 1 + "#interconnect-cells": const: 0 @@ -164,153 +169,12 @@ patternProperties: nvidia,emc-configuration: description: EMC timing characterization data. These are the registers (see - section "15.6.2 EMC Registers" in the TRM) whose values need to + section "20.11.2 EMC Registers" in the Tegra114 TRM or section + "15.6.2 EMC Registers" in the Tegra124 TRM) whose values need to be specified, according to the board documentation. $ref: /schemas/types.yaml#/definitions/uint32-array - items: - - description: EMC_RC - - description: EMC_RFC - - description: EMC_RFC_SLR - - description: EMC_RAS - - description: EMC_RP - - description: EMC_R2W - - description: EMC_W2R - - description: EMC_R2P - - description: EMC_W2P - - description: EMC_RD_RCD - - description: EMC_WR_RCD - - description: EMC_RRD - - description: EMC_REXT - - description: EMC_WEXT - - description: EMC_WDV - - description: EMC_WDV_MASK - - description: EMC_QUSE - - description: EMC_QUSE_WIDTH - - description: EMC_IBDLY - - description: EMC_EINPUT - - description: EMC_EINPUT_DURATION - - description: EMC_PUTERM_EXTRA - - description: EMC_PUTERM_WIDTH - - description: EMC_PUTERM_ADJ - - description: EMC_CDB_CNTL_1 - - description: EMC_CDB_CNTL_2 - - description: EMC_CDB_CNTL_3 - - description: EMC_QRST - - description: EMC_QSAFE - - description: EMC_RDV - - description: EMC_RDV_MASK - - description: EMC_REFRESH - - description: EMC_BURST_REFRESH_NUM - - description: EMC_PRE_REFRESH_REQ_CNT - - description: EMC_PDEX2WR - - description: EMC_PDEX2RD - - description: EMC_PCHG2PDEN - - description: EMC_ACT2PDEN - - description: EMC_AR2PDEN - - description: EMC_RW2PDEN - - description: EMC_TXSR - - description: EMC_TXSRDLL - - description: EMC_TCKE - - description: EMC_TCKESR - - description: EMC_TPD - - description: EMC_TFAW - - description: EMC_TRPAB - - description: EMC_TCLKSTABLE - - description: EMC_TCLKSTOP - - description: EMC_TREFBW - - description: EMC_FBIO_CFG6 - - description: EMC_ODT_WRITE - - description: EMC_ODT_READ - - description: EMC_FBIO_CFG5 - - description: EMC_CFG_DIG_DLL - - description: EMC_CFG_DIG_DLL_PERIOD - - description: EMC_DLL_XFORM_DQS0 - - description: EMC_DLL_XFORM_DQS1 - - description: EMC_DLL_XFORM_DQS2 - - description: EMC_DLL_XFORM_DQS3 - - description: EMC_DLL_XFORM_DQS4 - - description: EMC_DLL_XFORM_DQS5 - - description: EMC_DLL_XFORM_DQS6 - - description: EMC_DLL_XFORM_DQS7 - - description: EMC_DLL_XFORM_DQS8 - - description: EMC_DLL_XFORM_DQS9 - - description: EMC_DLL_XFORM_DQS10 - - description: EMC_DLL_XFORM_DQS11 - - description: EMC_DLL_XFORM_DQS12 - - description: EMC_DLL_XFORM_DQS13 - - description: EMC_DLL_XFORM_DQS14 - - description: EMC_DLL_XFORM_DQS15 - - description: EMC_DLL_XFORM_QUSE0 - - description: EMC_DLL_XFORM_QUSE1 - - description: EMC_DLL_XFORM_QUSE2 - - description: EMC_DLL_XFORM_QUSE3 - - description: EMC_DLL_XFORM_QUSE4 - - description: EMC_DLL_XFORM_QUSE5 - - description: EMC_DLL_XFORM_QUSE6 - - description: EMC_DLL_XFORM_QUSE7 - - description: EMC_DLL_XFORM_ADDR0 - - description: EMC_DLL_XFORM_ADDR1 - - description: EMC_DLL_XFORM_ADDR2 - - description: EMC_DLL_XFORM_ADDR3 - - description: EMC_DLL_XFORM_ADDR4 - - description: EMC_DLL_XFORM_ADDR5 - - description: EMC_DLL_XFORM_QUSE8 - - description: EMC_DLL_XFORM_QUSE9 - - description: EMC_DLL_XFORM_QUSE10 - - description: EMC_DLL_XFORM_QUSE11 - - description: EMC_DLL_XFORM_QUSE12 - - description: EMC_DLL_XFORM_QUSE13 - - description: EMC_DLL_XFORM_QUSE14 - - description: EMC_DLL_XFORM_QUSE15 - - description: EMC_DLI_TRIM_TXDQS0 - - description: EMC_DLI_TRIM_TXDQS1 - - description: EMC_DLI_TRIM_TXDQS2 - - description: EMC_DLI_TRIM_TXDQS3 - - description: EMC_DLI_TRIM_TXDQS4 - - description: EMC_DLI_TRIM_TXDQS5 - - description: EMC_DLI_TRIM_TXDQS6 - - description: EMC_DLI_TRIM_TXDQS7 - - description: EMC_DLI_TRIM_TXDQS8 - - description: EMC_DLI_TRIM_TXDQS9 - - description: EMC_DLI_TRIM_TXDQS10 - - description: EMC_DLI_TRIM_TXDQS11 - - description: EMC_DLI_TRIM_TXDQS12 - - description: EMC_DLI_TRIM_TXDQS13 - - description: EMC_DLI_TRIM_TXDQS14 - - description: EMC_DLI_TRIM_TXDQS15 - - description: EMC_DLL_XFORM_DQ0 - - description: EMC_DLL_XFORM_DQ1 - - description: EMC_DLL_XFORM_DQ2 - - description: EMC_DLL_XFORM_DQ3 - - description: EMC_DLL_XFORM_DQ4 - - description: EMC_DLL_XFORM_DQ5 - - description: EMC_DLL_XFORM_DQ6 - - description: EMC_DLL_XFORM_DQ7 - - description: EMC_XM2CMDPADCTRL - - description: EMC_XM2CMDPADCTRL4 - - description: EMC_XM2CMDPADCTRL5 - - description: EMC_XM2DQPADCTRL2 - - description: EMC_XM2DQPADCTRL3 - - description: EMC_XM2CLKPADCTRL - - description: EMC_XM2CLKPADCTRL2 - - description: EMC_XM2COMPPADCTRL - - description: EMC_XM2VTTGENPADCTRL - - description: EMC_XM2VTTGENPADCTRL2 - - description: EMC_XM2VTTGENPADCTRL3 - - description: EMC_XM2DQSPADCTRL3 - - description: EMC_XM2DQSPADCTRL4 - - description: EMC_XM2DQSPADCTRL5 - - description: EMC_XM2DQSPADCTRL6 - - description: EMC_DSR_VTTGEN_DRV - - description: EMC_TXDSRVTTGEN - - description: EMC_FBIO_SPARE - - description: EMC_ZCAL_WAIT_CNT - - description: EMC_MRS_WAIT_CNT2 - - description: EMC_CTT - - description: EMC_CTT_DURATION - - description: EMC_CFG_PIPE - - description: EMC_DYN_SELF_REF_CONTROL - - description: EMC_QPOP + minItems: 97 + maxItems: 143 required: - clock-frequency @@ -318,9 +182,7 @@ patternProperties: - nvidia,emc-auto-cal-config2 - nvidia,emc-auto-cal-config3 - nvidia,emc-auto-cal-interval - - nvidia,emc-bgbias-ctl0 - nvidia,emc-cfg - - nvidia,emc-cfg-2 - nvidia,emc-ctt-term-ctrl - nvidia,emc-mode-1 - nvidia,emc-mode-2 @@ -344,6 +206,22 @@ required: - "#interconnect-cells" - operating-points-v2 +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,tegra124-emc + then: + patternProperties: + "^emc-timings-[0-9]+$": + patternProperties: + "^timing-[0-9]+$": + required: + - nvidia,emc-bgbias-ctl0 + - nvidia,emc-cfg-2 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml index 7b18b4d11e0aea..f8747cebb6808c 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml @@ -19,7 +19,9 @@ description: | properties: compatible: - const: nvidia,tegra124-mc + enum: + - nvidia,tegra114-mc + - nvidia,tegra124-mc reg: maxItems: 1 @@ -64,29 +66,12 @@ patternProperties: nvidia,emem-configuration: $ref: /schemas/types.yaml#/definitions/uint32-array - description: | + description: Values to be written to the EMEM register block. See section - "15.6.1 MC Registers" in the TRM. - items: - - description: MC_EMEM_ARB_CFG - - description: MC_EMEM_ARB_OUTSTANDING_REQ - - description: MC_EMEM_ARB_TIMING_RCD - - description: MC_EMEM_ARB_TIMING_RP - - description: MC_EMEM_ARB_TIMING_RC - - description: MC_EMEM_ARB_TIMING_RAS - - description: MC_EMEM_ARB_TIMING_FAW - - description: MC_EMEM_ARB_TIMING_RRD - - description: MC_EMEM_ARB_TIMING_RAP2PRE - - description: MC_EMEM_ARB_TIMING_WAP2PRE - - description: MC_EMEM_ARB_TIMING_R2R - - description: MC_EMEM_ARB_TIMING_W2W - - description: MC_EMEM_ARB_TIMING_R2W - - description: MC_EMEM_ARB_TIMING_W2R - - description: MC_EMEM_ARB_DA_TURNS - - description: MC_EMEM_ARB_DA_COVERS - - description: MC_EMEM_ARB_MISC0 - - description: MC_EMEM_ARB_MISC1 - - description: MC_EMEM_ARB_RING1_THROTTLE + "20.11.1 MC Registers" in the Tegea114 TRM or + "15.6.1 MC Registers" in the Tegra124 TRM. + minItems: 18 + maxItems: 19 required: - clock-frequency diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml index 7b03b589168b1b..6c374e2b1543b4 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra186-mc.yaml @@ -32,6 +32,7 @@ properties: - nvidia,tegra186-mc - nvidia,tegra194-mc - nvidia,tegra234-mc + - nvidia,tegra238-mc - nvidia,tegra264-mc reg: @@ -266,6 +267,36 @@ allOf: interrupt-names: false + - if: + properties: + compatible: + const: nvidia,tegra238-mc + then: + properties: + reg: + minItems: 10 + maxItems: 10 + description: 9 memory controller channels and 1 for stream-id registers + + reg-names: + items: + - const: sid + - const: broadcast + - const: ch0 + - const: ch1 + - const: ch2 + - const: ch3 + - const: ch4 + - const: ch5 + - const: ch6 + - const: ch7 + + interrupts: + items: + - description: MC general interrupt + + interrupt-names: false + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml index 55caf69053995f..a33913fcd11f81 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-mc.yaml @@ -66,8 +66,8 @@ examples: - | memory-controller@7000f000 { compatible = "nvidia,tegra20-mc-gart"; - reg = <0x7000f000 0x400>, /* Controller registers */ - <0x58000000 0x02000000>; /* GART aperture */ + reg = <0x7000f000 0x400>, /* Controller registers */ + <0x58000000 0x02000000>; /* GART aperture */ clocks = <&clock_controller 32>; clock-names = "mc"; diff --git a/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml index 7a84f5bb7284ed..cdeca4c795f3a8 100644 --- a/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/renesas,rzg3e-xspi.yaml @@ -30,6 +30,8 @@ properties: - enum: - renesas,r9a09g056-xspi # RZ/V2N - renesas,r9a09g057-xspi # RZ/V2H(P) + - renesas,r9a09g077-xspi # RZ/T2H + - renesas,r9a09g087-xspi # RZ/N2H - const: renesas,r9a09g047-xspi reg: @@ -53,28 +55,38 @@ properties: - const: err_pulse clocks: - items: - - description: AHB clock - - description: AXI clock - - description: SPI clock - - description: Double speed SPI clock + oneOf: + - items: + - description: AHB clock + - description: AXI clock + - description: SPI clock + - description: Double speed SPI clock + - items: + - description: AHB clock + - description: SPI clock clock-names: - items: - - const: ahb - - const: axi - - const: spi - - const: spix2 + oneOf: + - items: + - const: ahb + - const: axi + - const: spi + - const: spix2 + - items: + - const: ahb + - const: spi power-domains: maxItems: 1 resets: + minItems: 1 items: - description: Hardware reset - description: AXI reset reset-names: + minItems: 1 items: - const: hresetn - const: aresetn @@ -109,6 +121,34 @@ required: - '#address-cells' - '#size-cells' +if: + properties: + compatible: + contains: + enum: + - renesas,r9a09g077-xspi + - renesas,r9a09g087-xspi +then: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 + resets: + maxItems: 1 + reset-names: + maxItems: 1 +else: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + resets: + minItems: 2 + reset-names: + minItems: 2 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml index 783ac984d89849..4cd5af38abce18 100644 --- a/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml @@ -128,7 +128,7 @@ examples: "mout_mx_mspll_ccore", "mout_mclk_cdrex"; operating-points-v2 = <&dmc_opp_table>; - devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, + devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>, <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>; device-handle = <&samsung_K3QF2F20DB>; vdd-supply = <&buck1_reg>; diff --git a/Documentation/devicetree/bindings/mfd/apple,smc.yaml b/Documentation/devicetree/bindings/mfd/apple,smc.yaml index 0410e712c900a7..34ce048619f5f7 100644 --- a/Documentation/devicetree/bindings/mfd/apple,smc.yaml +++ b/Documentation/devicetree/bindings/mfd/apple,smc.yaml @@ -49,6 +49,9 @@ properties: rtc: $ref: /schemas/rtc/apple,smc-rtc.yaml + hwmon: + $ref: /schemas/hwmon/apple,smc-hwmon.yaml + additionalProperties: false required: @@ -89,5 +92,38 @@ examples: nvmem-cells = <&rtc_offset>; nvmem-cell-names = "rtc_offset"; }; + + hwmon { + compatible = "apple,smc-hwmon"; + + current-ID0R { + apple,key-id = "ID0R"; + label = "AC Input Current"; + }; + + fan-F0Ac { + apple,key-id = "F0Ac"; + apple,fan-minimum = "F0Mn"; + apple,fan-maximum = "F0Mx"; + apple,fan-target = "F0Tg"; + apple,fan-mode = "F0Md"; + label = "Fan 1"; + }; + + power-PSTR { + apple,key-id = "PSTR"; + label = "Total System Power"; + }; + + temperature-TW0P { + apple,key-id = "TW0P"; + label = "WiFi/BT Module Temperature"; + }; + + voltage-VD0R { + apple,key-id = "VD0R"; + label = "AC Input Voltage"; + }; + }; }; }; diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index a87f31fce01952..948ba92ef49b93 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -46,6 +46,18 @@ properties: '#reset-cells': const: 1 + memory-region: + items: + - description: Region mapped through the first SSP address window. + - description: Region mapped through the second SSP address window. + - description: Region mapped through the TSP address window. + + memory-region-names: + items: + - const: ssp-0 + - const: ssp-1 + - const: tsp + patternProperties: '^p2a-control@[0-9a-f]+$': description: > @@ -87,6 +99,8 @@ patternProperties: - aspeed,ast2400-pinctrl - aspeed,ast2500-pinctrl - aspeed,ast2600-pinctrl + - aspeed,ast2700-soc0-pinctrl + - aspeed,ast2700-soc1-pinctrl required: - compatible @@ -156,6 +170,30 @@ required: - '#clock-cells' - '#reset-cells' +allOf: + - if: + properties: + compatible: + contains: + enum: + - aspeed,ast2700-scu0 + - aspeed,ast2700-scu1 + then: + patternProperties: + '^p2a-control@[0-9a-f]+$': false + '^smp-memram@[0-9a-f]+$': false + + - if: + not: + properties: + compatible: + contains: + const: aspeed,ast2700-scu0 + then: + properties: + memory-region: false + memory-region-names: false + additionalProperties: false examples: @@ -180,4 +218,81 @@ examples: reg = <0x7c 0x4>, <0x150 0x8>; }; }; + + - | + / { + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + ssp_region_0: memory@400000000 { + reg = <0x4 0x00000000 0x0 0x01000000>; + no-map; + }; + + ssp_region_1: memory@401000000 { + reg = <0x4 0x01000000 0x0 0x01000000>; + no-map; + }; + + tsp_region: memory@402000000 { + reg = <0x4 0x02000000 0x0 0x01000000>; + no-map; + }; + }; + + bus { + #address-cells = <2>; + #size-cells = <2>; + + syscon@12c02000 { + compatible = "aspeed,ast2700-scu0", "syscon", "simple-mfd"; + reg = <0 0x12c02000 0 0x1000>; + ranges = <0x0 0x0 0x12c02000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + + memory-region = <&ssp_region_0>, <&ssp_region_1>, + <&tsp_region>; + memory-region-names = "ssp-0", "ssp-1", "tsp"; + + silicon-id@0 { + compatible = "aspeed,ast2700-silicon-id", "aspeed,silicon-id"; + reg = <0x0 0x4>; + }; + + interrupt-controller@1b0 { + compatible = "aspeed,ast2700-scu-ic0"; + reg = <0x1b0 0x4>; + #interrupt-cells = <1>; + interrupts-extended = <&intc0 97>; + interrupt-controller; + }; + + interrupt-controller@1e0 { + compatible = "aspeed,ast2700-scu-ic1"; + reg = <0x1e0 0x4>; + #interrupt-cells = <1>; + interrupts-extended = <&intc0 98>; + interrupt-controller; + }; + + pinctrl@400 { + compatible = "aspeed,ast2700-soc0-pinctrl"; + reg = <0x400 0x318>; + emmc-state { + function = "EMMC"; + groups = "EMMCG1"; + }; + }; + }; + }; + }; + ... diff --git a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x-pmic.yaml b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x-pmic.yaml new file mode 100644 index 00000000000000..6f28f472e0f581 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x-pmic.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/hisilicon,hi655x-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon Hi655x Power Management Integrated Circuit + +maintainers: + - Chen Feng + - Daniel Lezcano + +description: + The hardware layout for access PMIC Hi655x from AP SoC Hi6220. + Between PMIC Hi655x and Hi6220, the physical signal channel is SSI. + We can use memory-mapped I/O to communicate. + +properties: + compatible: + const: hisilicon,hi655x-pmic + + reg: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + pmic-gpios: + maxItems: 1 + description: The GPIO used by PMIC IRQ + + '#clock-cells': + const: 0 + + clock-output-names: + maxItems: 1 + + regulators: + type: object + additionalProperties: false + + patternProperties: + '^LDO(2|7|10|13|14|15|17|19|21|22)$': + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupt-controller + - '#interrupt-cells' + - pmic-gpios + - '#clock-cells' + +additionalProperties: false + +examples: + - | + #include + + pmic: pmic@f8000000 { + compatible = "hisilicon,hi655x-pmic"; + reg = <0xf8000000 0x1000>; + #clock-cells = <0>; + interrupt-controller; + #interrupt-cells = <2>; + pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; + + regulators { + ldo2: LDO2 { + regulator-name = "LDO2_2V8"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <3200000>; + regulator-enable-ramp-delay = <120>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt b/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt deleted file mode 100644 index 9630ac0e4b56ef..00000000000000 --- a/Documentation/devicetree/bindings/mfd/hisilicon,hi655x.txt +++ /dev/null @@ -1,33 +0,0 @@ -Hisilicon Hi655x Power Management Integrated Circuit (PMIC) - -The hardware layout for access PMIC Hi655x from AP SoC Hi6220. -Between PMIC Hi655x and Hi6220, the physical signal channel is SSI. -We can use memory-mapped I/O to communicate. - -+----------------+ +-------------+ -| | | | -| Hi6220 | SSI bus | Hi655x | -| |-------------| | -| |(REGMAP_MMIO)| | -+----------------+ +-------------+ - -Required properties: -- compatible: Should be "hisilicon,hi655x-pmic". -- reg: Base address of PMIC on Hi6220 SoC. -- interrupt-controller: Hi655x has internal IRQs (has own IRQ domain). -- pmic-gpios: The GPIO used by PMIC IRQ. -- #clock-cells: From common clock binding; shall be set to 0 - -Optional properties: -- clock-output-names: From common clock binding to override the - default output clock name - -Example: - pmic: pmic@f8000000 { - compatible = "hisilicon,hi655x-pmic"; - reg = <0x0 0xf8000000 0x0 0x1000>; - interrupt-controller; - #interrupt-cells = <2>; - pmic-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>; - #clock-cells = <0>; - } diff --git a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml index 084960fd5a1fdd..c6f91e7bc8aa89 100644 --- a/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml +++ b/Documentation/devicetree/bindings/mfd/khadas,mcu.yaml @@ -18,6 +18,7 @@ properties: compatible: enum: - khadas,mcu # MCU revision is discoverable + - khadas,vim4-mcu # Different MCU variant, not discoverable "#cooling-cells": # Only needed for boards having FAN control feature const: 2 @@ -25,10 +26,26 @@ properties: reg: maxItems: 1 + fan-supply: + description: Phandle to the regulator that powers the fan. + required: - compatible - reg +allOf: + - if: + properties: + compatible: + contains: + const: khadas,vim4-mcu + then: + required: + - fan-supply + else: + properties: + fan-supply: false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml index 05c121b0cb3d86..3cbc0dc12c319f 100644 --- a/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt6397.yaml @@ -44,6 +44,10 @@ properties: - enum: - mediatek,mt6366 - const: mediatek,mt6358 + - items: + - enum: + - mediatek,mt6365 + - const: mediatek,mt6359 interrupts: maxItems: 1 @@ -70,6 +74,8 @@ properties: - mediatek,mt6397-rtc - items: - enum: + - mediatek,mt6359-rtc + - mediatek,mt6365-rtc - mediatek,mt6366-rtc - const: mediatek,mt6358-rtc @@ -98,6 +104,10 @@ properties: - enum: - mediatek,mt6366-regulator - const: mediatek,mt6358-regulator + - items: + - enum: + - mediatek,mt6365-regulator + - const: mediatek,mt6359-regulator required: - compatible @@ -124,6 +134,10 @@ properties: - enum: - mediatek,mt6366-sound - const: mediatek,mt6358-sound + - items: + - enum: + - mediatek,mt6365-codec + - const: mediatek,mt6359-codec required: - compatible @@ -225,12 +239,62 @@ properties: description: Pin controller + vsys-smps-supply: + description: Supply for regulator control logic + +patternProperties: + "^vsys-v[a-z]+[0-9]*-supply$": + description: Supplies for PMIC buck regulators + "^vs(ys|[12])-ldo[1-9]-supply$": + description: Supplies for PMIC LDO regulators + required: - compatible - regulators additionalProperties: false +allOf: + - if: + properties: + "compatible": + contains: + const: mediatek,mt6359 + then: + properties: + vsys-ldo1-supply: + description: Supply for LDOs vcn33_[12], vio28, vfe28, vibr + vsys-ldo2-supply: + description: Supply for LDOs vaux18, vbif28, vxo22, vrfck, vrfck_1, + vemc, vsim1, vsim2, vusb + vsys-vcore-supply: + description: Supply for buck regulator vcore + vsys-vgpu11-supply: + description: Supply for buck regulator vgpu11 + vsys-vmodem-supply: + description: Supply for buck regulator vmodem + vsys-vpa-supply: + description: Supply for buck regulator vpa + vsys-vproc1-supply: + description: Supply for buck regulator vproc1 + vsys-vproc2-supply: + description: Supply for buck regulator vproc2 + vsys-vpu-supply: + description: Supply for buck regulator vpu + vsys-vs1-supply: + description: Supply for buck regulator vs1 + vsys-vs2-supply: + description: Supply for buck regulator vs2 + vs1-ldo1-supply: + description: Supply for LDOs vaud18, vcamio, vm18, vufs + vs1-ldo2-supply: + description: Supply for LDOs vcn18, vefuse, vio18, vrf18 + vs2-ldo1-supply: + description: + Supply for LDOs vsram_proc1, vsram_proc2, vsram_others, vsram_md + vs2-ldo2-supply: + description: Supply for LDOs va09, va12, vcn13, vrf12 + examples: - | #include diff --git a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml index 14ae3f00ef7e00..7dd2fe035e6d3a 100644 --- a/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml +++ b/Documentation/devicetree/bindings/mfd/qcom,tcsr.yaml @@ -19,6 +19,7 @@ properties: - enum: - qcom,msm8976-tcsr - qcom,msm8998-tcsr + - qcom,nord-tcsr - qcom,qcm2290-tcsr - qcom,qcs404-tcsr - qcom,qcs615-tcsr @@ -42,6 +43,7 @@ properties: - qcom,tcsr-apq8064 - qcom,tcsr-apq8084 - qcom,tcsr-ipq5018 + - qcom,tcsr-ipq5210 - qcom,tcsr-ipq5332 - qcom,tcsr-ipq5424 - qcom,tcsr-ipq6018 diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml b/Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml index 0676890f101e54..a58d9455a1a542 100644 --- a/Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml +++ b/Documentation/devicetree/bindings/mfd/rockchip,rk816.yaml @@ -44,8 +44,7 @@ properties: description: Telling whether or not this PMIC is controlling the system power. - wakeup-source: - type: boolean + wakeup-source: true vcc1-supply: description: diff --git a/Documentation/devicetree/bindings/mfd/samsung,s2mu005-pmic.yaml b/Documentation/devicetree/bindings/mfd/samsung,s2mu005-pmic.yaml new file mode 100644 index 00000000000000..aff68c035b38ef --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/samsung,s2mu005-pmic.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/samsung,s2mu005-pmic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MU005 Power Management IC + +maintainers: + - Kaustabh Chakraborty + +description: | + The S2MU005 is a companion power management IC which includes subdevices for + a charger controller, an MUIC (Micro USB Interface Controller), and flash and + RGB LED controllers. + +allOf: + - $ref: /schemas/power/supply/power-supply.yaml# + +properties: + compatible: + const: samsung,s2mu005-pmic + + flash: + $ref: /schemas/leds/samsung,s2mu005-flash.yaml# + description: + Child node describing flash LEDs. + + interrupts: + maxItems: 1 + + muic: + $ref: /schemas/extcon/samsung,s2mu005-muic.yaml# + description: + Child node describing MUIC device. + + multi-led: + type: object + + allOf: + - $ref: /schemas/leds/leds-class-multicolor.yaml# + + properties: + compatible: + const: samsung,s2mu005-rgb + + required: + - compatible + + unevaluatedProperties: false + + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@3d { + compatible = "samsung,s2mu005-pmic"; + reg = <0x3d>; + interrupt-parent = <&gpa2>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + + monitored-battery = <&battery>; + + flash { + compatible = "samsung,s2mu005-flash"; + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_FLASH; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_FLASH; + function-enumerator = <1>; + }; + }; + + muic { + compatible = "samsung,s2mu005-muic"; + + connector { + compatible = "usb-b-connector"; + label = "micro-USB"; + type = "micro"; + }; + + port { + muic_to_usb: endpoint { + remote-endpoint = <&usb_to_muic>; + }; + }; + }; + + multi-led { + compatible = "samsung,s2mu005-rgb"; + color = ; + function = LED_FUNCTION_INDICATOR; + linux,default-trigger = "pattern"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml b/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml index b023e1ef8d3ccd..e74ec49709941f 100644 --- a/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml +++ b/Documentation/devicetree/bindings/mfd/sprd,sc2731.yaml @@ -54,7 +54,9 @@ properties: regulators: type: object - $ref: /schemas/regulator/sprd,sc2731-regulator.yaml# + oneOf: + - $ref: /schemas/regulator/sprd,sc2730-regulator.yaml# + - $ref: /schemas/regulator/sprd,sc2731-regulator.yaml# patternProperties: "^adc@[0-9a-f]+$": diff --git a/Documentation/devicetree/bindings/mfd/st,stmpe.yaml b/Documentation/devicetree/bindings/mfd/st,stmpe.yaml index df43878fbe18f3..4bb05d544901c8 100644 --- a/Documentation/devicetree/bindings/mfd/st,stmpe.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stmpe.yaml @@ -127,6 +127,10 @@ properties: "#pwm-cells": const: 2 + required: + - compatible + - "#pwm-cells" + touchscreen: type: object $ref: /schemas/input/touchscreen/touchscreen.yaml# diff --git a/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml b/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml index ba14663c9266a5..cdce83f0580415 100644 --- a/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml @@ -4,17 +4,16 @@ $id: http://devicetree.org/schemas/mfd/ti,bq25703a.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: BQ25703A Charger Manager/Buck/Boost Converter +title: BQ257xx Charger Manager/Buck/Boost Converter maintainers: - Chris Morgan -allOf: - - $ref: /schemas/power/supply/power-supply.yaml# - properties: compatible: - const: ti,bq25703a + enum: + - ti,bq25703a + - ti,bq25792 reg: const: 0x6b @@ -25,7 +24,6 @@ properties: powering the device. minimum: 50000 maximum: 6400000 - default: 3250000 interrupts: maxItems: 1 @@ -57,11 +55,11 @@ properties: minimum: 0 maximum: 6350000 regulator-min-microvolt: - minimum: 4480000 - maximum: 20800000 + minimum: 2800000 + maximum: 22000000 regulator-max-microvolt: - minimum: 4480000 - maximum: 20800000 + minimum: 2800000 + maximum: 22000000 enable-gpios: description: The BQ25703 may require both a register write and a GPIO @@ -74,6 +72,61 @@ properties: - regulator-min-microvolt - regulator-max-microvolt +allOf: + - $ref: /schemas/power/supply/power-supply.yaml# + - if: + properties: + compatible: + const: ti,bq25703a + then: + properties: + input-current-limit-microamp: + minimum: 50000 + maximum: 6400000 + default: 3250000 + regulators: + properties: + vbus: + properties: + regulator-min-microamp: + minimum: 0 + maximum: 6350000 + regulator-max-microamp: + minimum: 0 + maximum: 6350000 + regulator-min-microvolt: + minimum: 4480000 + maximum: 20800000 + regulator-max-microvolt: + minimum: 4480000 + maximum: 20800000 + - if: + properties: + compatible: + const: ti,bq25792 + then: + properties: + input-current-limit-microamp: + minimum: 100000 + maximum: 3300000 + default: 3000000 + regulators: + properties: + vbus: + properties: + regulator-min-microamp: + minimum: 0 + maximum: 3320000 + regulator-max-microamp: + minimum: 0 + maximum: 3320000 + regulator-min-microvolt: + minimum: 2800000 + maximum: 22000000 + regulator-max-microvolt: + minimum: 2800000 + maximum: 22000000 + unevaluatedProperties: false required: diff --git a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml index df45ff56d44455..801f305e037464 100644 --- a/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml +++ b/Documentation/devicetree/bindings/misc/fsl,qoriq-mc.yaml @@ -166,7 +166,7 @@ examples: */ ranges = <0x0 0x0 0x8 0x0c000000 0x4000000 0x1 0x0 0x8 0x18000000 0x8000000>; - + /* define map for ICIDs 23-64 */ iommu-map = <23 &smmu 23 41>; /* define msi map for ICIDs 23-64 */ diff --git a/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml b/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml index ca830dd06de2d9..2876fdd7c6e66b 100644 --- a/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml +++ b/Documentation/devicetree/bindings/misc/qcom,fastrpc.yaml @@ -25,6 +25,7 @@ properties: - items: - enum: - qcom,glymur-fastrpc + - qcom,hawi-fastrpc - const: qcom,kaanapali-fastrpc label: diff --git a/Documentation/devicetree/bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml index 41c9b22523e7dc..e447579e0f22ef 100644 --- a/Documentation/devicetree/bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/hisilicon,hi3798cv200-dw-mshc.yaml @@ -39,10 +39,11 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array description: | DWMMC core on Hi3798MV2x SoCs has a delay-locked-loop(DLL) attached to card data input path. - It is integrated into CRG core on the SoC and has to be controlled during tuning. + It is integrated into CRG core on the SoC and has to be controlled during tuning items: - - description: A phandle pointed to the CRG syscon node - - description: Sample DLL register offset in CRG address space + - items: + - description: A phandle pointed to the CRG syscon node + - description: Sample DLL register offset in CRG address space required: - compatible diff --git a/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml new file mode 100644 index 00000000000000..bd558a11b79294 --- /dev/null +++ b/Documentation/devicetree/bindings/mmc/qcom,sdhci-msm.yaml @@ -0,0 +1,282 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mmc/qcom,sdhci-msm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDHCI controller (sdhci-msm) + +maintainers: + - Bjorn Andersson + - Konrad Dybcio + +description: + Secure Digital Host Controller Interface (SDHCI) present on + Qualcomm SOCs supports SD/MMC/SDIO devices. + +properties: + compatible: + oneOf: + - enum: + - qcom,sdhci-msm-v4 + deprecated: true + - items: + - enum: + - qcom,apq8084-sdhci + - qcom,ipq4019-sdhci + - qcom,ipq8074-sdhci + - qcom,msm8226-sdhci + - qcom,msm8953-sdhci + - qcom,msm8974-sdhci + - qcom,msm8976-sdhci + - qcom,msm8916-sdhci + - qcom,msm8992-sdhci + - qcom,msm8994-sdhci + - qcom,msm8996-sdhci + - qcom,msm8998-sdhci + - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0 + - items: + - enum: + - qcom,eliza-sdhci + - qcom,hawi-sdhci + - qcom,ipq5018-sdhci + - qcom,ipq5210-sdhci + - qcom,ipq5332-sdhci + - qcom,ipq5424-sdhci + - qcom,ipq6018-sdhci + - qcom,ipq9574-sdhci + - qcom,ipq9650-sdhci + - qcom,kaanapali-sdhci + - qcom,milos-sdhci + - qcom,qcm2290-sdhci + - qcom,qcs404-sdhci + - qcom,qcs615-sdhci + - qcom,qcs8300-sdhci + - qcom,qdu1000-sdhci + - qcom,sa8775p-sdhci + - qcom,sar2130p-sdhci + - qcom,sc7180-sdhci + - qcom,sc7280-sdhci + - qcom,sc8280xp-sdhci + - qcom,sdm630-sdhci + - qcom,sdm670-sdhci + - qcom,sdm845-sdhci + - qcom,sdx55-sdhci + - qcom,sdx65-sdhci + - qcom,sdx75-sdhci + - qcom,shikra-sdhci + - qcom,sm6115-sdhci + - qcom,sm6125-sdhci + - qcom,sm6350-sdhci + - qcom,sm6375-sdhci + - qcom,sm7150-sdhci + - qcom,sm8150-sdhci + - qcom,sm8250-sdhci + - qcom,sm8350-sdhci + - qcom,sm8450-sdhci + - qcom,sm8550-sdhci + - qcom,sm8650-sdhci + - qcom,sm8750-sdhci + - qcom,x1e80100-sdhci + - const: qcom,sdhci-msm-v5 # for sdcc version 5.0 + + reg: + minItems: 1 + maxItems: 4 + + reg-names: + minItems: 1 + maxItems: 4 + + clocks: + minItems: 2 + items: + - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock + - description: SDC MMC clock, MCLK + - description: TCXO clock + - description: clock for Inline Crypto Engine + - description: SDCC bus voter clock + - description: reference clock for RCLK delay calibration + - description: sleep clock for RCLK delay calibration + + clock-names: + minItems: 2 + items: + - const: iface + - const: core + - const: xo + - enum: [ice, bus, cal, sleep] + - enum: [ice, bus, cal, sleep] + - enum: [ice, bus, cal, sleep] + - enum: [ice, bus, cal, sleep] + + dma-coherent: true + + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: hc_irq + - const: pwr_irq + + pinctrl-names: + minItems: 1 + items: + - const: default + - const: sleep + + pinctrl-0: + description: + Should specify pin control groups used for this controller. + + pinctrl-1: + description: + Should specify sleep pin control groups used for this controller. + + resets: + maxItems: 1 + + qcom,ddr-config: + $ref: /schemas/types.yaml#/definitions/uint32 + description: platform specific settings for DDR_CONFIG reg. + + qcom,dll-config: + $ref: /schemas/types.yaml#/definitions/uint32 + description: platform specific settings for DLL_CONFIG reg. + + iommus: + minItems: 1 + maxItems: 8 + description: | + phandle to apps_smmu node with sid mask. + + interconnects: + minItems: 1 + items: + - description: data path, sdhc to ddr + - description: config path, cpu to sdhc + + interconnect-names: + minItems: 1 + items: + - const: sdhc-ddr + - const: cpu-sdhc + + power-domains: + description: A phandle to sdhci power domain node + maxItems: 1 + + operating-points-v2: true + +patternProperties: + '^opp-table(-[a-z0-9]+)?$': + if: + properties: + compatible: + const: operating-points-v2 + then: + patternProperties: + '^opp-?[0-9]+$': + required: + - required-opps + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +allOf: + - $ref: sdhci-common.yaml# + + - if: + properties: + compatible: + contains: + enum: + - qcom,sdhci-msm-v4 + then: + properties: + reg: + minItems: 2 + items: + - description: Host controller register map + - description: SD Core register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 2 + items: + - const: hc + - const: core + - const: cqhci + - const: ice + else: + properties: + reg: + minItems: 1 + items: + - description: Host controller register map + - description: CQE register map + - description: Inline Crypto Engine register map + reg-names: + minItems: 1 + items: + - const: hc + - const: cqhci + - const: ice + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + sdhc_2: mmc@8804000 { + compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; + reg = <0 0x08804000 0 0x1000>; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "core", "xo"; + iommus = <&apps_smmu 0x4a0 0x0>; + qcom,dll-config = <0x0007642c>; + qcom,ddr-config = <0x80040868>; + power-domains = <&rpmhpd RPMHPD_CX>; + + operating-points-v2 = <&sdhc2_opp_table>; + + sdhc2_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-19200000 { + opp-hz = /bits/ 64 <19200000>; + required-opps = <&rpmhpd_opp_min_svs>; + }; + + opp-50000000 { + opp-hz = /bits/ 64 <50000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-202000000 { + opp-hz = /bits/ 64 <202000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml index 64fac0d11329ad..4d66966ce29001 100644 --- a/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml +++ b/Documentation/devicetree/bindings/mmc/renesas,sdhi.yaml @@ -52,6 +52,7 @@ properties: - renesas,sdhi-r8a77980 # R-Car V3H - renesas,sdhi-r8a77990 # R-Car E3 - renesas,sdhi-r8a77995 # R-Car D3 + - renesas,sdhi-r8a779md # R-Car M3Le - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2 - items: - enum: diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml deleted file mode 100644 index 695a95e8f35d2c..00000000000000 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ /dev/null @@ -1,279 +0,0 @@ -# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Qualcomm SDHCI controller (sdhci-msm) - -maintainers: - - Bjorn Andersson - - Konrad Dybcio - -description: - Secure Digital Host Controller Interface (SDHCI) present on - Qualcomm SOCs supports SD/MMC/SDIO devices. - -properties: - compatible: - oneOf: - - enum: - - qcom,sdhci-msm-v4 - deprecated: true - - items: - - enum: - - qcom,apq8084-sdhci - - qcom,ipq4019-sdhci - - qcom,ipq8074-sdhci - - qcom,msm8226-sdhci - - qcom,msm8953-sdhci - - qcom,msm8974-sdhci - - qcom,msm8976-sdhci - - qcom,msm8916-sdhci - - qcom,msm8992-sdhci - - qcom,msm8994-sdhci - - qcom,msm8996-sdhci - - qcom,msm8998-sdhci - - const: qcom,sdhci-msm-v4 # for sdcc versions less than 5.0 - - items: - - enum: - - qcom,ipq5018-sdhci - - qcom,ipq5210-sdhci - - qcom,ipq5332-sdhci - - qcom,ipq5424-sdhci - - qcom,ipq6018-sdhci - - qcom,ipq9574-sdhci - - qcom,ipq9650-sdhci - - qcom,kaanapali-sdhci - - qcom,milos-sdhci - - qcom,qcm2290-sdhci - - qcom,qcs404-sdhci - - qcom,qcs615-sdhci - - qcom,qcs8300-sdhci - - qcom,qdu1000-sdhci - - qcom,sa8775p-sdhci - - qcom,sar2130p-sdhci - - qcom,sc7180-sdhci - - qcom,sc7280-sdhci - - qcom,sc8280xp-sdhci - - qcom,sdm630-sdhci - - qcom,sdm670-sdhci - - qcom,sdm845-sdhci - - qcom,sdx55-sdhci - - qcom,sdx65-sdhci - - qcom,sdx75-sdhci - - qcom,sm6115-sdhci - - qcom,sm6125-sdhci - - qcom,sm6350-sdhci - - qcom,sm6375-sdhci - - qcom,sm7150-sdhci - - qcom,sm8150-sdhci - - qcom,sm8250-sdhci - - qcom,sm8350-sdhci - - qcom,sm8450-sdhci - - qcom,sm8550-sdhci - - qcom,sm8650-sdhci - - qcom,sm8750-sdhci - - qcom,x1e80100-sdhci - - const: qcom,sdhci-msm-v5 # for sdcc version 5.0 - - reg: - minItems: 1 - maxItems: 4 - - reg-names: - minItems: 1 - maxItems: 4 - - clocks: - minItems: 2 - items: - - description: Main peripheral bus clock, PCLK/HCLK - AHB Bus clock - - description: SDC MMC clock, MCLK - - description: TCXO clock - - description: clock for Inline Crypto Engine - - description: SDCC bus voter clock - - description: reference clock for RCLK delay calibration - - description: sleep clock for RCLK delay calibration - - clock-names: - minItems: 2 - items: - - const: iface - - const: core - - const: xo - - enum: [ice, bus, cal, sleep] - - enum: [ice, bus, cal, sleep] - - enum: [ice, bus, cal, sleep] - - enum: [ice, bus, cal, sleep] - - dma-coherent: true - - interrupts: - maxItems: 2 - - interrupt-names: - items: - - const: hc_irq - - const: pwr_irq - - pinctrl-names: - minItems: 1 - items: - - const: default - - const: sleep - - pinctrl-0: - description: - Should specify pin control groups used for this controller. - - pinctrl-1: - description: - Should specify sleep pin control groups used for this controller. - - resets: - maxItems: 1 - - qcom,ddr-config: - $ref: /schemas/types.yaml#/definitions/uint32 - description: platform specific settings for DDR_CONFIG reg. - - qcom,dll-config: - $ref: /schemas/types.yaml#/definitions/uint32 - description: platform specific settings for DLL_CONFIG reg. - - iommus: - minItems: 1 - maxItems: 8 - description: | - phandle to apps_smmu node with sid mask. - - interconnects: - minItems: 1 - items: - - description: data path, sdhc to ddr - - description: config path, cpu to sdhc - - interconnect-names: - minItems: 1 - items: - - const: sdhc-ddr - - const: cpu-sdhc - - power-domains: - description: A phandle to sdhci power domain node - maxItems: 1 - - operating-points-v2: true - -patternProperties: - '^opp-table(-[a-z0-9]+)?$': - if: - properties: - compatible: - const: operating-points-v2 - then: - patternProperties: - '^opp-?[0-9]+$': - required: - - required-opps - -required: - - compatible - - reg - - clocks - - clock-names - - interrupts - -allOf: - - $ref: sdhci-common.yaml# - - - if: - properties: - compatible: - contains: - enum: - - qcom,sdhci-msm-v4 - then: - properties: - reg: - minItems: 2 - items: - - description: Host controller register map - - description: SD Core register map - - description: CQE register map - - description: Inline Crypto Engine register map - reg-names: - minItems: 2 - items: - - const: hc - - const: core - - const: cqhci - - const: ice - else: - properties: - reg: - minItems: 1 - items: - - description: Host controller register map - - description: CQE register map - - description: Inline Crypto Engine register map - reg-names: - minItems: 1 - items: - - const: hc - - const: cqhci - - const: ice - -unevaluatedProperties: false - -examples: - - | - #include - #include - #include - #include - - sdhc_2: mmc@8804000 { - compatible = "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"; - reg = <0 0x08804000 0 0x1000>; - - interrupts = , - ; - interrupt-names = "hc_irq", "pwr_irq"; - - clocks = <&gcc GCC_SDCC2_AHB_CLK>, - <&gcc GCC_SDCC2_APPS_CLK>, - <&rpmhcc RPMH_CXO_CLK>; - clock-names = "iface", "core", "xo"; - iommus = <&apps_smmu 0x4a0 0x0>; - qcom,dll-config = <0x0007642c>; - qcom,ddr-config = <0x80040868>; - power-domains = <&rpmhpd RPMHPD_CX>; - - operating-points-v2 = <&sdhc2_opp_table>; - - sdhc2_opp_table: opp-table { - compatible = "operating-points-v2"; - - opp-19200000 { - opp-hz = /bits/ 64 <19200000>; - required-opps = <&rpmhpd_opp_min_svs>; - }; - - opp-50000000 { - opp-hz = /bits/ 64 <50000000>; - required-opps = <&rpmhpd_opp_low_svs>; - }; - - opp-100000000 { - opp-hz = /bits/ 64 <100000000>; - required-opps = <&rpmhpd_opp_svs>; - }; - - opp-202000000 { - opp-hz = /bits/ 64 <202000000>; - required-opps = <&rpmhpd_opp_svs_l1>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml index 9a055d963a7f0c..34d202af909f2d 100644 --- a/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml +++ b/Documentation/devicetree/bindings/mmc/spacemit,sdhci.yaml @@ -44,6 +44,18 @@ properties: - const: axi - const: sdh + pinctrl-names: + minItems: 1 + items: + - const: default + - const: uhs + + pinctrl-0: + description: Default pinctrl state for 3.3V operation + + pinctrl-1: + description: Optional pinctrl state for 1.8V UHS operation with "uhs" name + required: - compatible - reg @@ -62,4 +74,7 @@ examples: interrupt-parent = <&plic>; clocks = <&clk_apmu 10>, <&clk_apmu 13>; clock-names = "core", "io"; + pinctrl-names = "default", "uhs"; + pinctrl-0 = <&sdhci_default_cfg>; + pinctrl-1 = <&sdhci_uhs_cfg>; }; diff --git a/Documentation/devicetree/bindings/mtd/nand-chip.yaml b/Documentation/devicetree/bindings/mtd/nand-chip.yaml index 8800d1d0726656..effdc4f99017d6 100644 --- a/Documentation/devicetree/bindings/mtd/nand-chip.yaml +++ b/Documentation/devicetree/bindings/mtd/nand-chip.yaml @@ -23,6 +23,15 @@ properties: description: Contains the chip-select IDs. + nand-randomizer: + description: | + Control the data randomizer feature. + 0: Disable randomizer. + 1: Enable randomizer. + If absent, the current hardware state is left unchanged. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + required: - reg diff --git a/Documentation/devicetree/bindings/net/airoha,an8801.yaml b/Documentation/devicetree/bindings/net/airoha,an8801.yaml new file mode 100644 index 00000000000000..d6e5a60a6b20cd --- /dev/null +++ b/Documentation/devicetree/bindings/net/airoha,an8801.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/airoha,an8801.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Airoha AN8801R Series PHY + +maintainers: + - AngeloGioacchino Del Regno + +description: + The Airoha AN8801R is a low power single-port Ethernet PHY Transceiver + with Single-port serdes interface for 1000Base-X/RGMII; this chip is + compliant with 10Base-T, 100Base-TX and 1000Base-T IEEE 802.3(u,ab) + and supports Energy Efficient Ethernet (802.3az), Full Duplex Control + Flow (802.3x), auto-negotiation, crossover detect and autocorrection, + Wake-on-LAN with Magic Packet, and Jumbo Frame up to 9 Kilobytes. + This PHY also supports up to three user-configurable LEDs, which are + usually used for LAN Activity, 100M, 1000M indication. + +allOf: + - $ref: ethernet-phy.yaml# + +properties: + compatible: + enum: + - ethernet-phy-idc0ff.0421 + + reg: + maxItems: 1 + + leds: + type: object + description: + Describes the LEDs associated to the PHY + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^led@[0-2]$": + type: object + description: PHY LEDs + $ref: /schemas/leds/common.yaml# + + properties: + reg: + enum: [0, 1, 2] + + function-enumerator: + enum: [0, 1, 2] + description: | + Specifies a function for offloading LED functionality to the PHY: + 0 - No offloading + 1 - Link Availability + 2 - Network Activity + + required: + - reg + + unevaluatedProperties: false + + additionalProperties: false + + wakeup-source: + $ref: /schemas/types.yaml#/definitions/flag + description: + Enable Wake-on-LAN support + +required: + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-phy@0 { + compatible = "ethernet-phy-idc0ff.0421"; + reg = <0>; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { + reg = <0>; + color = ; + function = LED_FUNCTION_LAN; + default-state = "keep"; + }; + + led@1 { + reg = <1>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + default-state = "keep"; + }; + + led@2 { + reg = <2>; + color = ; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + default-state = "keep"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml index fbe2ddcdd909cb..17fe2edf4886ec 100644 --- a/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml +++ b/Documentation/devicetree/bindings/net/airoha,en7581-eth.yaml @@ -130,6 +130,42 @@ patternProperties: maximum: 4 description: GMAC port identifier + allOf: + - if: + properties: + reg: + contains: + items: + - enum: + - 3 + - 4 + then: + properties: + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + + patternProperties: + "^ethernet@[0-5]$": + type: object + unevaluatedProperties: false + $ref: ethernet-controller.yaml# + description: External ethernet port ID available on the GDM port + + properties: + compatible: + const: airoha,eth-port + + reg: + maximum: 5 + description: External ethernet port identifier + + required: + - reg + - compatible + required: - reg - compatible @@ -191,9 +227,27 @@ examples: #address-cells = <1>; #size-cells = <0>; - mac: ethernet@1 { + ethernet@1 { compatible = "airoha,eth-mac"; reg = <1>; }; + + ethernet@4 { + compatible = "airoha,eth-mac"; + reg = <4>; + + #address-cells = <1>; + #size-cells = <0>; + + ethernet@0 { + compatible = "airoha,eth-port"; + reg = <0>; + }; + + ethernet@1 { + compatible = "airoha,eth-port"; + reg = <1>; + }; + }; }; }; diff --git a/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml b/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml index 45630067d3c8ed..0beda26ae8bb45 100644 --- a/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml +++ b/Documentation/devicetree/bindings/net/bluetooth/qcom,wcn6855-bt.yaml @@ -50,9 +50,6 @@ properties: description: VDD_RFA_1P7 supply regulator handle deprecated: true - vddrfa1p8-supply: - description: VDD_RFA_1P8 supply regulator handle - vddrfacmn-supply: description: VDD_RFA_CMN supply regulator handle @@ -68,7 +65,7 @@ required: - vddbtcmx-supply - vddrfa0p8-supply - vddrfa1p2-supply - - vddrfa1p8-supply + - vddrfa1p7-supply - vddrfacmn-supply - vddwlcx-supply - vddwlmx-supply @@ -91,7 +88,7 @@ examples: vddbtcmx-supply = <&vreg_pmu_btcmx_0p8>; vddrfa0p8-supply = <&vreg_pmu_rfa_0p8>; vddrfa1p2-supply = <&vreg_pmu_rfa_1p2>; - vddrfa1p8-supply = <&vreg_pmu_rfa_1p7>; + vddrfa1p7-supply = <&vreg_pmu_rfa_1p7>; vddrfacmn-supply = <&vreg_pmu_rfa_cmn_0p8>; vddwlcx-supply = <&vreg_pmu_wlcx_0p8>; vddwlmx-supply = <&vreg_pmu_wlmx_0p8>; diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.txt b/Documentation/devicetree/bindings/net/dsa/dsa.txt deleted file mode 100644 index dab208b5c7c7e0..00000000000000 --- a/Documentation/devicetree/bindings/net/dsa/dsa.txt +++ /dev/null @@ -1,4 +0,0 @@ -Distributed Switch Architecture Device Tree Bindings ----------------------------------------------------- - -See Documentation/devicetree/bindings/net/dsa/dsa.yaml for the documentation. diff --git a/Documentation/devicetree/bindings/net/dsa/dsa.yaml b/Documentation/devicetree/bindings/net/dsa/dsa.yaml index 2abd036578d150..801e1411e5c2b6 100644 --- a/Documentation/devicetree/bindings/net/dsa/dsa.yaml +++ b/Documentation/devicetree/bindings/net/dsa/dsa.yaml @@ -28,7 +28,11 @@ properties: A two element list indicates which DSA cluster, and position within the cluster a switch takes. <0 0> is cluster 0, switch 0. <0 1> is cluster 0, switch 1. <1 0> is cluster 1, switch 0. A switch not part of any cluster - (single device hanging off a CPU port) must not specify this property + (single device hanging off a CPU port) does not usually need to specify + this property, and then it becomes cluster 0, switch 0. For a topology + aware switch, its switch index can be specified through this property, + even if it is not part of any cluster. Also, topology-unaware switches + must always be defined as index 0 of their cluster. $ref: /schemas/types.yaml#/definitions/uint32-array additionalProperties: true diff --git a/Documentation/devicetree/bindings/net/dsa/lan9303.txt b/Documentation/devicetree/bindings/net/dsa/lan9303.txt deleted file mode 100644 index 46a732087f5cab..00000000000000 --- a/Documentation/devicetree/bindings/net/dsa/lan9303.txt +++ /dev/null @@ -1,100 +0,0 @@ -SMSC/MicroChip LAN9303 three port ethernet switch -------------------------------------------------- - -Required properties: - -- compatible: should be - - "smsc,lan9303-i2c" for I2C managed mode - or - - "smsc,lan9303-mdio" for mdio managed mode - -Optional properties: - -- reset-gpios: GPIO to be used to reset the whole device -- reset-duration: reset duration in milliseconds, defaults to 200 ms - -Subnodes: - -The integrated switch subnode should be specified according to the binding -described in dsa/dsa.txt. The CPU port of this switch is always port 0. - -Note: always use 'reg = <0/1/2>;' for the three DSA ports, even if the device is -configured to use 1/2/3 instead. This hardware configuration will be -auto-detected and mapped accordingly. - -Example: - -I2C managed mode: - - master: masterdevice@X { - - fixed-link { /* RMII fixed link to LAN9303 */ - speed = <100>; - full-duplex; - }; - }; - - switch: switch@a { - compatible = "smsc,lan9303-i2c"; - reg = <0xa>; - reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - reset-duration = <200>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { /* RMII fixed link to master */ - reg = <0>; - ethernet = <&master>; - }; - - port@1 { /* external port 1 */ - reg = <1>; - label = "lan1"; - }; - - port@2 { /* external port 2 */ - reg = <2>; - label = "lan2"; - }; - }; - }; - -MDIO managed mode: - - master: masterdevice@X { - phy-handle = <&switch>; - - mdio { - #address-cells = <1>; - #size-cells = <0>; - - switch: switch-phy@0 { - compatible = "smsc,lan9303-mdio"; - reg = <0>; - reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; - reset-duration = <100>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - ethernet = <&master>; - }; - - port@1 { /* external port 1 */ - reg = <1>; - label = "lan1"; - }; - - port@2 { /* external port 2 */ - reg = <2>; - label = "lan2"; - }; - }; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/net/dsa/nxp,netc-switch.yaml b/Documentation/devicetree/bindings/net/dsa/nxp,netc-switch.yaml new file mode 100644 index 00000000000000..1b35e4cbd04908 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/nxp,netc-switch.yaml @@ -0,0 +1,131 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/nxp,netc-switch.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NETC Switch family + +description: > + The NETC presents itself as a multi-function PCIe Root Complex Integrated + Endpoint (RCiEP) and provides full 802.1Q Ethernet switch functionality, + advanced QoS with 8 traffic classes and 4 drop resilience levels, and a + full range of TSN standards capabilities. + + The CPU port of the switch connects to an internal ENETC. The switch and + the internal ENETC are fully integrated into the NETC IP, a back-to-back + MAC is not required. Instead, a light-weight "pseudo MAC" provides the + delineation between the switch and ENETC. This translates to lower power + (less logic and memory) and lower delay (as there is no serialization + delay across this link). + +maintainers: + - Wei Fang + +properties: + compatible: + enum: + - pci1131,eef2 + + reg: + maxItems: 1 + + dsa,member: + description: > + The property indicates DSA cluster and switch index. For NETC switch, + the valid range of the switch index is 1 ~ 7, the index is reflected + in the switch tag as an indication of the switch ID where the frame + originated. The value 0 is reserved for ENETC VEPA switch, whose ID + is hardwired to zero. + items: + - true + - minimum: 1 + maximum: 7 + + ethernet-ports: + type: object + patternProperties: + "^ethernet-port@[0-9a-f]$": + type: object + $ref: dsa-port.yaml# + + properties: + clocks: + items: + - description: MAC transmit/receive reference clock. + + clock-names: + items: + - const: ref + + mdio: + $ref: /schemas/net/mdio.yaml# + unevaluatedProperties: false + description: + Optional child node for switch port, otherwise use NETC EMDIO. + + unevaluatedProperties: false + +required: + - compatible + - reg + - dsa,member + - ethernet-ports + +allOf: + - $ref: /schemas/pci/pci-device.yaml + - $ref: dsa.yaml# + +unevaluatedProperties: false + +examples: + - | + pcie { + #address-cells = <3>; + #size-cells = <2>; + + ethernet-switch@0,2 { + compatible = "pci1131,eef2"; + reg = <0x200 0 0 0 0>; + dsa,member = <0 1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-port@0 { + reg = <0>; + phy-handle = <ðphy0>; + phy-mode = "mii"; + }; + + ethernet-port@1 { + reg = <1>; + phy-handle = <ðphy1>; + phy-mode = "mii"; + }; + + ethernet-port@2 { + reg = <2>; + clocks = <&scmi_clk 103>; + clock-names = "ref"; + phy-handle = <ðphy2>; + phy-mode = "rgmii-id"; + }; + + ethernet-port@3 { + reg = <3>; + ethernet = <&enetc3>; + phy-mode = "internal"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/dsa/smsc,lan9303.yaml b/Documentation/devicetree/bindings/net/dsa/smsc,lan9303.yaml new file mode 100644 index 00000000000000..42f8473538a078 --- /dev/null +++ b/Documentation/devicetree/bindings/net/dsa/smsc,lan9303.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/dsa/smsc,lan9303.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SMSC/MicroChip LAN9303 three port ethernet switch + +maintainers: + - Frank Li + +description: + The LAN9303 is a three port ethernet switch with integrated PHYs for the + two external ports. The third port is an RMII/MII interface to a host + processor. The device can be managed via I2C or MDIO. + + Note - always use 'reg = <0/1/2>;' for the three DSA ports, even if the + device is configured to use 1/2/3 instead. This hardware configuration + will be auto-detected and mapped accordingly. + +properties: + compatible: + enum: + - smsc,lan9303-i2c + - smsc,lan9303-mdio + + reg: + maxItems: 1 + + reset-gpios: + description: + GPIO to be used to reset the whole device + maxItems: 1 + + reset-duration: + description: + Reset duration in milliseconds + default: 200 + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + +unevaluatedProperties: false + +allOf: + - $ref: dsa.yaml# + +examples: + - | + #include + + /* I2C managed mode */ + i2c { + #address-cells = <1>; + #size-cells = <0>; + + switch@a { + compatible = "smsc,lan9303-i2c"; + reg = <0xa>; + reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + reset-duration = <200>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&master>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + }; + }; + }; + + - | + #include + + /* MDIO managed mode */ + mdio { + #address-cells = <1>; + #size-cells = <0>; + + switch@0 { + compatible = "smsc,lan9303-mdio"; + reg = <0>; + reset-gpios = <&gpio7 6 GPIO_ACTIVE_LOW>; + reset-duration = <100>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "cpu"; + ethernet = <&master>; + }; + + port@1 { + reg = <1>; + label = "lan1"; + }; + + port@2 { + reg = <2>; + label = "lan2"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 21a1a63506f010..c3ebb3af8b528b 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -106,10 +106,13 @@ properties: by software. clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 description: - External clock connected to the PHY. If not specified it is assumed - that the PHY uses a fixed crystal or an internal oscillator. + External clock connected to the PHY or RX and TX clocks that the PHY + requires to enable explicitly. If not specified it is assumed + that the PHY uses a fixed crystal or an internal oscillator or that the + RX/TX clocks are hardware enabled by default. enet-phy-lane-swap: $ref: /schemas/types.yaml#/definitions/flag diff --git a/Documentation/devicetree/bindings/net/mdio.txt b/Documentation/devicetree/bindings/net/mdio.txt deleted file mode 100644 index cf8a0105488e64..00000000000000 --- a/Documentation/devicetree/bindings/net/mdio.txt +++ /dev/null @@ -1 +0,0 @@ -This file has moved to mdio.yaml. diff --git a/Documentation/devicetree/bindings/net/mediatek,net.yaml b/Documentation/devicetree/bindings/net/mediatek,net.yaml index cc346946291af5..6bbd83c6aaf744 100644 --- a/Documentation/devicetree/bindings/net/mediatek,net.yaml +++ b/Documentation/devicetree/bindings/net/mediatek,net.yaml @@ -67,8 +67,7 @@ properties: - const: ppe sram: - $ref: /schemas/types.yaml#/definitions/phandle - description: phandle to mmio SRAM + maxItems: 1 mediatek,ethsys: $ref: /schemas/types.yaml#/definitions/phandle diff --git a/Documentation/devicetree/bindings/net/microchip,lan8650.yaml b/Documentation/devicetree/bindings/net/microchip,lan8650.yaml index 61e11d4a07c407..766ff58147ae36 100644 --- a/Documentation/devicetree/bindings/net/microchip,lan8650.yaml +++ b/Documentation/devicetree/bindings/net/microchip,lan8650.yaml @@ -67,7 +67,7 @@ examples: pinctrl-names = "default"; pinctrl-0 = <ð0_pins>; interrupt-parent = <&gpio>; - interrupts = <6 IRQ_TYPE_EDGE_FALLING>; + interrupts = <6 IRQ_TYPE_LEVEL_LOW>; local-mac-address = [04 05 06 01 02 03]; spi-max-frequency = <15000000>; }; diff --git a/Documentation/devicetree/bindings/net/microchip,lan95xx.yaml b/Documentation/devicetree/bindings/net/microchip,lan95xx.yaml index accff93d38f806..b9c39400904028 100644 --- a/Documentation/devicetree/bindings/net/microchip,lan95xx.yaml +++ b/Documentation/devicetree/bindings/net/microchip,lan95xx.yaml @@ -20,6 +20,8 @@ properties: compatible: items: - enum: + - usb424,7500 # SMSC LAN7500 USB Ethernet Device + - usb424,7505 # SMSC LAN7505 USB Ethernet Device - usb424,9500 # SMSC9500 USB Ethernet Device - usb424,9505 # SMSC9505 USB Ethernet Device - usb424,9530 # SMSC LAN9530 USB Ethernet Device diff --git a/Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml b/Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml index 306ef9ecf2b919..0f0f35865ef419 100644 --- a/Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml +++ b/Documentation/devicetree/bindings/net/microchip,lan966x-switch.yaml @@ -17,7 +17,7 @@ description: | properties: $nodename: - pattern: "^switch@[0-9a-f]+$" + pattern: "^(ethernet-)?switch@[0-9a-f]+$" compatible: const: microchip,lan966x-switch @@ -70,7 +70,7 @@ properties: additionalProperties: false patternProperties: - "^port@[0-9a-f]+$": + "^(ethernet-)?port@[0-9a-f]+$": type: object $ref: /schemas/net/ethernet-controller.yaml# @@ -138,7 +138,7 @@ additionalProperties: false examples: - | #include - switch: switch@e0000000 { + switch: ethernet-switch@e0000000 { compatible = "microchip,lan966x-switch"; reg = <0xe0000000 0x0100000>, <0xe2000000 0x0800000>; @@ -151,14 +151,14 @@ examples: #address-cells = <1>; #size-cells = <0>; - port0: port@0 { + port0: ethernet-port@0 { reg = <0>; phy-handle = <&phy0>; phys = <&serdes 0 0>; phy-mode = "gmii"; }; - port1: port@1 { + port1: ethernet-port@1 { reg = <1>; sfp = <&sfp_eth1>; managed = "in-band-status"; diff --git a/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml index ca61cc37a79028..ca4200afa793bc 100644 --- a/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml +++ b/Documentation/devicetree/bindings/net/pse-pd/microchip,pd692x0.yaml @@ -22,6 +22,10 @@ properties: reg: maxItems: 1 + disable-ports-gpios: + description: GPIO pin to disable PoE on all ports + maxItems: 1 + vdd-supply: description: Regulator that provides 3.3V VDD power supply. diff --git a/Documentation/devicetree/bindings/net/qca,ar803x.yaml b/Documentation/devicetree/bindings/net/qca,ar803x.yaml index 7ae5110e7aa2cc..53f648c4135fc7 100644 --- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml +++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml @@ -28,6 +28,16 @@ allOf: reg: const: 7 # This PHY is always at MDIO address 7 in the IPQ5018 SoC + clocks: + items: + - description: RX clock + - description: TX clock + + clock-names: + items: + - const: rx + - const: tx + resets: items: - description: @@ -42,6 +52,11 @@ allOf: of this PHY are directly connected to an RJ45 connector. type: boolean + required: + - clocks + - clock-names + - resets + properties: compatible: enum: @@ -162,6 +177,7 @@ examples: }; }; - | + #include #include mdio { @@ -172,6 +188,9 @@ examples: compatible = "ethernet-phy-id004d.d0c0"; reg = <7>; + clocks = <&gcc GCC_GEPHY_RX_CLK>, + <&gcc GCC_GEPHY_TX_CLK>; + clock-names = "rx", "tx"; resets = <&gcc GCC_GEPHY_MISC_ARES>; }; }; diff --git a/Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml b/Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml index b30544410d0923..33746c238513d7 100644 --- a/Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml +++ b/Documentation/devicetree/bindings/net/qcom,bam-dmux.yaml @@ -42,7 +42,19 @@ properties: description: State bits used by the AP to signal the modem. items: - description: Power control + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 - description: Power control acknowledgment + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: Names for the state bits used by the AP to signal the modem. diff --git a/Documentation/devicetree/bindings/net/qcom,ipa.yaml b/Documentation/devicetree/bindings/net/qcom,ipa.yaml index fdeaa81b96454e..68ec76fe447356 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipa.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipa.yaml @@ -128,7 +128,19 @@ properties: description: State bits used in by the AP to signal the modem. items: - description: Whether the "ipa-clock-enabled" state bit is valid + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 - description: Whether the IPA clock is enabled (if valid) + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml index 753f370b760593..6d0b21a10732a6 100644 --- a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml +++ b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Qualcomm IPQ packet process engine (PPE) maintainers: - - Luo Jie + - Luo Jie - Lei Wei - Suruchi Agarwal - Pavithra R diff --git a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml index 02e4e33e996984..271e05bae9c574 100644 --- a/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml +++ b/Documentation/devicetree/bindings/net/realtek,rtl9301-mdio.yaml @@ -18,7 +18,14 @@ properties: - realtek,rtl9302c-mdio - realtek,rtl9303-mdio - const: realtek,rtl9301-mdio - - const: realtek,rtl9301-mdio + - items: + - enum: + - realtek,rtl9312-mdio + - realtek,rtl9313-mdio + - const: realtek,rtl9311-mdio + - enum: + - realtek,rtl9301-mdio + - realtek,rtl9311-mdio '#address-cells': const: 1 diff --git a/Documentation/devicetree/bindings/net/renesas,ether.yaml b/Documentation/devicetree/bindings/net/renesas,ether.yaml index f0a52f47f95a0d..dd7187f12a6757 100644 --- a/Documentation/devicetree/bindings/net/renesas,ether.yaml +++ b/Documentation/devicetree/bindings/net/renesas,ether.yaml @@ -121,8 +121,7 @@ examples: #size-cells = <0>; phy1: ethernet-phy@1 { - compatible = "ethernet-phy-id0022.1537", - "ethernet-phy-ieee802.3-c22"; + compatible = "ethernet-phy-id0022.1537"; reg = <1>; interrupt-parent = <&irqc0>; interrupts = <0 IRQ_TYPE_LEVEL_LOW>; diff --git a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml index 313a1533166120..fdcc61c65f87d1 100644 --- a/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/starfive,jh7110-dwmac.yaml @@ -31,7 +31,7 @@ properties: - const: starfive,jh7110-dwmac - const: snps,dwmac-5.20 - items: - - const: starfive,jh8100-dwmac + - const: starfive,jhb100-dwmac - const: starfive,jh7110-dwmac - const: snps,dwmac-5.20 @@ -39,20 +39,24 @@ properties: maxItems: 1 clocks: + minItems: 5 items: - description: GMAC main clock - description: GMAC AHB clock - description: PTP clock - description: TX clock - description: GTX clock + - description: SGMII RX clock clock-names: + minItems: 5 items: - const: stmmaceth - const: pclk - const: ptp_ref - const: tx - const: gtx + - const: sgmii_rx starfive,tx-use-rgmii-clk: description: @@ -111,22 +115,19 @@ allOf: contains: const: starfive,jh7110-dwmac then: - properties: - interrupts: - minItems: 3 - maxItems: 3 - - interrupt-names: - minItems: 3 - maxItems: 3 - if: properties: compatible: contains: - const: starfive,jh8100-dwmac + const: starfive,jhb100-dwmac then: properties: + interrupts: + maxItems: 1 + + interrupt-names: + const: macirq + resets: maxItems: 1 @@ -134,6 +135,14 @@ allOf: const: stmmaceth else: properties: + interrupts: + minItems: 3 + maxItems: 3 + + interrupt-names: + minItems: 3 + maxItems: 3 + resets: minItems: 2 diff --git a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml index c296e571184843..883033b19b8f37 100644 --- a/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml +++ b/Documentation/devicetree/bindings/net/ti,icssg-prueth.yaml @@ -21,7 +21,7 @@ properties: - ti,am654-sr1-icssg-prueth # for AM65x SoC family, SR1.0 sram: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 description: phandle to MSMC SRAM node diff --git a/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml index a98ad45ca66f21..9370c43bc66a62 100644 --- a/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml +++ b/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml @@ -24,7 +24,7 @@ properties: - ti,am3359-prueth # for AM33x SoC family sram: - $ref: /schemas/types.yaml#/definitions/phandle + maxItems: 1 description: phandle to OCMC SRAM node diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml index c21d66c7cd558a..d4f4d72ee0d388 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath10k.yaml @@ -158,7 +158,13 @@ properties: description: State bits used by the AP to signal the WLAN Q6. items: - description: Signal bits used to enable/disable low power mode - on WCN in the case of WoW (Wake on Wireless). + on WCN in the case of WoW (Wake on Wireless). + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output. diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml index 0cc1dbf2beefa2..d4aa56e2f82335 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ath11k.yaml @@ -80,7 +80,13 @@ properties: description: State bits used by the AP to signal the WLAN Q6. items: - description: Signal bits used to enable/disable low power mode - on WCN6750 in the case of WoW (Wake on Wireless). + on WCN6750 in the case of WoW (Wake on Wireless). + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output. diff --git a/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml b/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml index 37d8a0da778097..18cd91e2728cf0 100644 --- a/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml +++ b/Documentation/devicetree/bindings/net/wireless/qcom,ipq5332-wifi.yaml @@ -168,8 +168,26 @@ properties: description: States used by the AP to signal the remote processor items: - description: Shutdown WCSS pd + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 - description: Stop WCSS pd + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 - description: Spawn WCSS pd + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: diff --git a/Documentation/devicetree/bindings/net/wireless/st,stlc4560.yaml b/Documentation/devicetree/bindings/net/wireless/st,stlc4560.yaml new file mode 100644 index 00000000000000..a32265c07350df --- /dev/null +++ b/Documentation/devicetree/bindings/net/wireless/st,stlc4560.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/wireless/st,stlc4560.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST/Intersil/Conexant stlc45xx/p54spi/cx3110x SPI wireless device + +maintainers: + - Christian Lamparter + +description: + The SPI variant of the Intersil Prism54 wireless device was sold + under a variety of names, including Conexant CX3110x and + ST Microelectronics STLC5460. + +allOf: + - $ref: ieee80211.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + oneOf: + - const: st,stlc4560 + - items: + - enum: + - cnxt,3110x + - isil,p54spi + - st,stlc4550 + - const: st,stlc4560 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + powerdown-gpios: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + wifi@0 { + compatible = "st,stlc4560"; + reg = <0>; + spi-max-frequency = <48000000>; + interrupts-extended = <&gpio 23>; + powerdown-gpios = <&gpio 1>; + }; + }; diff --git a/Documentation/devicetree/bindings/nvmem/nvmem-consumer.yaml b/Documentation/devicetree/bindings/nvmem/nvmem-consumer.yaml index a26633bf52dbf7..45836308c7244f 100644 --- a/Documentation/devicetree/bindings/nvmem/nvmem-consumer.yaml +++ b/Documentation/devicetree/bindings/nvmem/nvmem-consumer.yaml @@ -16,6 +16,8 @@ properties: $ref: /schemas/types.yaml#/definitions/phandle-array description: List of phandle to the nvmem providers. + items: + maxItems: 1 nvmem-cells: $ref: /schemas/types.yaml#/definitions/phandle-array diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml index 9d1349855b4221..e8b8131f5f23be 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.yaml @@ -66,16 +66,34 @@ properties: - const: dma reset-gpio: + deprecated: true description: Should specify the GPIO for controlling the PCI bus device reset signal. It's not polarity aware and defaults to active-low reset sequence (L=reset state, H=operation state) (optional required). + This property is deprecated, instead of referencing this property from the + host bridge node, use the reset-gpios property from the root port node. reset-gpio-active-high: + deprecated: true description: If present then the reset sequence using the GPIO specified in the "reset-gpio" property is reversed (H=reset state, L=operation state) (optional required). + This property is deprecated along with the reset-gpio property above, use + the reset-gpios property from the root port node. type: boolean + pcie@0: + description: + Describe the i.MX6 PCIe Root Port. + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + unevaluatedProperties: false + required: - compatible - reg @@ -236,6 +254,7 @@ unevaluatedProperties: false examples: - | #include + #include #include pcie: pcie@1ffc000 { @@ -262,5 +281,18 @@ examples: <&clks IMX6QDL_CLK_LVDS1_GATE>, <&clks IMX6QDL_CLK_PCIE_REF_125M>; clock-names = "pcie", "pcie_bus", "pcie_phy"; + + pcie_port0: pcie@0 { + compatible = "pciclass,0604"; + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + + reset-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>; + }; }; ... diff --git a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml index 54e2890ae6314a..394bb46b38e601 100644 --- a/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/intel-gw-pcie.yaml @@ -27,16 +27,20 @@ properties: - const: snps,dw-pcie reg: + minItems: 3 items: - description: Controller control and status registers. - description: PCIe configuration registers. - description: Controller application registers. + - description: Internal Address Translation Unit (iATU) registers. reg-names: + minItems: 3 items: - const: dbi - const: config - const: app + - const: atu ranges: maxItems: 1 @@ -95,8 +99,9 @@ examples: #size-cells = <2>; reg = <0xd0e00000 0x1000>, <0xd2000000 0x800000>, - <0xd0a41000 0x1000>; - reg-names = "dbi", "config", "app"; + <0xd0a41000 0x1000>, + <0xd0ec0000 0x1000>; + reg-names = "dbi", "config", "app", "atu"; linux,pci-domain = <0>; max-link-speed = <4>; bus-range = <0x00 0x08>; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml index e33bcc216e30cf..542252168388b7 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-mt7623.yaml @@ -125,8 +125,8 @@ examples: phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2"; power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000>, /* I/O space */ - <0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ + ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000>, /* I/O space */ + <0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>; /* memory space */ pcie@0,0 { device_type = "pci"; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml index 0b8c78ec4f91b2..c009a7a52bc63e 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - airoha,an7583-pcie + - econet,en7528-pcie - mediatek,mt2712-pcie - mediatek,mt7622-pcie - mediatek,mt7629-pcie @@ -226,6 +227,31 @@ allOf: mediatek,pbus-csr: false + - if: + properties: + compatible: + contains: + const: econet,en7528-pcie + then: + properties: + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + resets: false + + reset-names: false + + power-domains: false + + mediatek,pbus-csr: false + + required: + - phys + - phy-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml index 3a94a9c1bb1559..fb706b1397a3ba 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sm8550.yaml @@ -20,6 +20,7 @@ properties: - const: qcom,pcie-sm8550 - items: - enum: + - qcom,eliza-pcie - qcom,kaanapali-pcie - qcom,sar2130p-pcie - qcom,pcie-sm8650 @@ -91,6 +92,55 @@ required: allOf: - $ref: qcom,pcie-common.yaml# + - if: + properties: + compatible: + contains: + const: qcom,eliza-pcie + then: + properties: + reg: + minItems: 6 + reg-names: + minItems: 6 + + - if: + properties: + compatible: + contains: + const: qcom,eliza-pcie + then: + properties: + clocks: + minItems: 8 + maxItems: 8 + clock-names: + minItems: 8 + maxItems: 8 + + - if: + properties: + compatible: + contains: + const: qcom,eliza-pcie + then: + properties: + interrupts: + minItems: 9 + interrupt-names: + minItems: 9 + + - if: + properties: + compatible: + contains: + const: qcom,eliza-pcie + then: + properties: + resets: + minItems: 2 + reset-names: + minItems: 2 unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml index a67108c48feb8a..90086909e92102 100644 --- a/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045-pcie.yaml @@ -4,21 +4,27 @@ $id: http://devicetree.org/schemas/pci/renesas,r9a08g045-pcie.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/G3S PCIe host controller +title: Renesas RZ/G3S PCIe host controller (and similar SoCs) maintainers: - Claudiu Beznea -description: - Renesas RZ/G3{E,S} PCIe host controllers comply with PCIe - Base Specification 4.0 and support up to 5 GT/s (Gen2) for RZ/G3S and - up to 8 GT/s (Gen3) for RZ/G3E. +description: | + PCIe host controller found in Renesas RZ/G3S and similar SoCs complies + with PCIe Base Specification 4.0 and supports different link speeds + depending on the SoC variant: + - Gen2 (5 GT/s): RZ/G3S + - Gen3 (8 GT/s): RZ/G3E, RZ/V2N properties: compatible: - enum: - - renesas,r9a08g045-pcie # RZ/G3S - - renesas,r9a09g047-pcie # RZ/G3E + oneOf: + - enum: + - renesas,r9a08g045-pcie # RZ/G3S + - renesas,r9a09g047-pcie # RZ/G3E + - items: + - const: renesas,r9a09g056-pcie # RZ/V2N + - const: renesas,r9a09g047-pcie reg: maxItems: 1 @@ -152,6 +158,7 @@ patternProperties: enum: - 0x0033 - 0x0039 + - 0x003b clocks: items: diff --git a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml index f20ed7e709f7ca..57a8f163dda596 100644 --- a/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/samsung,exynos-pcie.yaml @@ -109,7 +109,7 @@ examples: num-lanes = <1>; num-viewport = <3>; bus-range = <0x00 0xff>; - ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, + ranges = <0x81000000 0 0 0x0c001000 0 0x00010000>, <0x82000000 0 0x0c011000 0x0c011000 0 0x03feefff>; vdd10-supply = <&ldo6_reg>; vdd18-supply = <&ldo7_reg>; diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml index f8b7ca57fff14c..ab482488b04753 100644 --- a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml @@ -30,6 +30,8 @@ properties: device-id: const: 0x2042 + dma-coherent: true + msi-parent: true allOf: @@ -60,5 +62,6 @@ examples: vendor-id = <0x1f1c>; device-id = <0x2042>; cdns,no-bar-match-nbits = <48>; + dma-coherent; msi-parent = <&msi>; }; diff --git a/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml b/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml index fae46606478095..b3ad05d90201ce 100644 --- a/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml +++ b/Documentation/devicetree/bindings/pci/toshiba,tc9563.yaml @@ -49,8 +49,9 @@ properties: A phandle to the parent I2C node and the slave address of the device used to configure tc9563 to change FTS, tx amplitude etc. items: - - description: Phandle to the I2C controller node - - description: I2C slave address + - items: + - description: Phandle to the I2C controller node + - description: I2C slave address patternProperties: "^pcie@[1-3],0$": diff --git a/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml new file mode 100644 index 00000000000000..512b935bf5d1e9 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/ultrarisc,dp1000-pcie.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/ultrarisc,dp1000-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC DP1000 PCIe Host Controller + +description: + UltraRISC DP1000 SoC PCIe host controller is based on the DesignWare PCIe IP. + +maintainers: + - Xincheng Zhang + - Jia Wang + +allOf: + - $ref: /schemas/pci/snps,dw-pcie.yaml# + +properties: + compatible: + const: ultrarisc,dp1000-pcie + + reg: + items: + - description: Data Bus Interface (DBI) registers. + - description: PCIe configuration space region. + + reg-names: + items: + - const: dbi + - const: config + + num-lanes: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [4, 16] + description: Number of lanes to use. + + interrupts: + items: + - description: MSI interrupt + - description: Legacy INTA interrupt + - description: Legacy INTB interrupt + - description: Legacy INTC interrupt + - description: Legacy INTD interrupt + + interrupt-names: + items: + - const: msi + - const: inta + - const: intb + - const: intc + - const: intd + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie@21000000 { + compatible = "ultrarisc,dp1000-pcie"; + reg = <0x0 0x21000000 0x0 0x01000000>, + <0x0 0x4fff0000 0x0 0x00010000>; + reg-names = "dbi", "config"; + ranges = <0x81000000 0x0 0x4fbf0000 0x0 0x4fbf0000 0x0 0x00400000>, + <0x82000000 0x0 0x40000000 0x0 0x40000000 0x0 0x0fbf0000>, + <0xc3000000 0x40 0x00000000 0x40 0x00000000 0xd 0x00000000>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + device_type = "pci"; + dma-coherent; + bus-range = <0x0 0xff>; + num-lanes = <16>; + interrupt-parent = <&plic>; + interrupts = <43>, <44>, <45>, <46>, <47>; + interrupt-names = "msi", "inta", "intb", "intc", "intd"; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &plic 44>, + <0x0 0x0 0x0 0x2 &plic 45>, + <0x0 0x0 0x0 0x3 &plic 46>, + <0x0 0x0 0x0 0x4 &plic 47>; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml new file mode 100644 index 00000000000000..61700b80e93f71 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/axiado,ax3000-emmc-phy.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/axiado,ax3000-emmc-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axiado AX3000 Arasan eMMC PHY + +maintainers: + - SriNavmani A + - Tzu-Hao Wei + - Prasad Bolisetty + +properties: + compatible: + const: axiado,ax3000-emmc-phy + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + phy@80801c00 { + compatible = "axiado,ax3000-emmc-phy"; + reg = <0x80801c00 0x1000>; + #phy-cells = <0>; + }; diff --git a/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml new file mode 100644 index 00000000000000..987d396c1c6422 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/econet,en751221-pcie-phy.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/econet,en751221-pcie-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: EcoNet PCI-Express PHY for EcoNet EN751221 and EN7528 + +maintainers: + - Caleb James DeLisle + +description: + The PCIe PHY supports physical layer functionality for PCIe Gen1 and + Gen1/Gen2 ports. On these SoCs, port 0 is a Gen1-only port while + port 1 is Gen1/Gen2 capable. + +properties: + compatible: + enum: + - econet,en751221-pcie-gen1 + - econet,en751221-pcie-gen2 + - econet,en7528-pcie-gen1 + - econet,en7528-pcie-gen2 + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <1>; + #size-cells = <1>; + + pcie-phy@1faf2000 { + compatible = "econet,en7528-pcie-gen1"; + reg = <0x1faf2000 0x1000>; + #phy-cells = <0>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml new file mode 100644 index 00000000000000..2e7d0abfa71ac4 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-10g.yaml @@ -0,0 +1,139 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/fsl,lynx-10g.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Lynx 10G SerDes PHY + +maintainers: + - Vladimir Oltean + +description: + The 10G Lynx is a multi-protocol SerDes block which handles networking, PCIe, + SATA and other high-speed interfaces. It is present on most QorIQ and + Layerscape SoCs. The register map is common, but the integration is + SoC-specific, with the differences consisting in register endianness, the + number of lanes, protocol converters available per lane and their location in + the PCCR registers. Some SoCs have multiple SerDes blocks and those differ in + their protocol capabilities per lane. + +properties: + compatible: + enum: + - fsl,ls1028a-serdes + - fsl,ls1046a-serdes1 + - fsl,ls1046a-serdes2 + - fsl,ls1088a-serdes1 + - fsl,ls1088a-serdes2 + - fsl,ls2088a-serdes1 + - fsl,ls2088a-serdes2 + + reg: + maxItems: 1 + + big-endian: true + + "#phy-cells": + const: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + +patternProperties: + "^phy@[0-7]$": + type: object + description: SerDes lane (single RX/TX differential pair) + + properties: + reg: + minimum: 0 + maximum: 7 + description: Lane index as seen in register map + + "#phy-cells": + const: 0 + + required: + - reg + - "#phy-cells" + + additionalProperties: false + +required: + - compatible + - reg + - "#phy-cells" + - "#address-cells" + - "#size-cells" + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,ls1028a-serdes + - fsl,ls1046a-serdes1 + - fsl,ls1046a-serdes2 + - fsl,ls1088a-serdes1 + - fsl,ls1088a-serdes2 + then: + patternProperties: + "^phy@[0-7]$": + properties: + reg: + minimum: 0 + maximum: 3 + - if: + properties: + compatible: + enum: + - fsl,ls1046a-serdes1 + - fsl,ls1046a-serdes2 + then: + required: + - big-endian + else: + properties: + big-endian: false + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + serdes@1ea0000 { + compatible = "fsl,ls1028a-serdes"; + reg = <0x0 0x1ea0000 0x0 0xffff>; + #address-cells = <1>; + #size-cells = <0>; + #phy-cells = <1>; + + phy@0 { + reg = <0>; + #phy-cells = <0>; + }; + + phy@1 { + reg = <1>; + #phy-cells = <0>; + }; + + phy@2 { + reg = <2>; + #phy-cells = <0>; + }; + + phy@3 { + reg = <3>; + #phy-cells = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml index e96229c2f8fb73..d73591315d4b99 100644 --- a/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml +++ b/Documentation/devicetree/bindings/phy/fsl,lynx-28g.yaml @@ -9,10 +9,37 @@ title: Freescale Lynx 28G SerDes PHY maintainers: - Ioana Ciornei +description: + The Lynx 28G is a multi-lane, multi-protocol SerDes (PCIe, SATA, Ethernet) + present in multiple instances on NXP LX2160A and LX2162A SoCs. All instances + share a common register map and programming model, however they differ in + supported protocols per lane in a way that is not detectable by said + programming model without prior knowledge. The distinction is made through + the compatible string. + properties: compatible: - enum: - - fsl,lynx-28g + oneOf: + - const: fsl,lynx-28g + deprecated: true + description: + Legacy compatibility string for Lynx 28G SerDes. Any assumption + regarding whether a certain lane supports a certain protocol may + be incorrect. Deprecated except when used as a fallback. Use + device-specific strings instead. + - items: + - const: fsl,lx2160a-serdes1 + - const: fsl,lynx-28g + - items: + - const: fsl,lx2160a-serdes2 + - const: fsl,lynx-28g + - items: + - const: fsl,lx2162a-serdes1 + - const: fsl,lynx-28g + - items: + - const: fsl,lx2162a-serdes2 + - const: fsl,lynx-28g + - const: fsl,lx2160a-serdes3 reg: maxItems: 1 @@ -51,6 +78,21 @@ required: - reg - "#phy-cells" +allOf: + # LX2162A SerDes 1 has fewer lanes than the others + - if: + properties: + compatible: + contains: + const: fsl,lx2162a-serdes1 + then: + patternProperties: + "^phy@[0-7]$": + properties: + reg: + minimum: 4 + maximum: 7 + additionalProperties: false examples: @@ -60,7 +102,7 @@ examples: #size-cells = <2>; serdes@1ea0000 { - compatible = "fsl,lynx-28g"; + compatible = "fsl,lx2160a-serdes1", "fsl,lynx-28g"; reg = <0x0 0x1ea0000 0x0 0x1e30>; #address-cells = <1>; #size-cells = <0>; diff --git a/Documentation/devicetree/bindings/phy/nxp,tja1145.yaml b/Documentation/devicetree/bindings/phy/nxp,tja1145.yaml new file mode 100644 index 00000000000000..fb068f7d774f3c --- /dev/null +++ b/Documentation/devicetree/bindings/phy/nxp,tja1145.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/nxp,tja1145.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TJA1145 CAN transceiver + +maintainers: + - Dimitri Fedrau + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: nxp,tja1145 + + interrupts: + maxItems: 1 + + reg: + maxItems: 1 + + "#phy-cells": + const: 0 + + spi-cpha: true + + spi-max-frequency: + maximum: 4000000 + + spi-cs-setup-delay-ns: + minimum: 50 + default: 50 + + spi-cs-hold-delay-ns: + minimum: 50 + default: 50 + + spi-cs-inactive-delay-ns: + minimum: 250 + default: 250 + + vcc-supply: + description: + CAN transceiver supply voltage + + vio-supply: + description: + Supply voltage for I/O level adaptor + + vbat-supply: + description: + Battery supply voltage + +required: + - compatible + - reg + - "#phy-cells" + - spi-cpha + +additionalProperties: false + +examples: + - | + #include + spi { + #address-cells = <1>; + #size-cells = <0>; + can-phy@0 { + compatible = "nxp,tja1145"; + interrupt-parent = <&gpio0>; + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + reg = <0>; + #phy-cells = <0>; + spi-cpha; + spi-max-frequency = <4000000>; + spi-cs-setup-delay-ns = <50>; + spi-cs-hold-delay-ns = <50>; + spi-cs-inactive-delay-ns = <250>; + vcc-supply = <®_5v0>; + vio-supply = <®_3v3>; + vbat-supply = <®_24v0>; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml index 966c70d746aa4d..f397ba3fa84acf 100644 --- a/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,dsi-phy-7nm.yaml @@ -20,6 +20,7 @@ properties: - qcom,dsi-phy-7nm - qcom,dsi-phy-7nm-8150 - qcom,kaanapali-dsi-phy-3nm + - qcom,milos-dsi-phy-4nm - qcom,sa8775p-dsi-phy-5nm - qcom,sar2130p-dsi-phy-5nm - qcom,sc7280-dsi-phy-7nm diff --git a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml index 4a1daae3d8d47c..0bf8bf4f66acfd 100644 --- a/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,edp-phy.yaml @@ -74,6 +74,7 @@ allOf: compatible: enum: - qcom,glymur-dp-phy + - qcom,sa8775p-edp-phy - qcom,x1e80100-dp-phy then: properties: diff --git a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml index 39851ba9de4369..449c2a7e5fecf7 100644 --- a/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml @@ -30,6 +30,10 @@ properties: - qcom,sdm660-qusb2-phy - qcom,sm4250-qusb2-phy - qcom,sm6115-qusb2-phy + - items: + - enum: + - qcom,ipq5210-qusb2-phy + - const: qcom,ipq6018-qusb2-phy - items: - enum: - qcom,sc7180-qusb2-phy diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 3a35120a77ec0c..108cf9dc86ea00 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -16,6 +16,8 @@ description: properties: compatible: enum: + - qcom,eliza-qmp-gen3x1-pcie-phy + - qcom,eliza-qmp-gen3x2-pcie-phy - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy - qcom,kaanapali-qmp-gen3x2-pcie-phy @@ -136,13 +138,22 @@ allOf: items: - description: port a - description: port b - required: - - qcom,4ln-config-sel else: properties: reg: maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - qcom,sc8280xp-qmp-gen3x4-pcie-phy + - qcom,x1e80100-qmp-gen4x4-pcie-phy + then: + required: + - qcom,4ln-config-sel + - if: properties: compatible: @@ -181,6 +192,8 @@ allOf: compatible: contains: enum: + - qcom,eliza-qmp-gen3x1-pcie-phy + - qcom,eliza-qmp-gen3x2-pcie-phy - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy - qcom,qcs8300-qmp-gen4x2-pcie-phy @@ -206,6 +219,8 @@ allOf: compatible: contains: enum: + - qcom,eliza-qmp-gen3x1-pcie-phy + - qcom,eliza-qmp-gen3x2-pcie-phy - qcom,glymur-qmp-gen4x2-pcie-phy - qcom,glymur-qmp-gen5x4-pcie-phy - qcom,kaanapali-qmp-gen3x2-pcie-phy diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml index 9616c736b6d461..b2c5c9a375a356 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml @@ -31,6 +31,7 @@ properties: - items: - enum: - qcom,eliza-qmp-ufs-phy + - qcom,nord-qmp-ufs-phy - const: qcom,sm8650-qmp-ufs-phy - items: - enum: diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml index 623c2f8c7d2206..01342823e57f05 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb3-uni-phy.yaml @@ -15,26 +15,32 @@ description: properties: compatible: - enum: - - qcom,glymur-qmp-usb3-uni-phy - - qcom,ipq5424-qmp-usb3-phy - - qcom,ipq6018-qmp-usb3-phy - - qcom,ipq8074-qmp-usb3-phy - - qcom,ipq9574-qmp-usb3-phy - - qcom,msm8996-qmp-usb3-phy - - qcom,qcs8300-qmp-usb3-uni-phy - - qcom,qdu1000-qmp-usb3-uni-phy - - qcom,sa8775p-qmp-usb3-uni-phy - - qcom,sc8180x-qmp-usb3-uni-phy - - qcom,sc8280xp-qmp-usb3-uni-phy - - qcom,sdm845-qmp-usb3-uni-phy - - qcom,sdx55-qmp-usb3-uni-phy - - qcom,sdx65-qmp-usb3-uni-phy - - qcom,sdx75-qmp-usb3-uni-phy - - qcom,sm8150-qmp-usb3-uni-phy - - qcom,sm8250-qmp-usb3-uni-phy - - qcom,sm8350-qmp-usb3-uni-phy - - qcom,x1e80100-qmp-usb3-uni-phy + oneOf: + - items: + - enum: + - qcom,glymur-qmp-usb3-uni-phy + - qcom,ipq5424-qmp-usb3-phy + - qcom,ipq6018-qmp-usb3-phy + - qcom,ipq8074-qmp-usb3-phy + - qcom,ipq9574-qmp-usb3-phy + - qcom,msm8996-qmp-usb3-phy + - qcom,qcs8300-qmp-usb3-uni-phy + - qcom,qdu1000-qmp-usb3-uni-phy + - qcom,sa8775p-qmp-usb3-uni-phy + - qcom,sc8180x-qmp-usb3-uni-phy + - qcom,sc8280xp-qmp-usb3-uni-phy + - qcom,sdm845-qmp-usb3-uni-phy + - qcom,sdx55-qmp-usb3-uni-phy + - qcom,sdx65-qmp-usb3-uni-phy + - qcom,sdx75-qmp-usb3-uni-phy + - qcom,sm8150-qmp-usb3-uni-phy + - qcom,sm8250-qmp-usb3-uni-phy + - qcom,sm8350-qmp-usb3-uni-phy + - qcom,x1e80100-qmp-usb3-uni-phy + - items: + - enum: + - qcom,ipq5210-qmp-usb3-phy + - const: qcom,ipq9574-qmp-usb3-phy reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml index 3d537b7f998598..4eff92343ce4f5 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-usb43dp-phy.yaml @@ -16,6 +16,10 @@ description: properties: compatible: oneOf: + - items: + - enum: + - qcom,eliza-qmp-usb3-dp-phy + - const: qcom,sm8650-qmp-usb3-dp-phy - items: - enum: - qcom,kaanapali-qmp-usb3-dp-phy diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml index 854f70af0a6c1f..096f6b546632ef 100644 --- a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml @@ -17,6 +17,7 @@ properties: oneOf: - items: - enum: + - qcom,eliza-snps-eusb2-phy - qcom,milos-snps-eusb2-phy - qcom,sar2130p-snps-eusb2-phy - qcom,sdx75-snps-eusb2-phy diff --git a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml index 58e735b5dd05a8..f50fc69fbbe495 100644 --- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml +++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml @@ -20,6 +20,7 @@ properties: - rockchip,rk3328-usb2phy - rockchip,rk3366-usb2phy - rockchip,rk3399-usb2phy + - rockchip,rk3528-usb2phy - rockchip,rk3562-usb2phy - rockchip,rk3568-usb2phy - rockchip,rk3576-usb2phy @@ -41,11 +42,15 @@ properties: maxItems: 3 clock-names: - minItems: 1 - items: + oneOf: - const: phyclk - - const: aclk - - const: aclk_slv + - items: + - const: phyclk + - const: pclk + - items: + - const: phyclk + - const: aclk + - const: aclk_slv assigned-clocks: description: @@ -65,6 +70,9 @@ properties: description: Muxed interrupt for both ports maxItems: 1 + power-domains: + maxItems: 1 + resets: maxItems: 2 @@ -145,6 +153,21 @@ anyOf: - host-port allOf: + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3528-usb2phy + - rockchip,rk3568-usb2phy + - rockchip,rv1108-usb2phy + then: + required: + - rockchip,usbgrf + else: + properties: + rockchip,usbgrf: false + - if: properties: compatible: @@ -204,6 +227,19 @@ allOf: clock-names: maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - rockchip,rk3528-usb2phy + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml index 43eaca90d88c02..18025e5f60d691 100644 --- a/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml +++ b/Documentation/devicetree/bindings/phy/spacemit,usb2-phy.yaml @@ -4,14 +4,16 @@ $id: http://devicetree.org/schemas/phy/spacemit,usb2-phy.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SpacemiT K1 SoC USB 2.0 PHY +title: SpacemiT K1/K3 SoC USB 2.0 PHY maintainers: - Ze Huang properties: compatible: - const: spacemit,k1-usb2-phy + enum: + - spacemit,k1-usb2-phy + - spacemit,k3-usb2-phy reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/ti,ds125df111.yaml b/Documentation/devicetree/bindings/phy/ti,ds125df111.yaml new file mode 100644 index 00000000000000..ca4605f1d6641a --- /dev/null +++ b/Documentation/devicetree/bindings/phy/ti,ds125df111.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/ti,ds125df111.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DS125DF111 Retimer PHY + +description: + This binding describes the TI DS125DF111 multi-protocol Retimer PHY. + +maintainers: + - Ioana Ciornei + +properties: + compatible: + const: ti,ds125df111 + + reg: + maxItems: 1 + + "#phy-cells": + const: 1 + description: | + The phandle's argument in the PHY specifier selects one of the two + channels of the retimer + +required: + - compatible + - reg + - "#phy-cells" + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + phy@18 { + compatible = "ti,ds125df111"; + reg = <0x18>; + #phy-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml index be41b4547ec6d6..60b644a4c6390f 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-gmii-sel.yaml @@ -47,15 +47,20 @@ description: | properties: compatible: - enum: - - ti,am3352-phy-gmii-sel - - ti,dra7xx-phy-gmii-sel - - ti,am43xx-phy-gmii-sel - - ti,dm814-phy-gmii-sel - - ti,am654-phy-gmii-sel - - ti,j7200-cpsw5g-phy-gmii-sel - - ti,j721e-cpsw9g-phy-gmii-sel - - ti,j784s4-cpsw9g-phy-gmii-sel + oneOf: + - enum: + - ti,am3352-phy-gmii-sel + - ti,dra7xx-phy-gmii-sel + - ti,am43xx-phy-gmii-sel + - ti,dm814-phy-gmii-sel + - ti,am654-phy-gmii-sel + - ti,j7200-cpsw5g-phy-gmii-sel + - ti,j721e-cpsw9g-phy-gmii-sel + - ti,j784s4-cpsw9g-phy-gmii-sel + - items: + - enum: + - ti,j722s-phy-gmii-sel + - const: ti,am654-phy-gmii-sel reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml index 3f16ff14484d2c..0653252c18d8e5 100644 --- a/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +++ b/Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml @@ -12,13 +12,18 @@ maintainers: properties: compatible: - enum: - - ti,j721e-wiz-16g - - ti,j721e-wiz-10g - - ti,j721s2-wiz-10g - - ti,am64-wiz-10g - - ti,j7200-wiz-10g - - ti,j784s4-wiz-10g + oneOf: + - enum: + - ti,j721e-wiz-16g + - ti,j721e-wiz-10g + - ti,j721s2-wiz-10g + - ti,am64-wiz-10g + - ti,j7200-wiz-10g + - ti,j784s4-wiz-10g + - items: + - enum: + - ti,j722s-wiz-10g + - const: ti,am64-wiz-10g power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml index 154e03da8ce989..f87b8274cc372f 100644 --- a/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/allwinner,sun55i-a523-pinctrl.yaml @@ -34,7 +34,7 @@ properties: interrupts: minItems: 2 - maxItems: 10 + maxItems: 11 description: One interrupt per external interrupt bank supported on the controller, sorted by bank number ascending order. @@ -61,7 +61,7 @@ properties: bank found in the controller $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 2 - maxItems: 10 + maxItems: 11 patternProperties: # It's pretty scary, but the basic idea is that: @@ -130,8 +130,8 @@ allOf: then: properties: interrupts: - minItems: 10 - maxItems: 10 + minItems: 11 + maxItems: 11 - if: properties: diff --git a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml index 6ba66c2033b467..b69db1b953455e 100644 --- a/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml +++ b/Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml @@ -17,6 +17,7 @@ properties: oneOf: - enum: - amlogic,pinctrl-a4 + - amlogic,pinctrl-a9 - amlogic,pinctrl-s6 - amlogic,pinctrl-s7 - items: diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml new file mode 100644 index 00000000000000..407a64f28d4979 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml @@ -0,0 +1,188 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc0-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 SoC0 Pin Controller + +maintainers: + - Billy Tsai + +description: > + The AST2700 features a dual-SoC architecture with two interconnected SoCs, + each having its own System Control Unit (SCU) for independent pin control. + This pin controller manages the pin multiplexing for SoC0. + + The SoC0 pin controller manages pin functions including eMMC, VGA DDC, + dual USB3/USB2 ports (A and B), JTAG, and PCIe root complex interfaces. + +properties: + compatible: + const: aspeed,ast2700-soc0-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-state$': + description: | + Pin control state. + + If 'function' is present, the node describes a pinmux state and must + specify 'groups'. + + For pin configuration, exactly one of 'groups' or 'pins' must be + specified in each state node. Group-level configuration applies to all + pins in the group. Pin-level configuration may be supplied in a + separate state node for individual pins; when both group-level and + pin-level configuration apply to the same pin, the pin-level + configuration takes precedence. + + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + - if: + required: + - function + then: + required: + - groups + - oneOf: + - required: + - groups + - required: + - pins + + additionalProperties: false + + properties: + function: + enum: + - EMMC + - JTAGDDR + - JTAGM0 + - JTAGPCIEA + - JTAGPCIEB + - JTAGPSP + - JTAGSSP + - JTAGTSP + - JTAGUSB3A + - JTAGUSB3B + - PCIERC0PERST + - PCIERC1PERST + - TSPRSTN + - UFSCLKI + - USB2AD0 + - USB2AD1 + - USB2AH + - USB2AHP + - USB2AHPD0 + - USB2AXH + - USB2AXH2B + - USB2AXHD1 + - USB2AXHP + - USB2AXHP2B + - USB2AXHPD1 + - USB2BD0 + - USB2BD1 + - USB2BH + - USB2BHP + - USB2BHPD0 + - USB2BXH + - USB2BXH2A + - USB2BXHD1 + - USB2BXHP + - USB2BXHP2A + - USB2BXHPD1 + - USB3AXH + - USB3AXH2B + - USB3AXHD + - USB3AXHP + - USB3AXHP2B + - USB3AXHPD + - USB3BXH + - USB3BXH2A + - USB3BXHD + - USB3BXHP + - USB3BXHP2A + - USB3BXHPD + - VB + - VGADDC + + groups: + enum: + - EMMCCDN + - EMMCG1 + - EMMCG4 + - EMMCG8 + - EMMCWPN + - JTAG0 + - PCIERC0PERST + - PCIERC1PERST + - TSPRSTN + - UFSCLKI + - USB2A + - USB2AAP + - USB2ABP + - USB2ADAP + - USB2AH + - USB2AHAP + - USB2B + - USB2BAP + - USB2BBP + - USB2BDBP + - USB2BH + - USB2BHBP + - USB3A + - USB3AAP + - USB3ABP + - USB3B + - USB3BAP + - USB3BBP + - VB0 + - VB1 + - VGADDC + + pins: + enum: + - AB13 + - AB14 + - AC13 + - AC14 + - AD13 + - AD14 + - AE13 + - AE14 + - AE15 + - AF13 + - AF14 + - AF15 + + drive-strength: + enum: [3, 6, 8, 11, 16, 18, 20, 23, 30, 32, 33, 35, 37, 38, 39, 41] + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + pinctrl@400 { + compatible = "aspeed,ast2700-soc0-pinctrl"; + reg = <0x400 0x318>; + emmc-state { + function = "EMMC"; + groups = "EMMCG1"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml new file mode 100644 index 00000000000000..76944fd14e2c74 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml @@ -0,0 +1,760 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/aspeed,ast2700-soc1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2700 SoC1 Pin Controller + +maintainers: + - Billy Tsai + +description: + The AST2700 features a dual-SoC architecture with two interconnected SoCs, + each having its own System Control Unit (SCU) for independent pin control. + This pin controller manages the pin multiplexing for SoC1. + + The SoC1 pin controller manages pin functions including eSPI, LPC and I2C, + among others. + +properties: + compatible: + const: aspeed,ast2700-soc1-pinctrl + reg: + maxItems: 1 + +patternProperties: + '-state$': + description: | + Pin control state. + + If `function` is present, the node describes a pinmux state and must + specify `groups`. + + For pin configuration, exactly one of `groups` or `pins` must be + specified in each state node. Group-level configuration applies to all + pins in the group. Pin-level configuration may be supplied in a + separate state node for individual pins; when both group-level and + pin-level configuration apply to the same pin, the pin-level + configuration takes precedence. + + type: object + allOf: + - $ref: pinmux-node.yaml# + - $ref: pincfg-node.yaml# + - if: + required: + - function + then: + required: + - groups + - oneOf: + - required: + - groups + - required: + - pins + additionalProperties: false + + properties: + function: + enum: + - ADC0 + - ADC1 + - ADC10 + - ADC11 + - ADC12 + - ADC13 + - ADC14 + - ADC15 + - ADC2 + - ADC3 + - ADC4 + - ADC5 + - ADC6 + - ADC7 + - ADC8 + - ADC9 + - AUXPWRGOOD0 + - AUXPWRGOOD1 + - CANBUS + - ESPI0 + - ESPI1 + - FSI0 + - FSI1 + - FSI2 + - FSI3 + - FWQSPI + - FWSPIABR + - FWWPN + - HBLED + - I2C0 + - I2C1 + - I2C10 + - I2C11 + - I2C12 + - I2C13 + - I2C14 + - I2C15 + - I2C2 + - I2C3 + - I2C4 + - I2C5 + - I2C6 + - I2C7 + - I2C8 + - I2C9 + - I2CF0 + - I2CF1 + - I2CF2 + - I3C0 + - I3C1 + - I3C10 + - I3C11 + - I3C12 + - I3C13 + - I3C14 + - I3C15 + - I3C2 + - I3C3 + - I3C4 + - I3C5 + - I3C6 + - I3C7 + - I3C8 + - I3C9 + - JTAGM1 + - LPC0 + - LPC1 + - LTPI + - MACLINK0 + - MACLINK1 + - MACLINK2 + - MDIO0 + - MDIO1 + - MDIO2 + - NCTS0 + - NCTS1 + - NCTS5 + - NCTS6 + - NDCD0 + - NDCD1 + - NDCD5 + - NDCD6 + - NDSR0 + - NDSR1 + - NDSR5 + - NDSR6 + - NDTR0 + - NDTR1 + - NDTR5 + - NDTR6 + - NRI0 + - NRI1 + - NRI5 + - NRI6 + - NRTS0 + - NRTS1 + - NRTS5 + - NRTS6 + - OSCCLK + - PCIERC + - PWM0 + - PWM1 + - PWM10 + - PWM11 + - PWM12 + - PWM13 + - PWM14 + - PWM15 + - PWM2 + - PWM3 + - PWM4 + - PWM5 + - PWM6 + - PWM7 + - PWM8 + - PWM9 + - QSPI0 + - QSPI1 + - QSPI2 + - RGMII0 + - RGMII1 + - RMII0 + - RMII0RCLKO + - RMII1 + - RMII1RCLKO + - SALT0 + - SALT1 + - SALT10 + - SALT11 + - SALT12 + - SALT13 + - SALT14 + - SALT15 + - SALT2 + - SALT3 + - SALT4 + - SALT5 + - SALT6 + - SALT7 + - SALT8 + - SALT9 + - SD + - SGMII + - SGPM0 + - SGPM1 + - SGPS + - SIOONCTRLN0 + - SIOONCTRLN1 + - SIOPBIN0 + - SIOPBIN1 + - SIOPBON0 + - SIOPBON1 + - SIOPWREQN0 + - SIOPWREQN1 + - SIOPWRGD1 + - SIOS3N0 + - SIOS3N1 + - SIOS5N0 + - SIOS5N1 + - SIOSCIN0 + - SIOSCIN1 + - SMON0 + - SMON1 + - SPI0 + - SPI0ABR + - SPI0CS1 + - SPI0WPN + - SPI1 + - SPI1ABR + - SPI1CS1 + - SPI1WPN + - SPI2 + - SPI2CS1 + - TACH0 + - TACH1 + - TACH10 + - TACH11 + - TACH12 + - TACH13 + - TACH14 + - TACH15 + - TACH2 + - TACH3 + - TACH4 + - TACH5 + - TACH6 + - TACH7 + - TACH8 + - TACH9 + - THRU0 + - THRU1 + - THRU2 + - THRU3 + - UART0 + - UART1 + - UART10 + - UART11 + - UART2 + - UART3 + - UART5 + - UART6 + - UART7 + - UART8 + - UART9 + - USB2C + - USB2D + - USBUART + - VGA + - VPI + - WDTRST0N + - WDTRST1N + - WDTRST2N + - WDTRST3N + - WDTRST4N + - WDTRST5N + - WDTRST6N + - WDTRST7N + + groups: + enum: + - ADC0 + - ADC1 + - ADC10 + - ADC11 + - ADC12 + - ADC13 + - ADC14 + - ADC15 + - ADC2 + - ADC3 + - ADC4 + - ADC5 + - ADC6 + - ADC7 + - ADC8 + - ADC9 + - AUXPWRGOOD0 + - AUXPWRGOOD1 + - CANBUS + - DI2C0 + - DI2C1 + - DI2C10 + - DI2C11 + - DI2C12 + - DI2C13 + - DI2C14 + - DI2C15 + - DI2C2 + - DI2C3 + - DI2C8 + - DI2C9 + - DSGPM0 + - ESPI0 + - ESPI1 + - FSI0 + - FSI1 + - FSI2 + - FSI3 + - FWQSPI + - FWSPIABR + - FWWPN + - HBLED + - HVI3C0 + - HVI3C1 + - HVI3C12 + - HVI3C13 + - HVI3C14 + - HVI3C15 + - HVI3C2 + - HVI3C3 + - I2C0 + - I2C1 + - I2C10 + - I2C11 + - I2C12 + - I2C13 + - I2C14 + - I2C15 + - I2C2 + - I2C3 + - I2C4 + - I2C5 + - I2C6 + - I2C7 + - I2C8 + - I2C9 + - I2CF0 + - I2CF1 + - I2CF2 + - I3C10 + - I3C11 + - I3C4 + - I3C5 + - I3C6 + - I3C7 + - I3C8 + - I3C9 + - JTAGM1 + - LPC0 + - LPC1 + - LTPI + - LTPI_PS_I2C0 + - LTPI_PS_I2C1 + - LTPI_PS_I2C2 + - LTPI_PS_I2C3 + - MACLINK0 + - MACLINK1 + - MACLINK2 + - MDIO0 + - MDIO1 + - MDIO2 + - NCTS0 + - NCTS1 + - NCTS5 + - NCTS6 + - NDCD0 + - NDCD1 + - NDCD5 + - NDCD6 + - NDSR0 + - NDSR1 + - NDSR5 + - NDSR6 + - NDTR0 + - NDTR1 + - NDTR5 + - NDTR6 + - NRI0 + - NRI1 + - NRI5 + - NRI6 + - NRTS0 + - NRTS1 + - NRTS5 + - NRTS6 + - OSCCLK + - PE2SGRSTN + - PWM0 + - PWM1 + - PWM10 + - PWM11 + - PWM12 + - PWM13 + - PWM14 + - PWM15 + - PWM2 + - PWM3 + - PWM4 + - PWM5 + - PWM6 + - PWM7 + - PWM8 + - PWM9 + - QSPI0 + - QSPI1 + - QSPI2 + - RGMII0 + - RGMII1 + - RMII0 + - RMII0RCLKO + - RMII1 + - RMII1RCLKO + - SALT0 + - SALT1 + - SALT10 + - SALT11 + - SALT12 + - SALT13 + - SALT14 + - SALT15 + - SALT2 + - SALT3 + - SALT4 + - SALT5 + - SALT6 + - SALT7 + - SALT8 + - SALT9 + - SD + - SGMII + - SGPM0 + - SGPM1 + - SGPS + - SIOONCTRLN0 + - SIOONCTRLN1 + - SIOPBIN0 + - SIOPBIN1 + - SIOPBON0 + - SIOPBON1 + - SIOPWREQN0 + - SIOPWREQN1 + - SIOPWRGD1 + - SIOS3N0 + - SIOS3N1 + - SIOS5N0 + - SIOS5N1 + - SIOSCIN0 + - SIOSCIN1 + - SMON0 + - SMON1 + - SPI0 + - SPI0ABR + - SPI0CS1 + - SPI0WPN + - SPI1 + - SPI1ABR + - SPI1CS1 + - SPI1WPN + - SPI2 + - SPI2CS1 + - TACH0 + - TACH1 + - TACH10 + - TACH11 + - TACH12 + - TACH13 + - TACH14 + - TACH15 + - TACH2 + - TACH3 + - TACH4 + - TACH5 + - TACH6 + - TACH7 + - TACH8 + - TACH9 + - THRU0 + - THRU1 + - THRU2 + - THRU3 + - UART0 + - UART1 + - UART10 + - UART11 + - UART2 + - UART3 + - UART5 + - UART6 + - UART7 + - UART8 + - UART9 + - USB2CD + - USB2CH + - USB2CU + - USB2CUD + - USB2DD + - USB2DH + - USBUART + - VGA + - VPI + - WDTRST0N + - WDTRST1N + - WDTRST2N + - WDTRST3N + - WDTRST4N + - WDTRST5N + - WDTRST6N + - WDTRST7N + + pins: + enum: + - A14 + - A15 + - A18 + - A19 + - A21 + - A22 + - A23 + - A24 + - A25 + - A26 + - A6 + - A7 + - A8 + - AA12 + - AA13 + - AA14 + - AA15 + - AA16 + - AA17 + - AA18 + - AA20 + - AA21 + - AA22 + - AA23 + - AA24 + - AA25 + - AA26 + - AB15 + - AB16 + - AB17 + - AB18 + - AB19 + - AB20 + - AB21 + - AB22 + - AB23 + - AB24 + - AB25 + - AB26 + - AC15 + - AC16 + - AC17 + - AC18 + - AC19 + - AC20 + - AC22 + - AC24 + - AC25 + - AC26 + - AD15 + - AD16 + - AD17 + - AD18 + - AD19 + - AD20 + - AD22 + - AD25 + - AD26 + - AE16 + - AE17 + - AE18 + - AE19 + - AE20 + - AE21 + - AE23 + - AE25 + - AE26 + - AF16 + - AF17 + - AF18 + - AF19 + - AF20 + - AF21 + - AF23 + - AF25 + - AF26 + - B10 + - B11 + - B12 + - B13 + - B14 + - B15 + - B16 + - B18 + - B19 + - B21 + - B22 + - B23 + - B24 + - B25 + - B26 + - B6 + - B7 + - B8 + - B9 + - C10 + - C11 + - C12 + - C13 + - C14 + - C15 + - C16 + - C17 + - C18 + - C19 + - C20 + - C23 + - C26 + - C6 + - C7 + - C8 + - C9 + - D10 + - D12 + - D14 + - D15 + - D19 + - D20 + - D24 + - D26 + - D7 + - D8 + - D9 + - E10 + - E11 + - E12 + - E13 + - E14 + - E26 + - E7 + - E8 + - E9 + - F10 + - F11 + - F12 + - F13 + - F14 + - F26 + - F7 + - F8 + - F9 + - G10 + - G11 + - G7 + - G8 + - G9 + - H10 + - H11 + - H7 + - H8 + - H9 + - J10 + - J11 + - J12 + - J13 + - J9 + - K12 + - K13 + - L12 + - M13 + - M14 + - M15 + - M16 + - N13 + - N14 + - N15 + - N25 + - N26 + - P13 + - P14 + - P25 + - P26 + - R14 + - R25 + - R26 + - T23 + - T24 + - U21 + - U22 + - U25 + - U26 + - V14 + - V16 + - V17 + - V18 + - V19 + - V20 + - V21 + - V22 + - V23 + - V24 + - W14 + - W16 + - W17 + - W18 + - W20 + - W21 + - W22 + - W25 + - W26 + - Y11 + - Y15 + - Y16 + - Y17 + - Y18 + - Y20 + - Y21 + - Y22 + - Y23 + - Y24 + - Y25 + - Y26 + + drive-strength: + enum: [4, 8, 12, 16] + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + +required: + - compatible + - reg + +allOf: + - $ref: pinctrl.yaml# + +additionalProperties: false + +examples: + - | + pinctrl@400 { + compatible = "aspeed,ast2700-soc1-pinctrl"; + reg = <0x400 0x2A0>; + sgpm0-state { + function = "SGPM0"; + groups = "SGPM0"; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index aa71398cf522fd..1468c6f87cfa6a 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -17,6 +17,7 @@ properties: enum: - mediatek,mt2701-pinctrl - mediatek,mt2712-pinctrl + - mediatek,mt6392-pinctrl - mediatek,mt6397-pinctrl - mediatek,mt7623-pinctrl - mediatek,mt8127-pinctrl diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml index 68e91c05f12204..9a937f414cc983 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6795-pinctrl.yaml @@ -152,6 +152,14 @@ patternProperties: $ref: /schemas/types.yaml#/definitions/uint32 enum: [0, 1, 2, 3] + slew-rate: + description: | + Set the slew rate. Valid arguments are described as below: + 0: Normal slew rate + 1: Slower slew + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + required: - pinmux diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml index e994b0c70dbfd2..1cf06e46f7bb0f 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8188-pinctrl.yaml @@ -67,6 +67,11 @@ properties: # PIN CONFIGURATION NODES patternProperties: + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + '-pins$': type: object additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml index db8224dfba2c1b..4910dc8e8aebde 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux-aon.yaml @@ -58,7 +58,11 @@ patternProperties: drive_soc_gpio27_pee6, drive_ao_retention_n_pee2, drive_vcomp_alert_pee1, drive_hdmi_cec_pgg0 ] -unevaluatedProperties: false +required: + - compatible + - reg + +additionalProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml index f5a3a881dec4f0..52b3d40e8839a2 100644 --- a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra234-pinmux.yaml @@ -115,7 +115,11 @@ patternProperties: drive_sdmmc1_dat2_pj4, drive_sdmmc1_dat1_pj3, drive_sdmmc1_dat0_pj2 ] -unevaluatedProperties: false +required: + - compatible + - reg + +additionalProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml new file mode 100644 index 00000000000000..2b2e1a82880e02 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-aon.yaml @@ -0,0 +1,102 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra238 AON Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra238-pinmux-aon + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra238-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2, + pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5, + soc_gpio25_paa6, soc_gpio26_paa7, + hdmi_cec_pbb0, + spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2, + spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5, + uart3_rx_pcc6, gen2_i2c_scl_pcc7, + gen2_i2c_sda_pdd0, gen8_i2c_scl_pdd1, + gen8_i2c_sda_pdd2, touch_clk_pdd3, dmic1_clk_pdd4, + dmic1_dat_pdd5, soc_gpio19_pdd6, pwm2_pdd7, + pwm3_pee0, pwm7_pee1, soc_gpio49_pee2, + soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5, + soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2, + soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5, + soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0, + soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3, + uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6, + uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1, + uart5_cts_phh2, soc_gpio86_phh3, + # drive groups (ordered PAA, PBB, PCC, PDD, PEE, PFF, PGG, PHH) + drive_bootv_ctl_n_paa0, drive_soc_gpio00_paa1, + drive_vcomp_alert_paa2, drive_pwm1_paa3, + drive_batt_oc_paa4, drive_soc_gpio04_paa5, + drive_soc_gpio25_paa6, drive_soc_gpio26_paa7, + drive_hdmi_cec_pbb0, + drive_spi2_sck_pcc0, drive_spi2_miso_pcc1, + drive_spi2_mosi_pcc2, drive_spi2_cs0_pcc3, + drive_spi2_cs1_pcc4, drive_uart3_tx_pcc5, + drive_uart3_rx_pcc6, drive_gen2_i2c_scl_pcc7, + drive_gen2_i2c_sda_pdd0, drive_gen8_i2c_scl_pdd1, + drive_gen8_i2c_sda_pdd2, drive_touch_clk_pdd3, + drive_dmic1_clk_pdd4, drive_dmic1_dat_pdd5, + drive_soc_gpio19_pdd6, drive_pwm2_pdd7, + drive_pwm3_pee0, drive_pwm7_pee1, + drive_soc_gpio49_pee2, drive_soc_gpio50_pee4, + drive_soc_gpio82_pee3, drive_soc_gpio71_pff2, + drive_soc_gpio76_pff7, drive_soc_gpio74_pff5, + drive_soc_gpio86_phh3, drive_soc_gpio72_pff3, + drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6, + drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5, + drive_soc_gpio73_pff4, drive_soc_gpio70_pff1, + drive_soc_gpio85_pgg6, drive_soc_gpio69_pff0, + drive_uart5_tx_pgg7, drive_uart5_rx_phh0, + drive_uart2_tx_pgg2, drive_uart2_rx_pgg3, + drive_uart2_cts_pgg5, drive_uart2_rts_pgg4, + drive_uart5_cts_phh2, drive_uart5_rts_phh1 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinmux@c300000 { + compatible = "nvidia,tegra238-pinmux-aon"; + reg = <0x0c300000 0x4000>; + + pinctrl-names = "cec"; + pinctrl-0 = <&cec_state>; + + cec_state: pinmux-cec { + cec { + nvidia,pins = "hdmi_cec_pbb0"; + nvidia,function = "hdmi_cec"; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml new file mode 100644 index 00000000000000..5c7608981f2d34 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux-common.yaml @@ -0,0 +1,73 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra238 Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +$ref: nvidia,tegra-pinmux-common.yaml + +properties: + nvidia,function: + enum: [ dca_vsync, dca_hsync, displaya, rsvd0, i2c7_clk, i2c7_dat, + i2c4_dat, i2c4_clk, i2c9_dat, i2c9_clk, usb_vbus_en0, + usb_vbus_en1, spi3_din, spi1_cs0, spi3_cs0, spi1_din, + spi3_cs1, spi1_sck, spi3_sck, spi1_cs1, spi1_dout, spi3_dout, + gp_pwm5, gp_pwm6, extperiph2_clk, extperiph1_clk, i2c3_dat, + i2c3_clk, extperiph4_clk, extperiph3_clk, dmic2_dat, + dmic2_clk, uarta_cts, uarta_rts, uarta_rxd, uarta_txd, + i2c5_clk, i2c5_dat, uartd_cts, uartd_rts, uartd_rxd, + uartd_txd, i2c1_clk, i2c1_dat, sdmmc1_cd, i2s2_sclk, + i2s2_sdata_out, i2s2_sdata_in, i2s2_lrck, i2s4_sclk, + i2s4_sdata_out, i2s4_sdata_in, i2s4_lrck, i2s1_sclk, + i2s1_sdata_out, i2s1_sdata_in, i2s1_lrck, aud_mclk, + i2s3_lrck, i2s3_sclk, i2s3_sdata_in, i2s3_sdata_out, + pe2_clkreq_l, pe1_clkreq_l, pe1_rst_l, pe0_clkreq_l, + pe0_rst_l, pe2_rst_l, pe3_clkreq_l, pe3_rst_l, + dp_aux_ch0_hpd, qspi0_io0, qspi0_io1, qspi0_sck, qspi0_cs_n, + uartg_cts, uartg_rts, uartg_txd, uartg_rxd, sdmmc1_clk, + sdmmc1_cmd, sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2, + sdmmc1_dat1, sdmmc1_dat0, ufs0, soc_therm_oc1, hdmi_cec, + gp_pwm4, uartc_rxd, uartc_txd, i2c8_dat, i2c8_clk, + spi2_dout, i2c2_clk, spi2_cs0, i2c2_dat, spi2_sck, spi2_din, + ppc_mode_1, ppc_ready, ppc_mode_2, ppc_cc, ppc_mode_0, + ppc_int_n, uarte_txd, uarte_rxd, uartb_txd, uartb_rxd, + uartb_cts, uartb_rts, uarte_cts, uarte_rts, gp_pwm7, + gp_pwm2, gp_pwm3, gp_pwm1, spi2_cs1, dmic1_clk, dmic1_dat, + rsvd1, dcb_hsync, dcb_vsync, soc_therm_oc4, gp_pwm8, + nv_therm_fan_tach0, wdt_reset_outa, ccla_la_trigger_mux, + dspk1_dat, dspk1_clk, nv_therm_fan_tach1, dspk0_dat, + dspk0_clk, i2s5_sclk, i2s6_lrck, i2s6_sdata_in, i2s6_sclk, + i2s6_sdata_out, i2s5_lrck, i2s5_sdata_out, i2s5_sdata_in, + sdmmc1_pe3_rst_l, sdmmc1_pe3_clkreq_l, touch_clk, + ppc_i2c_dat, wdt_reset_outb, spi5_cs1, ppc_rst_n, + ppc_i2c_clk, spi4_cs1, soc_therm_oc3, spi5_sck, spi5_miso, + spi4_sck, spi4_miso, spi4_cs0, spi4_mosi, spi5_cs0, + spi5_mosi, led_blink, rsvd2, dmic3_clk, dmic3_dat, + dmic4_clk, dmic4_dat, tsc_edge_out0, tsc_edge_out3, + tsc_edge_out1, tsc_edge_out2, dmic5_clk, dmic5_dat, rsvd3, + sdmmc1_wp, tsc_edge_out0a, tsc_edge_out0d, tsc_edge_out0b, + tsc_edge_out0c, soc_therm_oc2 ] + + # out of the common properties, only these are allowed for Tegra238 + nvidia,pins: true + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true + +required: + - nvidia,pins + +additionalProperties: false + +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml new file mode 100644 index 00000000000000..92d276634d7629 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra238-pinmux.yaml @@ -0,0 +1,219 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra238-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra238 Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra238-pinmux + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra238-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ gpu_pwr_req_pa0, gp_pwm5_pa1, gp_pwm6_pa2, spi3_sck_pa3, + spi3_miso_pa4, spi3_mosi_pa5, spi3_cs0_pa6, spi3_cs1_pa7, + spi1_sck_pb0, spi1_miso_pb1, spi1_mosi_pb2, spi1_cs0_pb3, + spi1_cs1_pb4, pwr_i2c_scl_pc0, pwr_i2c_sda_pc1, + extperiph1_clk_pc2, extperiph2_clk_pc3, cam_i2c_scl_pc4, + cam_i2c_sda_pc5, soc_gpio23_pc6, soc_gpio24_pc7, + soc_gpio27_pd0, soc_gpio55_pd1, soc_gpio29_pd2, + soc_gpio33_pd3, soc_gpio32_pd4, soc_gpio35_pd5, + soc_gpio37_pd6, soc_gpio56_pd7, uart1_tx_pe0, + uart1_rx_pe1, uart1_rts_pe2, uart1_cts_pe3, + soc_gpio13_pf0, soc_gpio14_pf1, soc_gpio15_pf2, + soc_gpio16_pf3, soc_gpio17_pf4, soc_gpio18_pf5, + soc_gpio20_pf6, soc_gpio21_pf7, soc_gpio22_pg0, + soc_gpio06_pg1, uart4_tx_pg2, uart4_rx_pg3, + uart4_rts_pg4, uart4_cts_pg5, soc_gpio41_pg6, + soc_gpio42_pg7, soc_gpio43_ph0, soc_gpio44_ph1, + gen1_i2c_scl_ph2, gen1_i2c_sda_ph3, cpu_pwr_req_ph4, + soc_gpio07_ph5, dap3_clk_pj0, dap3_dout_pj1, + dap3_din_pj2, dap3_fs_pj3, soc_gpio57_pj4, + soc_gpio58_pj5, soc_gpio59_pj6, soc_gpio60_pj7, + soc_gpio45_pk0, soc_gpio46_pk1, soc_gpio47_pk2, + soc_gpio48_pk3, qspi0_sck_pl0, qspi0_io0_pl1, + qspi0_io1_pl2, qspi0_cs_n_pl3, soc_gpio152_pl4, + soc_gpio153_pl5, soc_gpio154_pl6, soc_gpio155_pl7, + soc_gpio156_pm0, soc_gpio157_pm1, soc_gpio158_pm2, + soc_gpio159_pm3, soc_gpio160_pm4, soc_gpio161_pm5, + soc_gpio162_pm6, uart7_tx_pm7, uart7_rx_pn0, + uart7_rts_pn1, uart7_cts_pn2, soc_gpio167_pp0, + soc_gpio168_pp1, soc_gpio169_pp2, soc_gpio170_pp3, + dap4_sclk_pp4, dap4_dout_pp5, dap4_din_pp6, dap4_fs_pp7, + soc_gpio171_pq0, soc_gpio172_pq1, soc_gpio173_pq2, + soc_gpio61_pr0, soc_gpio62_pr1, soc_gpio63_pr2, + soc_gpio64_pr3, soc_gpio65_pr4, soc_gpio66_pr5, + soc_gpio67_pr6, soc_gpio68_pr7, gen4_i2c_scl_ps0, + gen4_i2c_sda_ps1, soc_gpio75_ps2, gen7_i2c_scl_ps3, + gen7_i2c_sda_ps4, soc_gpio78_ps5, gen9_i2c_scl_ps6, + gen9_i2c_sda_ps7, soc_gpio81_pt0, soc_gpio36_pt1, + soc_gpio53_pt2, soc_gpio38_pt3, soc_gpio40_pt4, + soc_gpio34_pt5, usb_vbus_en0_pt6, usb_vbus_en1_pt7, + sdmmc1_clk_pu0, sdmmc1_cmd_pu1, sdmmc1_dat0_pu2, + sdmmc1_dat1_pu3, sdmmc1_dat2_pu4, sdmmc1_dat3_pu5, + ufs0_ref_clk_pv0, ufs0_rst_n_pv1, pex_l0_clkreq_n_pw0, + pex_l0_rst_n_pw1, pex_l1_clkreq_n_pw2, + pex_l1_rst_n_pw3, pex_l2_clkreq_n_pw4, + pex_l2_rst_n_pw5, pex_l3_clkreq_n_pw6, + pex_l3_rst_n_pw7, pex_wake_n_px0, dp_aux_ch0_hpd_px1, + bootv_ctl_n_paa0, soc_gpio00_paa1, vcomp_alert_paa2, + pwm1_paa3, batt_oc_paa4, soc_gpio04_paa5, + soc_gpio25_paa6, soc_gpio26_paa7, hdmi_cec_pbb0, + spi2_sck_pcc0, spi2_miso_pcc1, spi2_mosi_pcc2, + spi2_cs0_pcc3, spi2_cs1_pcc4, uart3_tx_pcc5, + uart3_rx_pcc6, gen2_i2c_scl_pcc7, gen2_i2c_sda_pdd0, + gen8_i2c_scl_pdd1, gen8_i2c_sda_pdd2, touch_clk_pdd3, + dmic1_clk_pdd4, dmic1_dat_pdd5, soc_gpio19_pdd6, + pwm2_pdd7, pwm3_pee0, pwm7_pee1, soc_gpio49_pee2, + soc_gpio82_pee3, soc_gpio50_pee4, soc_gpio83_pee5, + soc_gpio69_pff0, soc_gpio70_pff1, soc_gpio71_pff2, + soc_gpio72_pff3, soc_gpio73_pff4, soc_gpio74_pff5, + soc_gpio80_pff6, soc_gpio76_pff7, soc_gpio77_pgg0, + soc_gpio84_pgg1, uart2_tx_pgg2, uart2_rx_pgg3, + uart2_rts_pgg4, uart2_cts_pgg5, soc_gpio85_pgg6, + uart5_tx_pgg7, uart5_rx_phh0, uart5_rts_phh1, + uart5_cts_phh2, soc_gpio86_phh3, sdmmc1_comp, + # drive groups + drive_soc_gpio36_pt1, drive_soc_gpio53_pt2, + drive_soc_gpio38_pt3, drive_soc_gpio40_pt4, + drive_soc_gpio75_ps2, drive_soc_gpio81_pt0, + drive_soc_gpio78_ps5, drive_soc_gpio34_pt5, + drive_gen7_i2c_scl_ps3, drive_gen7_i2c_sda_ps4, + drive_gen4_i2c_sda_ps1, drive_gen4_i2c_scl_ps0, + drive_gen9_i2c_sda_ps7, drive_gen9_i2c_scl_ps6, + drive_usb_vbus_en0_pt6, drive_usb_vbus_en1_pt7, + drive_soc_gpio61_pr0, drive_soc_gpio62_pr1, + drive_soc_gpio63_pr2, drive_soc_gpio64_pr3, + drive_soc_gpio65_pr4, drive_soc_gpio66_pr5, + drive_soc_gpio67_pr6, drive_soc_gpio68_pr7, + drive_spi3_miso_pa4, drive_spi1_cs0_pb3, + drive_spi3_cs0_pa6, drive_spi1_miso_pb1, + drive_spi3_cs1_pa7, drive_spi1_sck_pb0, + drive_spi3_sck_pa3, drive_spi1_cs1_pb4, + drive_spi1_mosi_pb2, drive_spi3_mosi_pa5, + drive_gpu_pwr_req_pa0, drive_gp_pwm5_pa1, + drive_gp_pwm6_pa2, drive_extperiph2_clk_pc3, + drive_extperiph1_clk_pc2, drive_cam_i2c_sda_pc5, + drive_cam_i2c_scl_pc4, drive_soc_gpio23_pc6, + drive_soc_gpio24_pc7, drive_soc_gpio27_pd0, + drive_soc_gpio29_pd2, drive_soc_gpio32_pd4, + drive_soc_gpio33_pd3, drive_soc_gpio35_pd5, + drive_soc_gpio37_pd6, drive_soc_gpio56_pd7, + drive_soc_gpio55_pd1, drive_uart1_cts_pe3, + drive_uart1_rts_pe2, drive_uart1_rx_pe1, + drive_uart1_tx_pe0, drive_pwr_i2c_scl_pc0, + drive_pwr_i2c_sda_pc1, drive_cpu_pwr_req_ph4, + drive_uart4_cts_pg5, drive_uart4_rts_pg4, + drive_uart4_rx_pg3, drive_uart4_tx_pg2, + drive_gen1_i2c_scl_ph2, drive_gen1_i2c_sda_ph3, + drive_soc_gpio20_pf6, drive_soc_gpio21_pf7, + drive_soc_gpio22_pg0, drive_soc_gpio13_pf0, + drive_soc_gpio14_pf1, drive_soc_gpio15_pf2, + drive_soc_gpio16_pf3, drive_soc_gpio17_pf4, + drive_soc_gpio18_pf5, drive_soc_gpio41_pg6, + drive_soc_gpio42_pg7, drive_soc_gpio43_ph0, + drive_soc_gpio44_ph1, drive_soc_gpio06_pg1, + drive_soc_gpio07_ph5, drive_dap4_sclk_pp4, + drive_dap4_dout_pp5, drive_dap4_din_pp6, + drive_dap4_fs_pp7, drive_soc_gpio167_pp0, + drive_soc_gpio168_pp1, drive_soc_gpio169_pp2, + drive_soc_gpio170_pp3, drive_soc_gpio171_pq0, + drive_soc_gpio172_pq1, drive_soc_gpio173_pq2, + drive_soc_gpio45_pk0, drive_soc_gpio46_pk1, + drive_soc_gpio47_pk2, drive_soc_gpio48_pk3, + drive_soc_gpio57_pj4, drive_soc_gpio58_pj5, + drive_soc_gpio59_pj6, drive_soc_gpio60_pj7, + drive_dap3_fs_pj3, drive_dap3_clk_pj0, + drive_dap3_din_pj2, drive_dap3_dout_pj1, + drive_pex_l2_clkreq_n_pw4, drive_pex_wake_n_px0, + drive_pex_l1_clkreq_n_pw2, drive_pex_l1_rst_n_pw3, + drive_pex_l0_clkreq_n_pw0, drive_pex_l0_rst_n_pw1, + drive_pex_l2_rst_n_pw5, drive_pex_l3_clkreq_n_pw6, + drive_pex_l3_rst_n_pw7, drive_dp_aux_ch0_hpd_px1, + drive_qspi0_io0_pl1, drive_qspi0_io1_pl2, + drive_qspi0_sck_pl0, drive_qspi0_cs_n_pl3, + drive_soc_gpio156_pm0, drive_soc_gpio155_pl7, + drive_soc_gpio160_pm4, drive_soc_gpio154_pl6, + drive_soc_gpio152_pl4, drive_soc_gpio153_pl5, + drive_soc_gpio161_pm5, drive_soc_gpio162_pm6, + drive_soc_gpio159_pm3, drive_soc_gpio157_pm1, + drive_soc_gpio158_pm2, drive_uart7_cts_pn2, + drive_uart7_rts_pn1, drive_uart7_tx_pm7, + drive_uart7_rx_pn0, drive_sdmmc1_clk_pu0, + drive_sdmmc1_cmd_pu1, drive_sdmmc1_dat3_pu5, + drive_sdmmc1_dat2_pu4, drive_sdmmc1_dat1_pu3, + drive_sdmmc1_dat0_pu2, drive_ufs0_rst_n_pv1, + drive_ufs0_ref_clk_pv0, drive_batt_oc_paa4, + drive_bootv_ctl_n_paa0, drive_vcomp_alert_paa2, + drive_hdmi_cec_pbb0, drive_touch_clk_pdd3, + drive_uart3_rx_pcc6, drive_uart3_tx_pcc5, + drive_gen8_i2c_sda_pdd2, drive_gen8_i2c_scl_pdd1, + drive_spi2_mosi_pcc2, drive_gen2_i2c_scl_pcc7, + drive_spi2_cs0_pcc3, drive_gen2_i2c_sda_pdd0, + drive_spi2_sck_pcc0, drive_spi2_miso_pcc1, + drive_soc_gpio49_pee2, drive_soc_gpio50_pee4, + drive_soc_gpio82_pee3, drive_soc_gpio71_pff2, + drive_soc_gpio76_pff7, drive_soc_gpio74_pff5, + drive_soc_gpio00_paa1, drive_soc_gpio19_pdd6, + drive_soc_gpio86_phh3, drive_soc_gpio72_pff3, + drive_soc_gpio77_pgg0, drive_soc_gpio80_pff6, + drive_soc_gpio84_pgg1, drive_soc_gpio83_pee5, + drive_soc_gpio73_pff4, drive_soc_gpio70_pff1, + drive_soc_gpio04_paa5, drive_soc_gpio85_pgg6, + drive_soc_gpio69_pff0, drive_soc_gpio25_paa6, + drive_soc_gpio26_paa7, drive_uart5_tx_pgg7, + drive_uart5_rx_phh0, drive_uart2_tx_pgg2, + drive_uart2_rx_pgg3, drive_uart2_cts_pgg5, + drive_uart2_rts_pgg4, drive_uart5_cts_phh2, + drive_uart5_rts_phh1, drive_pwm7_pee1, + drive_pwm2_pdd7, drive_pwm3_pee0, drive_pwm1_paa3, + drive_spi2_cs1_pcc4, drive_dmic1_clk_pdd4, + drive_dmic1_dat_pdd5, drive_sdmmc1_comp ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinmux@2430000 { + compatible = "nvidia,tegra238-pinmux"; + reg = <0x2430000 0x17000>; + + pinctrl-names = "pex_rst"; + pinctrl-0 = <&pex_rst_c5_out_state>; + + pex_rst_c5_out_state: pinmux-pex-rst-c5-out { + pexrst { + nvidia,pins = "pex_l3_rst_n_pw7"; + nvidia,schmitt = ; + nvidia,enable-input = ; + nvidia,io-hv = ; + nvidia,tristate = ; + nvidia,pull = ; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml new file mode 100644 index 00000000000000..682e6510ed457a --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-aon.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-aon.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 AON Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra264-pinmux-aon + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra264-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ soc_gpio00_paa0, vcomp_alert_paa1, ao_retention_n_paa2, + batt_oc_paa3, bootv_ctl_n_paa4, power_on_paa5, + hdmi_cec_paa6, soc_gpio07_paa7, soc_gpio08_pbb0, + soc_gpio09_pbb1, gen2_i2c_scl_pcc0, gen2_i2c_sda_pcc1, + gen3_i2c_scl_pcc2, gen3_i2c_sda_pcc3, gp_pwm4_pcc4, + uart0_tx_pcc5, uart0_rx_pcc6, spi2_sck_pcc7, + spi2_miso_pdd0, spi2_mosi_pdd1, spi2_cs0_n_pdd2, + soc_gpio21_pdd3, soc_gpio22_pdd4, soc_gpio23_pdd5, + soc_gpio24_pdd6, soc_gpio25_pdd7, soc_gpio26_pee0, + soc_gpio27_pee1, soc_gpio28_pee2, soc_gpio29_pee3, + drive_ao_retention_n_paa2, drive_batt_oc_paa3, + drive_power_on_paa5, drive_vcomp_alert_paa1, + drive_bootv_ctl_n_paa4, drive_soc_gpio00_paa0, + drive_soc_gpio07_paa7, drive_soc_gpio08_pbb0, + drive_soc_gpio09_pbb1, drive_hdmi_cec_paa6, + drive_gen2_i2c_scl_pcc0, drive_gen2_i2c_sda_pcc1, + drive_gen3_i2c_scl_pcc2, drive_gen3_i2c_sda_pcc3, + drive_gp_pwm4_pcc4, drive_uart0_tx_pcc5, + drive_uart0_rx_pcc6, drive_spi2_sck_pcc7, + drive_spi2_miso_pdd0, drive_spi2_mosi_pdd1, + drive_spi2_cs0_n_pdd2, drive_soc_gpio21_pdd3, + drive_soc_gpio22_pdd4, drive_soc_gpio23_pdd5, + drive_soc_gpio24_pdd6, drive_soc_gpio25_pdd7, + drive_soc_gpio26_pee0, drive_soc_gpio27_pee1, + drive_soc_gpio28_pee2, drive_soc_gpio29_pee3 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinmux@c7a2000 { + compatible = "nvidia,tegra264-pinmux-aon"; + reg = <0xc7a2000 0x2000>; + + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux-default { + uart0 { + nvidia,pins = "uart0_tx_pcc5"; + nvidia,function = "uarta_txd"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml new file mode 100644 index 00000000000000..d644c496d8a5d0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-common.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-common.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 Pinmux Common Properties + +maintainers: + - Thierry Reding + - Jon Hunter + +$ref: nvidia,tegra-pinmux-common.yaml + +properties: + nvidia,function: + enum: [ dca_vsync, dca_hsync, rsvd0, dp_aux_ch0_hpd, dp_aux_ch1_hpd, + dp_aux_ch2_hpd, dp_aux_ch3_hpd, gp_pwm2, gp_pwm3, i2c7_clk, + i2c7_dat, i2c9_clk, i2c9_dat, uartk_cts, uartk_rts, uartk_rxd, + uartk_txd, spi3_cs0, spi3_cs3, spi3_din, spi3_dout, spi3_sck, + uartf_cts, uartf_rts, uartf_rxd, uartf_txd, spi1_cs0, spi1_cs1, + spi1_din, spi1_dout, spi1_sck, extperiph2_clk, extperiph1_clk, + i2c12_clk, i2c12_dat, nv_therm_fan_tach0, gp_pwm9, uartj_cts, + uartj_rts, uartj_rxd, uartj_txd, i2c0_clk, i2c0_dat, i2c1_clk, + i2c1_dat, i2s2_lrck, i2s2_sclk, i2s2_sdata_out, i2s2_sdata_in, + gp_pwm10, uarte_cts, uarte_rts, uarte_rxd, uarte_txd, i2c5_dat, + i2c5_clk, i2s6_sdata_in, i2s6_sdata_out, i2s6_lrck, i2s6_sclk, + i2s4_sdata_out, i2s4_sclk, i2s4_sdata_in, i2s4_lrck, spi5_cs0, + spi5_din, spi5_dout, spi5_sck, aud_mclk, i2s1_sclk, i2s1_sdata_in, + i2s1_sdata_out, i2s1_lrck, i2c11_clk, i2c11_dat, xhalt_trig, + gp_pwm1, gp_pwm6, gp_pwm7, gp_pwm8, ufs0, pe1_clkreq_l, pe1_rst_l, + pe2_rst_l, pe2_clkreq_l, pe3_clkreq_l, pe3_rst_l, sgmii0_sma_mdio, + sgmii0_sma_mdc, usb_vbus_en0, usb_vbus_en1, eth1_mdio, pe4_clkreq_l, + pe4_rst_l, pe5_clkreq_l, pe5_rst_l, eth0_mdio, eth0_mdc, eth1_mdc, + eth2_mdio, eth2_mdc, eth3_mdio, eth3_mdc, qspi0_cs_n, qspi0_io0, + qspi0_io1, qspi0_io2, qspi0_io3, qspi0_sck, sdmmc1_clk, sdmmc1_cmd, + sdmmc1_comp, sdmmc1_dat3, sdmmc1_dat2, sdmmc1_dat1, sdmmc1_dat0, + qspi3_sck, qspi3_cs0, qspi3_io0, qspi3_io1, dcb_vsync, dcb_hsync, + dsa_lspii, dce_vsync, dce_hsync, dch_vsync, dch_hsync, bl_en, + bl_pwm_dim0, rsvd1, soc_therm_oc3, i2s5_sclk, i2s5_sdata_in, + extperiph3_clk, extperiph4_clk, i2s5_sdata_out, i2s5_lrck, + sdmmc1_cd, i2s7_sdata_in, spi4_sck, spi4_din, spi4_dout, spi4_cs0, + spi4_cs1, gp_pwm5, i2c14_clk, i2c14_dat, i2s8_sclk, i2s8_sdata_out, + i2s8_lrck, i2s8_sdata_in, i2c16_clk, i2c16_dat, i2s3_sclk, + i2s3_sdata_out, i2s3_sdata_in, i2s3_lrck, pm_trig1, pm_trig0, + qspi2_sck, qspi2_cs0, qspi2_io0, qspi2_io1, dcc_vsync, dcc_hsync, + rsvd2, dcf_vsync, dcf_hsync, soundwire1_clk, soundwire1_dat0, + soundwire1_dat1, soundwire1_dat2, dmic2_clk, dmic2_dat, + nv_therm_fan_tach1, i2c15_clk, i2c15_dat, i2s7_lrck, + ccla_la_trigger_mux, i2s7_sclk, i2s7_sdata_out, dmic1_dat, + dmic1_clk, dcd_vsync, dcd_hsync, rsvd3, dcg_vsync, dcg_hsync, + dspk1_clk, dspk1_dat, soc_therm_oc2, istctrl_ist_done_n, + soc_therm_oc1, tsc_edge_out0c, tsc_edge_out0d, tsc_edge_out0a, + tsc_edge_out0b, touch_clk, hdmi_cec, i2c2_clk, i2c2_dat, i2c3_clk, + i2c3_dat, gp_pwm4, uarta_txd, uarta_rxd, spi2_sck, spi2_din, + spi2_dout, spi2_cs0, tsc_sync1, tsc_edge_out3, tsc_edge_out0, + tsc_edge_out1, tsc_sync0, soundwire0_clk, soundwire0_dat0, + l0l1_rst_out_n, l2_rst_out_n, uartl_txd, uartl_rxd, i2s9_sclk, + i2s9_sdata_out, i2s9_sdata_in, i2s9_lrck, dmic5_dat, dmic5_clk, + tsc_edge_out2 ] + + # out of the common properties, only these are allowed for Tegra264 + nvidia,pins: true + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true + +required: + - nvidia,pins + +# We would typically use unevaluatedProperties here but that has the +# downside that all the properties in the common bindings become valid +# for all chip generations. In this case, however, we want the per-SoC +# bindings to be able to override which of the common properties are +# allowed, since not all pinmux generations support the same sets of +# properties. This way, the common bindings define the format of the +# properties but the per-SoC bindings define which of them apply to a +# given chip. +additionalProperties: false diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml new file mode 100644 index 00000000000000..c40409d3263c23 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-main.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-main.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 Main Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra264-pinmux-main + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra264-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3, ufs0_ref_clk_pa4, + ufs0_rst_n_pa5, soc_gpio250_pf0, soc_gpio251_pf1, + soc_gpio252_pf2, dp_aux_ch0_hpd_pf3, dp_aux_ch1_hpd_pf4, + dp_aux_ch2_hpd_pf5, dp_aux_ch3_hpd_pf6, pwm2_pf7, pwm3_pg0, + gen7_i2c_scl_pg1, gen7_i2c_sda_pg2, gen9_i2c_scl_pg3, + gen9_i2c_sda_pg4, sdmmc1_clk_px0, sdmmc1_cmd_px1, + sdmmc1_dat0_px2, sdmmc1_dat1_px3, sdmmc1_dat2_px4, + sdmmc1_dat3_px5, sdmmc1_comp, soc_gpio124_pl0, + soc_gpio125_pl1, fan_tach0_pl2, soc_gpio127_pl3, + soc_gpio128_pl4, soc_gpio129_pl5, soc_gpio130_pl6, + soc_gpio131_pl7, gp_pwm9_pm0, soc_gpio133_pm1, uart9_tx_pm2, + uart9_rx_pm3, uart9_rts_n_pm4, uart9_cts_n_pm5, + soc_gpio170_pu0, soc_gpio171_pu1, soc_gpio172_pu2, + soc_gpio173_pu3, soc_gpio174_pu4, soc_gpio175_pu5, + soc_gpio176_pu6, soc_gpio177_pu7, soc_gpio178_pv0, + pwm10_pv1, uart4_tx_pv2, uart4_rx_pv3, uart4_rts_n_pv4, + uart4_cts_n_pv5, dap2_clk_pv6, dap2_din_pv7, dap2_dout_pw0, + dap2_fs_pw1, gen1_i2c_scl_pw2, gen1_i2c_sda_pw3, + gen0_i2c_scl_pw4, gen0_i2c_sda_pw5, pwr_i2c_scl_pw6, + pwr_i2c_sda_pw7, soc_gpio138_pp0, soc_gpio139_pp1, + dap6_sclk_pp2, dap6_dout_pp3, dap6_din_pp4, dap6_fs_pp5, + dap4_sclk_pp6, dap4_dout_pp7, dap4_din_pq0, dap4_fs_pq1, + spi5_sck_pq2, spi5_miso_pq3, spi5_mosi_pq4, spi5_cs0_pq5, + soc_gpio152_pq6, soc_gpio153_pq7, aud_mclk_pr0, + soc_gpio155_pr1, dap1_sclk_pr2, dap1_out_pr3, dap1_in_pr4, + dap1_fs_pr5, gen11_i2c_scl_pr6, gen11_i2c_sda_pr7, + soc_gpio350_ps0, soc_gpio351_ps1, qspi0_sck_pt0, + qspi0_cs_n_pt1, qspi0_io0_pt2, qspi0_io1_pt3, qspi0_io2_pt4, + qspi0_io3_pt5, soc_gpio192_pt6, soc_gpio270_py0, + soc_gpio271_py1, soc_gpio272_py2, soc_gpio273_py3, + soc_gpio274_py4, soc_gpio275_py5, soc_gpio276_py6, + soc_gpio277_py7, soc_gpio278_pz0, soc_gpio279_pz1, + xhalt_trig_pz2, soc_gpio281_pz3, soc_gpio282_pz4, + soc_gpio283_pz5, soc_gpio284_pz6, soc_gpio285_pz7, + soc_gpio286_pal0, soc_gpio287_pal1, soc_gpio288_pal2, + cpu_pwr_req_ph0, gpu_pwr_req_ph1, uart10_tx_ph2, + uart10_rx_ph3, uart10_rts_n_ph4, uart10_cts_n_ph5, + spi3_sck_ph6, spi3_miso_ph7, spi3_mosi_pj0, spi3_cs0_pj1, + spi3_cs3_pj2, uart5_tx_pj3, uart5_rx_pj4, uart5_rts_n_pj5, + uart5_cts_n_pj6, spi1_sck_pj7, spi1_miso_pk0, spi1_mosi_pk1, + spi1_cs0_pk2, spi1_cs1_pk3, extperiph1_clk_pk4, + extperiph2_clk_pk5, gen12_i2c_scl_pk6, gen12_i2c_sda_pk7, + drive_cpu_pwr_req_ph0, drive_gpu_pwr_req_ph1, + drive_uart10_cts_n_ph5, drive_uart10_rts_n_ph4, + drive_uart10_rx_ph3, drive_uart10_tx_ph2, + drive_spi3_cs0_pj1, drive_spi3_cs3_pj2, + drive_spi3_miso_ph7, drive_spi3_mosi_pj0, + drive_spi3_sck_ph6, drive_uart5_cts_n_pj6, + drive_uart5_rts_n_pj5, drive_uart5_rx_pj4, + drive_uart5_tx_pj3, drive_spi1_cs0_pk2, + drive_spi1_cs1_pk3, drive_spi1_miso_pk0, + drive_spi1_mosi_pk1, drive_spi1_sck_pj7, + drive_extperiph2_clk_pk5, drive_extperiph1_clk_pk4, + drive_gen12_i2c_scl_pk6, drive_gen12_i2c_sda_pk7, + drive_soc_gpio124_pl0, drive_soc_gpio125_pl1, + drive_fan_tach0_pl2, drive_soc_gpio127_pl3, + drive_soc_gpio128_pl4, drive_soc_gpio129_pl5, + drive_soc_gpio130_pl6, drive_soc_gpio131_pl7, + drive_gp_pwm9_pm0, drive_soc_gpio133_pm1, + drive_uart9_cts_n_pm5, drive_uart9_rts_n_pm4, + drive_uart9_rx_pm3, drive_uart9_tx_pm2, + drive_sdmmc1_clk_px0, drive_sdmmc1_cmd_px1, + drive_sdmmc1_dat3_px5, drive_sdmmc1_dat2_px4, + drive_sdmmc1_dat1_px3, drive_sdmmc1_dat0_px2, + drive_qspi0_cs_n_pt1, drive_qspi0_io0_pt2, + drive_qspi0_io1_pt3, drive_qspi0_io2_pt4, + drive_qspi0_io3_pt5, drive_qspi0_sck_pt0, + drive_soc_gpio192_pt6, drive_soc_gpio138_pp0, + drive_soc_gpio139_pp1, drive_dap6_din_pp4, + drive_dap6_dout_pp3, drive_dap6_fs_pp5, + drive_dap6_sclk_pp2, drive_dap4_dout_pp7, + drive_dap4_sclk_pp6, drive_dap4_din_pq0, + drive_dap4_fs_pq1, drive_spi5_cs0_pq5, + drive_spi5_miso_pq3, drive_spi5_mosi_pq4, + drive_spi5_sck_pq2, drive_soc_gpio152_pq6, + drive_soc_gpio153_pq7, drive_soc_gpio155_pr1, + drive_aud_mclk_pr0, drive_dap1_sclk_pr2, + drive_dap1_in_pr4, drive_dap1_out_pr3, + drive_dap1_fs_pr5, drive_gen11_i2c_scl_pr6, + drive_gen11_i2c_sda_pr7, drive_soc_gpio350_ps0, + drive_soc_gpio351_ps1, drive_gen0_i2c_scl_pw4, + drive_gen0_i2c_sda_pw5, drive_gen1_i2c_scl_pw2, + drive_gen1_i2c_sda_pw3, drive_dap2_fs_pw1, + drive_dap2_clk_pv6, drive_dap2_din_pv7, + drive_dap2_dout_pw0, drive_pwm10_pv1, + drive_soc_gpio170_pu0, drive_soc_gpio171_pu1, + drive_soc_gpio172_pu2, drive_soc_gpio173_pu3, + drive_soc_gpio174_pu4, drive_soc_gpio175_pu5, + drive_soc_gpio176_pu6, drive_soc_gpio177_pu7, + drive_soc_gpio178_pv0, drive_uart4_cts_n_pv5, + drive_uart4_rts_n_pv4, drive_uart4_rx_pv3, + drive_uart4_tx_pv2, drive_pwr_i2c_sda_pw7, + drive_pwr_i2c_scl_pw6, drive_soc_gpio250_pf0, + drive_soc_gpio251_pf1, drive_soc_gpio252_pf2, + drive_dp_aux_ch0_hpd_pf3, drive_dp_aux_ch1_hpd_pf4, + drive_dp_aux_ch2_hpd_pf5, drive_dp_aux_ch3_hpd_pf6, + drive_pwm2_pf7, drive_pwm3_pg0, + drive_gen7_i2c_scl_pg1, drive_gen7_i2c_sda_pg2, + drive_gen9_i2c_scl_pg3, drive_gen9_i2c_sda_pg4, + drive_soc_gpio270_py0, drive_soc_gpio271_py1, + drive_soc_gpio272_py2, drive_soc_gpio273_py3, + drive_soc_gpio274_py4, drive_soc_gpio275_py5, + drive_soc_gpio276_py6, drive_soc_gpio277_py7, + drive_soc_gpio278_pz0, drive_soc_gpio279_pz1, + drive_soc_gpio282_pz4, drive_soc_gpio283_pz5, + drive_soc_gpio284_pz6, drive_soc_gpio285_pz7, + drive_soc_gpio286_pal0, drive_soc_gpio287_pal1, + drive_soc_gpio288_pal2, drive_xhalt_trig_pz2, + drive_soc_gpio281_pz3 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinmux@c281000 { + compatible = "nvidia,tegra264-pinmux-main"; + reg = <0xc281000 0xc000>; + + pinctrl-names = "default"; + pinctrl-0 = <&state_default>; + + state_default: pinmux-default { + sdmmc1 { + nvidia,pins = "sdmmc1_clk_px0"; + nvidia,function = "sdmmc1_cd"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml new file mode 100644 index 00000000000000..9a54795d9cc5e0 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra264-pinmux-uphy.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra264-pinmux-uphy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra264 UPHY Pinmux Controller + +maintainers: + - Thierry Reding + - Jon Hunter + +properties: + compatible: + const: nvidia,tegra264-pinmux-uphy + + reg: + maxItems: 1 + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra264-pinmux-common.yaml + + properties: + nvidia,pins: + items: + enum: [ eth1_mdio_pe0, pex_l4_clkreq_n_pd0, pex_l4_rst_n_pd1, + pex_l5_clkreq_n_pd2, pex_l5_rst_n_pd3, eth0_mdio_pd4, + eth0_mdc_pd5, eth1_mdc_pe1, eth2_mdio_pe2, eth2_mdc_pe3, + eth3_mdio_pd6, eth3_mdc_pd7, pex_l1_clkreq_n_pb0, + pex_l1_rst_n_pb1, pex_wake_n_pc2, pex_l2_rst_n_pb3, + pex_l2_clkreq_n_pb2, pex_l3_clkreq_n_pb4, pex_l3_rst_n_pb5, + sgmii0_sma_mdio_pc0, sgmii0_sma_mdc_pc1, soc_gpio113_pb6, + soc_gpio114_pb7, pwm1_pa0, pwm6_pa1, pwm7_pa2, pwm8_pa3, + ufs0_ref_clk_pa4, ufs0_rst_n_pa5, drive_eth1_mdio_pe0, + drive_pex_l4_clkreq_n_pd0, drive_pex_l4_rst_n_pd1, + drive_pex_l5_clkreq_n_pd2, drive_pex_l5_rst_n_pd3, + drive_eth0_mdio_pd4, drive_eth0_mdc_pd5, drive_eth1_mdc_pe1, + drive_eth2_mdio_pe2, drive_eth2_mdc_pe3, drive_eth3_mdio_pd6, + drive_eth3_mdc_pd7, drive_pex_l1_clkreq_n_pb0, + drive_pex_l1_rst_n_pb1, drive_pex_wake_n_pc2, + drive_pex_l2_rst_n_pb3, drive_pex_l2_clkreq_n_pb2, + drive_pex_l3_clkreq_n_pb4, drive_pex_l3_rst_n_pb5, + drive_sgmii0_sma_mdio_pc0, drive_sgmii0_sma_mdc_pc1, + drive_soc_gpio113_pb6, drive_soc_gpio114_pb7, + drive_pwm1_pa0, drive_pwm6_pa1, drive_pwm7_pa2, + drive_pwm8_pa3, drive_ufs0_ref_clk_pa4, drive_ufs0_rst_n_pa5 ] + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include + + pinmux@82e0000 { + compatible = "nvidia,tegra264-pinmux-uphy"; + reg = <0x82e0000 0x4000>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinmux_default>; + + pinmux_default: pinmux-default { + pex { + nvidia,pins = "pex_l1_rst_n_pb1"; + nvidia,pull = ; + nvidia,tristate = ; + nvidia,enable-input = ; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl-multiplexer.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl-multiplexer.yaml new file mode 100644 index 00000000000000..2b0385ed879b70 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl-multiplexer.yaml @@ -0,0 +1,57 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/pinctrl-multiplexer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Generic pinctrl device for on-board MUX Chips + +maintainers: + - Frank Li + +description: + Generic pinctrl device for on-board MUX Chips, which switch SoC signals + between different peripherals (e.g. MMC and UART). + + The MUX select lines are often driven by a I2C GPIO expander. + +properties: + compatible: + const: pinctrl-multiplexer + +patternProperties: + '-grp$': + type: object + additionalProperties: false + properties: + mux-states: + maxItems: 1 + + required: + - mux-states + +required: + - compatible + +allOf: + - $ref: pinctrl.yaml# + +unevaluatedProperties: false + +examples: + - | + pinctrl-mux { + compatible = "pinctrl-multiplexer"; + + uart-grp { + mux-states = <&mux 0>; + }; + + spi-grp { + mux-states = <&mux 1>; + }; + + i2c-grp { + mux-states = <&mux 2>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml index 290438826c507e..20176bf3074757 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml @@ -27,7 +27,7 @@ description: | properties: $nodename: - pattern: "^(pinctrl|pinmux)(@[0-9a-f]+)?$" + pattern: "^(pinctrl|pinmux)(@[0-9a-f]+|-[a-z0-9]+)?$" "#pinctrl-cells": description: > diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml index 28265042648797..aaaeca8e7bb7ad 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml @@ -86,16 +86,22 @@ $defs: qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable, qlink_big_request, qlink_little_enable, qlink_little_request, qlink_wmss, qspi0, qspi_clk, - qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, - qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1, - qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6, - qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2, - sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0, - tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1, - tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk, - uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data, - uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1, - vsense_trigger_mirnat, wcn_sw_ctrl ] + qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se2_l2_mira, + qup1_se2_l2_mirb, qup1_se2_l3_mira, qup1_se2_l3_mirb, + qup1_se3, qup1_se4_01, qup1_se4_23, + qup1_se5, qup1_se6, qup1_se6_l1_mira, + qup1_se6_l1_mirb, qup1_se6_l3_mira, qup1_se6_l3_mirb, + qup1_se7, qup1_se7_l0_mira, qup1_se7_l0_mirb, + qup1_se7_l1_mira, qup1_se7_l1_mirb, qup2_se0, qup2_se1, + qup2_se2, qup2_se3, qup2_se3_l0_mira, qup2_se3_l0_mirb, + qup2_se3_l1_mira, qup2_se3_l1_mirb, qup2_se4, qup2_se5, + qup2_se6, qup2_se7, resout_gpio, sd_write_protect, sdc1, + sdc2, sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, + tmess_prng0, tmess_prng1, tmess_prng2, tmess_prng3, + tsense_pwm1, tsense_pwm2, tsense_pwm3, tsense_pwm4, + uim0_clk, uim0_data, uim0_present, uim0_reset, uim1_clk, + uim1_data, uim1_present, uim1_reset, usb0_hs, usb_phy, + vfr_0, vfr_1, vsense_trigger_mirnat, wcn_sw_ctrl ] required: - pins diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml index cc5de9f7768014..de9a3e67e1bbe5 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq4019-pinctrl.yaml @@ -36,11 +36,6 @@ patternProperties: $ref: "#/$defs/qcom-ipq4019-tlmm-state" additionalProperties: false - "-hog(-[0-9]+)?$": - type: object - required: - - gpio-hog - $defs: qcom-ipq4019-tlmm-state: type: object diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml new file mode 100644 index 00000000000000..549eaa6aa11b4c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,ipq9650-tlmm.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,ipq9650-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ9650 TLMM pin controller + +maintainers: + - Bjorn Andersson + - Kathiravan Thirumoorthy + +description: + Top Level Mode Multiplexer pin controller in Qualcomm IPQ9650 SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,ipq9650-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 27 + + gpio-line-names: + maxItems: 54 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-ipq9650-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-ipq9650-tlmm-state" + additionalProperties: false + +$defs: + qcom-ipq9650-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$" + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ atest_char_start, atest_char_status0, atest_char_status1, + atest_char_status2, atest_char_status3, atest_tic_en, + audio_pri_mclk_in0, audio_pri_mclk_out0, audio_pri_mclk_in1, + audio_pri_mclk_out1, audio_pri, audio_sec, audio_sec_mclk_in0, + audio_sec_mclk_out0, audio_sec_mclk_in1, audio_sec_mclk_out1, + core_voltage_0, core_voltage_1, core_voltage_2, core_voltage_3, + core_voltage_4, cri_rng0, cri_rng1, cri_rng2, dbg_out_clk, + gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, + mdc_mst, mdc_slv0, mdc_slv1, mdio_mst, mdio_slv, mdio_slv0, + mdio_slv1, pcie0_clk_req_n, pcie0_wake, pcie1_clk_req_n, + pcie1_wake, pcie2_clk_req_n, pcie2_wake, pcie3_clk_req_n, + pcie3_wake, pcie4_clk_req_n, pcie4_wake, pll_bist_sync, + pll_test, pwm, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, + qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0, + qdss_cti_trig_out_a1, qdss_cti_trig_out_b0, qdss_cti_trig_out_b1, + qdss_traceclk_a, qdss_tracectl_a, qdss_tracedata_a, qspi_data, + qspi_clk, qspi_cs_n, qup_se0, qup_se1, qup_se2, qup_se3, + qup_se4, qup_se5, qup_se6, qup_se7, resout, rx_los0, rx_los1, + rx_los2, sdc_clk, sdc_cmd, sdc_data, tsens_max, tsn ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@1000000 { + compatible = "qcom,ipq9650-tlmm"; + reg = <0x01000000 0x300000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&tlmm 0 0 54>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <2>; + + qup-uart1-default-state { + pins = "gpio43", "gpio44"; + function = "qup_se6"; + drive-strength = <8>; + bias-pull-down; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml new file mode 100644 index 00000000000000..4bb511719f3130 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,nord-tlmm.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,nord-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. SA8797P TLMM block + +maintainers: + - Bartosz Golaszewski + +description: + Top Level Mode Multiplexer pin controller in Qualcomm SA8797P SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,nord-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 90 + + gpio-line-names: + maxItems: 181 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-nord-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-nord-tlmm-state" + additionalProperties: false + +$defs: + qcom-nord-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|180)$" + - enum: [ ufs_reset ] + minItems: 1 + maxItems: 16 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ aoss_cti, atest_char, atest_usb20, atest_usb21, + aud_intfc0_clk, aud_intfc0_data, aud_intfc0_ws, + aud_intfc10_clk, aud_intfc10_data, aud_intfc10_ws, + aud_intfc1_clk, aud_intfc1_data, aud_intfc1_ws, + aud_intfc2_clk, aud_intfc2_data, aud_intfc2_ws, + aud_intfc3_clk, aud_intfc3_data, aud_intfc3_ws, + aud_intfc4_clk, aud_intfc4_data, aud_intfc4_ws, + aud_intfc5_clk, aud_intfc5_data, aud_intfc5_ws, + aud_intfc6_clk, aud_intfc6_data, aud_intfc6_ws, + aud_intfc7_clk, aud_intfc7_data, aud_intfc7_ws, + aud_intfc8_clk, aud_intfc8_data, aud_intfc8_ws, + aud_intfc9_clk, aud_intfc9_data, aud_intfc9_ws, + aud_mclk0_mira, aud_mclk0_mirb, aud_mclk1_mira, aud_mclk1_mirb, + aud_mclk2_mira, aud_mclk2_mirb, aud_refclk0, aud_refclk1, + bist_done, ccu_async_in, ccu_i2c_scl, ccu_i2c_sda, ccu_timer, + clink_debug, dbg_out, dbg_out_clk, + ddr_bist_complete, ddr_bist_fail, ddr_bist_start, ddr_bist_stop, + ddr_pxi, dp_rx0, dp_rx00, dp_rx01, dp_rx0_mute, dp_rx1, dp_rx10, + dp_rx11, dp_rx1_mute, + edp0_hot, edp0_lcd, edp1_hot, edp1_lcd, edp2_hot, edp2_lcd, + edp3_hot, edp3_lcd, + emac0_mcg, emac0_mdc, emac0_mdio, emac0_ptp, emac1_mcg, + emac1_mdc, emac1_mdio, emac1_ptp, + gcc_gp1_clk, gcc_gp2_clk, gcc_gp3_clk, gcc_gp4_clk, gcc_gp5_clk, + gcc_gp6_clk, gcc_gp7_clk, gcc_gp8_clk, jitter_bist, lbist_pass, + mbist_pass, mdp0_vsync_out, mdp1_vsync_out, mdp_vsync_e, + mdp_vsync_p, mdp_vsync_s, + pcie0_clk_req_n, pcie1_clk_req_n, pcie2_clk_req_n, + pcie3_clk_req_n, phase_flag, pll_bist_sync, pll_clk_aux, + prng_rosc0, prng_rosc1, pwrbrk_i_n, qdss, qdss_cti, qspi, + qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5, + qup1_se0, qup1_se1, qup1_se3, qup1_se2, qup1_se4, qup1_se5, + qup1_se6, qup2_se0, qup2_se1, qup2_se2, qup2_se3, qup2_se4, + qup2_se5, qup2_se6, + sailss_ospi, sdc4_clk, sdc4_cmd, sdc4_data, smb_alert, + smb_alert_n, smb_clk, smb_dat, tb_trig_sdc4, tmess_prng0, + tmess_prng1, tsc_timer, tsense_pwm, usb0_hs, + usb0_phy_ps, usb1_hs, usb1_phy_ps, usb2_hs, usxgmii0_phy, + usxgmii1_phy, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@f100000 { + compatible = "qcom,nord-tlmm"; + reg = <0x0f100000 0xc0000>; + interrupts = ; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 181>; + wakeup-parent = <&pdc>; + + qup_uart15_default: qup-uart15-default-state { + pins = "gpio147", "gpio148"; + function = "qup2_se2"; + drive-strength = <2>; + bias-disable; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml index 386c31e9c52b89..b8109e6c2a109d 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,pmic-gpio.yaml @@ -30,6 +30,7 @@ properties: - qcom,pm7550-gpio - qcom,pm7550ba-gpio - qcom,pm8005-gpio + - qcom,pm8010-gpio - qcom,pm8018-gpio - qcom,pm8019-gpio - qcom,pm8038-gpio @@ -134,6 +135,7 @@ allOf: compatible: contains: enum: + - qcom,pm8010-gpio - qcom,pmi8950-gpio - qcom,pmr735d-gpio then: @@ -465,6 +467,7 @@ $defs: - gpio1-gpio10 for pm7325 - gpio1-gpio8 for pm7550ba - gpio1-gpio4 for pm8005 + - gpio1-gpio2 for pm8010 - gpio1-gpio6 for pm8018 - gpio1-gpio12 for pm8038 - gpio1-gpio40 for pm8058 diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml index 4fcac2e55b5542..3b33daedc018a2 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.yaml @@ -42,11 +42,6 @@ patternProperties: $ref: "#/$defs/qcom-sdm845-tlmm-state" additionalProperties: false - "-hog(-[0-9]+)?$": - type: object - required: - - gpio-hog - $defs: qcom-sdm845-tlmm-state: type: object diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml new file mode 100644 index 00000000000000..411c402f9044fa --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,shikra-tlmm.yaml @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,shikra-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Shikra TLMM block + +maintainers: + - Komal Bajaj + +description: | + Top Level Mode Multiplexer pin controller in Qualcomm Shikra SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,shikra-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 83 + + gpio-line-names: + maxItems: 166 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-shikra-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-shikra-tlmm-state" + additionalProperties: false + +$defs: + qcom-shikra-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-5][0-9]|16[0-5])$" + - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data, + sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + + enum: [ gpio, agera_pll, atest_bbrx, atest_char, atest_gpsadc, + atest_tsens, atest_usb, cam_mclk, cci_async, cci_i2c0, + cci_i2c1, cci_timer, char_exec, cri_trng, dac_calib, + dbg_out_clk, ddr_bist, ddr_pxi, dmic, emac_dll, emac_mcg, + emac_phy, emac0_ptp_aux, emac0_ptp_pps, emac1_ptp_aux, + emac1_ptp_pps, ext_mclk, gcc_gp, gsm0_tx, i2s0, i2s1, + i2s2, i2s3, jitter_bist, m_voc, mdp_vsync_e, mdp_vsync_out0, + mdp_vsync_out1, mdp_vsync_p, mdp_vsync_s, mpm_pwr, mss_lte, + nav_gpio, pa_indicator_or, pbs_in, pbs_out, pcie0_clk_req_n, + phase_flag, pll, prng_rosc, pwm, qdss_cti, qup0_se0, + qup0_se1, qup0_se1_01, qup0_se1_23, qup0_se2, qup0_se3_01, + qup0_se3_23, qup0_se4_01, qup0_se4_23, qup0_se5, qup0_se6, + qup0_se7_01, qup0_se7_23, qup0_se8, qup0_se9, qup0_se9_01, + qup0_se9_23, rgmii, sd_write_protect, sdc_cdc, sdc_tb_trig, + ssbi_wtr, swr0_rx, swr0_tx, tgu_ch_trigout, tsc_async, + tsense_pwm, uim1, uim2, unused_adsp, unused_gsm1, usb0_phy_ps, + vfr, vsense_trigger_mirnat, wlan ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + tlmm: pinctrl@500000 { + compatible = "qcom,shikra-tlmm"; + reg = <0x00500000 0x800000>; + + interrupts = ; + + gpio-controller; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + gpio-ranges = <&tlmm 0 0 166>; + + qup-uart0-default-state { + pins = "gpio0", "gpio1"; + function = "qup0_se1"; + drive-strength = <2>; + bias-disable; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml new file mode 100644 index 00000000000000..4903b2d37d89f2 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml @@ -0,0 +1,124 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM6350 SoC LPASS LPI TLMM + +maintainers: + - Luca Weiss + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SM6350 SoC. + +properties: + compatible: + const: qcom,sm6350-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + - description: LPASS LPI MCC registers + + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sm6350-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sm6350-lpass-state" + additionalProperties: false + +$defs: + qcom-sm6350-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|1[0-4])$" + + function: + enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk, + dmic3_data, gpio, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk, + i2s2_data, i2s2_ws, qua_mi2s_data, qua_mi2s_sclk, qua_mi2s_ws, + swr_rx_clk, swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk, + wsa_swr_data ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + + lpass_tlmm: pinctrl@33c0000 { + compatible = "qcom,sm6350-lpass-lpi-pinctrl"; + reg = <0x033c0000 0x20000>, + <0x03550000 0x10000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 15>; + + clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", + "audio"; + + i2s1_active: i2s1-active-state { + clk-pins { + pins = "gpio6"; + function = "i2s1_clk"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + ws-pins { + pins = "gpio7"; + function = "i2s1_ws"; + drive-strength = <8>; + bias-disable; + output-high; + }; + + data-pins { + pins = "gpio8", "gpio9"; + function = "i2s1_data"; + drive-strength = <8>; + bias-disable; + output-high; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml index aae3dcf6cac88a..aec72e8c062141 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,tlmm-common.yaml @@ -51,6 +51,12 @@ properties: should not be accessed by the OS. Please see the ../gpio/gpio.txt for more information. +patternProperties: + "-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + allOf: - $ref: pinctrl.yaml# diff --git a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml index 9562a043707ee2..adc5955a2047c2 100644 --- a/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/realtek,rtd1625-pinctrl.yaml @@ -110,7 +110,7 @@ patternProperties: input-schmitt-disable: true - input-voltage-microvolt: + input-threshold-voltage-microvolt: description: | Select the input receiver voltage domain for the pin. Valid arguments are: diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml index 00c05243b9a473..fb1fe1ea759fc6 100644 --- a/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml @@ -26,6 +26,7 @@ properties: - renesas,r9a07g043-pinctrl # RZ/G2UL{Type-1,Type-2} and RZ/Five - renesas,r9a07g044-pinctrl # RZ/G2{L,LC} - renesas,r9a08g045-pinctrl # RZ/G3S + - renesas,r9a08g046-pinctrl # RZ/G3L - renesas,r9a09g047-pinctrl # RZ/G3E - renesas,r9a09g056-pinctrl # RZ/V2N - renesas,r9a09g057-pinctrl # RZ/V2H(P) @@ -78,6 +79,26 @@ properties: - description: PFC main reset - description: Reset for the control register related to WDTUDFCA and WDTUDFFCM pins + reset-names: + oneOf: + - items: + - const: rstn + - const: port + - const: spare + - items: + - const: main + - const: error + + renesas,clonech: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to system controller + - description: offset of clone channel control register + description: + Phandle and offset to the system controller containing the clone channel + control values. + additionalProperties: anyOf: - type: object @@ -140,6 +161,15 @@ additionalProperties: allOf: - $ref: pinctrl.yaml# + - if: + properties: + compatible: + contains: + const: renesas,r9a08g046-pinctrl + then: + required: + - renesas,clonech + - if: properties: compatible: @@ -152,10 +182,14 @@ allOf: properties: resets: maxItems: 2 + reset-names: + maxItems: 2 else: properties: resets: minItems: 3 + reset-names: + minItems: 3 required: - compatible @@ -187,6 +221,7 @@ examples: resets = <&cpg R9A07G044_GPIO_RSTN>, <&cpg R9A07G044_GPIO_PORT_RESETN>, <&cpg R9A07G044_GPIO_SPARE_RESETN>; + reset-names = "rstn", "port", "spare"; power-domains = <&cpg>; scif0_pins: serial0 { diff --git a/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml new file mode 100644 index 00000000000000..c2332e6e60c25b --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/ultrarisc,dp1000-pinctrl.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/ultrarisc,dp1000-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: UltraRISC DP1000 Pin Controller + +maintainers: + - Jia Wang + +description: | + UltraRISC RISC-V SoC DP1000 pin controller. + The controller manages ports A, B, C, D and LPC. Ports A-D default to + GPIO and provide additional SPI, UART, I2C, and PWM mux functions. + LPC pins default to the LPC interface and can be muxed to eSPI. + All pins also support pin configuration, including drive strength, + pull-up, and pull-down settings. + +properties: + compatible: + const: ultrarisc,dp1000-pinctrl + + reg: + items: + - description: pin controller registers + +required: + - compatible + - reg + +patternProperties: + '.*-pins$': + type: object + unevaluatedProperties: false + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + - if: + properties: + pins: + items: + minimum: 40 + maximum: 52 + then: + properties: + function: + enum: + - lpc + - espi + else: + properties: + pins: + items: + maximum: 39 + function: + enum: + - gpio + - i2c + - pwm + - spi + - uart + + properties: + pins: + description: | + List of pins affected by this state node, using numeric pin IDs. + Pins 0-39 correspond to ports A-D, and pins 40-52 correspond + to LPC0-LPC12. + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + uniqueItems: true + items: + minimum: 0 + maximum: 52 + + function: + description: | + Mux function to select for the listed pins. Supported functions + depend on the selected pins and match the DP1000 hardware mux + table. + enum: + - gpio + - i2c + - pwm + - spi + - uart + - lpc + - espi + + bias-disable: true + bias-high-impedance: true + bias-pull-up: true + bias-pull-down: true + + drive-strength: + description: Output drive strength in mA. + enum: [20, 27, 33, 40] + + required: + - pins + - function + +unevaluatedProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pinctrl@11081000 { + compatible = "ultrarisc,dp1000-pinctrl"; + reg = <0x0 0x11081000 0x0 0x1000>; + + i2c0-pins { + pins = <12 13>; + function = "i2c"; + bias-pull-up; + drive-strength = <33>; + }; + + uart0-pins { + pins = <8 9>; + function = "uart"; + bias-pull-up; + drive-strength = <33>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml index caf15188099921..c9be097cfba0e4 100644 --- a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -43,7 +43,9 @@ properties: - apple,t6000-pmgr-pwrstate - const: apple,pmgr-pwrstate - items: - - const: apple,t6020-pmgr-pwrstate + - enum: + - apple,t6020-pmgr-pwrstate + - apple,t8122-pmgr-pwrstate - const: apple,t8103-pmgr-pwrstate reg: diff --git a/Documentation/devicetree/bindings/power/power-domain.yaml b/Documentation/devicetree/bindings/power/power-domain.yaml index b1147dbf2e7385..163b0af158fd2b 100644 --- a/Documentation/devicetree/bindings/power/power-domain.yaml +++ b/Documentation/devicetree/bindings/power/power-domain.yaml @@ -68,6 +68,21 @@ properties: by the given provider should be subdomains of the domain specified by this binding. + power-domains-child-ids: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + An array of child domain IDs that correspond to the power-domains + property. This property is only applicable to power domain providers + with "#power-domain-cells" > 0 (i.e., providers that supply multiple + power domains). It specifies which of the provider's child domains + should be associated with each parent domain listed in the power-domains + property. The number of elements in this array must match the number of + phandles in the power-domains property. Each element specifies the child + domain ID (index) that should be made a child domain of the corresponding + parent domain. This enables hierarchical power domain structures where + different child domains from the same provider can have different + parent domains. + required: - "#power-domain-cells" @@ -133,3 +148,22 @@ examples: min-residency-us = <7000>; }; }; + + - | + // Example: SCMI domain 15 -> MAIN_PD, SCMI domain 19 -> WKUP_PD + MAIN_PD: power-controller-main { + compatible = "foo,power-controller"; + #power-domain-cells = <0>; + }; + + WKUP_PD: power-controller-wkup { + compatible = "foo,power-controller"; + #power-domain-cells = <0>; + }; + + scmi_pds: power-controller-scmi { + compatible = "foo,power-controller"; + #power-domain-cells = <1>; + power-domains = <&MAIN_PD>, <&WKUP_PD>; + power-domains-child-ids = <15>, <19>; + }; diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 0bf1e13a99646c..0744a867c79eb2 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -35,6 +35,7 @@ properties: - qcom,msm8994-rpmpd - qcom,msm8996-rpmpd - qcom,msm8998-rpmpd + - qcom,nord-rpmhpd - qcom,qcm2290-rpmpd - qcom,qcs404-rpmpd - qcom,qcs615-rpmhpd @@ -55,6 +56,7 @@ properties: - qcom,sdx55-rpmhpd - qcom,sdx65-rpmhpd - qcom,sdx75-rpmhpd + - qcom,shikra-rpmpd - qcom,sm4450-rpmhpd - qcom,sm6115-rpmpd - qcom,sm6125-rpmpd diff --git a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml index d8f4f9ffe88421..25ef04b60ca17a 100644 --- a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml +++ b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml @@ -18,6 +18,7 @@ properties: - enum: - apple,t8103-fpwm - apple,t8112-fpwm + - apple,t8122-fpwm - apple,t6000-fpwm - apple,t6020-fpwm - const: apple,s5l-fpwm diff --git a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml index 8df327e5281075..f1422a401b6ba7 100644 --- a/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/marvell,pxa-pwm.yaml @@ -15,7 +15,9 @@ allOf: properties: compatible: contains: - const: spacemit,k1-pwm + enum: + - spacemit,k1-pwm + - spacemit,k3-pwm then: properties: "#pwm-cells": @@ -26,6 +28,26 @@ allOf: const: 1 description: | Used for specifying the period length in nanoseconds. + - if: + properties: + compatible: + contains: + enum: + - spacemit,k3-pwm + then: + required: + - clock-names + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 properties: compatible: @@ -36,7 +58,9 @@ properties: - marvell,pxa168-pwm - marvell,pxa910-pwm - items: - - const: spacemit,k1-pwm + - enum: + - spacemit,k1-pwm + - spacemit,k3-pwm - const: marvell,pxa910-pwm reg: @@ -47,7 +71,18 @@ properties: description: Number of cells in a pwm specifier. clocks: - maxItems: 1 + minItems: 1 + items: + - description: The function clock + - description: An optional bus clock + + clock-names: + minItems: 1 + maxItems: 2 + oneOf: + - items: + - const: func + - const: bus resets: maxItems: 1 diff --git a/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml new file mode 100644 index 00000000000000..f9f1f652e7527b --- /dev/null +++ b/Documentation/devicetree/bindings/pwm/qcom,ipq6018-pwm.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pwm/qcom,ipq6018-pwm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ6018 PWM controller + +maintainers: + - George Moussalem + +properties: + compatible: + oneOf: + - items: + - enum: + - qcom,ipq5018-pwm + - qcom,ipq5332-pwm + - qcom,ipq9574-pwm + - const: qcom,ipq6018-pwm + - const: qcom,ipq6018-pwm + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + "#pwm-cells": + const: 3 + +required: + - compatible + - reg + - clocks + - "#pwm-cells" + +additionalProperties: false + +examples: + - | + #include + + pwm: pwm@1941010 { + compatible = "qcom,ipq6018-pwm"; + reg = <0x01941010 0x20>; + clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clocks = <&gcc GCC_ADSS_PWM_CLK>; + assigned-clock-rates = <100000000>; + #pwm-cells = <3>; + }; diff --git a/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt b/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt deleted file mode 100644 index f401316e0248b6..00000000000000 --- a/Documentation/devicetree/bindings/pwm/st,stmpe-pwm.txt +++ /dev/null @@ -1,18 +0,0 @@ -== ST STMPE PWM controller == - -This is a PWM block embedded in the ST Microelectronics STMPE -(ST Multi-Purpose Expander) chips. The PWM is registered as a -subdevices of the STMPE MFD device. - -Required properties: -- compatible: should be: - - "st,stmpe-pwm" -- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of - the cells format. - -Example: - -pwm0: pwm { - compatible = "st,stmpe-pwm"; - #pwm-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6311-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6311-regulator.yaml new file mode 100644 index 00000000000000..f65ee2c90298f1 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6311-regulator.yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/mediatek,mt6311-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT6311 Regulator + +maintainers: + - AngeloGioacchino Del Regno + +description: + The MediaTek MT6311 is an I2C power management IC that provides one step-down + converter and one low-dropout regulator. The regulators are named VDVFS and + VBIASN, respectively. + +properties: + compatible: + const: mediatek,mt6311-regulator + + reg: + description: I2C slave address. + maxItems: 1 + + regulators: + type: object + description: List of regulators provided by this controller. + + patternProperties: + "^(VDVFS|VBIASN)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - regulators + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@6b { + compatible = "mediatek,mt6311-regulator"; + reg = <0x6b>; + + regulators { + VDVFS { + regulator-name = "VDVFS"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1400000>; + regulator-ramp-delay = <10000>; + }; + + VBIASN { + regulator-name = "VBIASN"; + regulator-min-microvolt = <200000>; + regulator-max-microvolt = <800000>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/regulator/mt6311-regulator.txt b/Documentation/devicetree/bindings/regulator/mt6311-regulator.txt deleted file mode 100644 index 84d544d8c1b142..00000000000000 --- a/Documentation/devicetree/bindings/regulator/mt6311-regulator.txt +++ /dev/null @@ -1,35 +0,0 @@ -Mediatek MT6311 Regulator - -Required properties: -- compatible: "mediatek,mt6311-regulator" -- reg: I2C slave address, usually 0x6b. -- regulators: List of regulators provided by this controller. It is named - to VDVFS and VBIASN. - The definition for each of these nodes is defined using the standard binding - for regulators at Documentation/devicetree/bindings/regulator/regulator.txt. - -The valid names for regulators are: -BUCK: - VDVFS -LDO: - VBIASN - -Example: - mt6311: pmic@6b { - compatible = "mediatek,mt6311-regulator"; - reg = <0x6b>; - - regulators { - mt6311_vcpu_reg: VDVFS { - regulator-name = "VDVFS"; - regulator-min-microvolt = < 600000>; - regulator-max-microvolt = <1400000>; - regulator-ramp-delay = <10000>; - }; - mt6311_ldo_reg: VBIASN { - regulator-name = "VBIASN"; - regulator-min-microvolt = <200000>; - regulator-max-microvolt = <800000>; - }; - }; - }; diff --git a/Documentation/devicetree/bindings/regulator/mt6359-regulator.yaml b/Documentation/devicetree/bindings/regulator/mt6359-regulator.yaml index fe4ac9350ba035..e3c20412c8a734 100644 --- a/Documentation/devicetree/bindings/regulator/mt6359-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/mt6359-regulator.yaml @@ -18,84 +18,50 @@ patternProperties: "^buck_v(s1|gpu11|modem|pu|core|s2|pa|proc2|proc1|core_sshub)$": type: object $ref: regulator.yaml# - - properties: - regulator-name: - pattern: "^v(s1|gpu11|modem|pu|core|s2|pa|proc2|proc1|core_sshub)$" - unevaluatedProperties: false "^ldo_v(ibr|rf12|usb|camio|efuse|xo22)$": type: object $ref: regulator.yaml# - - properties: - regulator-name: - pattern: "^v(ibr|rf12|usb|camio|efuse|xo22)$" - unevaluatedProperties: false "^ldo_v(rfck|emc|a12|a09|ufs|bbck)$": type: object $ref: regulator.yaml# - - properties: - regulator-name: - pattern: "^v(rfck|emc|a12|a09|ufs|bbck)$" - unevaluatedProperties: false - "^ldo_vcn(18|13|33_1_bt|13_1_wifi|33_2_bt|33_2_wifi)$": + "^ldo_vcn(18|13|33_[12])$": type: object $ref: regulator.yaml# - - properties: - regulator-name: - pattern: "^vcn(18|13|33_1_bt|13_1_wifi|33_2_bt|33_2_wifi)$" - unevaluatedProperties: false "^ldo_vsram_(proc2|others|md|proc1|others_sshub)$": type: object $ref: regulator.yaml# - - properties: - regulator-name: - pattern: "^vsram_(proc2|others|md|proc1|others_sshub)$" - unevaluatedProperties: false "^ldo_v(fe|bif|io)28$": type: object $ref: regulator.yaml# - - properties: - regulator-name: - pattern: "^v(fe|bif|io)28$" - unevaluatedProperties: false "^ldo_v(aud|io|aux|rf|m)18$": type: object $ref: regulator.yaml# - - properties: - regulator-name: - pattern: "^v(aud|io|aux|rf|m)18$" - unevaluatedProperties: false "^ldo_vsim[12]$": type: object $ref: regulator.yaml# + unevaluatedProperties: false - properties: - regulator-name: - pattern: "^vsim[12]$" - - required: - - regulator-name - + "^ldo_vcn33_[12]_(bt|wifi)$": + type: object + $ref: regulator.yaml# + description: + vcn33_[12]_(bt|wifi) are incorrect representations. + Use vcn33_[12] instead. + deprecated: true unevaluatedProperties: false additionalProperties: false @@ -246,13 +212,8 @@ examples: regulator-min-microvolt = <900000>; regulator-max-microvolt = <1300000>; }; - mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1_bt { - regulator-name = "vcn33_1_bt"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3500000>; - }; - mt6359_vcn33_1_wifi_ldo_reg: ldo_vcn33_1_wifi { - regulator-name = "vcn33_1_wifi"; + mt6359_vcn33_1_bt_ldo_reg: ldo_vcn33_1 { + regulator-name = "vcn33_1"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3500000>; }; @@ -313,13 +274,8 @@ examples: regulator-min-microvolt = <2500000>; regulator-max-microvolt = <3300000>; }; - mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2_bt { - regulator-name = "vcn33_2_bt"; - regulator-min-microvolt = <2800000>; - regulator-max-microvolt = <3500000>; - }; - mt6359_vcn33_2_wifi_ldo_reg: ldo_vcn33_2_wifi { - regulator-name = "vcn33_2_wifi"; + mt6359_vcn33_2_bt_ldo_reg: ldo_vcn33_2 { + regulator-name = "vcn33_2"; regulator-min-microvolt = <2800000>; regulator-max-microvolt = <3500000>; }; diff --git a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml index 9c879bc3c360f9..cbb74e8e875ded 100644 --- a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml @@ -17,6 +17,10 @@ properties: compatible: const: mediatek,mt6360-regulator + BUCK1_VIN-supply: + description: Input supply phandle(s) for BUCK1 + BUCK2_VIN-supply: + description: Input supply phandle(s) for BUCK2 LDO_VIN1-supply: description: Input supply phandle(s) for LDO1/2/3 LDO_VIN2-supply: diff --git a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml index 58bb0ad5dda44e..d93594304651cf 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,rpmh-regulator.yaml @@ -51,6 +51,7 @@ description: | For PM8450, smps1 - smps6, ldo1 - ldo4 For PM8550, smps1 - smps6, ldo1 - ldo17, bob1 - bob2 For PM8998, smps1 - smps13, ldo1 - ldo28, lvs1 - lvs2 + For PMAU0102, smps1 - smps8, ldo1 - ldo3 For PMH0101, ldo1 - ldo18, bob1 - bob2 For PMH0104, smps1 - smps4 For PMH0110, smps1 - smps10, ldo1 - ldo4 @@ -87,6 +88,7 @@ properties: - qcom,pm8550ve-rpmh-regulators - qcom,pm8550vs-rpmh-regulators - qcom,pm8998-rpmh-regulators + - qcom,pmau0102-rpmh-regulators - qcom,pmc8180-rpmh-regulators - qcom,pmc8180c-rpmh-regulators - qcom,pmc8380-rpmh-regulators @@ -417,6 +419,7 @@ allOf: properties: compatible: enum: + - qcom,pmau0102-rpmh-regulators - qcom,pmc8380-rpmh-regulators - qcom,pm8550ve-rpmh-regulators then: diff --git a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml index b7241ce975b961..0d8bc9bf996acd 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,smd-rpm-regulator.yaml @@ -35,6 +35,12 @@ description: For pm660l s1, s2, s3, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, bob + For pm8019, s1, s2, s3, s4, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, + l12, l13, l14 + + For pm8150, s1, s2, s3, s4, s5, s6, s7, s8, s9, s10, l1, l2, l3, l4, l5, l6, + l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18 + For pm8226, s1, s2, s3, s4, s5, l1, l2, l3, l4, l5, l6, l7, l8, l9, l10, l11, l12, l13, l14, l15, l16, l17, l18, l19, l20, l21, l22, l23, l24, l25, l26, l27, l28, lvs1 @@ -91,6 +97,8 @@ properties: - qcom,rpm-pm6125-regulators - qcom,rpm-pm660-regulators - qcom,rpm-pm660l-regulators + - qcom,rpm-pm8019-regulators + - qcom,rpm-pm8150-regulators - qcom,rpm-pm8226-regulators - qcom,rpm-pm8841-regulators - qcom,rpm-pm8909-regulators diff --git a/Documentation/devicetree/bindings/regulator/sgmicro,sgm3804.yaml b/Documentation/devicetree/bindings/regulator/sgmicro,sgm3804.yaml new file mode 100644 index 00000000000000..3716eaf81aa993 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/sgmicro,sgm3804.yaml @@ -0,0 +1,77 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/sgmicro,sgm3804.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SG Micro SGM3804 Single Inductor Dual Output Buck/Boost Converter + +maintainers: + - Neil Armstrong + +description: + The SGM3804 is a dual voltage regulator, designed to support positive/negative + supply for driving LCD panels. It support software-configurable output + switching. The output voltages can be programmed via an I2C compatible interface. + +properties: + compatible: + const: sgmicro,sgm3804 + + reg: + maxItems: 1 + + vin-supply: true + +patternProperties: + "^(pos|neg)$": + type: object + $ref: regulator.yaml# + + properties: + enable-gpios: true + + unevaluatedProperties: false + + required: + - enable-gpios + +required: + - compatible + - reg + - pos + - neg + +additionalProperties: false + +examples: + - | + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@3e { + compatible = "sgmicro,sgm3804"; + reg = <0x3e>; + + vin-supply = <&vin_reg>; + + pos { + regulator-name = "outpos"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-gpios = <&gpio 17 GPIO_ACTIVE_HIGH>; + }; + + neg { + regulator-name = "outneg"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-gpios = <&gpio 18 GPIO_ACTIVE_HIGH>; + }; + }; + }; +... + diff --git a/Documentation/devicetree/bindings/regulator/sprd,sc2730-regulator.yaml b/Documentation/devicetree/bindings/regulator/sprd,sc2730-regulator.yaml new file mode 100644 index 00000000000000..ab945c46b08e06 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/sprd,sc2730-regulator.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/sprd,sc2730-regulator.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Unisoc SC2730 Power Management IC regulators + +maintainers: + - Otto Pflüger + +patternProperties: + "^dcdc-(core|cpu|gen[0-1]|gpu|mem|memq|modem|sram)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^ldo-avdd(12|18)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^ldo-vdd(18-dcxo|28)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^ldo-vdd(emmccore|kpled|ldo[0-2]|sd(core|io)|sim[0-2]|usb33|wcn|wifipa)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^ldo-vddcam(a0|a1|d0|d1|io|mot)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^ldo-vddrf(1v25|18)$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + +additionalProperties: false +... diff --git a/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml b/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml index 76e8ca44906ac2..3f710433e9377b 100644 --- a/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/amlogic,meson-mx-ao-arc.yaml @@ -48,12 +48,7 @@ properties: minItems: 1 sram: - $ref: /schemas/types.yaml#/definitions/phandle - description: - phandles to a reserved SRAM region which is used as the memory of - the ARC core. The region should be defined as child nodes of the - AHB SRAM node as per the generic bindings in - Documentation/devicetree/bindings/sram/sram.yaml + maxItems: 1 amlogic,secbus2: $ref: /schemas/types.yaml#/definitions/phandle diff --git a/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml index ce8ec0119469c8..c18f71b648890d 100644 --- a/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/fsl,imx-rproc.yaml @@ -28,6 +28,9 @@ properties: - fsl,imx8qxp-cm4 - fsl,imx8ulp-cm33 - fsl,imx93-cm33 + - fsl,imx94-cm33s + - fsl,imx94-cm70 + - fsl,imx94-cm71 - fsl,imx95-cm7 clocks: diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml index faf2712e3d2722..4049157dd83d72 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,msm8916-mss-pil.yaml @@ -108,6 +108,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: Names of the states used by the AP to signal the Hexagon core diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml index 1b65813cc8adf5..4a1b439f985e3d 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,msm8996-mss-pil.yaml @@ -101,6 +101,13 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop modem + items: + - description: Phandle to the Shared Memory Point 2 Point or Shared + Memory Manager device handling the communication with a remote + processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: Names of the states used by the AP to signal the Hexagon core diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml index 68c17bf18987c4..4607b459131b4f 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,pas-common.yaml @@ -60,6 +60,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml index bca59394aef492..e5f5f92987e1dd 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,qcs404-cdsp-pil.yaml @@ -92,6 +92,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml index 540bdfca53d97d..823304afaa98f8 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,rpm-proc.yaml @@ -87,6 +87,7 @@ properties: - qcom,qcm2290-rpm-proc - qcom,qcs404-rpm-proc - qcom,sdm660-rpm-proc + - qcom,shikra-rpm-proc - qcom,sm6115-rpm-proc - qcom,sm6125-rpm-proc - qcom,sm6375-rpm-proc diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml index 7c9accac92d08c..21c82cd3be037e 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7180-mss-pil.yaml @@ -133,6 +133,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml index 94ca7a0cc203fb..23b8e3079f3b1b 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-adsp-pil.yaml @@ -91,6 +91,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml index f349c303fa07e4..43dfb90ac18d41 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-mss-pil.yaml @@ -147,6 +147,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml index f4118b2da5f655..f3f3432948edc9 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sc7280-wpss-pil.yaml @@ -104,6 +104,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sdm845-adsp-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sdm845-adsp-pil.yaml index a3c74871457fc5..9666ebf1e7b6bf 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sdm845-adsp-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sdm845-adsp-pil.yaml @@ -92,6 +92,12 @@ properties: description: States used by the AP to signal the Hexagon core items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,shikra-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,shikra-pas.yaml new file mode 100644 index 00000000000000..253b14eb2b598f --- /dev/null +++ b/Documentation/devicetree/bindings/remoteproc/qcom,shikra-pas.yaml @@ -0,0 +1,167 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/remoteproc/qcom,shikra-pas.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Shikra SoC Peripheral Authentication Service + +maintainers: + - Bibek Kumar Patro + - Komal Bajaj + +description: + Qualcomm Shikra SoC Peripheral Authentication Service loads and boots + firmware on the Qualcomm DSP Hexagon cores. + +properties: + compatible: + enum: + - qcom,shikra-cdsp-pas + - qcom,shikra-lpaicp-pas + - qcom,shikra-mpss-pas + + reg: + maxItems: 1 + + clocks: + items: + - description: XO clock + + clock-names: + items: + - const: xo + + memory-region: + minItems: 1 + maxItems: 2 + + smd-edge: false + + firmware-name: + minItems: 1 + items: + - description: Firmware name of the Hexagon core + - description: Firmware name of the Hexagon Devicetree + + glink-edge: + $ref: /schemas/remoteproc/qcom,glink-edge.yaml# + description: + Qualcomm G-Link subnode which represents communication edge, channels + and devices related to the remoteproc core. + unevaluatedProperties: false + + qcom,smem-states: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: States used by the AP to signal the Hexagon core + items: + - description: Stop the remote processor + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 + + qcom,smem-state-names: + description: The names of the state bits used for SMP2P output + items: + - const: stop + +required: + - compatible + - reg + - memory-region + +allOf: + - $ref: /schemas/remoteproc/qcom,pas-common.yaml# + + - if: + properties: + compatible: + enum: + - qcom,shikra-cdsp-pas + - qcom,shikra-mpss-pas + then: + properties: + interrupts: + minItems: 6 + interrupt-names: + minItems: 6 + memory-region: + maxItems: 1 + firmware-name: + maxItems: 1 + power-domains: + items: + - description: CX power domain + power-domain-names: + items: + - const: cx + + - if: + properties: + compatible: + enum: + - qcom,shikra-lpaicp-pas + then: + properties: + interrupts: + maxItems: 5 + interrupt-names: + maxItems: 5 + memory-region: + minItems: 2 + firmware-name: + minItems: 2 + power-domains: false + power-domain-names: false + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + #include + + remoteproc@b300000 { + compatible = "qcom,shikra-cdsp-pas"; + reg = <0x0b300000 0x100000>; + + interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, + <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "wdog", "fatal", "ready", + "handover", "stop-ack", "shutdown-ack"; + + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo"; + + interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG + &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>; + + power-domains = <&rpmpd RPMHPD_CX>; + power-domain-names = "cx"; + + memory-region = <&cdsp_mem>; + + qcom,smem-states = <&cdsp_smp2p_out 0>; + qcom,smem-state-names = "stop"; + + firmware-name = "qcom/shikra/cdsp.mbn"; + + glink-edge { + interrupts = ; + mboxes = <&apcs_glb 4>; + qcom,remote-pid = <5>; + label = "cdsp"; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml index 1e4db0c9fcf9fc..9f30a38152a387 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,sm8550-pas.yaml @@ -30,12 +30,14 @@ properties: - items: - enum: - qcom,glymur-adsp-pas + - qcom,hawi-adsp-pas - qcom,kaanapali-adsp-pas - qcom,sm8750-adsp-pas - const: qcom,sm8550-adsp-pas - items: - enum: - qcom,glymur-cdsp-pas + - qcom,hawi-cdsp-pas - qcom,kaanapali-cdsp-pas - const: qcom,sm8550-cdsp-pas - items: @@ -104,6 +106,8 @@ allOf: enum: - qcom,glymur-adsp-pas - qcom,glymur-cdsp-pas + - qcom,hawi-adsp-pas + - qcom,hawi-cdsp-pas - qcom,kaanapali-adsp-pas - qcom,kaanapali-cdsp-pas - qcom,sm8750-adsp-pas diff --git a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml index 117fb4d0c4ad2a..a55e55f5f01455 100644 --- a/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml +++ b/Documentation/devicetree/bindings/remoteproc/qcom,wcnss-pil.yaml @@ -84,6 +84,12 @@ properties: States used by the AP to signal the WCNSS core that it should shutdown items: - description: Stop the modem + items: + - description: Phandle to the Shared Memory Point 2 Point device + handling the communication with a remote processor + - description: Single bit index to toggle in the value sent to + the remote processor + maximum: 32 qcom,smem-state-names: description: The names of the state bits used for SMP2P output diff --git a/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml index b51bb863d759e7..8b1ed384ef22e4 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/ti,k3-dsp-rproc.yaml @@ -75,16 +75,8 @@ properties: # -------------------- sram: - $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 maxItems: 4 - items: - maxItems: 1 - description: | - phandles to one or more reserved on-chip SRAM regions. The regions - should be defined as child nodes of the respective SRAM node, and - should be defined as per the generic bindings in, - Documentation/devicetree/bindings/sram/sram.yaml allOf: - if: diff --git a/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml b/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml index 775e9b3a193878..14e6b2f817b319 100644 --- a/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml +++ b/Documentation/devicetree/bindings/remoteproc/ti,k3-r5f-rproc.yaml @@ -224,16 +224,8 @@ patternProperties: at 0x0) or 0 (BTCM at 0x0), default value is 1 if omitted. sram: - $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 maxItems: 4 - items: - maxItems: 1 - description: | - phandles to one or more reserved on-chip SRAM regions. The regions - should be defined as child nodes of the respective SRAM node, and - should be defined as per the generic bindings in, - Documentation/devicetree/bindings/sram/sram.yaml required: - compatible diff --git a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml index ee63c03949c93f..5ab19d70a34400 100644 --- a/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml +++ b/Documentation/devicetree/bindings/remoteproc/xlnx,zynqmp-r5fss.yaml @@ -106,20 +106,13 @@ patternProperties: - const: rx sram: - $ref: /schemas/types.yaml#/definitions/phandle-array minItems: 1 maxItems: 8 - items: - maxItems: 1 - description: | + description: phandles to one or more reserved on-chip SRAM regions. Other than TCM, the RPU can execute instructions and access data from the OCM memory, the main DDR memory, and other system memories. - The regions should be defined as child nodes of the respective SRAM - node, and should be defined as per the generic bindings in - Documentation/devicetree/bindings/sram/sram.yaml - memory-region: description: | List of phandles to the reserved memory regions associated with the @@ -135,6 +128,10 @@ patternProperties: - description: vring1 additionalItems: true + firmware-name: + maxItems: 1 + description: default firmware to load + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml b/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml new file mode 100644 index 00000000000000..4362bc058df419 --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/intel,wakeup-mailbox.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/intel,wakeup-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Wakeup Mailbox for Intel processors + +description: | + The Wakeup Mailbox provides a mechanism for the operating system to wake up + secondary CPUs on Intel processors. It is an alternative to the INIT-!INIT- + SIPI sequence used on most x86 systems. + + The structure and operation of the mailbox is described in the Multiprocessor + Wakeup Structure of the ACPI specification version 6.6 section 5.2.12.19 [1]. + + The implementation of the mailbox in platform firmware is described in the + Intel TDX Virtual Firmware Design Guide section 4.3.5 [2]. + + 1: https://uefi.org/specs/ACPI/6.6/05_ACPI_Software_Programming_Model.html#multiprocessor-wakeup-structure + 2: https://www.intel.com/content/www/us/en/content-details/733585/intel-tdx-virtual-firmware-design-guide.html + +maintainers: + - Ricardo Neri + +allOf: + - $ref: reserved-memory.yaml + +properties: + compatible: + const: intel,wakeup-mailbox + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <1>; + + wakeup-mailbox@ffff0000 { + compatible = "intel,wakeup-mailbox"; + reg = <0x0 0xffff0000 0x1000>; + }; + }; diff --git a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml index 4380f622f9a914..6efadc5f807859 100644 --- a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml +++ b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml @@ -7,7 +7,8 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Tegra CPU-NS - BPMP IPC reserved memory maintainers: - - Peter De Schrijver + - Thierry Reding + - Jonathan Hunter description: | Define a memory region used for communication between CPU-NS and BPMP. diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 2b0a8a93bb2144..5ffc40d599c022 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -457,6 +457,13 @@ properties: merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed of zc.adoc to src tree."). + - const: zclsd + description: + The Zclsd extension implements the compressed (16-bit) version of the + Load/Store Pair for RV32. As with Zilsd, this extension was ratified + in commit f88abf1 ("Integrating load/store pair for RV32 with the + main manual") of riscv-isa-manual. + - const: zcmop description: The standard Zcmop extension version 1.0, as ratified in commit @@ -487,6 +494,22 @@ properties: in commit 64074bc ("Update version numbers for Zfh/Zfinx") of riscv-isa-manual. + - const: zicbom + description: + The standard Zicbom extension for base cache management operations as + ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + + - const: zicbop + description: + The standard Zicbop extension for cache-block prefetch instructions + as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of + riscv-CMOs. + + - const: zicboz + description: + The standard Zicboz extension for cache-block zeroing as ratified + in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. + - const: ziccamoa description: The standard Ziccamoa extension for main memory (cacheability and @@ -514,6 +537,66 @@ properties: guarantee on LR/SC sequences, as ratified in commit b1d806605f87 ("Updated to ratified state.") of the riscv profiles specification. + - const: zicfilp + description: | + The standard Zicfilp extension for enforcing forward edge + control-flow integrity as ratified in commit 3f8e450 ("merge + pull request #227 from ved-rivos/0709") of riscv-cfi + github repo. + + - const: zicfiss + description: | + The standard Zicfiss extension for enforcing backward edge + control-flow integrity as ratified in commit 3f8e450 ("merge + pull request #227 from ved-rivos/0709") of riscv-cfi + github repo. + + - const: zicntr + description: + The standard Zicntr extension for base counters and timers, as + ratified in the 20191213 version of the unprivileged ISA + specification. + + - const: zicond + description: + The standard Zicond extension for conditional arithmetic and + conditional-select/move operations as ratified in commit 95cf1f9 + ("Add changes requested by Ved during signoff") of riscv-zicond. + + - const: zicsr + description: | + The standard Zicsr extension for control and status register + instructions, as ratified in the 20191213 version of the + unprivileged ISA specification. + + This does not include Chapter 10, "Counters", which documents + special case read-only CSRs, that were moved into the Zicntr and + Zihpm extensions after the ratification of the 20191213 version of + the unprivileged specification. + + - const: zifencei + description: + The standard Zifencei extension for instruction-fetch fence, as + ratified in the 20191213 version of the unprivileged ISA + specification. + + - const: zihintntl + description: + The standard Zihintntl extension for non-temporal locality hints, as + ratified in commit 0dc91f5 ("Zihintntl is ratified") of the + riscv-isa-manual. + + - const: zihintpause + description: + The standard Zihintpause extension for pause hints, as ratified in + commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. + + - const: zihpm + description: + The standard Zihpm extension for hardware performance counters, as + ratified in the 20191213 version of the unprivileged ISA + specification. + - const: zilsd description: The standard Zilsd extension which provides support for aligned @@ -521,12 +604,10 @@ properties: encodings, as ratified in commit f88abf1 ("Integrating load/store pair for RV32 with the main manual") of riscv-isa-manual. - - const: zclsd + - const: zimop description: - The Zclsd extension implements the compressed (16-bit) version of the - Load/Store Pair for RV32. As with Zilsd, this extension was ratified - in commit f88abf1 ("Integrating load/store pair for RV32 with the - main manual") of riscv-isa-manual. + The standard Zimop extension version 1.0, as ratified in commit + 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. - const: zk description: @@ -590,87 +671,6 @@ properties: in version 1.0 of RISC-V Cryptography Extensions Volume I specification. - - const: zicbom - description: - The standard Zicbom extension for base cache management operations as - ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. - - - const: zicbop - description: - The standard Zicbop extension for cache-block prefetch instructions - as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of - riscv-CMOs. - - - const: zicboz - description: - The standard Zicboz extension for cache-block zeroing as ratified - in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs. - - - const: zicfilp - description: | - The standard Zicfilp extension for enforcing forward edge - control-flow integrity as ratified in commit 3f8e450 ("merge - pull request #227 from ved-rivos/0709") of riscv-cfi - github repo. - - - const: zicfiss - description: | - The standard Zicfiss extension for enforcing backward edge - control-flow integrity as ratified in commit 3f8e450 ("merge - pull request #227 from ved-rivos/0709") of riscv-cfi - github repo. - - - const: zicntr - description: - The standard Zicntr extension for base counters and timers, as - ratified in the 20191213 version of the unprivileged ISA - specification. - - - const: zicond - description: - The standard Zicond extension for conditional arithmetic and - conditional-select/move operations as ratified in commit 95cf1f9 - ("Add changes requested by Ved during signoff") of riscv-zicond. - - - const: zicsr - description: | - The standard Zicsr extension for control and status register - instructions, as ratified in the 20191213 version of the - unprivileged ISA specification. - - This does not include Chapter 10, "Counters", which documents - special case read-only CSRs, that were moved into the Zicntr and - Zihpm extensions after the ratification of the 20191213 version of - the unprivileged specification. - - - const: zifencei - description: - The standard Zifencei extension for instruction-fetch fence, as - ratified in the 20191213 version of the unprivileged ISA - specification. - - - const: zihintpause - description: - The standard Zihintpause extension for pause hints, as ratified in - commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual. - - - const: zihintntl - description: - The standard Zihintntl extension for non-temporal locality hints, as - ratified in commit 0dc91f5 ("Zihintntl is ratified") of the - riscv-isa-manual. - - - const: zihpm - description: - The standard Zihpm extension for hardware performance counters, as - ratified in the 20191213 version of the unprivileged ISA - specification. - - - const: zimop - description: - The standard Zimop extension version 1.0, as ratified in commit - 58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual. - - const: ztso description: The standard Ztso extension for total store ordering, as ratified @@ -809,18 +809,18 @@ properties: instructions, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. - - const: zvksh - description: | - The standard Zvksh extension for ShangMi suite: SM3 secure hash - instructions, as ratified in commit 56ed795 ("Update - riscv-crypto-spec-vector.adoc") of riscv-crypto. - - const: zvksg description: The standard Zvksg extension for ShangMi algorithm suite with GCM instructions, as ratified in commit 56ed795 ("Update riscv-crypto-spec-vector.adoc") of riscv-crypto. + - const: zvksh + description: | + The standard Zvksh extension for ShangMi suite: SM3 secure hash + instructions, as ratified in commit 56ed795 ("Update + riscv-crypto-spec-vector.adoc") of riscv-crypto. + - const: zvkt description: The standard Zvkt extension for vector data-independent execution diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index b958b94a924dee..311bbccba0baa2 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -29,8 +29,14 @@ properties: - const: spacemit,k1 - items: - enum: + - deepcomputing,fml13v05 - spacemit,k3-pico-itx - const: spacemit,k3 + - items: + - enum: + - spacemit,k3-com260-ifx + - const: spacemit,k3-com260 + - const: spacemit,k3 additionalProperties: true diff --git a/Documentation/devicetree/bindings/rng/mtk-rng.yaml b/Documentation/devicetree/bindings/rng/mtk-rng.yaml index 7e8dc62e5d3a62..38e67861b88fa4 100644 --- a/Documentation/devicetree/bindings/rng/mtk-rng.yaml +++ b/Documentation/devicetree/bindings/rng/mtk-rng.yaml @@ -11,12 +11,13 @@ maintainers: properties: $nodename: - pattern: "^rng@[0-9a-f]+$" + pattern: "^rng(@[0-9a-f]+)?$" compatible: oneOf: - enum: - mediatek,mt7623-rng + - mediatek,mt7981-rng - items: - enum: - mediatek,mt7622-rng @@ -25,6 +26,11 @@ properties: - mediatek,mt8365-rng - mediatek,mt8516-rng - const: mediatek,mt7623-rng + - items: + - enum: + - mediatek,mt7987-rng + - mediatek,mt7988-rng + - const: mediatek,mt7981-rng reg: maxItems: 1 @@ -38,18 +44,37 @@ properties: required: - compatible - - reg - - clocks - - clock-names + +allOf: + - if: + properties: + compatible: + contains: + const: mediatek,mt7981-rng + then: + properties: + reg: false + clocks: false + clock-names: false + else: + required: + - reg + - clocks + - clock-names additionalProperties: false examples: - | #include - rng: rng@1020f000 { - compatible = "mediatek,mt7623-rng"; - reg = <0x1020f000 0x1000>; - clocks = <&infracfg CLK_INFRA_TRNG>; - clock-names = "rng"; + + rng@1020f000 { + compatible = "mediatek,mt7623-rng"; + reg = <0x1020f000 0x1000>; + clocks = <&infracfg CLK_INFRA_TRNG>; + clock-names = "rng"; + }; + - | + rng { + compatible = "mediatek,mt7981-rng"; }; diff --git a/Documentation/devicetree/bindings/rtc/epson,rx6110.txt b/Documentation/devicetree/bindings/rtc/epson,rx6110.txt deleted file mode 100644 index 3dc313e01f77e1..00000000000000 --- a/Documentation/devicetree/bindings/rtc/epson,rx6110.txt +++ /dev/null @@ -1,39 +0,0 @@ -Epson RX6110 Real Time Clock -============================ - -The Epson RX6110 can be used with SPI or I2C busses. The kind of -bus depends on the SPISEL pin and can not be configured via software. - -I2C mode --------- - -Required properties: - - compatible: should be: "epson,rx6110" - - reg : the I2C address of the device for I2C - -Example: - - rtc: rtc@32 { - compatible = "epson,rx6110" - reg = <0x32>; - }; - -SPI mode --------- - -Required properties: - - compatible: should be: "epson,rx6110" - - reg: chip select number - - spi-cs-high: RX6110 needs chipselect high - - spi-cpha: RX6110 works with SPI shifted clock phase - - spi-cpol: RX6110 works with SPI inverse clock polarity - -Example: - - rtc: rtc@3 { - compatible = "epson,rx6110" - reg = <3> - spi-cs-high; - spi-cpha; - spi-cpol; - }; diff --git a/Documentation/devicetree/bindings/rtc/epson,rx6110.yaml b/Documentation/devicetree/bindings/rtc/epson,rx6110.yaml new file mode 100644 index 00000000000000..55086ac7d1e25a --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/epson,rx6110.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/epson,rx6110.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Epson RX6110 Real Time Clock + +description: + The Epson RX6110 can be used with SPI or I2C busses. The kind of bus depends + on the SPISEL pin and cannot be configured via software. + +maintainers: + - Alexandre Belloni + +allOf: + - $ref: rtc.yaml# + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: epson,rx6110 + + reg: + maxItems: 1 + + spi-cs-high: true + spi-cpha: true + spi-cpol: true + +required: + - compatible + - reg + +dependencies: + spi-cs-high: [ spi-cpha, spi-cpol ] + spi-cpha: [ spi-cs-high, spi-cpol ] + spi-cpol: [ spi-cs-high, spi-cpha ] + +unevaluatedProperties: false + +examples: + # I2C mode + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + rtc@32 { + compatible = "epson,rx6110"; + reg = <0x32>; + }; + }; + + # SPI mode + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + + rtc@3 { + compatible = "epson,rx6110"; + reg = <3>; + spi-cs-high; + spi-cpha; + spi-cpol; + }; + }; diff --git a/Documentation/devicetree/bindings/rtc/rtc-ds1307.yaml b/Documentation/devicetree/bindings/rtc/rtc-ds1307.yaml index 98d10e680144c4..9b2796804f0748 100644 --- a/Documentation/devicetree/bindings/rtc/rtc-ds1307.yaml +++ b/Documentation/devicetree/bindings/rtc/rtc-ds1307.yaml @@ -31,6 +31,7 @@ properties: - epson,rx8025 - isil,isl12057 - epson,rx8130 + - epson,rx8901 - items: - enum: diff --git a/Documentation/devicetree/bindings/rtc/st,m41t93.yaml b/Documentation/devicetree/bindings/rtc/st,m41t93.yaml new file mode 100644 index 00000000000000..bdd995c5c1f468 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/st,m41t93.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/st,m41t93.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ST M41T93 RTC and compatible + +maintainers: + - Akhilesh Patil + +description: + ST M41T93 is spi based Real Time Clock (RTC) with time, date, + alarm, watchdog, square wave clock output, 8 bit timer and + 7 bytes of user SRAM. + +properties: + compatible: + enum: + - st,m41t93 + + reg: + maxItems: 1 + + "#clock-cells": + const: 0 + +required: + - compatible + - reg + +allOf: + - $ref: rtc.yaml + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +unevaluatedProperties: false + +examples: + - | + spi { + #address-cells = <1>; + #size-cells = <0>; + rtc@0 { + compatible = "st,m41t93"; + reg = <0>; + #clock-cells = <0>; + spi-max-frequency = <2000000>; + }; + }; + diff --git a/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml b/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml index 722176c831aa02..f4d0eed98a0837 100644 --- a/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml +++ b/Documentation/devicetree/bindings/rtc/trivial-rtc.yaml @@ -30,6 +30,8 @@ properties: - aspeed,ast2500-rtc # ASPEED BMC ast2600 Real-time Clock - aspeed,ast2600-rtc + # ASPEED BMC ast2700 Real-time Clock + - aspeed,ast2700-rtc # Conexant Digicolor Real Time Clock Controller - cnxt,cx92755-rtc # I2C, 32-Bit Binary Counter Watchdog RTC with Trickle Charger and Reset Input/Output diff --git a/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml index c8f01923cb25d4..8496f822dfa5cb 100644 --- a/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml +++ b/Documentation/devicetree/bindings/serial/qcom,sa8255p-geni-uart.yaml @@ -14,9 +14,16 @@ allOf: properties: compatible: - enum: - - qcom,sa8255p-geni-uart - - qcom,sa8255p-geni-debug-uart + oneOf: + - enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + - items: + - const: qcom,sa8797p-geni-uart + - const: qcom,sa8255p-geni-uart + - items: + - const: qcom,sa8797p-geni-debug-uart + - const: qcom,sa8255p-geni-debug-uart reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/serial/rs485.txt b/Documentation/devicetree/bindings/serial/rs485.txt deleted file mode 100644 index a7fe93efc4a508..00000000000000 --- a/Documentation/devicetree/bindings/serial/rs485.txt +++ /dev/null @@ -1 +0,0 @@ -See rs485.yaml diff --git a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml index 685c1eceb78257..49f51b00287952 100644 --- a/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml +++ b/Documentation/devicetree/bindings/serial/snps-dw-apb-uart.yaml @@ -78,6 +78,7 @@ properties: - starfive,jh7100-hsuart - starfive,jh7100-uart - starfive,jh7110-uart + - ultrarisc,dp1000-uart - const: snps,dw-apb-uart - const: snps,dw-apb-uart diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml index 51164772724f5a..419b32e2df9369 100644 --- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml +++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml @@ -26,7 +26,11 @@ description: | properties: compatible: - const: microchip,mpfs-irqmux + oneOf: + - items: + - const: microchip,pic64gx-irqmux + - const: microchip,mpfs-irqmux + - const: microchip,mpfs-irqmux reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml index c5c1bac2db013a..8eaa04431d7452 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml @@ -25,7 +25,9 @@ properties: compatible: items: - enum: + - qcom,eliza-aoss-qmp - qcom,glymur-aoss-qmp + - qcom,hawi-aoss-qmp - qcom,kaanapali-aoss-qmp - qcom,milos-aoss-qmp - qcom,qcs615-aoss-qmp diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index ff01d2f3ee5be1..2db4288a8a54a3 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -32,6 +32,11 @@ properties: - qcom,sm8450-pmic-glink - qcom,sm8550-pmic-glink - const: qcom,pmic-glink + - items: + - enum: + - qcom,hawi-pmic-glink + - const: qcom,kaanapali-pmic-glink + - const: qcom,pmic-glink - items: - enum: - qcom,sm7325-pmic-glink @@ -39,6 +44,7 @@ properties: - const: qcom,pmic-glink - items: - enum: + - qcom,eliza-pmic-glink - qcom,milos-pmic-glink - qcom,sm8650-pmic-glink - qcom,sm8750-pmic-glink diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml index 352af3426d3441..9c38ba59662b78 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,sa8255p-geni-se-qup.yaml @@ -19,7 +19,11 @@ description: properties: compatible: - const: qcom,sa8255p-geni-se-qup + oneOf: + - const: qcom,sa8255p-geni-se-qup + - items: + - const: qcom,sa8797p-geni-se-qup + - const: qcom,sa8255p-geni-se-qup reg: description: QUP wrapper common register address and length. @@ -49,7 +53,11 @@ patternProperties: properties: compatible: - const: qcom,sa8255p-geni-spi + oneOf: + - const: qcom,sa8255p-geni-spi + - items: + - const: qcom,sa8797p-geni-spi + - const: qcom,sa8255p-geni-spi "i2c@[0-9a-f]+$": type: object @@ -58,7 +66,11 @@ patternProperties: properties: compatible: - const: qcom,sa8255p-geni-i2c + oneOf: + - const: qcom,sa8255p-geni-i2c + - items: + - const: qcom,sa8797p-geni-i2c + - const: qcom,sa8255p-geni-i2c "serial@[0-9a-f]+$": type: object @@ -67,9 +79,16 @@ patternProperties: properties: compatible: - enum: - - qcom,sa8255p-geni-uart - - qcom,sa8255p-geni-debug-uart + oneOf: + - enum: + - qcom,sa8255p-geni-uart + - qcom,sa8255p-geni-debug-uart + - items: + - const: qcom,sa8797p-geni-uart + - const: qcom,sa8255p-geni-uart + - items: + - const: qcom,sa8797p-geni-debug-uart + - const: qcom,sa8255p-geni-debug-uart required: - compatible diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml new file mode 100644 index 00000000000000..72b9fa67d1f7b8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/renesas/renesas,r8a78000-mfis.yaml @@ -0,0 +1,221 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/renesas/renesas,r8a78000-mfis.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas MFIS (Multifunctional Interface) controller + +maintainers: + - Wolfram Sang + +description: + The Renesas Multifunctional Interface (MFIS) provides various functionality + like mailboxes, hardware spinlocks, product identification, error injection, + error detection and such. Parts of it can be used for communication between + different CPU cores. Those cores can be in various domains like AP, RT, or + SCP. Often multiple domain-specific MFIS instances exist in one SoC. + +properties: + compatible: + enum: + - renesas,r8a779g0-mfis # R-Car V4H + - renesas,r8a779h0-mfis # R-Car V4M + - renesas,r8a78000-mfis # R-Car X5H (AP<->AP, with PRR) + - renesas,r8a78000-mfis-scp # R-Car X5H (AP<->SCP, without PRR) + + reg: + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + items: + - const: common + - const: mboxes + + interrupts: + minItems: 12 + maxItems: 128 + description: + The interrupts raised by the remote doorbells. + + interrupt-names: + minItems: 12 + maxItems: 128 + description: + An interrupt name is constructed with the prefix 'ch'. Then, the + channel number as specified in the documentation of the SoC. Finally, + the letter 'i' if the interrupt is raised by the IICR register. Or 'e' + if it is raised by the EICR register. + + "#hwlock-cells": + const: 1 + + "#mbox-cells": + const: 2 + description: + The first cell is the channel number as specified in the documentation + of the SoC. The second cell may specify flags as described in the file + . + +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,r8a779g0-mfis + - renesas,r8a779h0-mfis + then: + properties: + reg: + maxItems: 1 + reg-names: + maxItems: 1 + interrupts: + maxItems: 12 + interrupt-names: + maxItems: 12 + items: + pattern: "^ch[0-9]+e$" + + - if: + properties: + compatible: + contains: + const: renesas,r8a78000-mfis + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + interrupts: + minItems: 128 + interrupt-names: + minItems: 128 + items: + pattern: "^ch[0-9]+[ie]$" + + - if: + properties: + compatible: + contains: + const: renesas,r8a78000-mfis-scp + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + interrupts: + minItems: 32 + maxItems: 32 + interrupt-names: + minItems: 32 + maxItems: 32 + items: + pattern: "^ch[0-9]+i$" + +required: + - compatible + - reg + - reg-names + - interrupts + - interrupt-names + - "#hwlock-cells" + - "#mbox-cells" + +additionalProperties: false + +examples: + - | + #include + system-controller@189e0000 { + compatible = "renesas,r8a78000-mfis"; + reg = <0x189e0000 0x1000>, <0x18800000 0x40000>; + reg-names = "common", "mboxes"; + interrupts = , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , ; + interrupt-names = "ch0i", "ch0e", "ch1i", "ch1e", "ch2i", "ch2e", "ch3i", "ch3e", + "ch4i", "ch4e", "ch5i", "ch5e", "ch6i", "ch6e", "ch7i", "ch7e", + "ch8i", "ch8e", "ch9i", "ch9e", "ch10i", "ch10e", "ch11i", "ch11e", + "ch12i", "ch12e", "ch13i", "ch13e", "ch14i", "ch14e", "ch15i", "ch15e", + "ch16i", "ch16e", "ch17i", "ch17e", "ch18i", "ch18e", "ch19i", "ch19e", + "ch20i", "ch20e", "ch21i", "ch21e", "ch22i", "ch22e", "ch23i", "ch23e", + "ch24i", "ch24e", "ch25i", "ch25e", "ch26i", "ch26e", "ch27i", "ch27e", + "ch28i", "ch28e", "ch29i", "ch29e", "ch30i", "ch30e", "ch31i", "ch31e", + "ch32i", "ch32e", "ch33i", "ch33e", "ch34i", "ch34e", "ch35i", "ch35e", + "ch36i", "ch36e", "ch37i", "ch37e", "ch38i", "ch38e", "ch39i", "ch39e", + "ch40i", "ch40e", "ch41i", "ch41e", "ch42i", "ch42e", "ch43i", "ch43e", + "ch44i", "ch44e", "ch45i", "ch45e", "ch46i", "ch46e", "ch47i", "ch47e", + "ch48i", "ch48e", "ch49i", "ch49e", "ch50i", "ch50e", "ch51i", "ch51e", + "ch52i", "ch52e", "ch53i", "ch53e", "ch54i", "ch54e", "ch55i", "ch55e", + "ch56i", "ch56e", "ch57i", "ch57e", "ch58i", "ch58e", "ch59i", "ch59e", + "ch60i", "ch60e", "ch61i", "ch61e", "ch62i", "ch62e", "ch63i", "ch63e"; + #hwlock-cells = <1>; + #mbox-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 5c22c51b1533d8..eeef34e3d7d070 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -473,6 +473,12 @@ properties: - const: renesas,r8a779mb - const: renesas,r8a7795 + - description: R-Car M3Le (R8A779MD) + items: + - const: renesas,geist # M3Le Geist (RTP8A779MDASKB0F10S) + - const: renesas,r8a779md + - const: renesas,r8a77965 + - description: R-Car X5H (R8A78000) items: - enum: diff --git a/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml index 1c502618de51f3..0b6fbab48b7438 100644 --- a/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml +++ b/Documentation/devicetree/bindings/soc/sophgo/sophgo.yaml @@ -31,6 +31,10 @@ properties: - milkv,duo-module-01-evb - const: milkv,duo-module-01 - const: sophgo,sg2000 + - items: + - enum: + - milkv,duo-s + - const: sophgo,sg2000 - items: - enum: - sipeed,licheerv-nano-b diff --git a/Documentation/devicetree/bindings/soc/ti/ti,omap-dmm.yaml b/Documentation/devicetree/bindings/soc/ti/ti,omap-dmm.yaml new file mode 100644 index 00000000000000..1a2b627cd2066e --- /dev/null +++ b/Documentation/devicetree/bindings/soc/ti/ti,omap-dmm.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/ti/ti,omap-dmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OMAP Dynamic Memory Manager (DMM) + +maintainers: + - Bhargav Joshi + +description: + The dynamic memory manager (DMM) is a module located immediately in front of + the SDRAM controllers (called EMIFs on OMAP). DMM manages various aspects of + memory accesses such as priority generation amongst initiators, configuration + of SDRAM interleaving, optimizing transfer of 2D block objects, and provide + MMU-like page translation for initiators which need contiguous dma bus + addresses. + +properties: + compatible: + enum: + - ti,omap4-dmm + - ti,omap5-dmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ti,hwmods: + $ref: /schemas/types.yaml#/definitions/string + description: Name of the hwmod associated to DMM, which is typically "dmm" + deprecated: true + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + + dmm@4e000000 { + compatible = "ti,omap4-dmm"; + reg = <0x4e000000 0x800>; + interrupts = ; + ti,hwmods = "dmm"; + }; diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs35l36.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs35l36.yaml new file mode 100644 index 00000000000000..2a142b32acf50d --- /dev/null +++ b/Documentation/devicetree/bindings/sound/cirrus,cs35l36.yaml @@ -0,0 +1,240 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/cirrus,cs35l36.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cirrus Logic CS35L36 Speaker Amplifier + +maintainers: + - David Rhodes + - patches@opensource.cirrus.com + +description: + CS35L36 is a boosted mono Class D amplifier + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - cirrus,cs35l36 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + VA-supply: + description: Voltage regulator of analog internal section + + VP-supply: + description: Voltage regulator of boost converter + + reset-gpios: + maxItems: 1 + + cirrus,boost-ctl-millivolt: + description: Boost converter output voltage (step 50) + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 2550 + maximum: 12000 + + cirrus,boost-peak-milliamp: + description: Boost-converter peak current limit (step 50) + $ref: /schemas/types.yaml#/definitions/uint32 + default: 4500 + minimum: 1600 + maximum: 4500 + + cirrus,boost-ind-nanohenry: + description: Initial inductor estimation reference value (1000=1μH, 1200=1.2μH) + $ref: /schemas/types.yaml#/definitions/uint32 + default: 1000 + + cirrus,multi-amp-mode: + description: Hi-Z ASP port when more than one amplifier in system + type: boolean + + cirrus,boost-ctl-select: + description: Boost converter control source selection + $ref: /schemas/types.yaml#/definitions/uint32 + default: 1 + enum: + - 0 # Control Port + - 1 # Class + - 2 # Sync + + cirrus,amp-pcm-inv: + description: Invert incoming PCM data when true + type: boolean + + cirrus,imon-pol-inv: + description: Invert polarity of outbound IMON feedback when true + type: boolean + + cirrus,vmon-pol-inv: + description: Invert polarity of outbound VMON feedback when true + type: boolean + + cirrus,dcm-mode-enable: + description: Enable boost converter automatic Discontinuous Conduction Mode + type: boolean + + cirrus,weak-fet-disable: + description: Reduce output driver strength in Weak-FET Drive Mode when true + type: boolean + + cirrus,classh-wk-fet-delay-ms: + description: Weak-FET entry delay + default: 100 + enum: [0, 5, 10, 50, 100, 200, 500, 1000] + + cirrus,classh-weak-fet-thld-millivolt: + description: Weak-FET drive threshold + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [50, 100, 150, 200, 250, 300, 350, 400, 450, 500, 550, 600, 650, 700] + + cirrus,temp-warn-threshold: + description: Overtemperature warning threshold + $ref: /schemas/types.yaml#/definitions/uint32 + default: 2 + enum: + - 0 # 105°C + - 1 # 115°C + - 2 # 125°C + - 3 # 135°C + + cirrus,irq-drive-select: + description: Interrupt output driver type + $ref: /schemas/types.yaml#/definitions/uint32 + default: 1 + enum: + - 0 # open-drain + - 1 # push-pull + + cirrus,irq-gpio-select: + description: Programmable IRQ pin selection + $ref: /schemas/types.yaml#/definitions/uint32 + enum: + - 0 # PDM_DATA/SWIRE_SD/INT + - 1 # GPIO + + cirrus,vpbr-config: + $ref: "#/$defs/vpbr-config" + +$defs: + vpbr-config: + description: Brownout prevention configuration sub-node + type: object + additionalProperties: false + + properties: + cirrus,vpbr-en: + description: VBST brownout prevention enable + $ref: /schemas/types.yaml#/definitions/uint32 + default: 0 + enum: + - 0 # disabled + - 1 # enabled + + cirrus,vpbr-thld: + description: Initial VPBR threshold voltage + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 2 + maximum: 31 + + cirrus,vpbr-atk-rate: + description: Attenuation attack step rate + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + cirrus,vpbr-atk-vol: + description: VP brownout prevention step size + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + cirrus,vpbr-max-attn: + description: Maximum attenuation during VP brownout prevention (dB) + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 15 + + cirrus,vpbr-wait: + description: Delay between brownout clearance and attenuation release (ms) + $ref: /schemas/types.yaml#/definitions/uint32 + default: 1 + enum: + - 0 # 10 + - 1 # 100 + - 2 # 250 + - 3 # 500 + + cirrus,vpbr-rel-rate: + description: Attenuation release step rate + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 7 + + cirrus,vpbr-mute-en: + description: Mute audio if maximum attenuation reached + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 1 + +required: + - compatible + - reg + - interrupts + - VA-supply + - cirrus,boost-ctl-millivolt + - cirrus,boost-peak-milliamp + +unevaluatedProperties: false + +examples: + - | + #include + #include + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + codec@40 { + compatible = "cirrus,cs35l36"; + reg = <0x40>; + VA-supply = <&dummy_vreg>; + VP-supply = <&dummy_vreg>; + reset-gpios = <&gpio0 54 GPIO_ACTIVE_HIGH>; + interrupts = <3 IRQ_TYPE_LEVEL_LOW>; + + cirrus,boost-ind-nanohenry = <1000>; + cirrus,boost-ctl-millivolt = <10000>; + cirrus,boost-peak-milliamp = <4500>; + cirrus,boost-ctl-select = <0>; + cirrus,classh-wk-fet-delay-ms = <100>; + cirrus,classh-weak-fet-thld-millivolt = <100>; + cirrus,temp-warn-threshold = <1>; + cirrus,multi-amp-mode; + cirrus,irq-drive-select = <1>; + cirrus,irq-gpio-select = <1>; + + cirrus,vpbr-config { + cirrus,vpbr-en = <0>; + cirrus,vpbr-thld = <5>; + cirrus,vpbr-atk-rate = <2>; + cirrus,vpbr-atk-vol = <1>; + cirrus,vpbr-max-attn = <9>; + cirrus,vpbr-wait = <1>; + cirrus,vpbr-rel-rate = <5>; + cirrus,vpbr-mute-en = <0>; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/cs35l36.txt b/Documentation/devicetree/bindings/sound/cs35l36.txt deleted file mode 100644 index d34117b8558e5b..00000000000000 --- a/Documentation/devicetree/bindings/sound/cs35l36.txt +++ /dev/null @@ -1,168 +0,0 @@ -CS35L36 Speaker Amplifier - -Required properties: - - - compatible : "cirrus,cs35l36" - - - reg : the I2C address of the device for I2C - - - VA-supply, VP-supply : power supplies for the device, - as covered in - Documentation/devicetree/bindings/regulator/regulator.txt. - - - cirrus,boost-ctl-millivolt : Boost Voltage Value. Configures the boost - converter's output voltage in mV. The range is from 2550mV to 12000mV with - increments of 50mV. - (Default) VP - - - cirrus,boost-peak-milliamp : Boost-converter peak current limit in mA. - Configures the peak current by monitoring the current through the boost FET. - Range starts at 1600mA and goes to a maximum of 4500mA with increments of - 50mA. - (Default) 4.50 Amps - - - cirrus,boost-ind-nanohenry : Inductor estimation LBST reference value. - Seeds the digital boost converter's inductor estimation block with the initial - inductance value to reference. - - 1000 = 1uH (Default) - 1200 = 1.2uH - -Optional properties: - - cirrus,multi-amp-mode : Boolean to determine if there are more than - one amplifier in the system. If more than one it is best to Hi-Z the ASP - port to prevent bus contention on the output signal - - - cirrus,boost-ctl-select : Boost converter control source selection. - Selects the source of the BST_CTL target VBST voltage for the boost - converter to generate. - 0x00 - Control Port Value - 0x01 - Class H Tracking (Default) - 0x10 - MultiDevice Sync Value - - - cirrus,amp-pcm-inv : Boolean to determine Amplifier will invert incoming - PCM data - - - cirrus,imon-pol-inv : Boolean to determine Amplifier will invert the - polarity of outbound IMON feedback data - - - cirrus,vmon-pol-inv : Boolean to determine Amplifier will invert the - polarity of outbound VMON feedback data - - - cirrus,dcm-mode-enable : Boost converter automatic DCM Mode enable. - This enables the digital boost converter to operate in a low power - (Discontinuous Conduction) mode during low loading conditions. - - - cirrus,weak-fet-disable : Boolean : The strength of the output drivers is - reduced when operating in a Weak-FET Drive Mode and must not be used to drive - a large load. - - - cirrus,classh-wk-fet-delay : Weak-FET entry delay. Controls the delay - (in ms) before the Class H algorithm switches to the weak-FET voltage - (after the audio falls and remains below the value specified in WKFET_AMP_THLD). - - 0 = 0ms - 1 = 5ms - 2 = 10ms - 3 = 50ms - 4 = 100ms (Default) - 5 = 200ms - 6 = 500ms - 7 = 1000ms - - - cirrus,classh-weak-fet-thld-millivolt : Weak-FET amplifier drive threshold. - Configures the signal threshold at which the PWM output stage enters - weak-FET operation. The range is 50mV to 700mV in 50mV increments. - - - cirrus,temp-warn-threshold : Amplifier overtemperature warning threshold. - Configures the threshold at which the overtemperature warning condition occurs. - When the threshold is met, the overtemperature warning attenuation is applied - and the TEMP_WARN_EINT interrupt status bit is set. - If TEMP_WARN_MASK = 0, INTb is asserted. - - 0 = 105C - 1 = 115C - 2 = 125C (Default) - 3 = 135C - - - cirrus,irq-drive-select : Selects the driver type of the selected interrupt - output. - - 0 = Open-drain - 1 = Push-pull (Default) - - - cirrus,irq-gpio-select : Selects the pin to serve as the programmable - interrupt output. - - 0 = PDM_DATA / SWIRE_SD / INT (Default) - 1 = GPIO - -Optional properties for the "cirrus,vpbr-config" Sub-node - - - cirrus,vpbr-en : VBST brownout prevention enable. Configures whether the - VBST brownout prevention algorithm is enabled or disabled. - - 0 = VBST brownout prevention disabled (default) - 1 = VBST brownout prevention enabled - - See Section 7.31.1 VPBR Config for configuration options & further details - - - cirrus,vpbr-thld : Initial VPBR threshold. Configures the VP brownout - threshold voltage - - - cirrus,cirrus,vpbr-atk-rate : Attenuation attack step rate. Configures the - amount delay between consecutive volume attenuation steps when a brownout - condition is present and the VP brownout condition is in an attacking state. - - - cirrus,vpbr-atk-vol : VP brownout prevention step size. Configures the VP - brownout prevention attacking attenuation step size when operating in either - digital volume or analog gain modes. - - - cirrus,vpbr-max-attn : Maximum attenuation that the VP brownout prevention - can apply to the audio signal. - - - cirrus,vpbr-wait : Configures the delay time between a brownout condition - no longer being present and the VP brownout prevention entering an attenuation - release state. - - - cirrus,vpbr-rel-rate : Attenuation release step rate. Configures the delay - between consecutive volume attenuation release steps when a brownout condition - is not longer present and the VP brownout is in an attenuation release state. - - - cirrus,vpbr-mute-en : During the attack state, if the vpbr-max-attn value - is reached, the error condition still remains, and this bit is set, the audio - is muted. - -Example: - -cs35l36: cs35l36@40 { - compatible = "cirrus,cs35l36"; - reg = <0x40>; - VA-supply = <&dummy_vreg>; - VP-supply = <&dummy_vreg>; - reset-gpios = <&gpio0 54 0>; - interrupt-parent = <&gpio8>; - interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - - cirrus,boost-ind-nanohenry = <1000>; - cirrus,boost-ctl-millivolt = <10000>; - cirrus,boost-peak-milliamp = <4500>; - cirrus,boost-ctl-select = <0x00>; - cirrus,weak-fet-delay = <0x04>; - cirrus,weak-fet-thld = <0x01>; - cirrus,temp-warn-threshold = <0x01>; - cirrus,multi-amp-mode; - cirrus,irq-drive-select = <0x01>; - cirrus,irq-gpio-select = <0x01>; - - cirrus,vpbr-config { - cirrus,vpbr-en = <0x00>; - cirrus,vpbr-thld = <0x05>; - cirrus,vpbr-atk-rate = <0x02>; - cirrus,vpbr-atk-vol = <0x01>; - cirrus,vpbr-max-attn = <0x09>; - cirrus,vpbr-wait = <0x01>; - cirrus,vpbr-rel-rate = <0x05>; - cirrus,vpbr-mute-en = <0x00>; - }; -}; diff --git a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml index 87559d0d079a7d..f8a602cee37b16 100644 --- a/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml +++ b/Documentation/devicetree/bindings/sound/davinci-mcasp-audio.yaml @@ -248,13 +248,13 @@ examples: reg-names = "mpu"; interrupts = <82>, <83>; interrupt-names = "tx", "rx"; - op-mode = <0>; /* MCASP_IIS_MODE */ + op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; ti,async-mode; dmas = <&main_udmap 0xc400>, <&main_udmap 0x4400>; dma-names = "tx", "rx"; serial-dir = < - 0 0 0 0 /* 0: INACTIVE, 1: TX, 2: RX */ + 0 0 0 0 /* 0: INACTIVE, 1: TX, 2: RX */ 0 0 0 0 0 0 0 1 2 0 0 0 >; diff --git a/Documentation/devicetree/bindings/sound/dmic-codec.yaml b/Documentation/devicetree/bindings/sound/dmic-codec.yaml index cc3c84dd4c26fd..83c23e029ea489 100644 --- a/Documentation/devicetree/bindings/sound/dmic-codec.yaml +++ b/Documentation/devicetree/bindings/sound/dmic-codec.yaml @@ -39,6 +39,10 @@ properties: wakeup-delay-ms: description: Delay (in ms) after enabling the DMIC + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible diff --git a/Documentation/devicetree/bindings/sound/fsl,micfil.yaml b/Documentation/devicetree/bindings/sound/fsl,micfil.yaml index c47b7a09749067..4c7dadb310de34 100644 --- a/Documentation/devicetree/bindings/sound/fsl,micfil.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,micfil.yaml @@ -66,6 +66,10 @@ properties: "#sound-dai-cells": const: 0 + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/sound/loongson,ls-audio-card.yaml b/Documentation/devicetree/bindings/sound/loongson,ls-audio-card.yaml index 61e8babed402f0..dc7f4afbb7775f 100644 --- a/Documentation/devicetree/bindings/sound/loongson,ls-audio-card.yaml +++ b/Documentation/devicetree/bindings/sound/loongson,ls-audio-card.yaml @@ -8,19 +8,22 @@ title: Loongson 7axxx/2kxxx ASoC audio sound card driver maintainers: - Yingkun Meng + - Binbin Zhou description: The binding describes the sound card present in loongson 7axxx/2kxxx platform. The sound card is an ASoC component which uses Loongson I2S controller to transfer the audio data. +allOf: + - $ref: sound-card-common.yaml# + properties: compatible: - const: loongson,ls-audio-card - - model: - $ref: /schemas/types.yaml#/definitions/string - description: User specified audio sound card name + enum: + - loongson,ls-audio-card # Loongson-2K1000/Loongson-2K2000/LS7A + - loongson,ls2k0300-forever-pi-audio-card # CTCISZ Forever Pi + - loongson,ls2k0300-dl2k0300b-audio-card # ATK-DL2K0300B mclk-fs: $ref: simple-card.yaml#/definitions/mclk-fs @@ -45,14 +48,25 @@ properties: required: - sound-dai + spkr-en-gpios: + maxItems: 1 + description: The GPIO that enables the speakers + + hp-ctl-gpios: + maxItems: 1 + description: The GPIO that control the headphones + + hp-det-gpios: + maxItems: 1 + description: The GPIO that detect headphones are plugged in + required: - compatible - - model - mclk-fs - cpu - codec -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -68,3 +82,28 @@ examples: sound-dai = <&es8323>; }; }; + + - | + #include + + sound { + compatible = "loongson,ls2k0300-dl2k0300b-audio-card"; + model = "loongson-audio"; + mclk-fs = <512>; + hp-det-gpios = <&gpio 81 GPIO_ACTIVE_HIGH>; + spkr-en-gpios = <&gpio 86 GPIO_ACTIVE_HIGH>; + hp-ctl-gpios = <&gpio 87 GPIO_ACTIVE_HIGH>; + audio-routing = + "Headphone", "LOUT1", + "Headphone", "ROUT1", + "Speaker", "LOUT2", + "Speaker", "ROUT2"; + + cpu { + sound-dai = <&i2s>; + }; + + codec { + sound-dai = <&es8388>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/loongson,ls2k1000-i2s.yaml b/Documentation/devicetree/bindings/sound/loongson,ls2k1000-i2s.yaml index da79510bb2d91b..51e23c189f7a11 100644 --- a/Documentation/devicetree/bindings/sound/loongson,ls2k1000-i2s.yaml +++ b/Documentation/devicetree/bindings/sound/loongson,ls2k1000-i2s.yaml @@ -14,9 +14,12 @@ allOf: properties: compatible: - const: loongson,ls2k1000-i2s + enum: + - loongson,ls2k0300-i2s + - loongson,ls2k1000-i2s reg: + minItems: 1 items: - description: Loongson I2S controller Registers. - description: APB DMA config register for Loongson I2S controller. @@ -49,6 +52,23 @@ required: unevaluatedProperties: false +if: + properties: + compatible: + contains: + enum: + - loongson,ls2k1000-i2s + +then: + properties: + reg: + minItems: 2 + +else: + properties: + reg: + maxItems: 1 + examples: - | #include diff --git a/Documentation/devicetree/bindings/sound/mediatek,mtk-btcvsd-snd.yaml b/Documentation/devicetree/bindings/sound/mediatek,mtk-btcvsd-snd.yaml new file mode 100644 index 00000000000000..1b74516554767c --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mtk-btcvsd-snd.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mtk-btcvsd-snd.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek ALSA BT SCO CVSD/MSBC + +maintainers: + - Luca Leonardo Scorcia + +properties: + compatible: + const: mediatek,mtk-btcvsd-snd + + reg: + items: + - description: PKV region + - description: SRAM_BANK2 region + + interrupts: + items: + - description: BT-SCO interrupt + + mediatek,infracfg: + $ref: /schemas/types.yaml#/definitions/phandle + description: The phandle of the infracfg controller + + mediatek,offset: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Array of register offsets and masks + items: + - description: infra_misc_offset + - description: infra_conn_bt_cvsd_mask + - description: cvsd_mcu_read_offset + - description: cvsd_mcu_write_offset + - description: cvsd_packet_indicator_offset + +required: + - compatible + - reg + - interrupts + - mediatek,infracfg + - mediatek,offset + +additionalProperties: false + +examples: + - | + #include + + mtk-btcvsd-snd@18000000 { + compatible = "mediatek,mtk-btcvsd-snd"; + reg = <0x18000000 0x1000>, + <0x18080000 0x8000>; + interrupts = ; + mediatek,infracfg = <&infrasys>; + mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>; + }; diff --git a/Documentation/devicetree/bindings/sound/mtk-btcvsd-snd.txt b/Documentation/devicetree/bindings/sound/mtk-btcvsd-snd.txt deleted file mode 100644 index 679e44839b48f4..00000000000000 --- a/Documentation/devicetree/bindings/sound/mtk-btcvsd-snd.txt +++ /dev/null @@ -1,24 +0,0 @@ -Mediatek ALSA BT SCO CVSD/MSBC Driver - -Required properties: -- compatible = "mediatek,mtk-btcvsd-snd"; -- reg: register location and size of PKV and SRAM_BANK2 -- interrupts: should contain BTSCO interrupt -- mediatek,infracfg: the phandles of INFRASYS -- mediatek,offset: Array contains of register offset and mask - infra_misc_offset, - infra_conn_bt_cvsd_mask, - cvsd_mcu_read_offset, - cvsd_mcu_write_offset, - cvsd_packet_indicator_offset - -Example: - - mtk-btcvsd-snd@18000000 { - compatible = "mediatek,mtk-btcvsd-snd"; - reg=<0 0x18000000 0 0x1000>, - <0 0x18080000 0 0x8000>; - interrupts = ; - mediatek,infracfg = <&infrasys>; - mediatek,offset = <0xf00 0x800 0xfd0 0xfd4 0xfd8>; - }; diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml index 2eed2277511f89..4988e7ed6e34b0 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-rx-macro.yaml @@ -21,6 +21,7 @@ properties: - qcom,sc8280xp-lpass-rx-macro - items: - enum: + - qcom,eliza-lpass-rx-macro - qcom,kaanapali-lpass-rx-macro - qcom,sm8650-lpass-rx-macro - qcom,sm8750-lpass-rx-macro diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml index e5e65e226a02df..d8682ff2e82c59 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-tx-macro.yaml @@ -21,6 +21,7 @@ properties: - qcom,sc8280xp-lpass-tx-macro - items: - enum: + - qcom,eliza-lpass-tx-macro - qcom,kaanapali-lpass-tx-macro - qcom,sm8650-lpass-tx-macro - qcom,sm8750-lpass-tx-macro diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml index 5c42b2b323ee41..aea31fbdad376a 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml @@ -21,6 +21,7 @@ properties: - qcom,sc8280xp-lpass-va-macro - items: - enum: + - qcom,eliza-lpass-va-macro - qcom,glymur-lpass-va-macro - qcom,kaanapali-lpass-va-macro - qcom,sm8650-lpass-va-macro diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml index d5f22b5cf0210b..9fedd80532e276 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml @@ -20,6 +20,7 @@ properties: - qcom,sc8280xp-lpass-wsa-macro - items: - enum: + - qcom,eliza-lpass-wsa-macro - qcom,glymur-lpass-wsa-macro - qcom,kaanapali-lpass-wsa-macro - qcom,sm8650-lpass-wsa-macro diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml index 15f38622b98b90..dae440ecab5903 100644 --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml @@ -23,6 +23,7 @@ properties: - const: qcom,sdm845-sndcard - items: - enum: + - qcom,eliza-sndcard - qcom,kaanapali-sndcard - qcom,sm8550-sndcard - qcom,sm8650-sndcard diff --git a/Documentation/devicetree/bindings/sound/samsung,tm2.yaml b/Documentation/devicetree/bindings/sound/samsung,tm2.yaml index 67586ba3e0a0fb..985b7d29cd3374 100644 --- a/Documentation/devicetree/bindings/sound/samsung,tm2.yaml +++ b/Documentation/devicetree/bindings/sound/samsung,tm2.yaml @@ -45,8 +45,12 @@ properties: description: Phandles to the I2S controllers. $ref: /schemas/types.yaml#/definitions/phandle-array items: - - description: Phandle to I2S0. - - description: Phandle to I2S1. + - items: + - description: Phandle to I2S0 + - description: Unused + - items: + - description: Phandle to I2S1 + - description: Unused mic-bias-gpios: description: GPIO pin that enables the Main Mic bias regulator. diff --git a/Documentation/devicetree/bindings/sound/simple-card.yaml b/Documentation/devicetree/bindings/sound/simple-card.yaml index a14716b2732f00..23310f303be371 100644 --- a/Documentation/devicetree/bindings/sound/simple-card.yaml +++ b/Documentation/devicetree/bindings/sound/simple-card.yaml @@ -315,7 +315,7 @@ examples: #address-cells = <1>; #size-cells = <0>; - simple-audio-card,dai-link@0 { /* I2S - HDMI */ + simple-audio-card,dai-link@0 { /* I2S - HDMI */ reg = <0>; format = "i2s"; cpu { @@ -326,7 +326,7 @@ examples: }; }; - simple-audio-card,dai-link@1 { /* S/PDIF - HDMI */ + simple-audio-card,dai-link@1 { /* S/PDIF - HDMI */ reg = <1>; cpu { sound-dai = <&audio1>; @@ -336,7 +336,7 @@ examples: }; }; - simple-audio-card,dai-link@2 { /* S/PDIF - S/PDIF */ + simple-audio-card,dai-link@2 { /* S/PDIF - S/PDIF */ reg = <2>; cpu { sound-dai = <&audio2>; diff --git a/Documentation/devicetree/bindings/sound/wlf,wm8524.yaml b/Documentation/devicetree/bindings/sound/wlf,wm8524.yaml index 4d951ece394e97..dffc41d5f7de1f 100644 --- a/Documentation/devicetree/bindings/sound/wlf,wm8524.yaml +++ b/Documentation/devicetree/bindings/sound/wlf,wm8524.yaml @@ -24,6 +24,10 @@ properties: description: a GPIO spec for the MUTE pin. + port: + $ref: audio-graph-port.yaml# + unevaluatedProperties: false + required: - compatible - wlf,mute-gpios diff --git a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml index 9447a2f371b56f..8e6973fa229c9e 100644 --- a/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml +++ b/Documentation/devicetree/bindings/soundwire/qcom,soundwire.yaml @@ -90,7 +90,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 qcom,ports-sinterval-low: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -101,7 +101,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 qcom,ports-sinterval: $ref: /schemas/types.yaml#/definitions/uint16-array @@ -112,7 +112,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 qcom,ports-offset1: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -123,7 +123,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 qcom,ports-offset2: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -134,7 +134,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 qcom,ports-lane-control: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -145,7 +145,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 qcom,ports-block-pack-mode: $ref: /schemas/types.yaml#/definitions/uint8-array @@ -158,7 +158,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 items: oneOf: - minimum: 0 @@ -175,7 +175,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 items: oneOf: - minimum: 0 @@ -192,7 +192,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 items: oneOf: - minimum: 0 @@ -208,7 +208,7 @@ properties: or applicable for the respective data port. More info in MIPI Alliance SoundWire 1.0 Specifications. minItems: 3 - maxItems: 16 + maxItems: 17 items: oneOf: - minimum: 0 diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt b/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt deleted file mode 100644 index fb38e96d395fbf..00000000000000 --- a/Documentation/devicetree/bindings/spi/nuvoton,npcm-fiu.txt +++ /dev/null @@ -1,58 +0,0 @@ -* Nuvoton FLASH Interface Unit (FIU) SPI Controller - -NPCM FIU supports single, dual and quad communication interface. - -The NPCM7XX supports three FIU modules, -FIU0 and FIUx supports two chip selects, -FIU3 support four chip select. - -The NPCM8XX supports four FIU modules, -FIU0 and FIUx supports two chip selects, -FIU1 and FIU3 supports four chip selects. - -Required properties: - - compatible : "nuvoton,npcm750-fiu" for Poleg NPCM7XX BMC - "nuvoton,npcm845-fiu" for Arbel NPCM8XX BMC - - #address-cells : should be 1. - - #size-cells : should be 0. - - reg : the first contains the register location and length, - the second contains the memory mapping address and length - - reg-names: Should contain the reg names "control" and "memory" - - clocks : phandle of FIU reference clock. - -Required properties in case the pins can be muxed: - - pinctrl-names : a pinctrl state named "default" must be defined. - - pinctrl-0 : phandle referencing pin configuration of the device. - -Optional property: - - nuvoton,spix-mode: enable spix-mode for an expansion bus to an ASIC or CPLD. - -Aliases: -- All the FIU controller nodes should be represented in the aliases node using - the following format 'fiu{n}' where n is a unique number for the alias. - In the NPCM7XX BMC: - fiu0 represent fiu 0 controller - fiu1 represent fiu 3 controller - fiu2 represent fiu x controller - - In the NPCM8XX BMC: - fiu0 represent fiu 0 controller - fiu1 represent fiu 1 controller - fiu2 represent fiu 3 controller - fiu3 represent fiu x controller - -Example: -fiu3: spi@c00000000 { - compatible = "nuvoton,npcm750-fiu"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; - reg-names = "control", "memory"; - clocks = <&clk NPCM7XX_CLK_AHB>; - pinctrl-names = "default"; - pinctrl-0 = <&spi3_pins>; - flash@0 { - ... - }; -}; - diff --git a/Documentation/devicetree/bindings/spi/nuvoton,npcm750-fiu.yaml b/Documentation/devicetree/bindings/spi/nuvoton,npcm750-fiu.yaml new file mode 100644 index 00000000000000..965904a9878559 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/nuvoton,npcm750-fiu.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/nuvoton,npcm750-fiu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM Flash Interface Unit (FIU) SPI Controller + +maintainers: + - Tomer Maimon + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +description: | + NPCM FIU supports single, dual and quad communication interface. + + The NPCM7XX supports three FIU modules: + FIU0 and FIUx support two chip selects + FIU3 supports four chip selects. + + The NPCM8XX supports four FIU modules: + FIU0 and FIUx support two chip selects + FIU1 and FIU3 support four chip selects. + + The FIU control register block is always required. The direct-mapped + flash window is optional because the controller can still access flash + through the UMA path when that mapping is not described. + + Alias convention: + The '/aliases' node should define: + For NPCM7xx: fiu0=&fiu0; fiu1=&fiu3; fiu2=&fiux; + For NPCM8xx: fiu0=&fiu0; fiu1=&fiu3; fiu2=&fiux; fiu3=&fiu1; + +properties: + compatible: + enum: + - nuvoton,npcm750-fiu # Poleg NPCM7XX + - nuvoton,npcm845-fiu # Arbel NPCM8XX + + reg: + description: + The first resource is the FIU control register block. An optional second + resource describes the direct-mapped flash window used for direct + read/write accesses. + minItems: 1 + items: + - description: FIU control registers + - description: Memory-mapped flash contents + + reg-names: + description: + Resource names for the control registers and optional direct-mapped + flash window. + minItems: 1 + items: + - const: control + - const: memory + + clocks: + maxItems: 1 + description: FIU reference clock. + + nuvoton,spix-mode: + type: boolean + description: Enable SPIX mode for an expansion bus to an ASIC or CPLD. + +required: + - compatible + - reg + - reg-names + - clocks + +unevaluatedProperties: false + +examples: + - | + #include + spi@fb000000 { + compatible = "nuvoton,npcm750-fiu"; + reg = <0xfb000000 0x1000>, <0x80000000 0x10000000>; + reg-names = "control", "memory"; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clk NPCM7XX_CLK_SPI0>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml index 1696ac46a660ec..ee2199027e895a 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-qcom-qspi.yaml @@ -13,13 +13,11 @@ description: The QSPI controller allows SPI protocol communication in single, dual, or quad wire transmission modes for read/write access to slaves such as NOR flash. -allOf: - - $ref: /schemas/spi/spi-controller.yaml# - properties: compatible: items: - enum: + - qcom,qcs615-qspi - qcom,sc7180-qspi - qcom,sc7280-qspi - qcom,sdm845-qspi @@ -67,6 +65,23 @@ required: - clock-names - clocks +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + - if: + properties: + compatible: + contains: + const: qcom,qcs615-qspi + then: + properties: + interconnects: + minItems: 2 + interconnect-names: + minItems: 2 + required: + - interconnects + - interconnect-names + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml index 8ebebcebca1605..95a5bd894e93d2 100644 --- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml +++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.yaml @@ -50,10 +50,15 @@ properties: - enum: - mscc,ocelot-spi - mscc,jaguar2-spi - - renesas,rzn1-spi - sophgo,sg2042-spi - thead,th1520-spi - const: snps,dw-apb-ssi + - description: Vendor controllers which use snps,dwc-ssi-2.00a as fallback + items: + - enum: + - starfive,jhb100-spi + - const: snps,dwc-ssi-2.00a + - const: snps,dwc-ssi-1.01a - description: Intel Keem Bay SPI Controller const: intel,keembay-ssi - description: Intel Mount Evans Integrated Management Complex SPI Controller @@ -88,6 +93,9 @@ properties: - const: ssi_clk - const: pclk + power-domains: + maxItems: 1 + resets: maxItems: 1 diff --git a/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml new file mode 100644 index 00000000000000..e82c7f8d0b981f --- /dev/null +++ b/Documentation/devicetree/bindings/spi/spacemit,k1-spi.yaml @@ -0,0 +1,84 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/spacemit,k1-spi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 SoC Serial Peripheral Interface (SPI) + +maintainers: + - Alex Elder + +description: + The SpacemiT K1 SoC implements a SPI controller that has two 32-entry + FIFOs, for transmit and receive. Details are currently available in + section 18.2.1 of the K1 User Manual, found in the SpacemiT Keystone + K1 Documentation[1]. The controller transfers words using PIO. DMA + transfers are supported as well, if both TX and RX DMA channels are + specified, + + [1] https://developer.spacemit.com/documentation + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: spacemit,k1-spi + + reg: + maxItems: 1 + + clocks: + items: + - description: Core clock + - description: Bus clock + + clock-names: + items: + - const: core + - const: bus + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + dmas: + items: + - description: RX DMA channel + - description: TX DMA channel + + dma-names: + items: + - const: rx + - const: tx + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - interrupts + +unevaluatedProperties: false + +examples: + - | + + #include + spi@d401c000 { + compatible = "spacemit,k1-spi"; + reg = <0xd401c000 0x30>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&syscon_apbc CLK_SSP3>, + <&syscon_apbc CLK_SSP3_BUS>; + clock-names = "core", "bus"; + resets = <&syscon_apbc RESET_SSP3>; + interrupts = <55>; + dmas = <&pdma 20>, <&pdma 19>; + dma-names = "rx", "tx"; + }; diff --git a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml index 472e92974714b2..6d7d595e4ab312 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32-spi.yaml @@ -89,12 +89,10 @@ properties: - const: rxm2m sram: - $ref: /schemas/types.yaml#/definitions/phandle - description: | - Phandles to a reserved SRAM region which is used as temporary - storage memory between DMA and MDMA engines. - The region should be defined as child node of the AHB SRAM node - as per the generic bindings in Documentation/devicetree/bindings/sram/sram.yaml + maxItems: 1 + description: + SRAM region which is used as temporary storage memory between DMA and + MDMA engines. power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml b/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml index 272bc308726b2d..b6be47f67fcb5d 100644 --- a/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml +++ b/Documentation/devicetree/bindings/spi/st,stm32mp25-ospi.yaml @@ -49,8 +49,9 @@ properties: description: configure OCTOSPI delay block. $ref: /schemas/types.yaml#/definitions/phandle-array items: - - description: phandle to syscfg - - description: register offset within syscfg + - items: + - description: phandle to syscfg + - description: register offset within syscfg access-controllers: description: phandle to the rifsc device to check access right diff --git a/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml b/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml index 3b5005b96c6d5d..1593a1183a367b 100644 --- a/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml +++ b/Documentation/devicetree/bindings/spmi/qcom,glymur-spmi-pmic-arb.yaml @@ -25,6 +25,7 @@ properties: oneOf: - items: - enum: + - qcom,hawi-spmi-pmic-arb - qcom,kaanapali-spmi-pmic-arb - const: qcom,glymur-spmi-pmic-arb - enum: diff --git a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml index e7f7cf72719ea8..6e6ab2168a2a28 100644 --- a/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml +++ b/Documentation/devicetree/bindings/sram/allwinner,sun4i-a10-system-control.yaml @@ -80,6 +80,7 @@ patternProperties: - const: allwinner,sun4i-a10-sram-c1 - const: allwinner,sun4i-a10-sram-d - const: allwinner,sun50i-a64-sram-c + - const: allwinner,sun50i-h616-ve-sram - items: - enum: - allwinner,sun5i-a13-sram-a3-a4 @@ -103,7 +104,9 @@ patternProperties: - allwinner,sun7i-a20-sram-d - const: allwinner,sun4i-a10-sram-d - items: - - const: allwinner,sun50i-h6-sram-c + - enum: + - allwinner,sun50i-h6-sram-c + - allwinner,sun50i-h616-sram-c - const: allwinner,sun50i-a64-sram-c required: diff --git a/Documentation/devicetree/bindings/sram/sram-consumer.yaml b/Documentation/devicetree/bindings/sram/sram-consumer.yaml new file mode 100644 index 00000000000000..f00087bd2879b9 --- /dev/null +++ b/Documentation/devicetree/bindings/sram/sram-consumer.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sram/sram-consumer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SRAM Consumers + +maintainers: + - Rob Herring + +select: true + +properties: + sram: + description: + Phandles to one or more reserved on-chip SRAM regions. The regions + should be defined as child nodes of the respective SRAM node, and + should be defined as per the generic bindings in, + Documentation/devicetree/bindings/sram/sram.yaml + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + maxItems: 1 + +additionalProperties: true +... diff --git a/Documentation/devicetree/bindings/sram/sram.yaml b/Documentation/devicetree/bindings/sram/sram.yaml index 8985f89170beb0..eb695698a03e44 100644 --- a/Documentation/devicetree/bindings/sram/sram.yaml +++ b/Documentation/devicetree/bindings/sram/sram.yaml @@ -34,6 +34,7 @@ properties: - nvidia,tegra186-sysram - nvidia,tegra194-sysram - nvidia,tegra234-sysram + - qcom,eliza-imem - qcom,hawi-imem - qcom,kaanapali-imem - qcom,milos-imem @@ -83,6 +84,7 @@ patternProperties: - allwinner,sun4i-a10-sram-d - allwinner,sun9i-a80-smp-sram - allwinner,sun50i-a64-sram-c + - allwinner,sun50i-h616-ve-sram - amlogic,meson8-ao-arc-sram - amlogic,meson8b-ao-arc-sram - amlogic,meson8-smp-sram diff --git a/Documentation/devicetree/bindings/submitting-patches.rst b/Documentation/devicetree/bindings/submitting-patches.rst index 81e27e50f9057d..2a5533f68830b5 100644 --- a/Documentation/devicetree/bindings/submitting-patches.rst +++ b/Documentation/devicetree/bindings/submitting-patches.rst @@ -64,9 +64,10 @@ I. For patch submitters 7) DTS is treated in general as driver-independent hardware description, thus any DTS patches, regardless whether using existing or new bindings, should - be placed at the end of patchset to indicate no dependency of drivers on - the DTS. DTS will be anyway applied through separate tree or branch, so - different order would indicate the series is non-bisectable. + be a separate posting or, when combined with driver patches, placed at the + end of the patchset to indicate no dependency of drivers on the DTS. DTS + will be anyway applied through separate tree or branch, so different order + would indicate the series is non-bisectable. If a driver subsystem maintainer prefers to apply entire set, instead of their relevant portion of patchset, please split the DTS patches into diff --git a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml index 70b273271754b9..8cfa44dcda58cf 100644 --- a/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/amlogic,thermal.yaml @@ -21,7 +21,9 @@ properties: - amlogic,g12a-cpu-thermal - amlogic,g12a-ddr-thermal - const: amlogic,g12a-thermal - - const: amlogic,a1-cpu-thermal + - enum: + - amlogic,a1-cpu-thermal + - amlogic,t7-thermal reg: maxItems: 1 @@ -42,12 +44,34 @@ properties: '#thermal-sensor-cells': const: 0 + amlogic,secure-monitor: + description: phandle to the secure monitor + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the secure monitor + - description: sensor index to get specific calibration data + required: - compatible - reg - interrupts - clocks - - amlogic,ao-secure + +allOf: + - if: + properties: + compatible: + contains: + enum: + - amlogic,a1-cpu-thermal + - amlogic,g12a-thermal + then: + required: + - amlogic,ao-secure + else: + required: + - amlogic,secure-monitor unevaluatedProperties: false @@ -62,4 +86,16 @@ examples: #thermal-sensor-cells = <0>; amlogic,ao-secure = <&sec_AO>; }; + - | + #include + #include + + temperature-sensor@20000 { + compatible = "amlogic,t7-thermal"; + reg = <0x20000 0x50>; + interrupts = ; + clocks = <&clkc_periphs CLKID_TS>; + #thermal-sensor-cells = <0>; + amlogic,secure-monitor = <&sm 1>; + }; ... diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 7d34ba00e684fc..f0efaa8349ee58 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -56,8 +56,10 @@ properties: - enum: - qcom,eliza-tsens - qcom,glymur-tsens + - qcom,hawi-tsens - qcom,kaanapali-tsens - qcom,milos-tsens + - qcom,nord-tsens - qcom,msm8953-tsens - qcom,msm8996-tsens - qcom,msm8998-tsens @@ -74,6 +76,7 @@ properties: - qcom,sdm630-tsens - qcom,sdm670-tsens - qcom,sdm845-tsens + - qcom,shikra-tsens - qcom,sm6115-tsens - qcom,sm6350-tsens - qcom,sm6375-tsens diff --git a/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml b/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml index aa756dae512a2c..f3b136f5e1cba1 100644 --- a/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/qoriq-thermal.yaml @@ -25,6 +25,7 @@ properties: enum: - fsl,qoriq-tmu - fsl,imx8mq-tmu + - fsl,imx93-tmu reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml new file mode 100644 index 00000000000000..6dad76a7dd3613 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/spacemit,k1-tsensor.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/spacemit,k1-tsensor.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 Thermal Sensor + +description: + The SpacemiT K1 Thermal Sensor monitors the temperature of the SoC + using multiple internal sensors (e.g., soc, package, gpu, clusters). + +maintainers: + - Shuwei Wu + +$ref: thermal-sensor.yaml# + +properties: + compatible: + const: spacemit,k1-tsensor + + reg: + maxItems: 1 + + clocks: + items: + - description: Core clock for thermal sensor + - description: Bus clock for thermal sensor + + clock-names: + items: + - const: core + - const: bus + + interrupts: + maxItems: 1 + + resets: + items: + - description: Reset for the thermal sensor + + "#thermal-sensor-cells": + const: 1 + description: + The first cell indicates the sensor ID. + 0 = soc + 1 = package + 2 = gpu + 3 = cluster0 + 4 = cluster1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - resets + - "#thermal-sensor-cells" + +additionalProperties: false + +examples: + - | + #include + + thermal@d4018000 { + compatible = "spacemit,k1-tsensor"; + reg = <0xd4018000 0x100>; + clocks = <&syscon_apbc CLK_TSEN>, + <&syscon_apbc CLK_TSEN_BUS>; + clock-names = "core", "bus"; + interrupts = <61>; + resets = <&syscon_apbc RESET_TSEN>; + #thermal-sensor-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml b/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml index b9022f1613d815..28f5818f1e60c3 100644 --- a/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml +++ b/Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml @@ -44,10 +44,14 @@ select: true properties: "#cooling-cells": description: - Must be 2, in order to specify minimum and maximum cooling state used in + Must be 2 or 3. If 2, specifies minimum and maximum cooling state used in the cooling-maps reference. The first cell is the minimum cooling state and the second cell is the maximum cooling state requested. - const: 2 + If 3, the first cell specifies the thermal mitigation device specifier + index for devices that support multiple thermal mitigation mechanisms. + The two other cells are respectively the minimum cooling state and the + maximum cooling state. + enum: [2, 3] additionalProperties: true diff --git a/Documentation/devicetree/bindings/thermal/thermal-zones.yaml b/Documentation/devicetree/bindings/thermal/thermal-zones.yaml index 07d9f576ffe7b6..999ad40a20d5ca 100644 --- a/Documentation/devicetree/bindings/thermal/thermal-zones.yaml +++ b/Documentation/devicetree/bindings/thermal/thermal-zones.yaml @@ -211,7 +211,8 @@ patternProperties: device. Using the THERMAL_NO_LIMIT (-1UL) constant in the cooling-device phandle limit specifier lets the framework use the minimum and maximum cooling state for that cooling - device automatically. + device automatically. If three arguments are specified, + the first argument is the cooling device specifier. contribution: $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml index f1853daec2f9ad..3e2725c5699532 100644 --- a/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml +++ b/Documentation/devicetree/bindings/timer/allwinner,sun5i-a13-hstimer.yaml @@ -15,9 +15,13 @@ properties: oneOf: - const: allwinner,sun5i-a13-hstimer - const: allwinner,sun7i-a20-hstimer + - const: allwinner,sun20i-d1-hstimer - items: - const: allwinner,sun6i-a31-hstimer - const: allwinner,sun7i-a20-hstimer + - items: + - const: allwinner,sun50i-h616-hstimer + - const: allwinner,sun20i-d1-hstimer reg: maxItems: 1 @@ -45,7 +49,10 @@ required: if: properties: compatible: - const: allwinner,sun5i-a13-hstimer + anyOf: + - const: allwinner,sun5i-a13-hstimer + - contains: + const: allwinner,sun20i-d1-hstimer then: properties: diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml index c5fc3b6c8bd0bf..c65e48a155ab6e 100644 --- a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml +++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml @@ -10,13 +10,8 @@ maintainers: - Marc Zyngier - Mark Rutland description: |+ - ARM cores may have a per-core architected timer, which provides per-cpu timers, - or a memory mapped architected timer, which provides up to 8 frames with a - physical and optional virtual timer per frame. - - The per-core architected timer is attached to a GIC to deliver its - per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC - to deliver its interrupts via SPIs. + The per-core architected timer is expected to deliver per-CPU interrupts + (commonly to a GIC to deliver its per-processor interrupts as PPIs). properties: compatible: @@ -33,13 +28,13 @@ properties: - const: arm,armv7-timer interrupts: - minItems: 1 + minItems: 2 items: - - description: secure timer irq - - description: non-secure timer irq - - description: virtual timer irq - - description: hypervisor timer irq - - description: hypervisor virtual timer irq + - description: EL1 secure physical timer irq, if EL3 is implemented + - description: EL1 non-secure physical timer irq + - description: EL1 virtual timer irq + - description: EL2 physical timer irq, if EL2 is implemented + - description: EL2 virtual timer irq, if FEAT_VHE is implemented interrupt-names: oneOf: diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml index 9898dc7ea97be4..6d41fb12037934 100644 --- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml +++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml @@ -14,6 +14,7 @@ properties: oneOf: - const: fsl,imx1-gpt - const: fsl,imx21-gpt + - const: fsl,imx25-epit - items: - const: fsl,imx27-gpt - const: fsl,imx21-gpt diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml index 3ad10c5b66ba54..ecff2912d812b8 100644 --- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml @@ -112,6 +112,8 @@ properties: - renesas,r9a07g043-mtu3 # RZ/{G2UL,Five} - renesas,r9a07g044-mtu3 # RZ/G2{L,LC} - renesas,r9a07g054-mtu3 # RZ/V2L + - renesas,r9a09g077-mtu3 # RZ/T2H + - renesas,r9a09g087-mtu3 # RZ/N2H - const: renesas,rz-mtu3 reg: @@ -162,7 +164,6 @@ properties: - description: MTU8.TGRC input capture/compare match - description: MTU8.TGRD input capture/compare match - description: MTU8.TCNT overflow - - description: MTU8.TCNT underflow interrupt-names: items: @@ -209,7 +210,6 @@ properties: - const: tgic8 - const: tgid8 - const: tciv8 - - const: tciu8 clocks: maxItems: 1 @@ -233,7 +233,22 @@ required: - interrupt-names - clocks - power-domains - - resets + +allOf: + - if: + properties: + compatible: + contains: + enum: + - renesas,r9a07g043-mtu3 + - renesas,r9a07g044-mtu3 + - renesas,r9a07g054-mtu3 + then: + required: + - resets + else: + properties: + resets: false additionalProperties: false @@ -287,8 +302,7 @@ examples: , , , - , - ; + ; interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tciv0", "tgie0", "tgif0", "tgia1", "tgib1", "tciv1", "tciu1", @@ -298,7 +312,7 @@ examples: "tgiu5", "tgiv5", "tgiw5", "tgia6", "tgib6", "tgic6", "tgid6", "tciv6", "tgia7", "tgib7", "tgic7", "tgid7", "tciv7", - "tgia8", "tgib8", "tgic8", "tgid8", "tciv8", "tciu8"; + "tgia8", "tgib8", "tgic8", "tgid8", "tciv8"; clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; power-domains = <&cpg>; resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml index 3c16b260db040d..105e3ef539e6fd 100644 --- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml +++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml @@ -38,6 +38,7 @@ properties: - starfive,jh7100-clint # StarFive JH7100 - starfive,jh7110-clint # StarFive JH7110 - starfive,jh8100-clint # StarFive JH8100 + - starfive,jhb100-clint # StarFive JHB100 - tenstorrent,blackhole-clint # Tenstorrent Blackhole - const: sifive,clint0 # SiFive CLINT v0 IP block - items: @@ -51,6 +52,7 @@ properties: - allwinner,sun20i-d1-clint - sophgo,cv1800b-clint - sophgo,cv1812h-clint + - sophgo,sg2000-clint - sophgo,sg2002-clint - thead,th1520-clint - const: thead,c900-clint @@ -72,22 +74,6 @@ properties: minItems: 1 maxItems: 4095 - sifive,fine-ctr-bits: - maximum: 15 - description: The width in bits of the fine counter. - -if: - properties: - compatible: - contains: - const: sifive,clint2 -then: - required: - - sifive,fine-ctr-bits -else: - properties: - sifive,fine-ctr-bits: false - additionalProperties: false required: diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index 23fd4513933a4c..435c4baab43652 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -67,8 +67,10 @@ properties: - arduino,unoq-mcu # Temperature monitoring of Astera Labs PT5161L PCIe retimer - asteralabs,pt5161l - # i2c h/w elliptic curve crypto module + # ATECC508A - i2c h/w elliptic curve crypto module - atmel,atecc508a + # ATECC608B - i2c h/w elliptic curve crypto module + - atmel,atecc608b # ATSHA204 - i2c h/w symmetric crypto module - atmel,atsha204 # ATSHA204A - i2c h/w symmetric crypto module @@ -99,6 +101,8 @@ properties: - delta,dps800 # Delta Electronics DPS920AB 920W 54V Power Supply - delta,dps920ab + # 600W Non-isolated 1/8th Brick DC/DC Power Modules + - delta,e50sn12051 # 1/4 Brick DC/DC Regulated Power Module - delta,q54sj108a2 # 1300W 1/4 Brick DC/DC Regulated Power Module @@ -127,6 +131,8 @@ properties: - domintech,dmard09 # DMARD10: 3-axis Accelerometer - domintech,dmard10 + # Freescale 2.4 GHz IEEE® 802.15.4/ZigBee + - fsl,mc1323 # MMA7660FC: 3-Axis Orientation/Motion Detection Sensor - fsl,mma7660 # MMA8450Q: Xtrinsic Low-power, 3-axis Xtrinsic Accelerometer @@ -192,6 +198,8 @@ properties: - jedec,spd5118 # Linear Technology LTC2488 - lineartechnology,ltc2488 + # Regulated 12V, 860W, Digital DC/DC Power Module + - luxshare,lx1308 # 5 Bit Programmable, Pulse-Width Modulator - maxim,ds1050 # 10 kOhm digital potentiometer with I2C interface @@ -336,6 +344,8 @@ properties: - mps,mp29612 # Monolithic Power Systems Inc. multi-phase controller mp29816 - mps,mp29816 + # Monolithic Power Systems Inc. multi-phase controller mp2985 + - mps,mp2985 # Monolithic Power Systems Inc. multi-phase controller mp2993 - mps,mp2993 # Monolithic Power Systems Inc. hot-swap protection device @@ -352,6 +362,8 @@ properties: - mps,mp9941 # Monolithic Power Systems Inc. digital step-down converter mp9945 - mps,mp9945 + # Murata D1U74T-W power supply unit + - murata,d1u74t # Temperature sensor with integrated fan control - national,lm63 # Temperature sensor with integrated fan control diff --git a/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml index 75fae9f1eba7e3..db165a235cb6d8 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,sa8255p-ufshc.yaml @@ -11,7 +11,11 @@ maintainers: properties: compatible: - const: qcom,sa8255p-ufshc + oneOf: + - const: qcom,sa8255p-ufshc + - items: + - const: qcom,sa8797p-ufshc + - const: qcom,sa8255p-ufshc reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml b/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml index f28641c6e68fea..b441f0d26081d9 100644 --- a/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml +++ b/Documentation/devicetree/bindings/ufs/qcom,sm8650-ufshc.yaml @@ -16,7 +16,9 @@ select: contains: enum: - qcom,eliza-ufshc + - qcom,hawi-ufshc - qcom,kaanapali-ufshc + - qcom,nord-ufshc - qcom,sm8650-ufshc - qcom,sm8750-ufshc required: @@ -27,7 +29,9 @@ properties: items: - enum: - qcom,eliza-ufshc + - qcom,hawi-ufshc - qcom,kaanapali-ufshc + - qcom,nord-ufshc - qcom,sm8650-ufshc - qcom,sm8750-ufshc - const: qcom,ufshc @@ -74,6 +78,7 @@ allOf: contains: enum: - qcom,eliza-ufshc + - qcom,nord-ufshc then: properties: reg: diff --git a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml index a7eb7ad85a94e5..710ce493f3b67a 100644 --- a/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml +++ b/Documentation/devicetree/bindings/ufs/samsung,exynos-ufs.yaml @@ -19,6 +19,7 @@ properties: - samsung,exynos7-ufs - samsung,exynosautov9-ufs - samsung,exynosautov9-ufs-vh + - samsung,exynosautov920-ufs - tesla,fsd-ufs reg: diff --git a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml index a199e5ba641612..e8082c5c05a258 100644 --- a/Documentation/devicetree/bindings/usb/cdns,usb3.yaml +++ b/Documentation/devicetree/bindings/usb/cdns,usb3.yaml @@ -4,29 +4,37 @@ $id: http://devicetree.org/schemas/usb/cdns,usb3.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Cadence USBSS-DRD controller +title: Cadence USBSS and USBSSP DRD controller maintainers: - Pawel Laszczak +description: + Cadence USB dual-role controller. Covers USBSS (SuperSpeed, USB 3.0) and + USBSSP (SuperSpeed Plus, USB 3.1 gen2x1). Both variants share the same + DRD/OTG register interface, so the driver auto-detects the controller + version at runtime. + properties: compatible: - const: cdns,usb3 + oneOf: + - const: cdns,usb3 + - items: + - {} + - const: cdns,cdnsp reg: - items: - - description: OTG controller registers - - description: XHCI Host controller registers - - description: DEVICE controller registers + minItems: 2 + maxItems: 3 reg-names: + minItems: 2 + maxItems: 3 items: - - const: otg - - const: xhci - - const: dev + enum: [ otg, xhci, dev ] interrupts: - minItems: 3 + minItems: 2 items: - description: XHCI host controller interrupt - description: Device controller interrupt @@ -35,7 +43,7 @@ properties: cleared by xhci core, this interrupt is optional interrupt-names: - minItems: 3 + minItems: 2 items: - const: host - const: peripheral @@ -49,7 +57,7 @@ properties: cdns3 to type C connector. maximum-speed: - enum: [super-speed, high-speed, full-speed] + enum: [super-speed-plus, super-speed, high-speed, full-speed] phys: minItems: 1 @@ -87,6 +95,47 @@ allOf: - $ref: usb-drd.yaml# - $ref: usb-xhci.yaml# + - if: + properties: + compatible: + contains: + const: cdns,cdnsp + then: + properties: + reg: + items: + - description: XHCI Host controller registers + - description: DEVICE controller registers + reg-names: + items: + - const: xhci + - const: dev + interrupts: + maxItems: 2 + interrupt-names: + items: + - const: host + - const: peripheral + dr_mode: + enum: [host, peripheral] + else: + properties: + reg: + items: + - description: OTG controller registers + - description: XHCI Host controller registers + - description: DEVICE controller registers + reg-names: + items: + - const: otg + - const: xhci + - const: dev + interrupts: + minItems: 3 + maxItems: 4 + interrupt-names: + minItems: 3 + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/usb/chipidea,usb2-common.yaml b/Documentation/devicetree/bindings/usb/chipidea,usb2-common.yaml index 10020af15afc4a..e6a5e79df34841 100644 --- a/Documentation/devicetree/bindings/usb/chipidea,usb2-common.yaml +++ b/Documentation/devicetree/bindings/usb/chipidea,usb2-common.yaml @@ -97,7 +97,9 @@ properties: minItems: 1 items: - description: vbus extcon + maxItems: 1 - description: id extcon + maxItems: 1 phy-clkgate-delay-us: description: diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml index 691d6cf02c2724..620b564914d43c 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.yaml @@ -45,11 +45,11 @@ properties: clocks: minItems: 1 - maxItems: 2 + maxItems: 3 clock-names: minItems: 1 - maxItems: 2 + maxItems: 3 operating-points-v2: description: A phandle to the OPP table containing the performance states. @@ -61,9 +61,10 @@ properties: offset, and phy index $ref: /schemas/types.yaml#/definitions/phandle-array items: - - description: phandle to TCSR node - - description: register offset - - description: phy index + - items: + - description: phandle to TCSR node + - description: register offset + - description: phy index nvidia,phy: description: phandle of usb phy that connects to the port. Use "phys" instead. @@ -91,6 +92,27 @@ allOf: - $ref: chipidea,usb2-common.yaml# - $ref: usb-hcd.yaml# - $ref: usb-drd.yaml# + - if: + properties: + compatible: + contains: + const: qcom,ci-hdrc + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + items: + - const: iface + - const: core + - const: fs + else: + properties: + clocks: + maxItems: 2 + clock-names: + maxItems: 2 unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml b/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml index 9a94b2a74a1eb2..e8b8c03f87a0ed 100644 --- a/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml +++ b/Documentation/devicetree/bindings/usb/genesys,gl850g.yaml @@ -15,6 +15,7 @@ properties: - usb5e3,608 - usb5e3,610 - usb5e3,620 + - usb5e3,625 - usb5e3,626 reg: true @@ -26,6 +27,10 @@ properties: description: The regulator that provides 3.3V or 5.0V core power to the hub. + vdd12-supply: + description: + The regulator that provides 1.2V power to the hub. + peer-hub: true ports: @@ -56,6 +61,7 @@ allOf: properties: peer-hub: false vdd-supply: false + vdd12-supply: false - if: properties: @@ -68,6 +74,18 @@ allOf: properties: peer-hub: true vdd-supply: true + vdd12-supply: false + + - if: + properties: + compatible: + contains: + enum: + - usb5e3,625 + then: + properties: + peer-hub: true + vdd-supply: true unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml b/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml index 6d3fa2bc9ceec3..ba790c4488b767 100644 --- a/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml +++ b/Documentation/devicetree/bindings/usb/qcom,pmic-typec.yaml @@ -79,22 +79,17 @@ properties: - const: fr-swap vdd-vbus-supply: - description: VBUS power supply. + deprecated: true + description: use connector/vbus-supply instead. vdd-pdphy-supply: description: VDD regulator supply to the PDPHY. - port: - $ref: /schemas/graph.yaml#/properties/port - description: - Contains a port which produces data-role switching messages. - required: - compatible - reg - interrupts - interrupt-names - - vdd-vbus-supply allOf: - if: diff --git a/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt b/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt deleted file mode 100644 index 6f8115db2ea9b1..00000000000000 --- a/Documentation/devicetree/bindings/usb/richtek,rt1711h.txt +++ /dev/null @@ -1,44 +0,0 @@ -Richtek RT1711H TypeC PD Controller. - -Required properties: - - compatible : Must be "richtek,rt1711h". - - reg : Must be 0x4e, it's slave address of RT1711H. - - interrupts : where a is the interrupt number and b represents an - encoding of the sense and level information for the interrupt. - -Required sub-node: -- connector: The "usb-c-connector" attached to the tcpci chip, the bindings - of connector node are specified in - Documentation/devicetree/bindings/connector/usb-connector.yaml - -Example : -rt1711h@4e { - compatible = "richtek,rt1711h"; - reg = <0x4e>; - interrupt-parent = <&gpio26>; - interrupts = <0 IRQ_TYPE_LEVEL_LOW>; - - usb_con: connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - power-role = "dual"; - try-power-role = "sink"; - source-pdos = ; - sink-pdos = ; - op-sink-microwatt = <10000000>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@1 { - reg = <1>; - usb_con_ss: endpoint { - remote-endpoint = <&usb3_data_ss>; - }; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml b/Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml index 7ded3638451841..e3357f5abe2b1f 100644 --- a/Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml +++ b/Documentation/devicetree/bindings/usb/richtek,rt1711h.yaml @@ -43,8 +43,7 @@ properties: vbus-supply: description: VBUS power supply - wakeup-source: - type: boolean + wakeup-source: true connector: type: object diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml index fd1b13c0ed6bb3..0554dbc4b85413 100644 --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml @@ -26,6 +26,7 @@ select: contains: enum: - rockchip,rk3328-dwc3 + - rockchip,rk3528-dwc3 - rockchip,rk3562-dwc3 - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 @@ -38,6 +39,7 @@ properties: items: - enum: - rockchip,rk3328-dwc3 + - rockchip,rk3528-dwc3 - rockchip,rk3562-dwc3 - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 @@ -135,6 +137,7 @@ allOf: compatible: contains: enum: + - rockchip,rk3528-dwc3 - rockchip,rk3568-dwc3 - rockchip,rk3576-dwc3 then: diff --git a/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml b/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml index 653a89586f4e9b..0aaaadb584e46f 100644 --- a/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml +++ b/Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml @@ -88,7 +88,7 @@ examples: power-domains = <&k3_pds 288 TI_SCI_PD_EXCLUSIVE>; clocks = <&k3_clks 288 15>, <&k3_clks 288 3>; clock-names = "ref", "lpm"; - assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ + assigned-clocks = <&k3_clks 288 15>; /* USB2_REFCLK */ assigned-clock-parents = <&k3_clks 288 16>; /* HFOSC0 */ #address-cells = <2>; #size-cells = <2>; @@ -99,9 +99,9 @@ examples: <0x00 0x6010000 0x00 0x10000>, <0x00 0x6020000 0x00 0x10000>; reg-names = "otg", "xhci", "dev"; - interrupts = , /* irq.0 */ - , /* irq.6 */ - ; /* otgirq.0 */ + interrupts = , /* irq.0 */ + , /* irq.6 */ + ; /* otgirq.0 */ interrupt-names = "host", "peripheral", "otg"; diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 28784d66ae7ba5..396044f368e7cf 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -437,6 +437,8 @@ patternProperties: description: Diodes, Inc. "^dioo,.*": description: Dioo Microcircuit Co., Ltd + "^displaytech,.*": + description: Displaytech Ltd. "^djn,.*": description: Shenzhen DJN Optronics Technology Co., Ltd "^dlc,.*": @@ -489,6 +491,8 @@ patternProperties: description: Emtop Embedded Solutions "^eeti,.*": description: eGalax_eMPIA Technology Inc + "^efinix,.*": + description: Efinix, Inc. "^egnite,.*": description: egnite GmbH "^einfochips,.*": @@ -656,6 +660,8 @@ patternProperties: description: Giantec Semiconductor, Inc. "^giantplus,.*": description: Giantplus Technology Co., Ltd. + "^gira,.*": + description: Gira Giersiepen GmbH & Co. KG "^glinet,.*": description: GL Intelligence, Inc. "^globalscale,.*": @@ -981,6 +987,8 @@ patternProperties: description: Shenzhen Luckfox Technology Co., Ltd. "^lunzn,.*": description: Shenzhen Lunzn Technology Co., Ltd. + "^luxshare,.*": + description: Luxshare-ICT Co., Ltd. "^luxul,.*": description: Lagrand | AV "^lwn,.*": @@ -1783,6 +1791,8 @@ patternProperties: description: Variscite Ltd. "^vdl,.*": description: Van der Laan b.v. + "^verbatim,.*": + description: Verbatim Corporation "^verisilicon,.*": description: VeriSilicon Microelectronics (Shanghai) Co., Ltd. "^vertexcom,.*": diff --git a/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml b/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml new file mode 100644 index 00000000000000..f1107c5527887c --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/andestech,ae350-wdt.yaml @@ -0,0 +1,53 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/andestech,ae350-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Andes ATCWDT200 Watchdog Timer + +maintainers: + - CL Wang + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - items: + - enum: + - andestech,qilai-wdt + - const: andestech,ae350-wdt + - const: andestech,ae350-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + andestech,clock-source: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + Select the clock source for the watchdog timer. + 0 - External clock + 1 - P clock + +required: + - compatible + - reg + - clocks + - andestech,clock-source + +unevaluatedProperties: false + +examples: + - | + watchdog@f0500000 { + compatible = "andestech,ae350-wdt"; + reg = <0xf0500000 0x20>; + clocks = <&clk_wdt>; + andestech,clock-source = <0>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml index 05602678c070d7..845b5e8b5abc33 100644 --- a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml @@ -16,7 +16,9 @@ properties: compatible: oneOf: - items: - - const: apple,t6020-wdt + - enum: + - apple,t6020-wdt + - apple,t8122-wdt - const: apple,t8103-wdt - items: - enum: diff --git a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml index 0821ba0e84a3ca..872a8471ef65fe 100644 --- a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml @@ -18,12 +18,7 @@ allOf: properties: compatible: - oneOf: - - items: - - enum: - - kontron,sa67mcu-wdt - - const: kontron,sl28cpld-wdt - - const: kontron,sl28cpld-wdt + const: kontron,sl28cpld-wdt reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml index 9f861045b71e83..74117f5726a77b 100644 --- a/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml @@ -18,15 +18,19 @@ properties: - items: - enum: - qcom,apss-wdt-glymur + - qcom,apss-wdt-hawi - qcom,kpss-wdt-ipq4019 - qcom,apss-wdt-ipq5018 + - qcom,apss-wdt-ipq5210 - qcom,apss-wdt-ipq5332 - qcom,apss-wdt-ipq5424 - qcom,apss-wdt-ipq9574 + - qcom,apss-wdt-ipq9650 - qcom,apss-wdt-kaanapali - qcom,apss-wdt-msm8226 - qcom,apss-wdt-msm8974 - qcom,apss-wdt-msm8994 + - qcom,apss-wdt-nord - qcom,apss-wdt-qcm2290 - qcom,apss-wdt-qcs404 - qcom,apss-wdt-qcs615 @@ -40,6 +44,7 @@ properties: - qcom,apss-wdt-sdm845 - qcom,apss-wdt-sdx55 - qcom,apss-wdt-sdx65 + - qcom,apss-wdt-shikra - qcom,apss-wdt-sm6115 - qcom,apss-wdt-sm6350 - qcom,apss-wdt-sm8150 @@ -84,6 +89,12 @@ properties: minItems: 1 maxItems: 5 + sram: + maxItems: 1 + description: + A reference to an region residing in IMEM(on-chip SRAM), which contains + the system restart reason value populated by the bootloader. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml index 099200c4f1364f..975c5aa4d747f5 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,r9a09g057-wdt.yaml @@ -89,11 +89,11 @@ examples: - | #include - watchdog@11c00400 { + watchdog@14400000 { compatible = "renesas,r9a09g057-wdt"; - reg = <0x11c00400 0x400>; - clocks = <&cpg CPG_MOD 0x4b>, <&cpg CPG_MOD 0x4c>; + reg = <0x14400000 0x400>; + clocks = <&cpg CPG_MOD 0x4d>, <&cpg CPG_MOD 0x4e>; clock-names = "pclk", "oscclk"; - resets = <&cpg 0x75>; + resets = <&cpg 0x76>; power-domains = <&cpg>; }; diff --git a/Documentation/devicetree/bindings/watchdog/renesas,rzg2l-wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,rzg2l-wdt.yaml index a4d06c9c8b86b6..40b4fb26d9c578 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,rzg2l-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,rzg2l-wdt.yaml @@ -18,6 +18,7 @@ properties: - renesas,r9a07g044-wdt # RZ/G2{L,LC} - renesas,r9a07g054-wdt # RZ/V2L - renesas,r9a08g045-wdt # RZ/G3S + - renesas,r9a08g046-wdt # RZ/G3L - const: renesas,rzg2l-wdt - items: diff --git a/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml b/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml index 7e3ee533cd568f..0e4b5b529e9c55 100644 --- a/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/renesas,rzn1-wdt.yaml @@ -29,7 +29,6 @@ properties: required: - compatible - reg - - interrupts - clocks allOf: diff --git a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml b/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml index 609e98cdaaffdd..9d25f5e497e238 100644 --- a/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/snps,dw-wdt.yaml @@ -29,10 +29,12 @@ properties: - rockchip,rk3368-wdt - rockchip,rk3399-wdt - rockchip,rk3506-wdt + - rockchip,rk3528-wdt - rockchip,rk3562-wdt - rockchip,rk3568-wdt - rockchip,rk3576-wdt - rockchip,rk3588-wdt + - rockchip,rv1103b-wdt - rockchip,rv1108-wdt - rockchip,rv1126-wdt - const: snps,dw-wdt diff --git a/Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml b/Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml new file mode 100644 index 00000000000000..5c2541ac60cf3b --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/technologic,ts4800-wdt.yaml @@ -0,0 +1,40 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/technologic,ts4800-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Technologic Systems TS-4800 Watchdog + +maintainers: + - Eduard Bostina + +properties: + compatible: + const: technologic,ts4800-wdt + + syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: Phandle to the FPGA's syscon + - description: Offset to the watchdog register + description: Phandle / integers array that points to the syscon node which + describes the FPGA's syscon registers. + +required: + - compatible + - syscon + +allOf: + - $ref: watchdog.yaml# + +unevaluatedProperties: false + +examples: + - | + watchdog { + compatible = "technologic,ts4800-wdt"; + syscon = <&syscon 0xe>; + timeout-sec = <10>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml b/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml index 62ddc284a524ce..2966e5bfb6c09a 100644 --- a/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/ti,rti-wdt.yaml @@ -23,6 +23,7 @@ allOf: properties: compatible: enum: + - ti,am62l-rti-wdt - ti,j7-rti-wdt reg: diff --git a/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt b/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt deleted file mode 100644 index 8f6caad4258d15..00000000000000 --- a/Documentation/devicetree/bindings/watchdog/ts4800-wdt.txt +++ /dev/null @@ -1,25 +0,0 @@ -Technologic Systems Watchdog - -Required properties: -- compatible: must be "technologic,ts4800-wdt" -- syscon: phandle / integer array that points to the syscon node which - describes the FPGA's syscon registers. - - phandle to FPGA's syscon - - offset to the watchdog register - -Optional property: -- timeout-sec: contains the watchdog timeout in seconds. - -Example: - -syscon: syscon@b0010000 { - compatible = "syscon", "simple-mfd"; - reg = <0xb0010000 0x3d>; - reg-io-width = <2>; - - wdt@e { - compatible = "technologic,ts4800-wdt"; - syscon = <&syscon 0xe>; - timeout-sec = <10>; - }; -} diff --git a/Documentation/devicetree/bindings/writing-bindings.rst b/Documentation/devicetree/bindings/writing-bindings.rst index 667816dd7d5041..1a51764833a1f6 100644 --- a/Documentation/devicetree/bindings/writing-bindings.rst +++ b/Documentation/devicetree/bindings/writing-bindings.rst @@ -53,7 +53,17 @@ Properties - DON'T use wildcards or device-family names in compatible strings. - DO use fallback compatibles when devices are the same as or a superset of - prior implementations. + prior implementations. Fallback compatibles are applicable especially + when sharing a programming interface or when able to discover the + variants. + + - DON'T add fake fallback compatibles when software cannot use such to match + and bind to a device, and still operate correctly. + + - DO use the commit message to explain why devices that may appear + compatible in a diff (e.g. no differences in property use, same handling + by the software) but are not made compatible in the binding, are not + compatible. - DO add new compatibles in case there are new features or bugs. diff --git a/Documentation/devicetree/bindings/writing-schema.rst b/Documentation/devicetree/bindings/writing-schema.rst index 2ff5b0565a313d..3ffd0828617aa0 100644 --- a/Documentation/devicetree/bindings/writing-schema.rst +++ b/Documentation/devicetree/bindings/writing-schema.rst @@ -132,7 +132,7 @@ examples provider binding, other nodes referenced by phandle. Note: YAML doesn't allow leading tabs, so spaces must be used instead. -Unless noted otherwise, all properties are required. +Unless noted otherwise, all above schema properties are required. Property Schema --------------- diff --git a/Documentation/driver-api/dpll.rst b/Documentation/driver-api/dpll.rst index 93c191b2d08984..bae14766d4f7bc 100644 --- a/Documentation/driver-api/dpll.rst +++ b/Documentation/driver-api/dpll.rst @@ -65,35 +65,43 @@ request, where user provides attributes that result in single pin match. Pin selection ============= -In general, selected pin (the one which signal is driving the dpll -device) can be obtained from ``DPLL_A_PIN_STATE`` attribute, and only -one pin shall be in ``DPLL_PIN_STATE_CONNECTED`` state for any dpll -device. +Pin state (``DPLL_A_PIN_STATE``) reflects the administrative intent set +by the user. Pin operational state (``DPLL_A_PIN_OPERSTATE``) reflects +what the hardware is actually doing with the pin. Pin selection can be done either manually or automatically, depending on hardware capabilities and active dpll device work mode (``DPLL_A_MODE`` attribute). The consequence is that there are -differences for each mode in terms of available pin states, as well as -for the states the user can request for a dpll device. +differences for each mode in terms of available pin states the user can +request for a dpll device. -In manual mode (``DPLL_MODE_MANUAL``) the user can request or receive -one of following pin states: +In manual mode (``DPLL_MODE_MANUAL``) the user can request one of +following pin states: -- ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device -- ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll +- ``DPLL_PIN_STATE_CONNECTED`` - the pin is selected to drive dpll device +- ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not selected to drive + dpll device -In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can request or -receive one of following pin states: +In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can request one of +following pin states: - ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid input for automatic selection algorithm - ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as a valid input for automatic selection algorithm -In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can only receive -pin state ``DPLL_PIN_STATE_CONNECTED`` once automatic selection -algorithm locks a dpll device with one of the inputs. +The actual hardware status of a pin is reported via the operational +state (``DPLL_A_PIN_OPERSTATE``) attribute nested under the parent +device: + +- ``DPLL_PIN_OPERSTATE_ACTIVE`` - pin is qualified and actively used + by the DPLL +- ``DPLL_PIN_OPERSTATE_STANDBY`` - pin is qualified but not actively + used by the DPLL +- ``DPLL_PIN_OPERSTATE_NO_SIGNAL`` - pin does not have a valid signal +- ``DPLL_PIN_OPERSTATE_QUAL_FAILED`` - pin signal failed qualification + checks Shared pins =========== @@ -250,6 +258,26 @@ in the ``DPLL_A_PIN_PHASE_OFFSET`` attribute. ``DPLL_A_PHASE_OFFSET_MONITOR`` attr state of a feature =============================== ======================== +Fractional frequency offset +=========================== + +The fractional frequency offset (FFO) is reported through two attributes +that carry the same measurement at different precisions: + +- ``DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET`` in PPM (parts per million) +- ``DPLL_A_PIN_FRACTIONAL_FREQUENCY_OFFSET_PPT`` in PPT (parts per trillion) + +Both attributes appear at the top level of a pin and inside each +``pin-parent-device`` nest. Two FFO types are defined: + +- ``DPLL_FFO_PORT_RXTX_RATE`` - RX vs TX symbol rate offset (top-level) +- ``DPLL_FFO_PIN_DEVICE`` - pin vs parent DPLL offset (per-parent) + +The driver declares which types it supports via the ``supported_ffo`` +bitmask in ``struct dpll_pin_ops``. The core only calls the ``ffo_get`` +callback for types the driver has opted into. The requested type is +passed to the driver in the ``struct dpll_ffo_param``. + Frequency monitor ================= diff --git a/Documentation/driver-api/driver-model/platform.rst b/Documentation/driver-api/driver-model/platform.rst index cf5ff48d3115cc..9673470bded297 100644 --- a/Documentation/driver-api/driver-model/platform.rst +++ b/Documentation/driver-api/driver-model/platform.rst @@ -70,7 +70,8 @@ Kernel modules can be composed of several platform drivers. The platform core provides helpers to register and unregister an array of drivers:: int __platform_register_drivers(struct platform_driver * const *drivers, - unsigned int count, struct module *owner); + unsigned int count, struct module *owner, + const char *mod_name); void platform_unregister_drivers(struct platform_driver * const *drivers, unsigned int count); diff --git a/Documentation/driver-api/eisa.rst b/Documentation/driver-api/eisa.rst index 3563e5f7e98d6e..e98b21b608657b 100644 --- a/Documentation/driver-api/eisa.rst +++ b/Documentation/driver-api/eisa.rst @@ -1,3 +1,5 @@ +.. SPDX-License-Identifier: GPL-2.0 + ================ EISA bus support ================ diff --git a/Documentation/driver-api/iio/buffers.rst b/Documentation/driver-api/iio/buffers.rst index 63f364e862d1c9..8779022e3da503 100644 --- a/Documentation/driver-api/iio/buffers.rst +++ b/Documentation/driver-api/iio/buffers.rst @@ -37,9 +37,10 @@ directory contains attributes of the following form: * :file:`index`, the scan_index of the channel. * :file:`type`, description of the scan element data storage within the buffer and hence the form in which it is read from user space. - Format is [be|le]:[s|u]bits/storagebits[Xrepeat][>>shift] . + Format is [be|le]:[f|s|u]bits/storagebits[Xrepeat][>>shift] . * *be* or *le*, specifies big or little endian. + * *f*, specifies if floating-point. * *s* or *u*, specifies if signed (2's complement) or unsigned. * *bits*, is the number of valid data bits. * *storagebits*, is the number of bits (after padding) that it occupies in the @@ -78,7 +79,7 @@ fields in iio_chan_spec definition:: /* other members */ int scan_index struct { - char sign; + char format; u8 realbits; u8 storagebits; u8 shift; @@ -98,7 +99,7 @@ following channel definition:: /* other stuff here */ .scan_index = 0, .scan_type = { - .sign = 's', + .format = IIO_SCAN_FORMAT_SIGNED_INT, .realbits = 12, .storagebits = 16, .shift = 4, diff --git a/Documentation/driver-api/iio/triggered-buffers.rst b/Documentation/driver-api/iio/triggered-buffers.rst index 417555dbbdf4f4..23762b06fdc65a 100644 --- a/Documentation/driver-api/iio/triggered-buffers.rst +++ b/Documentation/driver-api/iio/triggered-buffers.rst @@ -29,21 +29,21 @@ A typical triggered buffer setup looks like this:: irqreturn_t sensor_trigger_handler(int irq, void *p) { - u16 buf[8]; + IIO_DECLARE_BUFFER_WITH_TS(u16, buf, 3) = { }; int i = 0; /* read data for each active channel */ - for_each_set_bit(bit, active_scan_mask, masklength) - buf[i++] = sensor_get_data(bit) + iio_for_each_active_channel(indio_dev, bit) + buf[i++] = sensor_get_data(bit); - iio_push_to_buffers_with_timestamp(indio_dev, buf, timestamp); + iio_push_to_buffers_with_ts(indio_dev, buf, sizeof(buf), timestamp); iio_trigger_notify_done(trigger); return IRQ_HANDLED; } /* setup triggered buffer, usually in probe function */ - iio_triggered_buffer_setup(indio_dev, sensor_iio_polfunc, + iio_triggered_buffer_setup(indio_dev, sensor_iio_pollfunc, sensor_trigger_handler, sensor_buffer_setup_ops); diff --git a/Documentation/driver-api/ipmi.rst b/Documentation/driver-api/ipmi.rst index f52ab2df256958..d08cee98e34a39 100644 --- a/Documentation/driver-api/ipmi.rst +++ b/Documentation/driver-api/ipmi.rst @@ -495,7 +495,7 @@ tuned to the user's desired performance. The driver supports a hot add and remove of interfaces. This way, interfaces can be added or removed after the kernel is up and running. -This is done using /sys/modules/ipmi_si/parameters/hotmod, which is a +This is done using /sys/module/ipmi_si/parameters/hotmod, which is a write-only parameter. You write a string to this interface. The string has the format:: diff --git a/Documentation/driver-api/mailbox.rst b/Documentation/driver-api/mailbox.rst index 463dd032b96cd4..d46c60bd5df64b 100644 --- a/Documentation/driver-api/mailbox.rst +++ b/Documentation/driver-api/mailbox.rst @@ -87,8 +87,8 @@ a message and a callback function to the API and return immediately). struct async_pkt ap; struct sync_pkt sp; - dc_sync = kzalloc(sizeof(*dc_sync), GFP_KERNEL); - dc_async = kzalloc(sizeof(*dc_async), GFP_KERNEL); + dc_sync = kzalloc_obj(*dc_sync); + dc_async = kzalloc_obj(*dc_async); /* Populate non-blocking mode client */ dc_async->cl.dev = &pdev->dev; diff --git a/Documentation/driver-api/media/camera-sensor.rst b/Documentation/driver-api/media/camera-sensor.rst index 94bd1dae82d5c5..c8552f70f49613 100644 --- a/Documentation/driver-api/media/camera-sensor.rst +++ b/Documentation/driver-api/media/camera-sensor.rst @@ -114,7 +114,7 @@ of the device. This is because the power state of the device is only changed after the power state transition has taken place. The ``s_ctrl`` callback can be used to obtain device's power state after the power state transition: -.. c:function:: int pm_runtime_get_if_in_use(struct device *dev); +.. c:function:: int pm_runtime_get_if_active(struct device *dev); The function returns a non-zero value if it succeeded getting the power count or runtime PM was disabled, in either of which cases the driver may proceed to diff --git a/Documentation/driver-api/media/tx-rx.rst b/Documentation/driver-api/media/tx-rx.rst index 22e1b13ecde9a1..7df2407817b351 100644 --- a/Documentation/driver-api/media/tx-rx.rst +++ b/Documentation/driver-api/media/tx-rx.rst @@ -93,7 +93,8 @@ where * - variable or constant - description * - link_freq - - The value of the ``V4L2_CID_LINK_FREQ`` integer64 menu item. + - The value of the :ref:`V4L2_CID_LINK_FREQ ` integer64 + menu item. * - nr_of_lanes - Number of data lanes used on the CSI-2 link. * - 2 diff --git a/Documentation/driver-api/media/v4l2-fh.rst b/Documentation/driver-api/media/v4l2-fh.rst index a934caa483a438..ff1fdd89750406 100644 --- a/Documentation/driver-api/media/v4l2-fh.rst +++ b/Documentation/driver-api/media/v4l2-fh.rst @@ -42,7 +42,7 @@ Example: ... - my_fh = kzalloc(sizeof(*my_fh), GFP_KERNEL); + my_fh = kzalloc_obj(*my_fh); ... diff --git a/Documentation/driver-api/mtd/spi-nor.rst b/Documentation/driver-api/mtd/spi-nor.rst index 148fa4288760b6..747a326fb6c0d5 100644 --- a/Documentation/driver-api/mtd/spi-nor.rst +++ b/Documentation/driver-api/mtd/spi-nor.rst @@ -203,3 +203,173 @@ section, after the ``---`` marker. mtd.writesize = 1 mtd.oobsize = 0 regions = 0 + +5) If your flash supports locking, please go through the following test + procedure to make sure it correctly behaves. The below example + expects the typical situation where eraseblocks and lock sectors have + the same size. In case you enabled MTD_SPI_NOR_USE_4K_SECTORS, you + must adapt `bs` accordingly. + + Warning: These tests may hard lock your device! Make sure: + + - The device is not hard locked already (#WP strapped to low and + SR_SRWD bit set) + - If you have a WPn pin, you may want to set `no-wp` in your DT for + the time of the test, to only make use of software protection. + Otherwise, clearing the locking state depends on the WPn + signal and if it is tied to low, the flash will be permanently + locked. + + Test full chip locking and make sure expectations, the MEMISLOCKED + ioctl output, the debugfs output and experimental results are all + aligned:: + + root@1:~# alias show_sectors='grep -A4 "locked sectors" /sys/kernel/debug/spi-nor/spi0.0/params' + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -i /dev/mtd0 + Device: /dev/mtd0 + Start: 0 + Len: 0x4000000 + Lock status: unlocked + Return code: 0 + root@1:~# mtd_debug erase /dev/mtd0 0 2097152 + Erased 2097152 bytes from address 0x00000000 in flash + root@1:~# mtd_debug write /dev/mtd0 0 2097152 spi_test + Copied 2097152 bytes from spi_test to address 0x00000000 in flash + root@1:~# mtd_debug read /dev/mtd0 0 2097152 spi_read + Copied 2097152 bytes from address 0x00000000 in flash to spi_read + root@1:~# sha256sum spi* + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_read + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_test + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-03ffffff | unlocked | 1024 + + root@1:~# flash_lock -l /dev/mtd0 + root@1:~# flash_lock -i /dev/mtd0 + Device: /dev/mtd0 + Start: 0 + Len: 0x4000000 + Lock status: locked + Return code: 1 + root@1:~# mtd_debug erase /dev/mtd0 0 2097152 + Erased 2097152 bytes from address 0x00000000 in flash + root@1:~# mtd_debug read /dev/mtd0 0 2097152 spi_read + Copied 2097152 bytes from address 0x00000000 in flash to spi_read + root@1:~# sha256sum spi* + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_read + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_test + root@1:~# dd if=/dev/urandom of=./spi_test2 bs=1M count=2 + 2+0 records in + 2+0 records out + root@1:~# mtd_debug write /dev/mtd0 0 2097152 spi_test2 + Copied 2097152 bytes from spi_test2 to address 0x00000000 in flash + root@1:~# mtd_debug read /dev/mtd0 0 2097152 spi_read2 + Copied 2097152 bytes from address 0x00000000 in flash to spi_read2 + root@1:~# sha256sum spi* + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_read + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_read2 + c444216a6ba2a4a66cccd60a0dd062bce4b865dd52b200ef5e21838c4b899ac8 spi_test + bea9334df51c620440f86751cba0799214a016329f1736f9456d40cf40efdc88 spi_test2 + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-03ffffff | locked | 1024 + root@1:~# flash_lock -u /dev/mtd0 + + Once we trust the debugfs output we can use it to test various + situations. Check top locking/unlocking (end of the device):: + + root@1:~# size=$(cat /sys/class/mtd/mtd0/size) + root@1:~# bs=$(cat /sys/class/mtd/mtd0/erasesize) + root@1:~# nsectors=$(grep unlocked /sys/kernel/debug/spi-nor/spi0.0/params | sed -e 's/.*unlocked | //') + root@1:~# ss=$(($size / $nsectors)) + root@1:~# bps=$(($ss / $bs)) + + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -l /dev/mtd0 $(($size - (2 * $ss))) $((2 * $bps)) # last two + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-03fdffff | unlocked | 1022 + 03fe0000-03ffffff | locked | 2 + root@1:~# flash_lock -u /dev/mtd0 $(($size - (2 * $ss))) $((1 * $bps)) # last one + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-03feffff | unlocked | 1023 + 03ff0000-03ffffff | locked | 1 + + If the flash features 4 block protection bits (BP), we can protect + more than 4MB (typically 128 64kiB-blocks or more), with a finer + grain than locking the entire device:: + + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -l /dev/mtd0 $(($size - (2**7 * $ss))) $((2**7 * $bps)) + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-037fffff | unlocked | 896 + 03800000-03ffffff | locked | 128 + + If the flash features a Top/Bottom (TB) bit, we can protect the + beginning of the flash:: + + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -l /dev/mtd0 0 $((2 * $bps)) # first two + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-0001ffff | locked | 2 + 00020000-03ffffff | unlocked | 1022 + root@1:~# flash_lock -u /dev/mtd0 $ss $((1 * $bps)) # first one + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-0000ffff | locked | 1 + 00010000-03ffffff | unlocked | 1023 + + If the flash features a Complement (CMP) bit, we can protect with + more granularity above half of the capacity. Let's lock all but one + block, then unlock one more block:: + + root@1:~# all_but_one=$((($size / $bs) - ($ss / $bs))) + + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -l /dev/mtd0 $ss $all_but_one # all but the first + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-0000ffff | unlocked | 1 + 00010000-03ffffff | locked | 1023 + root@1:~# flash_lock -u /dev/mtd0 $ss $(($ss / $bs)) # all but the two first + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-0001ffff | unlocked | 2 + 00020000-03ffffff | locked | 1022 + root@1:~# flash_lock -u /dev/mtd0 + root@1:~# flash_lock -l /dev/mtd0 0 $all_but_one # same from the other side + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-03feffff | locked | 1023 + 03ff0000-03ffffff | unlocked | 1 + root@1:~# flash_lock -u /dev/mtd0 $(($size - (2 * $ss))) $(($ss / $bs)) # all but two + root@1:~# show_sectors + software locked sectors + region (in hex) | status | #sectors + ------------------+----------+--------- + 00000000-03fdffff | locked | 1022 + 03fe0000-03ffffff | unlocked | 2 diff --git a/Documentation/driver-api/nvdimm/btt.rst b/Documentation/driver-api/nvdimm/btt.rst index 2d8269f834bd60..d29fab95f14942 100644 --- a/Documentation/driver-api/nvdimm/btt.rst +++ b/Documentation/driver-api/nvdimm/btt.rst @@ -161,9 +161,8 @@ process:: nlanes = min(nfree, num_cpus) A lane number is obtained at the start of any IO, and is used for indexing into -all the on-disk and in-memory data structures for the duration of the IO. If -there are more CPUs than the max number of available lanes, than lanes are -protected by spinlocks. +all the on-disk and in-memory data structures for the duration of the IO. Lanes +are protected by mutexes. d. In-memory data structure: Read Tracking Table (RTT) diff --git a/Documentation/driver-api/serial/serial-rs485.rst b/Documentation/driver-api/serial/serial-rs485.rst index dce061ef764770..f53043d2107159 100644 --- a/Documentation/driver-api/serial/serial-rs485.rst +++ b/Documentation/driver-api/serial/serial-rs485.rst @@ -132,4 +132,4 @@ RS485 Serial Communications 6. References ============= -.. [#DT-bindings] Documentation/devicetree/bindings/serial/rs485.txt +.. [#DT-bindings] Documentation/devicetree/bindings/serial/rs485.yaml diff --git a/Documentation/driver-api/uio-howto.rst b/Documentation/driver-api/uio-howto.rst index 907ffa3b38f5b7..c08472dfbcfeb3 100644 --- a/Documentation/driver-api/uio-howto.rst +++ b/Documentation/driver-api/uio-howto.rst @@ -246,10 +246,10 @@ the members are required, others are optional. hardware interrupt number. The flags given here will be used in the call to :c:func:`request_irq()`. -- ``int (*mmap)(struct uio_info *info, struct vm_area_struct *vma)``: +- ``int (*mmap_prepare)(struct uio_info *info, struct vm_area_desc *desc)``: Optional. If you need a special :c:func:`mmap()` function, you can set it here. If this pointer is not NULL, your - :c:func:`mmap()` will be called instead of the built-in one. + ``mmap_prepare`` will be called instead of the built-in one. - ``int (*open)(struct uio_info *info, struct inode *inode)``: Optional. You might want to have your own :c:func:`open()`, diff --git a/Documentation/features/core/thread-info-in-task/arch-support.txt b/Documentation/features/core/thread-info-in-task/arch-support.txt index f3d744c76061c8..e26efdfbb6b400 100644 --- a/Documentation/features/core/thread-info-in-task/arch-support.txt +++ b/Documentation/features/core/thread-info-in-task/arch-support.txt @@ -12,7 +12,7 @@ | arm64: | ok | | csky: | TODO | | hexagon: | TODO | - | loongarch: | TODO | + | loongarch: | ok | | m68k: | TODO | | microblaze: | TODO | | mips: | TODO | diff --git a/Documentation/filesystems/9p.rst b/Documentation/filesystems/9p.rst index be3504ca034a83..3f65db648db06a 100644 --- a/Documentation/filesystems/9p.rst +++ b/Documentation/filesystems/9p.rst @@ -23,13 +23,10 @@ the 9p client is available in the form of a USENIX paper: Other applications are described in the following papers: * XCPU & Clustering - http://xcpu.org/papers/xcpu-talk.pdf * KVMFS: control file system for KVM - http://xcpu.org/papers/kvmfs.pdf * CellFS: A New Programming Model for the Cell BE - http://xcpu.org/papers/cellfs-talk.pdf * PROSE I/O: Using 9p to enable Application Partitions - http://plan9.escet.urjc.es/iwp9/cready/PROSE_iwp9_2006.pdf + http://web.archive.org/web/20110101152020/http://plan9.escet.urjc.es/iwp9/cready/PROSE_iwp9_2006.pdf * VirtFS: A Virtualization Aware File System pass-through https://kernel.org/doc/ols/2010/ols2010-pages-109-120.pdf @@ -238,6 +235,11 @@ Options cachetag cache tag to use the specified persistent cache. cache tags for existing cache sessions can be listed at /sys/fs/9p/caches. (applies only to cache=fscache) + + negtimeout the duration (in milliseconds) that negative dentries (paths + that do not actually exist) are retained in the cache. If + set to a negative value, those entries are kept indefinitely + until evicted by the buffer cache management system ============= =============================================================== Behavior diff --git a/Documentation/filesystems/adding-new-filesystems.rst b/Documentation/filesystems/adding-new-filesystems.rst new file mode 100644 index 00000000000000..a3d0bf16f73a04 --- /dev/null +++ b/Documentation/filesystems/adding-new-filesystems.rst @@ -0,0 +1,195 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. _adding_new_filesystems: + +Adding New Filesystems +====================== + +This document describes what is involved in adding a new filesystem to the +Linux kernel. + +Every filesystem merged into the kernel becomes the collective responsibility +of the VFS maintainers and the wider filesystem development community. +Experience has shown that filesystems which become unmaintained impose a +significant and ongoing burden: they are hard or impossible to test, they +block infrastructure changes because someone must update or preserve old APIs +for code that nobody is actively looking after, and they accumulate unfixed +bugs. The requirements and expectations described here are informed by this +experience and are intended to ensure that new filesystems enter the kernel +on a sustainable footing. + + +Do You Need a New In-Kernel Filesystem? +--------------------------------------- + +Before proposing a new in-kernel filesystem, consider whether one of the +alternatives might be more appropriate. + + - If an existing in-kernel filesystem covers the same use case, improving it + is generally preferred over adding a new implementation. The kernel + community favors incremental improvement over parallel implementations. + + - If the filesystem serves a niche audience or has a small user base, a FUSE + (Filesystem in Userspace) implementation may be a better fit. FUSE + filesystems avoid the long-term kernel maintenance commitment and can be + developed and released on their own schedule. + + - If kernel-level performance, reliability, or integration is genuinely + required, make the case explicitly. Explain who the users are, what the + use case is, and why a FUSE implementation would not be sufficient. + + +Technical Requirements +---------------------- + +New filesystems must use current kernel interfaces and practices. +Submitting a filesystem built on outdated APIs creates an unacceptable +maintenance debt and is likely to face pushback during review. + +Use modern VFS interfaces + Do not use interfaces listed in + :ref:`Documentation/process/deprecated.rst `. + + Use folios rather than raw page operations for page cache management and + iomap rather than buffer heads for block mapping and I/O. See + ``Documentation/filesystems/iomap/index.rst`` for iomap documentation. + + Block-based filesystems that need functionality not currently provided by + iomap should be prepared to explain why adding that functionality to iomap + is infeasible, rather than reimplementing their own block mapping layer. + + Network filesystems should consider using the netfs library + (``Documentation/filesystems/netfs_library.rst``), or be prepared to explain + why it is not a good fit. + +Provide userspace utilities + A ``mkfs`` tool is expected so that the filesystem can be created and used + by testers and users. A ``fsck`` tool is strongly recommended; while not + strictly required for every filesystem type, the ability to verify + consistency and repair corruption is an important part of a mature + filesystem. + +Be testable + The filesystem must be testable in a meaningful way. The + `fstests `_ + framework (also known as xfstests) is the standard testing infrastructure + for Linux filesystems and its use is highly recommended. At a minimum, + there must be a credible and documented way to test the filesystem and + detect regressions. When submitting, include a summary of test results + indicating which tests pass, fail, or are not applicable. + +Provide documentation + A documentation file under ``Documentation/filesystems/`` describing the + filesystem, its on-disk format, mount options, and any notable design + decisions is recommended. + + +Community and Maintainership Expectations +----------------------------------------- + +Merging a filesystem is a long-term commitment. The kernel community +needs confidence that the filesystem will be actively maintained after it +is merged. + +Identified maintainers + The submission must include a ``MAINTAINERS`` entry with at least one + maintainer (``M:``), a mailing list (``L:``), and a git tree (``T:``). + Having two or more maintainers is strongly preferred so that coverage + does not depend on a single person. The maintainers are expected to be + the primary points of contact for the filesystem going forward. + +Demonstrated commitment + A track record of maintaining kernel code -- for example, in other + subsystems -- significantly strengthens the case for a new filesystem. + Maintainers who are already known and trusted within the community face + less friction during review. + +Sustained backing + Major filesystems in Linux have organizational or corporate support behind + their development. Filesystems that depend entirely on volunteer effort + face higher scrutiny about their long-term viability. + +Responsiveness + The maintainer is expected to respond to bug reports, address review + feedback, and adapt the filesystem to VFS infrastructure changes such as + folio conversions, iomap migration, and mount API updates. Unresponsive + maintainership is one of the primary reasons filesystems end up on the + path to deprecation. + +User base + Clearly describe who the users of this filesystem are and the scale of the + user base. Filesystems with a very small or unclear user base face a + harder path to acceptance and a higher risk of future deprecation. + +Building your track record + A practical way to demonstrate many of the qualities above is to maintain + the filesystem out-of-tree for a period before requesting a merge. This + shows sustained commitment, builds a visible user base, and gives reviewers + confidence that the code and its maintainer will persist after merging. + That said, it is recognized that for some filesystems the user base grows + significantly only after upstreaming, so a compelling case for expected + adoption can substitute for a large existing user base. + + +Submission Process +------------------ + +This section covers what is specific to filesystem submissions, over and +above the normal submission advice in +:ref:`Documentation/process/submitting-patches.rst ` and +:ref:`Documentation/process/submit-checklist.rst `. + + - Send patches to the linux-fsdevel mailing list + (``linux-fsdevel@vger.kernel.org``). CC the relevant VFS maintainers as + listed in the ``MAINTAINERS`` file under + ``FILESYSTEMS (VFS and infrastructure)``. + + - Structure the submission logically. It is neither acceptable to send one + large patch containing the entire filesystem, nor is a replay of the full + development history helpful to reviewers. Instead, split the series by + topic -- for example: superblock and mount handling, inode operations, + directory operations, address space operations, and so on -- so that each + patch is reviewable in isolation. + + - Separate any filesystem-specific ioctls into their own patches with + dedicated justification. Interfaces beyond those already common across + other filesystems will receive additional scrutiny because they are hard + to maintain and may conflict with future generic interfaces. + + - Expect thorough review. Filesystem code interacts deeply with the VFS, + memory management, and block layers, so reviewers will examine the code + carefully. Address all review feedback and be prepared for multiple + revision cycles. + + - It may be appropriate to mark the filesystem as experimental in its Kconfig + help text for the first few releases to set expectations while the code + stabilizes in-tree. + + +Ongoing Obligations +------------------- + +Merging is not the finish line. Maintaining a filesystem in the kernel is an +ongoing commitment. + + - Adapt to VFS infrastructure changes. The VFS layer evolves continuously; + maintainers are expected to keep up with conversions such as folio + migration, iomap adoption, and mount API updates. + + - Maintain test coverage. As test suites evolve, the filesystem's test + results should be kept current. + + - Handle security issues and regression promptly. Both those reported + by ordinary users and those reported by test bots and fuzzing tools. + The filesystem must handle corrupted input gracefully without corrupting + memory, hanging, or crashing the kernel. + + - Engage with the wider filesystem community. Participate on linux-fsdevel, + share approaches to common problems, and look for opportunities to reuse + shared infrastructure. It is inappropriate to develop in isolation on a + private list and surface patches only at merge time. + + - Filesystems that become unmaintained -- where the maintainer stops + responding, infrastructure changes go unadapted, and testing becomes + impossible -- are candidates for deprecation and eventual removal from + the kernel. diff --git a/Documentation/filesystems/cramfs.rst b/Documentation/filesystems/cramfs.rst index afbdbde98bd25f..221c0bf91b9c81 100644 --- a/Documentation/filesystems/cramfs.rst +++ b/Documentation/filesystems/cramfs.rst @@ -28,8 +28,10 @@ Only the low 8 bits of gid are stored. The current version of mkcramfs simply truncates to 8 bits, which is a potential security issue. -Hard links are supported, but hard linked files -will still have a link count of 1 in the cramfs image. +Hard links are not preserved. mkcramfs deduplicates files with +identical content, but two names for the same on-disk inode in the +source tree become two separate (content-shared) entries in the +image, and cramfs always reports a link count of 1. Cramfs directories have no ``.`` or ``..`` entries. Directories (like every other file on cramfs) always have a link count of 1. (There's @@ -40,12 +42,16 @@ No timestamps are stored in a cramfs, so these default to the epoch the update lasts only as long as the inode is cached in memory, after which the timestamp reverts to 1970, i.e. moves backwards in time. -Currently, cramfs must be written and read with architectures of the -same endianness, and can be read only by kernels with PAGE_SIZE -== 4096. At least the latter of these is a bug, but it hasn't been -decided what the best fix is. For the moment if you have larger pages -you can just change the #define in mkcramfs.c, so long as you don't -mind the filesystem becoming unreadable to future kernels. +The on-disk layout is host-endian: the kernel does not swab, and +refuses to mount an image whose endianness does not match the CPU. +For cross-builds, mkcramfs -B / -L forces the output endianness so +that a host of one endianness can produce an image for a target of +the other. + +The on-disk block size is fixed at 4096 bytes. On systems with a +larger PAGE_SIZE you can change the #define in mkcramfs.c, with the +caveat that the resulting image will only be readable on kernels +configured for the same PAGE_SIZE. Memory Mapped cramfs image diff --git a/Documentation/filesystems/erofs.rst b/Documentation/filesystems/erofs.rst index fe06308e546c1a..4230884fb3592f 100644 --- a/Documentation/filesystems/erofs.rst +++ b/Documentation/filesystems/erofs.rst @@ -7,83 +7,90 @@ EROFS - Enhanced Read-Only File System Overview ======== -EROFS filesystem stands for Enhanced Read-Only File System. It aims to form a -generic read-only filesystem solution for various read-only use cases instead -of just focusing on storage space saving without considering any side effects -of runtime performance. - -It is designed to meet the needs of flexibility, feature extendability and user -payload friendly, etc. Apart from those, it is still kept as a simple -random-access friendly high-performance filesystem to get rid of unneeded I/O -amplification and memory-resident overhead compared to similar approaches. - -It is implemented to be a better choice for the following scenarios: - - - read-only storage media or - - - part of a fully trusted read-only solution, which means it needs to be +EROFS (Enhanced Read-Only File System) is a modern, efficient, and secure +read-only kernel filesystem designed for various use cases including immutable +system images, container images, application sandbox images, and dataset +distribution. + +An immutable image filesystem can be regarded as an enhanced archive format +which allows golden images to be built once and mounted everywhere -- images are +bit-for-bit identical across all deployments and can be verified, audited, or +shared without concerns about runtime modifications (in this model, all user +writes should be redirected into another trusted filesystem, for example, via +overlayfs for copy-on-write-style redirection, by design). + +EROFS is a dedicated implementation of the image filesystem idea above, with a +flexible, hierarchical on-disk design so that needed features can be enabled on +demand. Filesystem data in the core format is strictly block-aligned in order +to perform optimally on all kinds of storage media, including block devices and +memory-backed devices. The on-disk format is easy to parse and purposely avoids +the unnecessary metadata redundancy found in generic writable filesystems, which +can suffer from extra inconsistency issues -- making it ideal for security +auditing and untrusted remote access. In addition, designs such as inline data, +inline/shared extended attributes, and optimized (de)compression provide better +space efficiency while maintaining high performance. + +In short, EROFS aims to be a better fit for the following scenarios: + + - As part of a secure immutable storage solution, where it needs to be immutable and bit-for-bit identical to the official golden image for - their releases due to security or other considerations and - - - hope to minimize extra storage space with guaranteed end-to-end performance - by using compact layout, transparent file compression and direct access, - especially for those embedded devices with limited memory and high-density - hosts with numerous containers. + each individual copy, in order to meet security, data sharing, and/or + other requirements; -Here are the main features of EROFS: + - Minimizing storage overhead with guaranteed end-to-end performance + by using compact (meta)data layout, optimized transparent data compression, + deduplication and direct access, especially for those embedded devices with + limited memory and high-density hosts with numerous containers. - - Little endian on-disk design; +Here is the list of highlights: - - Block-based distribution and file-based distribution over fscache are - supported; + - Little endian on-disk design with 48-bit block addressing, supporting up + to 1 EiB filesystem capacity with 4 KiB block size; - - Support multiple devices to refer to external blobs, which can be used - for container images; + - Two compact inode metadata layouts for space and performance efficiency: - - 32-bit block addresses for each device, therefore 16TiB address space at - most with 4KiB block size for now; + ======================== ======== ====================================== + compact extended + ======================== ======== ====================================== + Inode core metadata size 32 bytes 64 bytes + Max file size 4 GiB 16 EiB (also limited by max. vol size) + Max uids/gids 65536 4294967296 + Nanosecond timestamps no yes + Max hardlinks 65536 4294967296 + ======================== ======== ====================================== - - Two inode layouts for different requirements: + - Support tailpacking inline data for better space efficiency and reduce + unneeded I/O amplification; - ===================== ============ ====================================== - compact (v1) extended (v2) - ===================== ============ ====================================== - Inode metadata size 32 bytes 64 bytes - Max file size 4 GiB 16 EiB (also limited by max. vol size) - Max uids/gids 65536 4294967296 - Per-inode timestamp no yes (64 + 32-bit timestamp) - Max hardlinks 65536 4294967296 - Metadata reserved 8 bytes 18 bytes - ===================== ============ ====================================== + - Block-based and file-backed distribution are both supported; - - Support extended attributes as an option; + - Multiple devices to reference external data blobs: inode data can be + optionally placed into external blobs, which enables image layering and data + sharing among different filesystems; - - Support a bloom filter that speeds up negative extended attribute lookups; + - Inline and shared extended attributes with an optional bloom filter that + speeds up negative extended attribute lookups; - - Support POSIX.1e ACLs by using extended attributes; + - POSIX.1e ACLs by using extended attributes; - - Support transparent data compression as an option: - LZ4, MicroLZMA, DEFLATE and Zstandard algorithms can be used on a per-file - basis; In addition, inplace decompression is also supported to avoid bounce - compressed buffers and unnecessary page cache thrashing. + - Transparent data compression as an option: Supported algorithms (LZ4, + MicroLZMA, DEFLATE and Zstandard) can be selected on a per-inode basis. + Both the on-disk metadata and decompression runtime have been heavily + optimized to minimize the overhead for better performance. - - Support chunk-based data deduplication and rolling-hash compressed data - deduplication; + - Merging tail-end data into a special inode as fragments; - - Support tailpacking inline compared to byte-addressed unaligned metadata - or smaller block size alternatives; + - Chunk-based deduplication and rolling-hash compressed data deduplication; - - Support merging tail-end data into a special inode as fragments. + - Direct I/O and FSDAX support on uncompressed inodes for use cases such as + secure containers, loop devices, and ramdisks that do not need page caching; - - Support large folios to make use of THPs (Transparent Hugepages); + - Page cache sharing among inodes with identical content fingerprints on + the same machine. - - Support direct I/O on uncompressed files to avoid double caching for loop - devices; +For more detailed information, please refer to our documentation site: - - Support FSDAX on uncompressed images for secure containers and ramdisks in - order to get rid of unnecessary page cache. - - - Support file-based on-demand loading with the Fscache infrastructure. +- https://erofs.docs.kernel.org The following git tree provides the file system user-space tools under development, such as a formatting tool (mkfs.erofs), an on-disk consistency & @@ -91,10 +98,6 @@ compatibility checking tool (fsck.erofs), and a debugging tool (dump.erofs): - git://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs-utils.git -For more information, please also refer to the documentation site: - -- https://erofs.docs.kernel.org - Bugs and patches are welcome, please kindly help us and send to the following linux-erofs mailing list: @@ -127,12 +130,9 @@ dax A legacy option which is an alias for ``dax=always``. device=%s Specify a path to an extra device to be used together. directio (For file-backed mounts) Use direct I/O to access backing files, and asynchronous I/O will be enabled if supported. -fsid=%s Specify a filesystem image ID for Fscache back-end. -domain_id=%s Specify a trusted domain ID for fscache mode so that - different images with the same blobs, identified by blob IDs, - can share storage within the same trusted domain. - Also used for different filesystems with inode page sharing - enabled to share page cache within the trusted domain. +domain_id=%s Specify a trusted domain ID. Filesystems sharing the same + domain ID can share page cache across mounts when inode + page sharing is enabled. (not shown in mountinfo output) fsoffset=%llu Specify block-aligned filesystem offset for the primary device. inode_share Enable inode page sharing for this filesystem. Inodes with identical content within the same domain ID can share the diff --git a/Documentation/filesystems/f2fs.rst b/Documentation/filesystems/f2fs.rst index 7e40316312867c..8c4a14ae444f47 100644 --- a/Documentation/filesystems/f2fs.rst +++ b/Documentation/filesystems/f2fs.rst @@ -137,6 +137,15 @@ noacl Disable POSIX Access Control List. Note: acl is enabled active_logs=%u Support configuring the number of active logs. In the current design, f2fs supports only 2, 4, and 6 logs. Default number is 6. + When the underlying block device exposes write + streams, the default active_logs=6 configuration + maps hot, warm, and cold DATA writes to streams 1, + 2, and 3, respectively. If only one or two write + streams are available, f2fs falls back to mapping + all DATA writes to stream 1 or mapping hot/warm + to stream 1 and cold to stream 2. If no write + streams are exposed, f2fs leaves the stream + unset. disable_ext_identify Disable the extension list configured by mkfs, so f2fs is not aware of cold files such as media files. inline_xattr Enable the inline xattrs feature. diff --git a/Documentation/filesystems/index.rst b/Documentation/filesystems/index.rst index fc7254d01a2b2d..1f71cf1595476c 100644 --- a/Documentation/filesystems/index.rst +++ b/Documentation/filesystems/index.rst @@ -43,6 +43,7 @@ algorithms work. caching/index porting + adding-new-filesystems Filesystem support layers ========================= diff --git a/Documentation/filesystems/locking.rst b/Documentation/filesystems/locking.rst index 8421ea21bd35e3..08d01bc62c319e 100644 --- a/Documentation/filesystems/locking.rst +++ b/Documentation/filesystems/locking.rst @@ -416,20 +416,6 @@ lm_open_conflict yes no no lm_breaker_timedout yes no no ====================== ============= ================= ========= -buffer_head -=========== - -prototypes:: - - void (*b_end_io)(struct buffer_head *bh, int uptodate); - -locking rules: - -called from interrupts. In other words, extreme care is needed here. -bh is locked, but that's all warranties we have here. Currently only RAID1, -highmem, fs/buffer.c, and fs/ntfs/aops.c are providing these. Block devices -call this method upon the IO completion. - block_device_operations ======================= prototypes:: @@ -584,7 +570,7 @@ write_info: yes dqonoff_sem FS recursion means calling ->quota_read() and ->quota_write() from superblock operations. -More details about quota locking can be found in fs/dquot.c. +More details about quota locking can be found in fs/quota/dquot.c. vm_operations_struct ==================== diff --git a/Documentation/filesystems/ntfs.rst b/Documentation/filesystems/ntfs.rst index 5c96b04a4d7a88..4bfa392daec6a6 100644 --- a/Documentation/filesystems/ntfs.rst +++ b/Documentation/filesystems/ntfs.rst @@ -156,4 +156,17 @@ windows_names= Refuse creation/rename of files with characters or discard= Issue block device discard for clusters freed on file deletion/truncation to inform underlying storage. + +native_symlink=raw|rel Configure how absolute symbolic links and mount + points (junctions) are handled. Under "raw" + (default), the absolute target path is returned + as-is without translation. Under "rel", it is + rewritten as a relative path anchored at + the volume root. + +symlink=wsl|native Configure how symbolic links are created. Under + "wsl" (default), WSL (Windows Subsystem for + Linux) compatible symlinks are created. Under + "native", Windows native symbolic links are + created. ======================= ==================================================== diff --git a/Documentation/filesystems/porting.rst b/Documentation/filesystems/porting.rst index fdf074429cd3ab..d13f0a23c882fc 100644 --- a/Documentation/filesystems/porting.rst +++ b/Documentation/filesystems/porting.rst @@ -1297,7 +1297,6 @@ Several functions are renamed: - kern_path_locked -> start_removing_path - kern_path_create -> start_creating_path - user_path_create -> start_creating_user_path -- user_path_locked_at -> start_removing_user_path_at - done_path_create -> end_creating_path --- @@ -1385,3 +1384,20 @@ for_each_alias(dentry, inode) instead of hlist_for_each_entry; better yet, see if any of the exported primitives could be used instead of the entire loop. You still need to hold ->i_lock of the inode over either form of manual loop. + +--- + +**mandatory** + +d_alloc_parallel() no longer requires a waitqueue_head. + +--- + +**mandatory** + +d_dispose_if_unused() is gone; use __move_to_shrink_list() if you really +need that functionality, but watch out for memory safety issues - just +as with d_dispose_if_unused() these are not trivial; with this variant +of API it's more explicit, since grabbing ->d_lock is caller-side, but +d_dispose_if_unused() had all the same issues. It's a low-level primitive; +use only if you have no alternative. diff --git a/Documentation/filesystems/proc.rst b/Documentation/filesystems/proc.rst index db6167befb7b2c..2ccd5b2dfdd33a 100644 --- a/Documentation/filesystems/proc.rst +++ b/Documentation/filesystems/proc.rst @@ -23,13 +23,13 @@ fixes/update part 1.1 Stefani Seibold June 9 2009 1 Collecting System Information 1.1 Process-Specific Subdirectories 1.2 Kernel data - 1.3 IDE devices in /proc/ide - 1.4 Networking info in /proc/net - 1.5 SCSI info - 1.6 Parallel port info in /proc/parport - 1.7 TTY info in /proc/tty - 1.8 Miscellaneous kernel statistics in /proc/stat - 1.9 Ext4 file system parameters + 1.3 Networking info in /proc/net + 1.4 SCSI info + 1.5 Parallel port info in /proc/parport + 1.6 TTY info in /proc/tty + 1.7 Miscellaneous kernel statistics in /proc/stat + 1.8 Ext4 file system parameters + 1.9 /proc/consoles - Shows registered system consoles 2 Modifying System Parameters @@ -52,6 +52,7 @@ fixes/update part 1.1 Stefani Seibold June 9 2009 4 Configuring procfs 4.1 Mount options + 4.2 Mount restrictions 5 Filesystem behavior @@ -118,7 +119,7 @@ PTRACE_MODE_ATTACH permissions; CAP_PERFMON capability does not grant access to /proc/PID/mem for other processes. Note that an open file descriptor to /proc/ or to any of its -contained files or subdirectories does not prevent being reused +contained files or subdirectories does not prevent from being reused for some other process in the event that exits. Operations on open /proc/ file descriptors corresponding to dead processes never act on any new process that the kernel may, through chance, have @@ -2211,7 +2212,7 @@ the process is maintaining. Example output:: | lr-------- 1 root root 64 Jan 27 11:24 400000-41a000 -> /usr/bin/ls The name of a link represents the virtual memory bounds of a mapping, i.e. -vm_area_struct::vm_start-vm_area_struct::vm_end. +vm_area_struct::vm_start - vm_area_struct::vm_end. The main purpose of the map_files is to retrieve a set of memory mapped files in a fast way instead of parsing /proc//maps or @@ -2425,7 +2426,9 @@ prohibited by hidepid=. If you use some daemon like identd which needs to learn information about processes information, just add identd to this group. subset=pid hides all top level files and directories in the procfs that -are not related to tasks. +are not related to tasks. This option cannot be changed on an existing +procfs instance because overmounts that existed before the change could +otherwise remain reachable after the top level procfs entries are hidden. pidns= specifies a pid namespace (either as a string path to something like `/proc/$pid/ns/pid`, or a file descriptor when using `FSCONFIG_SET_FD`) that @@ -2434,6 +2437,20 @@ will use the calling process's active pid namespace. Note that the pid namespace of an existing procfs instance cannot be modified (attempting to do so will give an `-EBUSY` error). +4.2 Mount restrictions +-------------------------- + +If user namespaces are in use, the kernel additionally checks the instances of +procfs available to the mounter and will not allow procfs to be mounted if: + + 1. This mount is not fully visible unless the new procfs is going to be + mounted with subset=pid option. + + a. Its root directory is not the root directory of the filesystem. + b. If any file or non-empty procfs directory is hidden by another mount. + + 2. A new mount overrides the readonly option or any option from atime family. + Chapter 5: Filesystem behavior ============================== diff --git a/Documentation/filesystems/resctrl.rst b/Documentation/filesystems/resctrl.rst index b003bed339fddd..e4b66af55ffba0 100644 --- a/Documentation/filesystems/resctrl.rst +++ b/Documentation/filesystems/resctrl.rst @@ -427,9 +427,9 @@ with the following files: Two MBM events are supported by default: mbm_local_bytes and mbm_total_bytes. Each MBM event's sub-directory contains a file named "event_filter" that is - used to view and modify which memory transactions the MBM event is configured - with. The file is accessible only when "mbm_event" counter assignment mode is - enabled. + used to view and (if writable) modify which memory transactions the MBM event + is configured with. The file is accessible only when "mbm_event" counter + assignment mode is enabled. List of memory transaction types supported: @@ -454,9 +454,8 @@ with the following files: # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter local_reads,local_non_temporal_writes,local_reads_slow_memory - Modify the event configuration by writing to the "event_filter" file within - the "event_configs" directory. The read/write "event_filter" file contains the - configuration of the event that reflects which memory transactions are counted by it. + The memory transactions the MBM event is configured with can be changed + if "event_filter" is writable. For example:: @@ -480,6 +479,12 @@ with the following files: "1": Auto assignment is enabled. + Automatic counter assignment is done with best effort. If auto + assignment is enabled but there are not enough available counters then + monitor group creation could succeed while one or more events belonging + to the group may not have a counter assigned in all domains. Consult + mbm_L3_assignments for counter assignment states of the new groups. + Example:: # echo 0 > /sys/fs/resctrl/info/L3_MON/mbm_assign_on_mkdir @@ -570,6 +575,11 @@ All groups contain the following files: then the task must already belong to the CTRL_MON parent of this group. The task is removed from any previous MON group. + When writing to this file, a task id of 0 is interpreted as the + task id of the currently running task. On reading the file, a task + id of 0 will never be shown and there is no representation of the + idle tasks. Instead, a CPU's idle task is always considered as a + member of the group owning the CPU. "cpus": Reading this file shows a bitmask of the logical CPUs owned by diff --git a/Documentation/filesystems/smb/ksmbd.rst b/Documentation/filesystems/smb/ksmbd.rst index 67cb68ea6e6880..672c5d3892ff91 100644 --- a/Documentation/filesystems/smb/ksmbd.rst +++ b/Documentation/filesystems/smb/ksmbd.rst @@ -97,7 +97,7 @@ ACLs Partially Supported. only DACLs available, SACLs to allow future support for running as a domain member. Kerberos Supported. -Durable handle v1,v2 Planned for future. +Durable handle v1,v2 Supported. Persistent handle Planned for future. SMB2 notify Planned for future. Sparse file support Supported. @@ -111,7 +111,7 @@ DCE/RPC support Partially Supported. a few calls(NetShareEnumAll, for Witness protocol e.g.) ksmbd/nfsd interoperability Planned for future. The features that ksmbd support are Leases, Notify, ACLs and Share modes. -SMB3.1.1 Compression Planned for future. +SMB3.1.1 Compression Supported. SMB3.1.1 over QUIC Planned for future. Signing/Encryption over RDMA Planned for future. SMB3.1.1 GMAC signing support Planned for future. diff --git a/Documentation/firmware-guide/acpi/dsd/motorcomm-yt8xxx-phy.rst b/Documentation/firmware-guide/acpi/dsd/motorcomm-yt8xxx-phy.rst new file mode 100644 index 00000000000000..d64a396fac8159 --- /dev/null +++ b/Documentation/firmware-guide/acpi/dsd/motorcomm-yt8xxx-phy.rst @@ -0,0 +1,107 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================== +Motorcomm yt8xxx PHY properties (_DSD) +====================================== + +This document describes ACPI _DSD device properties for Motorcomm yt8xxx +Ethernet PHYs supported by the in-kernel driver in +``drivers/net/phy/motorcomm.c``. + +The properties are exposed on the PHY device object under the MDIO bus ACPI +device (the same objects that are registered via +``fwnode_mdiobus_register_phy()``). MAC-side connection properties such as +``phy-handle`` and ``phy-mode`` are documented in [acpi-mdio-phy]_. + +Property names and semantics are intentionally aligned with the Devicetree +binding [motorcomm-yt8xxx]_ so that the same driver code path +(``device_property_*`` on ``&phydev->mdio.dev``) can consume firmware +described either as Devicetree or ACPI _DSD. + +UUID and placement +================== + +Per [acpi-dsd-properties-rules]_ and [acpi-mdio-phy]_, properties must be +placed in an _DSD package using the standard Device Properties UUID:: + + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301") + +Properties +========== + +Unless noted otherwise, integer properties use the same allowed values and +defaults as [motorcomm-yt8xxx]_. + +``rx-internal-delay-ps`` (u32, optional) + RGMII RX internal delay in picoseconds. Only meaningful when the link is + using RGMII modes with RX internal delay; see [motorcomm-yt8xxx]_. + +``tx-internal-delay-ps`` (u32, optional) + RGMII TX internal delay in picoseconds. Only meaningful when the link is + using RGMII modes with TX internal delay; see [motorcomm-yt8xxx]_. + +``motorcomm,clk-out-frequency-hz`` (u32, optional) + Clock output frequency on the PHY clock output pin. Allowed values and + default are defined in [motorcomm-yt8xxx]_. + +``motorcomm,keep-pll-enabled`` (boolean, optional) + If true, keep the PLL enabled even when there is no link (useful for using + the clock output without an Ethernet link). See [motorcomm-yt8xxx]_. + +``motorcomm,auto-sleep-disabled`` (boolean, optional) + If true, disable the PHY auto-sleep behavior described in + [motorcomm-yt8xxx]_. + +``motorcomm,rx-clk-drv-microamp`` (u32, optional) + Drive strength for the ``rx_clk`` RGMII pad in microamps. Allowed values + depend on the configured RGMII LDO voltage; see [motorcomm-yt8xxx]_. + +``motorcomm,rx-data-drv-microamp`` (u32, optional) + Drive strength for the ``rx_data`` and ``rx_ctl`` RGMII pads in microamps. + See [motorcomm-yt8xxx]_. + +``motorcomm,tx-clk-adj-enabled`` (boolean, optional) + Enables adjustments related to ``motorcomm,tx-clk-*-inverted`` usage; see + [motorcomm-yt8xxx]_. + +``motorcomm,tx-clk-10-inverted`` (boolean, optional) +``motorcomm,tx-clk-100-inverted`` (boolean, optional) +``motorcomm,tx-clk-1000-inverted`` (boolean, optional) + Per-speed TX clock inversion options; see [motorcomm-yt8xxx]_. + +ASL example (illustrative) +========================== + +The example below only shows PHY-local _DSD properties. A real platform +still needs a MAC ``phy-handle`` and ``phy-mode`` package as in +[acpi-mdio-phy]_. + +.. code-block:: none + + Scope (\_SB.MDI0) + { + Device (PHY4) + { + Name (_ADR, 0x4) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package (2) { "rx-internal-delay-ps", 2100 }, + Package (2) { "tx-internal-delay-ps", 150 }, + Package (2) { "motorcomm,clk-out-frequency-hz", 0 }, + Package (2) { "motorcomm,keep-pll-enabled", 1 }, + Package (2) { "motorcomm,auto-sleep-disabled", 1 }, + } + }) + } + } + +References +========== + +.. [acpi-mdio-phy] Documentation/firmware-guide/acpi/dsd/phy.rst +.. [acpi-dsd-properties-rules] + Documentation/firmware-guide/acpi/DSD-properties-rules.rst +.. [motorcomm-yt8xxx] + Documentation/devicetree/bindings/net/motorcomm,yt8xxx.yaml diff --git a/Documentation/firmware-guide/acpi/index.rst b/Documentation/firmware-guide/acpi/index.rst index b246902f523fe4..db9eb7229948c6 100644 --- a/Documentation/firmware-guide/acpi/index.rst +++ b/Documentation/firmware-guide/acpi/index.rst @@ -11,6 +11,7 @@ ACPI Support dsd/graph dsd/data-node-references dsd/leds + dsd/motorcomm-yt8xxx-phy dsd/phy enumeration osi diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst index 033167025fccae..d553dd599c9669 100644 --- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst +++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst @@ -233,8 +233,15 @@ we have a dedicated glossary for Display Core at TC Texture Cache + TCC + Texture Cache per Channel - L2 cache attached to the memory channels. + May be used when shader cores are accessing memory. + Despite "Texture" in the name, this is used by any kind of memory access. + TCCs may be mapped to TCPs, depending on the architecture. + TCP (AMDGPU) - Texture Cache per Pipe. Even though the name "Texture" is part of this + Texture Cache per Pipe - L1 cache attached to each CU. + Even though the name "Texture" is part of this acronym, the TCP represents the path to memory shaders; i.e., it is not related to texture. The name is a leftover from older designs where shader stages had different cache designs; it refers to the L1 cache in older diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst index 8732084186a480..b2ab182236efb1 100644 --- a/Documentation/gpu/amdgpu/index.rst +++ b/Documentation/gpu/amdgpu/index.rst @@ -23,3 +23,4 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures. debugfs process-isolation amdgpu-glossary + ptl diff --git a/Documentation/gpu/amdgpu/ptl.rst b/Documentation/gpu/amdgpu/ptl.rst new file mode 100644 index 00000000000000..c7f16dea795460 --- /dev/null +++ b/Documentation/gpu/amdgpu/ptl.rst @@ -0,0 +1,94 @@ +======================================= +Peak Tops Limiter (PTL) sysfs Interface +======================================= + +Overview +-------- +The Peak Tops Limiter (PTL) sysfs interface enables users to control and +configure the PTL feature for each GPU individually. All PTL-related +sysfs files are located under `/sys/class/drm/cardX/device/ptl/`, where +`X` is the GPU index. Through these files, users can enable or disable +PTL, set preferred data formats, and query supported formats for each GPU. + +PTL sysfs files +---------------- +The following files are available under `/sys/class/drm/cardX/device/ptl/`: + +- `ptl_enable` +- `ptl_format` +- `ptl_supported_formats` + +PTL Enable/Disable +------------------ +File: `ptl_enable` +Type: Read/Write (rw) + +Read: Returns the current PTL status as a string: `enabled` if PTL +is active, or `disabled` if inactive. + +Write: + +- Write `1` or `enabled` to enable PTL +- Write `0` or `disabled` to disable PTL + +Examples:: + + # Query PTL status + cat /sys/class/drm/card1/device/ptl/ptl_enable + # Output: enabled + + # Enable PTL + sudo bash -c "echo 1 > /sys/class/drm/card1/device/ptl/ptl_enable" + + # Disable PTL + sudo bash -c "echo 0 > /sys/class/drm/card1/device/ptl/ptl_enable" + +PTL Format (Preferred Data Formats) +----------------------------------- +File: `ptl_format` +Type: Read/Write (rw) + +Read: Returns the two preferred formats, e.g. `I8,F32`. + +Write: Accepts two formats separated by a comma, e.g. `I8,F32`. + +- Both formats must be supported and different. +- If an invalid format is provided (not supported, or both formats are the + same), the driver will return "write error: Invalid argument". + +Examples:: + + # Query PTL formats + cat /sys/class/drm/card1/device/ptl/ptl_format + # Output: I8,F32 + + # Set PTL formats + sudo bash -c "echo I8,F32 > /sys/class/drm/card1/device/ptl/ptl_format" + +Supported Formats +----------------- +File: `ptl_supported_formats` +Type: Read-only (r) + +Read: Returns a comma-separated list of supported formats, e.g. +`I8,F16,BF16,F32,F64`. + +Example:: + + # Check supported formats + cat /sys/class/drm/card1/device/ptl/ptl_supported_formats + # Output: I8,F16,BF16,F32,F64 + +Behavioral Notes +---------------- +- PTL formats can only be set when PTL is enabled. +- If PTL is disabled, `ptl_format` returns `N/A`. +- Only two formats can be set at a time, and they must be from the supported set and different.. +- All commands support per-GPU targeting. +- Root permission is required to enable/disable PTL or change formats. +- If the hardware does not support PTL, the PTL sysfs directory will not + be created. + +Implementation +-------------- +The PTL sysfs nodes are implemented in `drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c`. diff --git a/Documentation/gpu/driver-uapi.rst b/Documentation/gpu/driver-uapi.rst index 1f15a8ca126516..627fc68c7a21ac 100644 --- a/Documentation/gpu/driver-uapi.rst +++ b/Documentation/gpu/driver-uapi.rst @@ -2,6 +2,8 @@ DRM Driver uAPI =============== +.. contents:: + drm/i915 uAPI ============= diff --git a/Documentation/gpu/drivers.rst b/Documentation/gpu/drivers.rst index 2e13e0ad7e88bb..20d2c454aa1d9a 100644 --- a/Documentation/gpu/drivers.rst +++ b/Documentation/gpu/drivers.rst @@ -8,6 +8,7 @@ GPU Driver Documentation amdgpu/index i915 imagination/index + intel-display/index mcde meson nouveau diff --git a/Documentation/gpu/drm-internals.rst b/Documentation/gpu/drm-internals.rst index 94f93fd3b8a0a0..a3ce25a36f1d7e 100644 --- a/Documentation/gpu/drm-internals.rst +++ b/Documentation/gpu/drm-internals.rst @@ -18,6 +18,8 @@ event handling, memory management, output management, framebuffer management, command submission & fencing, suspend/resume support, and DMA services. +.. contents:: + Driver Initialization ===================== diff --git a/Documentation/gpu/drm-kms-helpers.rst b/Documentation/gpu/drm-kms-helpers.rst index b4a9e5ae81f6e5..80453dda33b848 100644 --- a/Documentation/gpu/drm-kms-helpers.rst +++ b/Documentation/gpu/drm-kms-helpers.rst @@ -33,6 +33,8 @@ There are a few areas these helpers can grouped into: pipeline: Planes, handling rectangles for visibility checking and scissoring, flip queues and assorted bits. +.. contents:: + Modeset Helper Reference for Common Vtables =========================================== diff --git a/Documentation/gpu/drm-kms.rst b/Documentation/gpu/drm-kms.rst index 2292e65f044c3b..fa69a5450f9674 100644 --- a/Documentation/gpu/drm-kms.rst +++ b/Documentation/gpu/drm-kms.rst @@ -1,3 +1,6 @@ + +.. _drm-kms: + ========================= Kernel Mode Setting (KMS) ========================= @@ -15,6 +18,8 @@ be setup by initializing the following fields. - struct drm_mode_config_funcs \*funcs; Mode setting functions. +.. contents:: + Overview ======== @@ -206,11 +211,11 @@ Atomic Mode Setting style=dashed label="Free-standing state" - "drm_atomic_state" -> "duplicated drm_plane_state A" - "drm_atomic_state" -> "duplicated drm_plane_state B" - "drm_atomic_state" -> "duplicated drm_crtc_state" - "drm_atomic_state" -> "duplicated drm_connector_state" - "drm_atomic_state" -> "duplicated driver private state" + "drm_atomic_commit" -> "duplicated drm_plane_state A" + "drm_atomic_commit" -> "duplicated drm_plane_state B" + "drm_atomic_commit" -> "duplicated drm_crtc_state" + "drm_atomic_commit" -> "duplicated drm_connector_state" + "drm_atomic_commit" -> "duplicated driver private state" } subgraph cluster_current { @@ -230,7 +235,7 @@ Atomic Mode Setting "driver private object" -> "driver private state" } - "drm_atomic_state" -> "drm_device" [label="atomic_commit"] + "drm_atomic_commit" -> "drm_device" [label="atomic_commit"] "duplicated drm_plane_state A" -> "drm_device"[style=invis] } @@ -265,7 +270,7 @@ Taken all together there's two consequences for the atomic design: drm_private_state`. - An atomic update is assembled and validated as an entirely free-standing pile - of structures within the :c:type:`drm_atomic_state ` + of structures within the :c:type:`drm_atomic_commit ` container. Driver private state structures are also tracked in the same structure; see the next chapter. Only when a state is committed is it applied to the driver and modeset objects. This way rolling back an update boils down diff --git a/Documentation/gpu/drm-mm.rst b/Documentation/gpu/drm-mm.rst index 32fb506db05b57..2dea94f77d52dc 100644 --- a/Documentation/gpu/drm-mm.rst +++ b/Documentation/gpu/drm-mm.rst @@ -25,6 +25,8 @@ share it. GEM has simpler initialization and execution requirements than TTM, but has no video RAM management capabilities and is thus limited to UMA devices. +.. contents:: + The Translation Table Manager (TTM) =================================== diff --git a/Documentation/gpu/drm-ras.rst b/Documentation/gpu/drm-ras.rst index 70b246a78fc8a1..83c21853b74b60 100644 --- a/Documentation/gpu/drm-ras.rst +++ b/Documentation/gpu/drm-ras.rst @@ -24,6 +24,8 @@ Key Goals: nodes for different IP blocks, sub-blocks, or other logical subdivisions as applicable. +.. contents:: + Nodes ===== @@ -52,6 +54,8 @@ User space tools can: as a parameter. * Query specific error counter values with the ``get-error-counter`` command, using both ``node-id`` and ``error-id`` as parameters. +* Clear specific error counters with the ``clear-error-counter`` command, using both + ``node-id`` and ``error-id`` as parameters. YAML-based Interface -------------------- @@ -101,3 +105,9 @@ Example: Query an error counter for a given node sudo ynl --family drm_ras --do get-error-counter --json '{"node-id":0, "error-id":1}' {'error-id': 1, 'error-name': 'error_name1', 'error-value': 0} +Example: Clear an error counter for a given node + +.. code-block:: bash + + sudo ynl --family drm_ras --do clear-error-counter --json '{"node-id":0, "error-id":1}' + None diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst index 579e87cb9ff75a..93df92c4ac8cf8 100644 --- a/Documentation/gpu/drm-uapi.rst +++ b/Documentation/gpu/drm-uapi.rst @@ -16,6 +16,8 @@ management, and output management. Cover generic ioctls and sysfs layout here. We only need high-level info, since man pages should cover the rest. +.. contents:: + libdrm Device Lookup ==================== @@ -118,6 +120,10 @@ is already rather painful for the DRM subsystem, with multiple different uAPIs for the same thing co-existing. If we add a few more complete mistakes into the mix every year it would be entirely unmanageable. +The DRM subsystem has however no concern with independent closed-source +userspace implementations. To officialize that position, the DRM uAPI headers +are covered by the MIT license. + .. _drm_render_node: Render nodes @@ -568,7 +574,7 @@ ENOSPC: EPERM/EACCES: Returned for an operation that is valid, but needs more privileges. E.g. root-only or much more common, DRM master-only operations return - this when called by unpriviledged clients. There's no clear + this when called by unprivileged clients. There's no clear difference between EACCES and EPERM. ENODEV: @@ -761,4 +767,4 @@ Stable uAPI events From ``drivers/gpu/drm/scheduler/gpu_scheduler_trace.h`` .. kernel-doc:: drivers/gpu/drm/scheduler/gpu_scheduler_trace.h - :doc: uAPI trace events \ No newline at end of file + :doc: uAPI trace events diff --git a/Documentation/gpu/drm-usage-stats.rst b/Documentation/gpu/drm-usage-stats.rst index 63d6b2abe5adf9..70b7cfcc194f7c 100644 --- a/Documentation/gpu/drm-usage-stats.rst +++ b/Documentation/gpu/drm-usage-stats.rst @@ -16,6 +16,8 @@ output is split between common and driver specific parts. Having said that, wherever possible effort should still be made to standardise as much as possible. +.. contents:: + File format specification ========================= @@ -215,3 +217,4 @@ Driver specific implementations * :ref:`panfrost-usage-stats` * :ref:`panthor-usage-stats` * :ref:`xe-usage-stats` +* :ref:`amdxdna-usage-stats` diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index eba09c3ddce42f..0c9d6875853315 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -1,3 +1,6 @@ + +.. _drm/i915: + =========================== drm/i915 Intel GFX Driver =========================== @@ -7,6 +10,9 @@ models) integrated GFX chipsets with both Intel display and rendering blocks. This excludes a set of SoC platforms with an SGX rendering unit, those have basic support through the gma500 drm driver. +The display, or :ref:`drm-kms`, support for drm/i915 is provided by +:ref:`drm/intel-display`, and shared with :ref:`drm/xe `. + Core Driver Infrastructure ========================== @@ -64,200 +70,6 @@ Workarounds .. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c :doc: Hardware workarounds -Display Hardware Handling -========================= - -This section covers everything related to the display hardware including -the mode setting infrastructure, plane, sprite and cursor handling and -display, output probing and related topics. - -Mode Setting Infrastructure ---------------------------- - -The i915 driver is thus far the only DRM driver which doesn't use the -common DRM helper code to implement mode setting sequences. Thus it has -its own tailor-made infrastructure for executing a display configuration -change. - -Frontbuffer Tracking --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c - :doc: frontbuffer tracking - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h - :internal: - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c - :internal: - -Display FIFO Underrun Reporting -------------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c - :doc: fifo underrun handling - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c - :internal: - -Plane Configuration -------------------- - -This section covers plane configuration and composition with the primary -plane, sprites, cursors and overlays. This includes the infrastructure -to do atomic vsync'ed updates of all this state and also tightly coupled -topics like watermark setup and computation, framebuffer compression and -panel self refresh. - -Atomic Plane Helpers --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c - :doc: atomic plane helpers - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c - :internal: - -Asynchronous Page Flip ----------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c - :doc: asynchronous flip implementation - -Output Probing --------------- - -This section covers output probing and related infrastructure like the -hotplug interrupt storm detection and mitigation code. Note that the -i915 driver still uses most of the common DRM helper code for output -probing, so those sections fully apply. - -Hotplug -------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c - :doc: Hotplug - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c - :internal: - -High Definition Audio ---------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c - :doc: High Definition Audio over HDMI and Display Port - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c - :internal: - -.. kernel-doc:: include/drm/intel/i915_component.h - :internal: - -Intel HDMI LPE Audio Support ----------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c - :doc: LPE Audio integration for HDMI or DP playback - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c - :internal: - -Panel Self Refresh PSR (PSR/SRD) --------------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c - :doc: Panel Self Refresh (PSR/SRD) - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c - :internal: - -Frame Buffer Compression (FBC) ------------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c - :doc: Frame Buffer Compression (FBC) - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c - :internal: - -Display Refresh Rate Switching (DRRS) -------------------------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c - :doc: Display Refresh Rate Switching (DRRS) - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c - :internal: - -DPIO ----- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c - :doc: DPIO - -DMC Firmware Support --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c - :doc: DMC Firmware Support - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c - :internal: - -DMC Flip Queue --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_flipq.c - :doc: DMC Flip Queue - -DMC wakelock support --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c - :doc: DMC wakelock support - -Video BIOS Table (VBT) ----------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c - :doc: Video BIOS Table (VBT) - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c - :internal: - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h - :internal: - -Display clocks --------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c - :doc: CDCLK / RAWCLK - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c - :internal: - -Display PLLs ------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c - :doc: Display PLLs - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c - :internal: - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h - :internal: - -Display State Buffer --------------------- - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c - :doc: DSB - -.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c - :internal: - GT Programming ============== @@ -568,7 +380,7 @@ The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_ DMC --- -See `DMC Firmware Support`_ +See :ref:`drm/intel-display/dmc`. Tracing ======= diff --git a/Documentation/gpu/index.rst b/Documentation/gpu/index.rst index 5d708a106b3fac..65bf3b26e4f4c5 100644 --- a/Documentation/gpu/index.rst +++ b/Documentation/gpu/index.rst @@ -3,6 +3,7 @@ GPU Driver Developer's Guide ============================ .. toctree:: + :maxdepth: 2 introduction drm-internals diff --git a/Documentation/gpu/intel-display/async-flip.rst b/Documentation/gpu/intel-display/async-flip.rst new file mode 100644 index 00000000000000..40f93e885bb787 --- /dev/null +++ b/Documentation/gpu/intel-display/async-flip.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Asynchronous Page Flip +====================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c + :doc: asynchronous flip implementation diff --git a/Documentation/gpu/intel-display/atomic.rst b/Documentation/gpu/intel-display/atomic.rst new file mode 100644 index 00000000000000..43a473181e7a1e --- /dev/null +++ b/Documentation/gpu/intel-display/atomic.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Atomic Modeset Support +====================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic.c + :doc: atomic modeset support + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic.c + :internal: diff --git a/Documentation/gpu/intel-display/audio.rst b/Documentation/gpu/intel-display/audio.rst new file mode 100644 index 00000000000000..eef95df75f8d29 --- /dev/null +++ b/Documentation/gpu/intel-display/audio.rst @@ -0,0 +1,23 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +High Definition Audio +===================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c + :doc: High Definition Audio over HDMI and Display Port + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c + :internal: + +.. kernel-doc:: include/drm/intel/i915_component.h + :internal: + +Intel HDMI LPE Audio Support +============================ + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c + :doc: LPE Audio integration for HDMI or DP playback + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c + :internal: diff --git a/Documentation/gpu/intel-display/casf.rst b/Documentation/gpu/intel-display/casf.rst new file mode 100644 index 00000000000000..406778ccd94cac --- /dev/null +++ b/Documentation/gpu/intel-display/casf.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Content Adaptive Sharpness Filter (CASF) +======================================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_casf.c + :doc: Content Adaptive Sharpness Filter (CASF) diff --git a/Documentation/gpu/intel-display/cdclk.rst b/Documentation/gpu/intel-display/cdclk.rst new file mode 100644 index 00000000000000..a66d623b0ec9ba --- /dev/null +++ b/Documentation/gpu/intel-display/cdclk.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display clocks +============== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c + :doc: CDCLK / RAWCLK + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c + :internal: diff --git a/Documentation/gpu/intel-display/cmtg.rst b/Documentation/gpu/intel-display/cmtg.rst new file mode 100644 index 00000000000000..04edd0bd165d2b --- /dev/null +++ b/Documentation/gpu/intel-display/cmtg.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Common Primary Timing Generator (CMTG) +====================================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cmtg.c + :doc: Common Primary Timing Generator (CMTG) diff --git a/Documentation/gpu/intel-display/dmc.rst b/Documentation/gpu/intel-display/dmc.rst new file mode 100644 index 00000000000000..4368da4c70489d --- /dev/null +++ b/Documentation/gpu/intel-display/dmc.rst @@ -0,0 +1,26 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +.. _drm/intel-display/dmc: + +DMC Firmware Support +==================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c + :doc: DMC Firmware Support + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c + :internal: + + +DMC Flip Queue +============== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_flipq.c + :doc: DMC Flip Queue + +DMC wakelock support +==================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c + :doc: DMC wakelock support diff --git a/Documentation/gpu/intel-display/dpio.rst b/Documentation/gpu/intel-display/dpio.rst new file mode 100644 index 00000000000000..84d92ac162f85b --- /dev/null +++ b/Documentation/gpu/intel-display/dpio.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +DPIO +==== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c + :doc: DPIO diff --git a/Documentation/gpu/intel-display/dpll.rst b/Documentation/gpu/intel-display/dpll.rst new file mode 100644 index 00000000000000..c750352e0ae501 --- /dev/null +++ b/Documentation/gpu/intel-display/dpll.rst @@ -0,0 +1,14 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display PLLs +============ + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c + :doc: Display PLLs + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c + :internal: + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h + :internal: diff --git a/Documentation/gpu/intel-display/drrs.rst b/Documentation/gpu/intel-display/drrs.rst new file mode 100644 index 00000000000000..a5aaba63d6b951 --- /dev/null +++ b/Documentation/gpu/intel-display/drrs.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display Refresh Rate Switching (DRRS) +===================================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c + :doc: Display Refresh Rate Switching (DRRS) + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c + :internal: diff --git a/Documentation/gpu/intel-display/dsb.rst b/Documentation/gpu/intel-display/dsb.rst new file mode 100644 index 00000000000000..857aca59995ada --- /dev/null +++ b/Documentation/gpu/intel-display/dsb.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display State Buffer +==================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c + :doc: DSB + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c + :internal: diff --git a/Documentation/gpu/intel-display/fbc.rst b/Documentation/gpu/intel-display/fbc.rst new file mode 100644 index 00000000000000..de9e19021f507a --- /dev/null +++ b/Documentation/gpu/intel-display/fbc.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Frame Buffer Compression (FBC) +============================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c + :doc: Frame Buffer Compression (FBC) + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c + :internal: diff --git a/Documentation/gpu/intel-display/fifo-underrun.rst b/Documentation/gpu/intel-display/fifo-underrun.rst new file mode 100644 index 00000000000000..5d8f0192150694 --- /dev/null +++ b/Documentation/gpu/intel-display/fifo-underrun.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Display FIFO Underrun Reporting +=============================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c + :doc: fifo underrun handling + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c + :internal: diff --git a/Documentation/gpu/intel-display/frontbuffer.rst b/Documentation/gpu/intel-display/frontbuffer.rst new file mode 100644 index 00000000000000..7ae38e0827bf17 --- /dev/null +++ b/Documentation/gpu/intel-display/frontbuffer.rst @@ -0,0 +1,14 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Frontbuffer Tracking +==================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c + :doc: frontbuffer tracking + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h + :internal: + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c + :internal: diff --git a/Documentation/gpu/intel-display/hotplug.rst b/Documentation/gpu/intel-display/hotplug.rst new file mode 100644 index 00000000000000..f33bc0087c2787 --- /dev/null +++ b/Documentation/gpu/intel-display/hotplug.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Hotplug +======= + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c + :doc: Hotplug + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c + :internal: diff --git a/Documentation/gpu/intel-display/index.rst b/Documentation/gpu/intel-display/index.rst new file mode 100644 index 00000000000000..01c3d1e576b713 --- /dev/null +++ b/Documentation/gpu/intel-display/index.rst @@ -0,0 +1,44 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +.. _drm/intel-display: + +==================== +Intel Display Driver +==================== + +The Intel display driver provides the display, or :ref:`drm-kms`, support for +both the :ref:`drm/xe ` and :ref:`drm/i915 ` Intel GPU +drivers. + +The source code currently resides under ``drivers/gpu/drm/i915/display`` due to +historical reasons, and it's compiled separately into both drm/xe and drm/i915 +kernel modules. + +The drm/xe and drm/i915 drivers are the "core" or "parent" drivers for display, +as they initialize and own the drm device, and pass that on to the display +driver. The display driver isn't an independent driver in that sense. + +.. toctree:: + :maxdepth: 1 + :caption: Detailed display topics + + async-flip + atomic + audio + casf + cdclk + cmtg + dmc + dpio + dpll + drrs + dsb + fbc + fifo-underrun + frontbuffer + hotplug + plane + psr + snps-phy + vbt diff --git a/Documentation/gpu/intel-display/plane.rst b/Documentation/gpu/intel-display/plane.rst new file mode 100644 index 00000000000000..59932a82051b54 --- /dev/null +++ b/Documentation/gpu/intel-display/plane.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Atomic Plane Helpers +==================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c + :doc: atomic plane helpers + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c + :internal: diff --git a/Documentation/gpu/intel-display/psr.rst b/Documentation/gpu/intel-display/psr.rst new file mode 100644 index 00000000000000..63e56abcdd5646 --- /dev/null +++ b/Documentation/gpu/intel-display/psr.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Panel Self Refresh PSR (PSR/SRD) +================================ + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c + :doc: Panel Self Refresh (PSR/SRD) + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c + :internal: diff --git a/Documentation/gpu/intel-display/snps-phy.rst b/Documentation/gpu/intel-display/snps-phy.rst new file mode 100644 index 00000000000000..c9e333fa7f62ed --- /dev/null +++ b/Documentation/gpu/intel-display/snps-phy.rst @@ -0,0 +1,8 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Synopsis PHY support +==================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_snps_phy.c + :doc: Synopsis PHY support diff --git a/Documentation/gpu/intel-display/vbt.rst b/Documentation/gpu/intel-display/vbt.rst new file mode 100644 index 00000000000000..be69f7fd7b396a --- /dev/null +++ b/Documentation/gpu/intel-display/vbt.rst @@ -0,0 +1,14 @@ +.. SPDX-License-Identifier: MIT +.. Copyright © 2026 Intel Corporation + +Video BIOS Table (VBT) +====================== + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c + :doc: Video BIOS Table (VBT) + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c + :internal: + +.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h + :internal: diff --git a/Documentation/gpu/introduction.rst b/Documentation/gpu/introduction.rst index d8f519693fc2ce..64074ac22d9b73 100644 --- a/Documentation/gpu/introduction.rst +++ b/Documentation/gpu/introduction.rst @@ -16,6 +16,8 @@ found in current kernels. [Insert diagram of typical DRM stack here] +.. contents:: + Style Guidelines ================ diff --git a/Documentation/gpu/komeda-kms.rst b/Documentation/gpu/komeda-kms.rst index eaea40eb725b75..9c074594065904 100644 --- a/Documentation/gpu/komeda-kms.rst +++ b/Documentation/gpu/komeda-kms.rst @@ -367,7 +367,7 @@ So, one KMS-Obj represents a sub-pipeline of komeda resources. So, for komeda, we treat KMS crtc/plane/connector as users of pipeline and component, and at any one time a pipeline/component only can be used by one user. And pipeline/component will be treated as private object of DRM-KMS; the -state will be managed by drm_atomic_state as well. +state will be managed by drm_atomic_commit as well. How to map plane to Layer(input) pipeline ----------------------------------------- @@ -416,8 +416,8 @@ Add :c:type:`drm_private_obj` to :c:type:`komeda_component`, :c:type:`komeda_pip ... } -Tracking component_state/pipeline_state by drm_atomic_state ------------------------------------------------------------ +Tracking component_state/pipeline_state by drm_atomic_commit +------------------------------------------------------------ Add :c:type:`drm_private_state` and user to :c:type:`komeda_component_state`, :c:type:`komeda_pipeline_state` @@ -454,7 +454,7 @@ similar, usually including the following steps: put the data flow into next stage. Setup 2: check user_state with component features and capabilities to see if requirements can be met; if not, return fail. - Setup 3: get component_state from drm_atomic_state, and try set to set + Setup 3: get component_state from drm_atomic_commit, and try set to set user to component; fail if component has been assigned to another user already. Setup 3: configure the component_state, like set its input component, diff --git a/Documentation/gpu/nova/core/vbios.rst b/Documentation/gpu/nova/core/vbios.rst index efd40087480c4f..9d3379ccfb3070 100644 --- a/Documentation/gpu/nova/core/vbios.rst +++ b/Documentation/gpu/nova/core/vbios.rst @@ -46,12 +46,71 @@ region is only accessible to heavy-secure ucode. are of type 0xE0 and can be identified as such. This could be subject to change in future generations. +IFR Header +---------- +On Kepler and later GPUs, the ROM begins with an Init-from-ROM (IFR) header +rather than a standard PCI ROM signature (0xAA55). The driver must parse the +IFR header to find where the PCI ROM images actually start. + +Init-from-ROM (IFR) is a special GPU feature used for power management +on some Nvidia GPUs. It references data in the VBIOS for its operation, +but for drivers the important piece is a header that precedes the +VBIOS PCI Expansion ROM. + +Most such GPUs do not need to parse the IFR header in order to find the +VBIOS, but the Nvidia GA100 is the exception. GA100 lacks a display engine, +so the PRAMIN method (which reads the VBIOS from VRAM via display hardware) +is unavailable, forcing the driver to read the ROM directly via PROM. +On other similar GPUs, either PRAMIN succeeds before PROM is tried, or the +IFR hardware has already applied the ROM offset so that PROM reads +transparently skip the IFR header. + +The driver should first check for the standard 0xAA55 signature at offset 0. +If found, there is no IFR header and the PCI ROM images start at +offset 0. If not found, check for the IFR signature and parse the header to +determine the PCI ROM image offset. + +Fixed Header Format +~~~~~~~~~~~~~~~~~~~ + +The IFR header begins with four 32-bit words at fixed offsets:: + + Offset Name Fields + ------ ------- ------ + 0x00 FIXED0 bits 31:0 - Signature (must be 0x4947564E, ASCII "NVGI") + 0x04 FIXED1 bit 31 - Reserved + bits 30:16 - FIXED_DATA_SIZE Fixed data size (offset to extended section) + bits 15:8 - VERSIONSW Software version + bits 7:0 - Reserved + 0x08 FIXED2 bit 31 - Reserved + bits 30:20 - Reserved (zero) + bits 19:0 - TOTAL_DATA_SIZE Total data size + +Finding the PCI ROM Image Offset +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +The method to find this offset depends on `VERSIONSW`. + +- **Version 1 and 2**: Read `FIXED_DATA_SIZE` from `FIXED1` to get the extended + section offset. The PCI ROM image is the 32-bit value at `FIXED_DATA_SIZE + 4`. + +- **Version 3**: Read `TOTAL_DATA_SIZE` from `FIXED2`. The 32-bit value at that + offset is a flash status offset. Add 4096 to get the ROM directory offset, + `ROM_DIRECTORY_OFFSET`. The ROM directory must have signature 0x44524652 + (ASCII "RFRD"). The PCI ROM image offset is the 32-bit value at + `ROM_DIRECTORY_OFFSET + 8`. + +The PCI ROM image offset must be 4-byte aligned. All offsets are relative to the +start of ROM (BAR0 + 0x300000). + VBIOS ROM Layout ---------------- -The VBIOS layout is roughly a series of concatenated images laid out as follows:: +The VBIOS (PCI Expansion ROM) is a series of concatenated images laid out as +follows. On GPUs with an IFR header, this layout begins at the image offset +determined by parsing the IFR header. On older GPUs, it begins at offset 0:: +----------------------------------------------------------------------------+ - | VBIOS (Starting at ROM_OFFSET: 0x300000) | + | VBIOS (Starting at ROM_OFFSET: 0x300000 + IFR image offset) | +----------------------------------------------------------------------------+ | +-----------------------------------------------+ | | | PciAt Image (Type 0x00) | | @@ -173,7 +232,7 @@ Falcon data in the VBIOS which contains the PMU lookup table. This lookup table used to find the required Falcon ucode based on an application ID. The location of the PMU lookup table is found by scanning the BIT (`BIOS Information Table`_) -tokens for a token with the id `BIT_TOKEN_ID_FALCON_DATA` (0x70) which indicates the +tokens for a token with the Falcon data token id (0x70) which indicates the offset of the same from the start of the VBIOS image. Unfortunately, the offset does not account for the EFI image located between the PciAt and FwSec images. The `vbios.rs` code compensates for this with appropriate arithmetic. diff --git a/Documentation/gpu/rfc/index.rst b/Documentation/gpu/rfc/index.rst index ef19b0ba2a3ea4..26a7ebe6fb4459 100644 --- a/Documentation/gpu/rfc/index.rst +++ b/Documentation/gpu/rfc/index.rst @@ -18,23 +18,9 @@ host such documentation: .. toctree:: - gpusvm.rst - -.. toctree:: - - i915_gem_lmem.rst - -.. toctree:: - - i915_scheduler.rst - -.. toctree:: - - i915_small_bar.rst - -.. toctree:: - - i915_vm_bind.rst - -.. toctree:: - color_pipeline.rst \ No newline at end of file + gpusvm + i915_gem_lmem + i915_scheduler + i915_small_bar + i915_vm_bind + color_pipeline diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index bc9f14c8a2ec22..cdddf8db35f533 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -152,29 +152,6 @@ Contact: Simona Vetter, respective driver maintainers Level: Advanced -Rename drm_atomic_state ------------------------ - -The KMS framework uses two slightly different definitions for the ``state`` -concept. For a given object (plane, CRTC, encoder, etc., so -``drm_$OBJECT_state``), the state is the entire state of that object. However, -at the device level, ``drm_atomic_state`` refers to a state update for a -limited number of objects. - -The state isn't the entire device state, but only the full state of some -objects in that device. This is confusing to newcomers, and -``drm_atomic_state`` should be renamed to something clearer like -``drm_atomic_commit``. - -In addition to renaming the structure itself, it would also imply renaming some -related functions (``drm_atomic_state_alloc``, ``drm_atomic_state_get``, -``drm_atomic_state_put``, ``drm_atomic_state_init``, -``__drm_atomic_state_free``, etc.). - -Contact: Maxime Ripard - -Level: Advanced - Fallout from atomic KMS ----------------------- diff --git a/Documentation/gpu/xe/index.rst b/Documentation/gpu/xe/index.rst index bc432c95d1a359..665c0e93601c50 100644 --- a/Documentation/gpu/xe/index.rst +++ b/Documentation/gpu/xe/index.rst @@ -1,5 +1,7 @@ .. SPDX-License-Identifier: (GPL-2.0+ OR MIT) +.. _drm/xe: + ======================= drm/xe Intel GFX Driver ======================= @@ -8,6 +10,9 @@ The drm/xe driver supports some future GFX cards with rendering, display, compute and media. Support for currently available platforms like TGL, ADL, DG2, etc is provided to prototype the driver. +The display, or :ref:`drm-kms`, support for drm/xe is provided by +:ref:`drm/intel-display`, and shared with :ref:`drm/i915 `. + .. toctree:: :titlesonly: @@ -29,3 +34,4 @@ DG2, etc is provided to prototype the driver. xe_device xe-drm-usage-stats.rst xe_configfs + xe_gt_stats diff --git a/Documentation/gpu/xe/xe_firmware.rst b/Documentation/gpu/xe/xe_firmware.rst index 9c15a300bc6257..d3030d1c9a8458 100644 --- a/Documentation/gpu/xe/xe_firmware.rst +++ b/Documentation/gpu/xe/xe_firmware.rst @@ -7,10 +7,10 @@ Firmware Firmware Layout =============== -.. kernel-doc:: drivers/gpu/drm/xe/xe_uc_fw_abi.h +.. kernel-doc:: drivers/gpu/drm/xe/abi/uc_fw_abi.h :doc: CSS-based Firmware Layout -.. kernel-doc:: drivers/gpu/drm/xe/xe_uc_fw_abi.h +.. kernel-doc:: drivers/gpu/drm/xe/abi/uc_fw_abi.h :doc: GSC-based Firmware Layout Write Once Protected Content Memory (WOPCM) Layout diff --git a/Documentation/gpu/xe/xe_gt_stats.rst b/Documentation/gpu/xe/xe_gt_stats.rst new file mode 100644 index 00000000000000..5ff806abaddb8a --- /dev/null +++ b/Documentation/gpu/xe/xe_gt_stats.rst @@ -0,0 +1,11 @@ +.. SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +================ +Xe GT Statistics +================ + +.. kernel-doc:: drivers/gpu/drm/xe/xe_gt_stats.c + :doc: Xe GT Statistics + +.. kernel-doc:: drivers/gpu/drm/xe/xe_gt_stats_types.h + :internal: diff --git a/Documentation/hwmon/adt7411.rst b/Documentation/hwmon/adt7411.rst index 57ad16fb216af6..28b6f3cb6b86cc 100644 --- a/Documentation/hwmon/adt7411.rst +++ b/Documentation/hwmon/adt7411.rst @@ -30,11 +30,36 @@ Check the datasheet for details. sysfs-Interface --------------- -================ ================= -in0_input vdd voltage input -in[1-8]_input analog 1-8 input -temp1_input temperature input -================ ================= +================ ================================= +in0_input vdd voltage input +in0_min vdd low limit +in0_max vdd high limit +in0_alarm vdd alarm +in[1-8]_input analog 1-8 input +in[1-8]_min analog input low limit +in[1-8]_max analog input high limit +in[1-8]_alarm analog input alarm +temp1_input internal temperature input +temp1_min internal temperature low limit +temp1_max internal temperature high limit +temp1_min_alarm internal temperature low alarm +temp1_max_alarm internal temperature high alarm +================ ================================= + +If the external temperature sensor is enabled, the following attributes are +also available: + +================ ================================================ +temp2_input external temperature input +temp2_min external temperature low limit +temp2_max external temperature high limit +temp2_min_alarm external temperature low alarm +temp2_max_alarm external temperature high alarm +temp2_fault external temperature sensor fault +================ ================================================ + +If the external temperature sensor is enabled, analog inputs in1 and in2 are +not available. Besides standard interfaces, this driver adds (0 = off, 1 = on): @@ -47,4 +72,4 @@ Besides standard interfaces, this driver adds (0 = off, 1 = on): Notes ----- -SPI, external temperature sensor and limit registers are not supported yet. +SPI is not supported yet. diff --git a/Documentation/hwmon/arctic_fan_controller.rst b/Documentation/hwmon/arctic_fan_controller.rst new file mode 100644 index 00000000000000..b5be88ae464d7d --- /dev/null +++ b/Documentation/hwmon/arctic_fan_controller.rst @@ -0,0 +1,56 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Kernel driver arctic_fan_controller +===================================== + +Supported devices: + +* ARCTIC Fan Controller (USB HID, VID 0x3904, PID 0xF001) + +Author: Aureo Serrano de Souza + +Description +----------- + +This driver provides hwmon support for the ARCTIC Fan Controller, a USB +Custom HID device with 10 fan channels. The device sends IN reports about +once per second containing current RPM values (bytes 11-30, 10 x uint16 LE). +Fan speed control is manual-only: the device does not change PWM +autonomously; it only applies a new duty cycle when it receives an OUT +report from the host. + +After the device applies an OUT report, it sends back a 2-byte ACK IN +report (Report ID 0x02, byte 1 = 0x00 on success) confirming the command +was applied. + +Usage notes +----------- + +Since it is a USB device, hotplug is supported. The device is autodetected. + +The device does not support GET_REPORT, so the driver cannot read back the +current hardware PWM state at probe time. The cached PWM values (readable +via pwm[1-10]) start at 0 and reflect only values that have been +successfully written. Because each OUT report carries all 10 channel values, +writing a single channel also sends the cached values for all other channels. +Users should set all channels to the desired values before relying on the +cached state. + +On system suspend, the device may lose power and reset its PWM channels to +hardware defaults. The driver clears its cached duty values on resume so +that reads reflect the unknown hardware state rather than stale pre-suspend +values. Userspace is responsible for re-applying the desired duty cycles +after resume. + +Sysfs entries +------------- + +================ ============================================================== +fan[1-10]_input Fan speed in RPM (read-only). Updated from IN reports at ~1 Hz. +pwm[1-10] PWM duty cycle (0-255). Write: sends an OUT report setting the + duty cycle (scaled from 0-255 to 0-100% for the device); + the cached value is updated only after the device ACKs the + command with a success status. Read: returns the last + successfully written value; initialized to 0 at driver load + and after resume (hardware state unknown). +================ ============================================================== diff --git a/Documentation/hwmon/asus_ec_sensors.rst b/Documentation/hwmon/asus_ec_sensors.rst index 9ad3f0a57f55f3..77a709517437ad 100644 --- a/Documentation/hwmon/asus_ec_sensors.rst +++ b/Documentation/hwmon/asus_ec_sensors.rst @@ -29,9 +29,12 @@ Supported boards: * ROG MAXIMUS XI HERO * ROG MAXIMUS XI HERO (WI-FI) * ROG MAXIMUS Z690 FORMULA + * ROG MAXIMUS Z790 EXTREME * ROG STRIX B550-E GAMING * ROG STRIX B550-I GAMING + * ROG STRIX B650E-E GAMING WIFI * ROG STRIX B650E-I GAMING WIFI + * ROG STRIX B850-E GAMING WIFI * ROG STRIX B850-I GAMING WIFI * ROG STRIX X470-F GAMING * ROG STRIX X470-I GAMING diff --git a/Documentation/hwmon/coretemp.rst b/Documentation/hwmon/coretemp.rst index 7a5fbb37b0f33c..f63b21f24d42c1 100644 --- a/Documentation/hwmon/coretemp.rst +++ b/Documentation/hwmon/coretemp.rst @@ -22,8 +22,7 @@ Supported chips: Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide - - http://softwarecommunity.intel.com/Wiki/Mobility/720.htm + (https://www.intel.com/content/www/us/en/developer/articles/technical/intel-sdm.html) Author: Rudolf Marek @@ -51,12 +50,13 @@ All Sysfs entries are named with their core_id (represented here by 'X'). ================= ======================================================== tempX_input Core temperature (in millidegrees Celsius). -tempX_max All cooling devices should be turned on (on Core2). +tempX_max Maximum recommended operating temperature (Tcontrol). + All cooling devices should be turned on. tempX_crit Maximum junction temperature (in millidegrees Celsius). tempX_crit_alarm Set when Out-of-spec bit is set, never clears. Correct CPU operation is no longer guaranteed. tempX_label Contains string "Core X", where X is processor - number. For Package temp, this will be "Physical id Y", + number. For Package temp, this will be "Package id Y", where Y is the package number. ================= ======================================================== diff --git a/Documentation/hwmon/d1u74t.rst b/Documentation/hwmon/d1u74t.rst new file mode 100644 index 00000000000000..3a9eedbda4837e --- /dev/null +++ b/Documentation/hwmon/d1u74t.rst @@ -0,0 +1,81 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Kernel driver d1u74t +==================== + +Supported chips: + + * Murata D1U74T + + Prefix: 'd1u74t' + + Addresses scanned: - + + Datasheet: Publicly available at the Murata website + +Authors: + Abdurrahman Hussain + + +Description +----------- + +This driver implements support for Murata D1U74T Power Supply with +PMBus support. + +The driver is a client driver to the core PMBus driver. +Please see Documentation/hwmon/pmbus.rst for details on PMBus client drivers. + + +Usage Notes +----------- + +This driver does not auto-detect devices. You will have to instantiate the +devices explicitly. Please see Documentation/i2c/instantiating-devices.rst for +details. + + +Sysfs entries +------------- + +======================= ====================================================== +curr1_label "iin" +curr1_input Measured input current +curr1_alarm Input current alarm +curr1_rated_max Maximum rated input current + +curr2_label "iout1" +curr2_input Measured output current +curr2_max Maximum output current +curr2_max_alarm Output current high alarm +curr2_crit Critical high output current +curr2_crit_alarm Output current critical high alarm +curr2_rated_max Maximum rated output current + +in1_label "vin" +in1_input Measured input voltage +in1_alarm Input voltage alarm +in1_rated_min Minimum rated input voltage +in1_rated_max Maximum rated input voltage + +in2_label "vout1" +in2_input Measured output voltage +in2_alarm Output voltage alarm +in2_rated_min Minimum rated output voltage +in2_rated_max Maximum rated output voltage + +power1_label "pin" +power1_input Measured input power +power1_alarm Input power alarm +power1_rated_max Maximum rated input power + +temp[1-3]_input Measured temperature +temp[1-3]_max Maximum temperature +temp[1-3]_max_alarm Maximum temperature alarm +temp[1-3]_rated_max Maximum rated temperature + +fan1_alarm Fan 1 warning +fan1_fault Fan 1 fault +fan1_input Fan 1 speed in RPM +fan1_target Fan 1 target +======================= ====================================================== diff --git a/Documentation/hwmon/e50sn12051.rst b/Documentation/hwmon/e50sn12051.rst new file mode 100644 index 00000000000000..cbbfa7895d8297 --- /dev/null +++ b/Documentation/hwmon/e50sn12051.rst @@ -0,0 +1,81 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Kernel driver e50sn12051 +======================== + +Supported chips: + + * Delta E50SN12051 + + Prefix: 'e50sn12051' + + Addresses scanned: - + + Datasheet: + + Provided by Delta upon request and NDA + +Description +----------- + +E50SN12051 is a 600W non-isolated 1/8th brick DC-DC power module. + +This driver supports the E50SN12051 PMBus compliant monitor device. + +The device provides measurements for: + +* Input voltage +* Output current +* Output voltage +* Temperature + +The driver is based on the PMBus core and exposes standard hwmon +sysfs attributes. + +Sysfs attributes +---------------- + +======================= ======================================================= +curr1_label "iout1" +curr1_crit Critical maximum current. + From IOUT_OC_FAULT_LIMIT register. +curr1_crit_alarm Current critical high alarm. + From IOUT_OC_FAULT status. +curr1_input Measured current. + From READ_IOUT register. +curr1_max Maximum current. + From IOUT_OC_WARN_LIMIT register. +curr1_max_alarm Current high alarm. + From IOUT_OC_WARN_LIMIT status. + +in1_label "vin" +in1_alarm Input voltage alarm. +in1_input Measured voltage. + From READ_VIN register. + +in2_label "vout1" +in2_crit Critical maximum voltage. + From VOUT_OV_FAULT_LIMIT register. +in2_crit_alarm Voltage critical high alarm. + From VOLTAGE_OV_FAULT status. +in2_input Measured voltage. + From READ_VOUT register. +in2_max Maximum voltage. + From VOUT_OV_WARN_LIMIT register. +in2_max_alarm Voltage high alarm. + From VOLTAGE_OV_WARNING status. + +temp1_crit Critical high temperature. + From OT_FAULT_LIMIT register. +temp1_crit_alarm Module temperature critical high alarm. + Set by comparing READ_TEMPERATURE_1 with OT_FAULT_LIMIT + if TEMP_OT_FAULT status is set. +temp1_input Measured module's hot spot temperature. + From READ_TEMPERATURE_1 register. +temp1_max Maximum temperature. + From OT_WARN_LIMIT register. +temp1_max_alarm Module temperature high alarm. + Set by comparing READ_TEMPERATURE_1 with OT_WARN_LIMIT if + TEMP_OT_WARNING status is set. +======================= ======================================================= + diff --git a/Documentation/hwmon/emc1812.rst b/Documentation/hwmon/emc1812.rst new file mode 100644 index 00000000000000..0b4fbcaaea71a4 --- /dev/null +++ b/Documentation/hwmon/emc1812.rst @@ -0,0 +1,67 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Kernel driver emc1812 +===================== + +Supported chips: + + * Microchip EMC1812, EMC1813, EMC1814, EMC1815, EMC1833 + + Prefix: 'emc1812' + + Datasheets: + + - https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/EMC1812-3-4-5-33-Data-Sheet-DS20005751.pdf + +Author: + Marius Cristea + + +Description +----------- + +The Microchip EMC181x/33 chips contain up to 4 remote temperature sensors +and one internal. +- The EMC1812 is a single channel remote temperature sensor. +- The EMC1813 and EMC1833 are dual channel remote temperature sensor. The +remote channels for this selection of devices can support substrate diodes, +discrete diode-connected transistors or CPU/GPU thermal diodes. +- The EMC1814 is a three channel remote temperature sensor that supports +Anti-Parallel Diode (APD) only on one channel. For the channel that does not +support APD functionality, substrate diodes, discrete diode-connected +transistors or CPU/GPU thermal diodes are supported. For the channel that +supports APD, only discrete diode-connected transistors may be implemented. +However, if APD is disabled on the EMC1814, then the channel that supports +APD will be functional with substrate diodes, discrete diode-connected +transistors and CPU/GPU thermal diodes. +- The EMC1815 is a four channel remote temperature sensor. + +The EMC1815 and EMC1833 support APD on all channels. When APD is enabled, +the channels support only diode-connected transistors. If APD is disabled, +then the channels will support substrate transistors, discrete diode-connected +transistors and CPU/GPU thermal diodes. + +Note: Disabling APD functionality to implement substrate diodes on devices +that support APD eliminates the benefit of APD (two diodes on one channel). + +The chips implement three limits for each sensor: low (tempX_min), high +(tempX_max) and critical (tempX_crit). The chips also implement an +hysteresis mechanism which applies to all limits. The relative difference +is stored in a single register on the chip, which means that the relative +difference between the limit and its hysteresis is always the same for +all three limits. + +This implementation detail implies the following: + +* When setting a limit, its hysteresis will automatically follow, the + difference staying unchanged. For example, if the old critical limit was + 80 degrees C, and the hysteresis was 75 degrees C, and you change the + critical limit to 90 degrees C, then the hysteresis will automatically + change to 85 degrees C. +* The hysteresis values can't be set independently. We decided to make + only tempX_crit_hyst writable, while all other hysteresis attributes + are read-only. Setting tempX_crit_hyst writes the difference between + tempX_crit_hyst and tempX_crit into the chip, and the same relative + hysteresis applies automatically to all other limits. +* The limits should be set before the hysteresis. At power up the device + starts with 10 degree hysteresis. diff --git a/Documentation/hwmon/htu31.rst b/Documentation/hwmon/htu31.rst index ccde84264643d7..9ab774dcf65dea 100644 --- a/Documentation/hwmon/htu31.rst +++ b/Documentation/hwmon/htu31.rst @@ -35,3 +35,10 @@ temp1_input: temperature input humidity1_input: humidity input heater_enable: heater control =================== ================= + +debugfs-Interface +----------------- + +=================== ========================================= +serial_number: unique serial number of the sensor +=================== ========================================= diff --git a/Documentation/hwmon/hwmon-kernel-api.rst b/Documentation/hwmon/hwmon-kernel-api.rst index 1d7f1397a82744..9fcde32a140df6 100644 --- a/Documentation/hwmon/hwmon-kernel-api.rst +++ b/Documentation/hwmon/hwmon-kernel-api.rst @@ -85,9 +85,10 @@ removal. When using ``[devm_]hwmon_device_register_with_info()`` to register the hardware monitoring device, accesses using the associated access functions are serialised by the hardware monitoring core. If a driver needs locking -for other functions such as interrupt handlers or for attributes which are -fully implemented in the driver, hwmon_lock() and hwmon_unlock() can be used -to ensure that calls to those functions are serialized. +for other functions such as interrupt handlers, attributes which are fully +implemented in the driver, or debugfs functions, hwmon_lock() and hwmon_unlock() +can be used to ensure that calls to those functions are serialized. Those +functions also support guard() and scoped_guard() variants. Using devm_hwmon_device_register_with_info() -------------------------------------------- diff --git a/Documentation/hwmon/ina238.rst b/Documentation/hwmon/ina238.rst index 43950d1ec551f7..a75b79e17d9dfa 100644 --- a/Documentation/hwmon/ina238.rst +++ b/Documentation/hwmon/ina238.rst @@ -106,4 +106,8 @@ energy1_input Energy measurement (uJ) temp1_input Die temperature measurement (mC) temp1_max Maximum die temperature threshold (mC) temp1_max_alarm Maximum die temperature alarm + +samples ADC averaging count (1, 4, 16, 64, 128, 256, 512, 1024) +update_interval Total ADC conversion cycle time including averaging (ms) +update_interval_us Total ADC conversion cycle time including averaging (us) ======================= ======================================================= diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst index 8b655e5d6b68b9..29130df44d12f6 100644 --- a/Documentation/hwmon/index.rst +++ b/Documentation/hwmon/index.rst @@ -43,6 +43,7 @@ Hardware Monitoring Kernel Drivers amc6821 aps-379 aquacomputer_d5next + arctic_fan_controller asb100 asc7621 aspeed-g6-pwm-tach @@ -60,6 +61,7 @@ Hardware Monitoring Kernel Drivers corsair-psu cros_ec_hwmon crps + d1u74t da9052 da9055 dell-smm-hwmon @@ -68,7 +70,9 @@ Hardware Monitoring Kernel Drivers drivetemp ds1621 ds620 + e50sn12051 emc1403 + emc1812 emc2103 emc2305 emc6w201 @@ -145,7 +149,9 @@ Hardware Monitoring Kernel Drivers ltc4260 ltc4261 ltc4282 + ltc4283 ltc4286 + lx1308 macsmc-hwmon max127 max15301 @@ -158,6 +164,8 @@ Hardware Monitoring Kernel Drivers max197 max20730 max20751 + max20830 + max20860a max31722 max31730 max31760 @@ -185,6 +193,7 @@ Hardware Monitoring Kernel Drivers mp2925 mp29502 mp2975 + mp2985 mp2993 mp5023 mp5920 @@ -216,6 +225,7 @@ Hardware Monitoring Kernel Drivers pmbus powerz powr1220 + prom21-xhci pt5161l pxe1610 pwm-fan diff --git a/Documentation/hwmon/lm75.rst b/Documentation/hwmon/lm75.rst index 4269da04508ef5..ca46754e028b38 100644 --- a/Documentation/hwmon/lm75.rst +++ b/Documentation/hwmon/lm75.rst @@ -181,3 +181,19 @@ is supported by this driver, other specific enhancements are not. The LM77 is not supported, contrary to what we pretended for a long time. Both chips are simply not compatible, value encoding differs. + +sysfs-Interface +--------------- + +The following list includes the sysfs attributes that the driver provides, their +permissions and a short description: + +=============================== ======= =========================================== +Name Perm Description +=============================== ======= =========================================== +temp1_input RO Temperature input +temp1_label RO Descriptive name for the sensor +temp1_max RW Maximum temperature +temp1_max_hyst RW Maximum hysteresis temperature +update_interval RW Update conversions interval in milliseconds +=============================== ======= =========================================== diff --git a/Documentation/hwmon/ltc4283.rst b/Documentation/hwmon/ltc4283.rst new file mode 100644 index 00000000000000..99b1ee05f62993 --- /dev/null +++ b/Documentation/hwmon/ltc4283.rst @@ -0,0 +1,267 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +Kernel drivers ltc4283 +========================================== + +Supported chips: + + * Analog Devices LTC4283 + + Prefix: 'ltc4283' + + Addresses scanned: - + + Datasheet: + + https://www.analog.com/media/en/technical-documentation/data-sheets/ltc4283.pdf + +Author: Nuno Sá + +Description +___________ + +The LTC4283 negative voltage hot swap controller drives an external N-channel +MOSFET to allow a board to be safely inserted and removed from a live backplane. +The device features programmable current limit with foldback and independently +adjustable inrush current to optimize the MOSFET safe operating area (SOA). The +SOA timer limits MOSFET temperature rise for reliable protection against +overstresses. An I2C interface and onboard gear-shift ADC allow monitoring of +board current, voltage, power, energy, and fault status. Additional features +respond to input UV/OV, interrupt the host when a fault has occurred, notify +when output power is good, detect insertion of a board, turn off the MOSFET +if an external supply monitor fails to indicate power good within a timeout +period, and auto-reboot after a programmable delay following a host commanded +turn-off. + +Sysfs entries +_____________ + +The following attributes are supported. Limits are read-write and all the other +attributes are read-only. Note that the VADIOx channels might not be available +if the ADIO pins are used as GPIOs (naturally also affects the respective +differential channels). + +======================= ========================================== +in0_lcrit_alarm Critical Undervoltage alarm +in0_crit_alarm Critical Overvoltage alarm +in0_reset_history Clears Under and Overvoltage fault logs. +in0_label Channel label (VIN) + +in1_input Output voltage (mV). +in1_min Undervoltage threshold +in1_max Overvoltage threshold +in1_lowest Lowest measured voltage +in1_highest Highest measured voltage +in1_reset_history Write 1 to reset history. +in1_min_alarm Undervoltage alarm +in1_max_alarm Overvoltage alarm +in1_label Channel label (VPWR) + +in2_input Output voltage (mV). +in2_min Undervoltage threshold +in2_max Overvoltage threshold +in2_lowest Lowest measured voltage +in2_highest Highest measured voltage +in2_reset_history Write 1 to reset history. +in2_min_alarm Undervoltage alarm +in2_max_alarm Overvoltage alarm +in2_enable Enable/Disable monitoring. +in2_label Channel label (VADI1) + +in3_input Output voltage (mV). +in3_min Undervoltage threshold +in3_max Overvoltage threshold +in3_lowest Lowest measured voltage +in3_highest Highest measured voltage +in3_reset_history Write 1 to reset history. +in3_min_alarm Undervoltage alarm +in3_max_alarm Overvoltage alarm +in3_enable Enable/Disable monitoring. +in3_label Channel label (VADI2) + +in4_input Output voltage (mV). +in4_min Undervoltage threshold +in4_max Overvoltage threshold +in4_lowest Lowest measured voltage +in4_highest Highest measured voltage +in4_reset_history Write 1 to reset history. +in4_min_alarm Undervoltage alarm +in4_max_alarm Overvoltage alarm +in4_enable Enable/Disable monitoring. +in4_label Channel label (VADI3) + +in5_input Output voltage (mV). +in5_min Undervoltage threshold +in5_max Overvoltage threshold +in5_lowest Lowest measured voltage +in5_highest Highest measured voltage +in5_reset_history Write 1 to reset history. +in5_min_alarm Undervoltage alarm +in5_max_alarm Overvoltage alarm +in5_enable Enable/Disable monitoring. +in5_label Channel label (VADI4) + +in6_input Output voltage (mV). +in6_min Undervoltage threshold +in6_max Overvoltage threshold +in6_lowest Lowest measured voltage +in6_highest Highest measured voltage +in6_reset_history Write 1 to reset history. +in6_min_alarm Undervoltage alarm +in6_max_alarm Overvoltage alarm +in6_enable Enable/Disable monitoring. +in6_label Channel label (VADIO1) + +in7_input Output voltage (mV). +in7_min Undervoltage threshold +in7_max Overvoltage threshold +in7_lowest Lowest measured voltage +in7_highest Highest measured voltage +in7_reset_history Write 1 to reset history. +in7_min_alarm Undervoltage alarm +in7_max_alarm Overvoltage alarm +in7_enable Enable/Disable monitoring. +in7_label Channel label (VADIO2) + +in8_input Output voltage (mV). +in8_min Undervoltage threshold +in8_max Overvoltage threshold +in8_lowest Lowest measured voltage +in8_highest Highest measured voltage +in8_reset_history Write 1 to reset history. +in8_min_alarm Undervoltage alarm +in8_max_alarm Overvoltage alarm +in8_enable Enable/Disable monitoring. +in8_label Channel label (VADIO3) + +in9_input Output voltage (mV). +in9_min Undervoltage threshold +in9_max Overvoltage threshold +in9_lowest Lowest measured voltage +in9_highest Highest measured voltage +in9_reset_history Write 1 to reset history. +in9_min_alarm Undervoltage alarm +in9_max_alarm Overvoltage alarm +in9_enable Enable/Disable monitoring. +in9_label Channel label (VADIO4) + +in10_input Output voltage (mV). +in10_min Undervoltage threshold +in10_max Overvoltage threshold +in10_lowest Lowest measured voltage +in10_highest Highest measured voltage +in10_reset_history Write 1 to reset history. +in10_min_alarm Undervoltage alarm +in10_max_alarm Overvoltage alarm +in10_enable Enable/Disable monitoring. +in10_label Channel label (DRNS) + +in11_input Output voltage (mV). +in11_min Undervoltage threshold +in11_max Overvoltage threshold +in11_lowest Lowest measured voltage +in11_highest Highest measured voltage +in11_reset_history Write 1 to reset history. + Also clears fet bad and short fault logs. +in11_min_alarm Undervoltage alarm +in11_max_alarm Overvoltage alarm +in11_enable Enable/Disable monitoring +in11_fault Failure in the MOSFET. Either bad or shorted FET. +in11_label Channel label (DRAIN) + +in12_input Output voltage (mV). +in12_min Undervoltage threshold +in12_max Overvoltage threshold +in12_lowest Lowest measured voltage +in12_highest Highest measured voltage +in12_reset_history Write 1 to reset history. +in12_min_alarm Undervoltage alarm +in12_max_alarm Overvoltage alarm +in12_enable Enable/Disable monitoring. +in12_label Channel label (ADIN2-ADIN1) + +in13_input Output voltage (mV). +in13_min Undervoltage threshold +in13_max Overvoltage threshold +in13_lowest Lowest measured voltage +in13_highest Highest measured voltage +in13_reset_history Write 1 to reset history. +in13_min_alarm Undervoltage alarm +in13_max_alarm Overvoltage alarm +in13_enable Enable/Disable monitoring. +in13_label Channel label (ADIN4-ADIN3) + +in14_input Output voltage (mV). +in14_min Undervoltage threshold +in14_max Overvoltage threshold +in14_lowest Lowest measured voltage +in14_highest Highest measured voltage +in14_reset_history Write 1 to reset history. +in14_min_alarm Undervoltage alarm +in14_max_alarm Overvoltage alarm +in14_enable Enable/Disable monitoring. +in14_label Channel label (ADIO2-ADIO1) + +in15_input Output voltage (mV). +in15_min Undervoltage threshold +in15_max Overvoltage threshold +in15_lowest Lowest measured voltage +in15_highest Highest measured voltage +in15_reset_history Write 1 to reset history. +in15_min_alarm Undervoltage alarm +in15_max_alarm Overvoltage alarm +in15_enable Enable/Disable monitoring. +in15_label Channel label (ADIO4-ADIO3) + +curr1_input Sense current (mA) +curr1_min Undercurrent threshold +curr1_max Overcurrent threshold +curr1_lowest Lowest measured current +curr1_highest Highest measured current +curr1_reset_history Write 1 to reset curr1 history. + Also clears overcurrent fault logs. +curr1_min_alarm Undercurrent alarm +curr1_max_alarm Overcurrent alarm +curr1_crit_alarm Critical Overcurrent alarm +curr1_label Channel label (ISENSE) + +power1_input Power (in uW) +power1_min Low power threshold +power1_max High power threshold +power1_input_lowest Historical minimum power use +power1_input_highest Historical maximum power use +power1_reset_history Write 1 to reset power1 history. + Also clears power fault logs. +power1_min_alarm Low power alarm +power1_max_alarm High power alarm +power1_label Channel label (Power) + +energy1_input Measured energy over time (in microJoule) +energy1_enable Enable/Disable Energy accumulation +======================= ========================================== + +DebugFs entries +_______________ + +The chip also has a fault log register where failures can be logged. Hence, +as these are logging events, we give access to them in debugfs. Note that +even if some failure is detected in these logs, it does necessarily mean +that the failure is still present. As mentioned in the proper Sysfs entries, +these logs can be cleared by writing in the proper reset_history attribute. + +.. warning:: The debugfs interface is subject to change without notice + and is only available when the kernel is compiled with + ``CONFIG_DEBUG_FS`` defined. + +``/sys/kernel/debug/i2c/i2c-[X]/[X]-addr/`` +contains the following attributes: + +============================== ========================================================== +power1_failed_fault_log Set to 1 by a power1 fault occurring. +power1_good_input_fault_log Set to 1 by a power1 good input fault occurring at PGIO3. +in11_fet_short_fault_log Set to 1 when a FET-short fault occurs. +in11_fet_bad_fault_log Set to 1 when a FET-BAD fault occurs. +in0_lcrit_fault_log Set to 1 by a VIN undervoltage fault occurring. +in0_crit_fault_log Set to 1 by a VIN overvoltage fault occurring. +curr1_crit_fault_log Set to 1 by an overcurrent fault occurring. +============================== ========================================================== diff --git a/Documentation/hwmon/lx1308.rst b/Documentation/hwmon/lx1308.rst new file mode 100644 index 00000000000000..c1b72e1647c529 --- /dev/null +++ b/Documentation/hwmon/lx1308.rst @@ -0,0 +1,90 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Kernel driver lx1308 +==================== + +Supported chips: + + * Luxshare LX1308 + + Prefixes: 'lx1308' + + Addresses scanned: - + + Datasheet: Datasheet is not publicly available. + +Author: Brian Chiang + + +Description +----------- + +The LX1308 is a high-efficiency, non-isolated, regulated 12V, 860W, +digital DC/DC power module. The module operates from a 40V to 60V DC +primary bus and provides a 12V regulated output voltage. It can deliver +up to 860W continuous and 1300W in transient. + +The module has slow OCP and fast OCP. If the module output current is higher +than slow OCP set point and the lasting time is also longer than the delay, +the module will shut down and retry 3 time, if the fault still exists then +module enter latch mode. + +If the module output current is higher than fast OCP set point then it shut +down and enter latch mode. + +The driver is a client driver to the core PMBus driver. +Please see Documentation/hwmon/pmbus.rst for details on PMBus client drivers. + + +Usage Notes +----------- + +This driver does not auto-detect devices. You will have to instantiate the +devices explicitly. Please see Documentation/i2c/instantiating-devices.rst for +details. + + +Sysfs entries +------------- + +======================= ====================================================== +curr1_alarm Input current alarm +curr1_input Input current (IIN) +curr1_label "iin" +curr2_crit Output over current fault threshold (slow OCP, 60ms delay) +curr2_crit_alarm Output over current fault alarm +curr2_input Output current (IOUT) +curr2_label "iout1" +curr2_max Output over current warning threshold (slow OCP, 60ms delay) +curr2_max_alarm Output over current warning alarm +in1_crit Input over voltage fault threshold +in1_crit_alarm Input over voltage fault alarm +in1_input Input voltage (VIN) +in1_label "vin" +in1_lcrit Input under voltage fault threshold +in1_lcrit_alarm Input under voltage fault alarm +in1_max Input over voltage warning threshold +in1_max_alarm Input over voltage warning alarm +in1_min Input under voltage warning threshold +in1_min_alarm Input under voltage warning alarm +in2_crit Output over voltage fault threshold +in2_crit_alarm Output over voltage fault alarm +in2_input Output voltage (VOUT) +in2_label "vout1" +in2_lcrit Output under voltage fault threshold +in2_lcrit_alarm Output under voltage fault alarm +in2_max Output over voltage warning threshold +in2_max_alarm Output over voltage warning alarm +in2_min Output under voltage warning threshold +in2_min_alarm Output under voltage warning alarm +power1_alarm Input power alarm +power1_input Input power (PIN) +power1_label "pin" +power2_input Output power (POUT) +power2_label "pout1" +temp1_crit Over temperature fault threshold +temp1_crit_alarm Over temperature fault alarm +temp1_input Module hot spot temperature +temp1_max Over temperature warning threshold +temp1_max_alarm Over temperature warning alarm +======================= ====================================================== diff --git a/Documentation/hwmon/max20830.rst b/Documentation/hwmon/max20830.rst new file mode 100644 index 00000000000000..936e409dcc5c08 --- /dev/null +++ b/Documentation/hwmon/max20830.rst @@ -0,0 +1,49 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Kernel driver max20830 +====================== + +Supported chips: + + * Analog Devices MAX20830 + + Prefix: 'max20830' + + Addresses scanned: - + + Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/max20830.pdf + +Author: + + - Alexis Czezar Torreno + + +Description +----------- + +This driver supports hardware monitoring for Analog Devices MAX20830 +Step-Down Switching Regulator with PMBus Interface. + +The MAX20830 is a 2.7V to 16V, 30A fully integrated step-down DC-DC switching +regulator. Through the PMBus interface, the device can monitor input/output +voltages, output current and temperature. + +The driver is a client driver to the core PMBus driver. Please see +Documentation/hwmon/pmbus.rst for details on PMBus client drivers. + +Sysfs entries +------------- + +================= ======================================== +in1_label "vin" +in1_input Measured input voltage +in1_alarm Input voltage alarm +in2_label "vout1" +in2_input Measured output voltage +in2_alarm Output voltage alarm +curr1_label "iout1" +curr1_input Measured output current +curr1_alarm Output current alarm +temp1_input Measured temperature +temp1_alarm Chip temperature alarm +================= ======================================== diff --git a/Documentation/hwmon/max20860a.rst b/Documentation/hwmon/max20860a.rst new file mode 100644 index 00000000000000..ea6d2228fafc03 --- /dev/null +++ b/Documentation/hwmon/max20860a.rst @@ -0,0 +1,57 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Kernel driver max20860a +======================= + +Supported chips: + + * Analog Devices MAX20860A + + Prefix: 'max20860a' + + Addresses scanned: - + + Datasheet: https://www.analog.com/en/products/max20860a.html + +Author: + + - Syed Arif + - Sanman Pradhan + + +Description +----------- + +This driver supports hardware monitoring for Analog Devices MAX20860A +Step-Down Switching Regulator with PMBus Interface. + +The MAX20860A is a fully integrated step-down DC-DC switching regulator. +Through the PMBus interface, the device can monitor input/output voltages, +output current and temperature. + +The driver is a client driver to the core PMBus driver. Please see +Documentation/hwmon/pmbus.rst for details on PMBus client drivers. + +Usage Notes +----------- + +This driver does not auto-detect devices. You will have to instantiate +the devices explicitly. + +Sysfs entries +------------- + +================= ======================================== +in1_label "vin" +in1_input Measured input voltage +in1_alarm Input voltage alarm +in2_label "vout1" +in2_input Measured output voltage +in2_alarm Output voltage alarm +curr1_label "iout1" +curr1_input Measured output current +curr1_alarm Output current alarm +temp1_input Measured temperature +temp1_alarm Chip temperature alarm +temp2_input Measured temperature (secondary) +================= ======================================== diff --git a/Documentation/hwmon/max31730.rst b/Documentation/hwmon/max31730.rst index 1c5a32b641879d..0936ba2eac2474 100644 --- a/Documentation/hwmon/max31730.rst +++ b/Documentation/hwmon/max31730.rst @@ -1,4 +1,4 @@ -Kernel driver max31790 +Kernel driver max31730 ====================== Supported chips: diff --git a/Documentation/hwmon/max34440.rst b/Documentation/hwmon/max34440.rst index d6d4fbc863d96c..e7421f4dbf38fc 100644 --- a/Documentation/hwmon/max34440.rst +++ b/Documentation/hwmon/max34440.rst @@ -19,6 +19,14 @@ Supported chips: Datasheet: - + * ADI ADPM12250 + + Prefixes: 'adpm12250' + + Addresses scanned: - + + Datasheet: - + * Maxim MAX34440 Prefixes: 'max34440' @@ -87,11 +95,11 @@ This driver supports multiple devices: hardware monitoring for Maxim MAX34440 PMBus 6-Channel Power-Supply Manager, MAX34441 PMBus 5-Channel Power-Supply Manager and Intelligent Fan Controller, and MAX34446 PMBus Power-Supply Data Logger; PMBus Voltage Monitor and Sequencers for MAX34451, MAX34460, and -MAX34461; PMBus DC/DC Power Module ADPM12160, and ADPM12200. The MAX34451 -supports monitoring voltage or current of 12 channels based on GIN pins. The -MAX34460 supports 12 voltage channels, and the MAX34461 supports 16 voltage -channels. The ADPM12160, and ADPM12200 also monitors both input and output -of voltage and current. +MAX34461; PMBus DC/DC Power Module ADPM12160, ADPM12200, and ADPM12250. The +MAX34451 supports monitoring voltage or current of 12 channels based on GIN +pins. The MAX34460 supports 12 voltage channels, and the MAX34461 supports 16 +voltage channels. The ADPM12160, ADPM12200, and ADPM12250 also monitors both +input and output of voltage and current. The driver is a client driver to the core PMBus driver. Please see Documentation/hwmon/pmbus.rst for details on PMBus client drivers. @@ -149,7 +157,7 @@ in[1-6]_reset_history Write any value to reset history. .. note:: - MAX34446 only supports in[1-4]. - - ADPM12160, and ADPM12200 only supports in[1-2]. Label is "vin1" + - ADPM12160, ADPM12200, and ADPM12250 only supports in[1-2]. Label is "vin1" and "vout1" respectively. Curr @@ -172,8 +180,9 @@ curr[1-6]_reset_history Write any value to reset history. - in6 and curr6 attributes only exist for MAX34440. - MAX34446 only supports curr[1-4]. - - For ADPM12160, and ADPM12200, curr[1] is "iin1" and curr[2-6] - are "iout[1-5]". + - For ADPM12160, ADPM12200, and ADPM12250, curr[1] is "iin1" + - For ADPM12160, and ADPM12200 curr[2-6] are "iout[1-5]". + - For ADPM12250, curr[2-4] are "iout[1-3]". Power ~~~~~ @@ -209,7 +218,7 @@ temp[1-8]_reset_history Write any value to reset history. .. note:: - temp7 and temp8 attributes only exist for MAX34440. - MAX34446 only supports temp[1-3]. - - ADPM12160, and ADPM12200 only supports temp[1]. + - ADPM12160, ADPM12200, and ADPM12250 only supports temp[1]. .. note:: diff --git a/Documentation/hwmon/mp2985.rst b/Documentation/hwmon/mp2985.rst new file mode 100644 index 00000000000000..87a39c8a300c6a --- /dev/null +++ b/Documentation/hwmon/mp2985.rst @@ -0,0 +1,147 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Kernel driver mp2985 +==================== + +Supported chips: + + * MPS mp2985 + + Prefix: 'mp2985' + +Author: + + Wensheng Wang + +Description +----------- + +This driver implements support for Monolithic Power Systems, Inc. (MPS) +MP2985 Dual Loop Digital Multi-phase Controller. + +Device compliant with: + +- PMBus rev 1.3 interface. + +The driver exports the following attributes via the 'sysfs' files +for input voltage: + +**in1_input** + +**in1_label** + +**in1_crit** + +**in1_crit_alarm** + +**in1_lcrit** + +**in1_lcrit_alarm** + +**in1_max** + +**in1_max_alarm** + +**in1_min** + +**in1_min_alarm** + +The driver provides the following attributes for output voltage: + +**in2_input** + +**in2_label** + +**in2_crit** + +**in2_crit_alarm** + +**in2_lcrit** + +**in2_lcrit_alarm** + +**in3_input** + +**in3_label** + +**in3_crit** + +**in3_crit_alarm** + +**in3_lcrit** + +**in3_lcrit_alarm** + +The driver provides the following attributes for input current: + +**curr1_input** + +**curr1_label** + +The driver provides the following attributes for output current: + +**curr2_input** + +**curr2_label** + +**curr2_crit** + +**curr2_crit_alarm** + +**curr2_max** + +**curr2_max_alarm** + +**curr3_input** + +**curr3_label** + +**curr3_crit** + +**curr3_crit_alarm** + +**curr3_max** + +**curr3_max_alarm** + +The driver provides the following attributes for input power: + +**power1_input** + +**power1_label** + +**power2_input** + +**power2_label** + +The driver provides the following attributes for output power: + +**power3_input** + +**power3_label** + +**power4_input** + +**power4_label** + +The driver provides the following attributes for temperature: + +**temp1_input** + +**temp1_crit** + +**temp1_crit_alarm** + +**temp1_max** + +**temp1_max_alarm** + +**temp2_input** + +**temp2_crit** + +**temp2_crit_alarm** + +**temp2_max** + +**temp2_max_alarm** diff --git a/Documentation/hwmon/nct7802.rst b/Documentation/hwmon/nct7802.rst index 8b7365a7cb3227..366050ea595ccf 100644 --- a/Documentation/hwmon/nct7802.rst +++ b/Documentation/hwmon/nct7802.rst @@ -24,6 +24,22 @@ speed sensors. Smart Fan™ speed control is available via pwmX_auto_point attributes. +Sysfs Attributes +---------------- + +Sysfs attributes unique to this chip are documented below. For common +attributes, see Documentation/hwmon/sysfs-interface.rst. + +step_up_time + Time interval between successive duty cycle increases + when in Smart Fan mode. Specified in milliseconds and + rounded to intervals of 100 in the range 100-25500. + +step_down_time + Time interval between successive duty cycle decreases + when in Smart Fan mode. Specified in milliseconds and + rounded to intervals of 100 in the range 100-25500. + Tested Boards and BIOS Versions ------------------------------- diff --git a/Documentation/hwmon/pmbus.rst b/Documentation/hwmon/pmbus.rst index a8e01a5b96da30..23c42c3122746b 100644 --- a/Documentation/hwmon/pmbus.rst +++ b/Documentation/hwmon/pmbus.rst @@ -3,17 +3,18 @@ Kernel driver pmbus Supported chips: - * Flex BMR310, BMR453, BMR454, BMR456, BMR457, BMR458, BMR480, - BMR490, BMR491, BMR492 + * Flex BMR310, BMR316, BMR321, BMR350, BMR351, BMR453, BMR454, + BMR456, BMR457, BMR458, BMR480, BMR490, BMR491, BMR492 - Prefixes: 'bmr310', 'bmr453', 'bmr454', 'bmr456', 'bmr457', 'bmr458', 'bmr480', + Prefixes: 'bmr310', 'bmr316', 'bmr321', 'bmr350', 'bmr351', + 'bmr453', 'bmr454', 'bmr456', 'bmr457', 'bmr458', 'bmr480', 'bmr490', 'bmr491', 'bmr492' Addresses scanned: - Datasheets: - https://flexpowermodules.com/products + https://flex.com/products/power-modules/product-selector * ON Semiconductor ADP4000, NCP4200, NCP4208 diff --git a/Documentation/hwmon/prom21-xhci.rst b/Documentation/hwmon/prom21-xhci.rst new file mode 100644 index 00000000000000..7984fb187bd8a7 --- /dev/null +++ b/Documentation/hwmon/prom21-xhci.rst @@ -0,0 +1,101 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Kernel driver prom21-xhci +========================= + +Supported chips: + + * AMD Promontory 21 (PROM21) xHCI USB host controller + + Prefix: 'prom21_xhci' + + PCI IDs: 1022:43fc, 1022:43fd + +Author: + + - Jihong Min + +Description +----------- + +This driver exposes the temperature sensor in AMD PROM21 xHCI controllers. + +The driver binds to an auxiliary device created by the xHCI PCI driver for +supported controllers. The sensor value is accessed through a vendor-specific +index/data register pair in the controller's PCI MMIO BAR. +The auxiliary device is created by the ``xhci-pci-prom21`` PCI glue driver. +USB host operation is otherwise delegated to the common ``xhci-pci`` code. + +PROM21 is an AMD chipset IP used in single-chip or daisy-chained configurations +to build AMD 6xx/8xx series chipsets. Since the xHCI controllers are +integrated in PROM21, this temperature can also be used as a monitor for a +temperature close to the AMD chipset temperature. + +Register access +--------------- + +The temperature value is read through a vendor-specific index/data register +pair in the xHCI PCI MMIO BAR. The driver uses the following byte offsets from +the MMIO BAR base: + +======================= ===================================================== +0x3000 Vendor index register +0x3008 Vendor data register +======================= ===================================================== + +The driver saves the current vendor index register value, writes the +temperature selector ``0x0001e520`` to the vendor index register, reads the +vendor data register, and restores the previous vendor index value before +returning. The raw temperature value is the low 8 bits of the vendor data +register value. + +The hwmon core serializes this driver's callbacks, and the driver restores the +previous index value after each read. This does not provide synchronization +with firmware, SMM, ACPI AML, or any other user outside this driver. + +No public AMD reference is available for the register pair or the raw value. +The register pair was identified on an X870E system with two PROM21 xHCI +controllers. One controller was passed through to a Windows VM, and the same +controller's PCI MMIO BAR was observed from the Linux host while HWiNFO64 was +reporting the PROM21 xHCI temperature. In the test environment, the reported +temperature was very stable at idle and the displayed sensor resolution was +low, which made it possible to look for a consistently repeating MMIO response +for the same reported temperature. During observation, offset 0x3000 repeatedly +contained selector ``0x0001e520``. Writing the same selector to offset 0x3000 +from Linux and then reading offset 0x3008 reproduced the same raw value, so the +offsets are treated as a vendor index/data register pair. + +The conversion formula was empirically inferred by matching observed raw +8-bit values against HWiNFO64's reported PROM21 xHCI temperature for the same +controller. The observed mapping is: + + temp[C] = raw * 0.9066 - 78.624 + +Runtime PM +---------- + +The driver does not wake the xHCI PCI device for hwmon reads. It reads the +temperature only when the parent device is already active. A read from a +suspended device returns ``-ENODATA``. After a successful read, the driver +drops its active-only runtime PM reference and lets the PM core re-evaluate the +idle state. + +Sysfs entries +------------- + +======================= ===================================================== +temp1_input Temperature in millidegrees Celsius +======================= ===================================================== + +The hwmon device name is ``prom21_xhci``. The sysfs path depends on the hwmon +device number assigned by the kernel. Userspace can locate the device by +matching the ``name`` attribute: + +.. code-block:: sh + + for hwmon in /sys/class/hwmon/hwmon*; do + [ "$(cat "$hwmon/name")" = "prom21_xhci" ] || continue + cat "$hwmon/temp1_input" + done + +If the raw register value is invalid, ``temp1_input`` returns ``-ENODATA``. diff --git a/Documentation/hwmon/raspberrypi-hwmon.rst b/Documentation/hwmon/raspberrypi-hwmon.rst index 8038ade36490a0..db315184b8616d 100644 --- a/Documentation/hwmon/raspberrypi-hwmon.rst +++ b/Documentation/hwmon/raspberrypi-hwmon.rst @@ -20,6 +20,17 @@ undervoltage conditions. Sysfs entries ------------- -======================= ================== +======================= ====================================================== +in0_input Core voltage in millivolts +in1_input SDRAM controller voltage in millivolts +in2_input SDRAM I/O voltage in millivolts +in3_input SDRAM PHY voltage in millivolts +in0_label "core" +in1_label "sdram_c" +in2_label "sdram_i" +in3_label "sdram_p" in0_lcrit_alarm Undervoltage alarm -======================= ================== +======================= ====================================================== + +The voltage inputs and labels are only exposed if the firmware reports support +for the corresponding voltage ID. diff --git a/Documentation/hwmon/sysfs-interface.rst b/Documentation/hwmon/sysfs-interface.rst index f76e9f8cc1adae..94e1bbce172a33 100644 --- a/Documentation/hwmon/sysfs-interface.rst +++ b/Documentation/hwmon/sysfs-interface.rst @@ -106,6 +106,10 @@ Global attributes `update_interval` The interval at which the chip will update readings. +`update_interval_us` + The interval at which the chip will update readings, + expressed in microseconds for finer resolution. + ******** Voltages diff --git a/Documentation/iio/ad4691.rst b/Documentation/iio/ad4691.rst new file mode 100644 index 00000000000000..e45733341a4bb1 --- /dev/null +++ b/Documentation/iio/ad4691.rst @@ -0,0 +1,227 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +============= +AD4691 driver +============= + +ADC driver for Analog Devices Inc. AD4691 family of multichannel SAR ADCs. +The module name is ``ad4691``. + + +Supported devices +================= + +The following chips are supported by this driver: + +* `AD4691 `_ — 16-channel, 500 kSPS +* `AD4692 `_ — 16-channel, 1 MSPS +* `AD4693 `_ — 8-channel, 500 kSPS +* `AD4694 `_ — 8-channel, 1 MSPS + + +IIO channels +============ + +Each physical ADC input maps to one IIO voltage channel. The AD4691 and AD4692 +expose 16 channels (``voltage0`` through ``voltage15``); the AD4693 and AD4694 +expose 8 channels (``voltage0`` through ``voltage7``). + +All channels share a common scale (``in_voltage_scale``), derived from the +reference voltage. Each channel exposes: + +* ``in_voltageN_raw`` — single-shot ADC result + +The following attributes are shared across all channels: + +* ``in_voltage_sampling_frequency`` — effective output rate, defined as the + internal oscillator frequency divided by the oversampling ratio. Writing this + attribute selects the nearest achievable rate for the current OSR; the value + read back reflects the actual rate after snapping to the closest valid + oscillator entry. +* ``in_voltage_sampling_frequency_available`` — list of achievable effective + rates for the current oversampling ratio. The list updates dynamically when + the oversampling ratio changes. + +The following attributes are shared across all channels and only available in +CNV Burst Mode: + +* ``in_voltage_oversampling_ratio`` — hardware oversampling depth applied to + all channels; see `Oversampling`_ below. +* ``in_voltage_oversampling_ratio_available`` — valid ratios: 1, 2, 4, 8, 16, + 32. + + +Operating modes +=============== + +The driver supports two operating modes, selected automatically from the +device tree at probe time. + +Manual Mode +----------- + +Selected when no ``pwms`` property is present in the device tree. The CNV pin +is tied to the SPI chip-select: every CS assertion triggers a conversion and +returns the previous result. A user-defined IIO trigger (e.g. hrtimer trigger) +drives the buffer. + +Oversampling is not supported in Manual Mode. + +CNV Burst Mode +-------------- + +Selected when a ``pwms`` property is present in the device tree. A PWM drives +the CNV pin at the configured conversion rate. A GP pin wired to the SoC and +declared in the device tree signals DATA_READY at the end of each burst, +triggering a readout of all active channel results into the IIO buffer. + +The buffer output rate is controlled by the ``sampling_frequency`` attribute +on the IIO buffer. In practice the PWM rate should be set low enough to allow +the SPI readout to complete before the next conversion burst begins. + +Autonomous Mode (idle / single-shot) +------------------------------------- + +When the IIO buffer is disabled, ``in_voltageN_raw`` reads perform a single +conversion on the requested channel using the internal oscillator. The +oscillator is started and stopped around each read to save power. + + +Oversampling +============ + +In CNV Burst Mode a shared hardware accumulator averages a configurable number +of successive conversions across all active channels. The result is always a +16-bit mean, so the buffer data type (shown in ``buffer0/in_voltageN_type``) +is unaffected by the oversampling ratio. Valid ratios are 1, 2, 4, 8, 16 and +32; the default is 1 (no averaging). Oversampling is not supported in Manual +Mode. + +.. code-block:: bash + + # Set oversampling ratio to 16 (shared across all channels) + echo 16 > /sys/bus/iio/devices/iio:device0/in_voltage_oversampling_ratio + + # Read the resulting effective sampling frequency + cat /sys/bus/iio/devices/iio:device0/in_voltage_sampling_frequency + +Writing ``in_voltage_oversampling_ratio`` stores the new shared depth and snaps +the internal oscillator to the largest valid table entry that is both less than +or equal to ``old_effective_rate × new_osr`` and evenly divisible by +``new_osr``. This preserves an integer read-back of +``in_voltage_sampling_frequency`` after the change and keeps the oscillator as +close as possible to the previous effective rate. + + +Reference voltage +================= + +The driver supports two reference configurations, mutually exclusive: + +* **External reference** (``ref-supply``): a voltage between 2.4 V and 5.25 V + supplied externally. +* **Buffered internal reference** (``refin-supply``): an internal reference + buffer is enabled by the driver. + +Exactly one of ``ref-supply`` or ``refin-supply`` must be present in the +device tree. The reference voltage determines the full-scale range reported +via ``in_voltage_scale``. + + +LDO supply +========== + +The chip contains an internal LDO that powers part of the analog front-end. +The supply configuration is mutually exclusive: + +* **External VDD** (``vdd-supply``): an external 1.8 V supply is used directly; + the internal LDO is disabled. +* **Internal LDO** (``ldo-in-supply``): the internal LDO is enabled and fed + from the ``ldo-in`` regulator. Use this when no external 1.8 V VDD is present. + +Exactly one of ``vdd-supply`` or ``ldo-in-supply`` must be provided. + + +Reset +===== + +The driver supports two reset mechanisms: + +* **Hardware reset** (``reset-gpios`` in device tree): the GPIO line is + asserted then deasserted at probe; the driver waits 300 µs for the chip + to complete its internal reset sequence before accepting SPI commands. +* **Software reset** (fallback when ``reset-gpios`` is absent): written + automatically at probe. + + +GP pins and interrupts +====================== + +The chip exposes up to four general-purpose (GP) pins. In CNV Burst Mode +(non-offload), one GP pin must be wired to an interrupt-capable SoC input and +declared in the device tree using the ``interrupts`` and ``interrupt-names`` +properties. The ``interrupt-names`` value identifies which GP pin is used +(``"gp0"`` through ``"gp3"``). + +Example device tree fragment:: + + adc@0 { + compatible = "adi,ad4692"; + ... + interrupt-parent = <&gpio0>; + interrupts = <17 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "gp0"; + }; + + +SPI offload support +=================== + +When a SPI offload engine (e.g. the AXI SPI Engine) is present, the driver +uses DMA-backed transfers for CPU-independent, high-throughput data capture. +SPI offload is detected automatically at probe; if no offload hardware is +available the driver falls back to the software triggered-buffer path. + +Two SPI offload sub-modes exist: + +CNV Burst offload +----------------- + +Used when a ``pwms`` property is present and SPI offload is available. The PWM +drives CNV at the configured rate; on DATA_READY the offload engine reads all +active channel results and streams them directly to the IIO DMA buffer with no +CPU involvement. The GP pin used as DATA_READY trigger is supplied by the +trigger-source consumer at buffer enable time; no ``interrupt-names`` entry is +required. + +Manual offload +-------------- + +Used when no ``pwms`` property is present and SPI offload is available. A +periodic SPI offload trigger controls the conversion rate and the offload engine +streams results directly to the IIO DMA buffer. + +The ``sampling_frequency`` attribute on the IIO buffer controls the trigger +rate (in Hz). The initial rate is 100 kHz. + +Oversampling is not supported in Manual Mode. + + +Buffer data format +================== + +The sample format in the IIO buffer depends on whether SPI offload is in use. + +Software triggered-buffer path (no SPI offload) +------------------------------------------------ + +Each active channel occupies one 16-bit big-endian slot (``storagebits=16``, +``endianness=be``). Active channels are packed densely in scan-index order, +followed by a 64-bit software timestamp appended by the IIO core. + +SPI offload path +---------------- + +Each active channel occupies one 16-bit CPU-native slot (``storagebits=16``, +``endianness=cpu``). The SPI offload engine streams 16-bit words directly from +the SPI Engine into the DMA buffer; no software timestamp is appended. diff --git a/Documentation/iio/adxl313.rst b/Documentation/iio/adxl313.rst index 966e72c0109aa4..3641193bf64778 100644 --- a/Documentation/iio/adxl313.rst +++ b/Documentation/iio/adxl313.rst @@ -11,7 +11,7 @@ This driver supports Analog Device's ADXL313 on SPI/I2C bus. * `ADXL313 `_ -The ADXL313is a low noise density, low power, 3-axis accelerometer with +The ADXL313 is a low noise density, low power, 3-axis accelerometer with selectable measurement ranges. The ADXL313 supports the ±0.5 g, ±1 g, ±2 g and ±4 g ranges. @@ -38,7 +38,7 @@ specific device folder path ``/sys/bus/iio/devices/iio:deviceX``. +---------------------------------------------------+----------------------------------------------------------+ | in_accel_x_raw | Raw X-axis accelerometer channel value. | +---------------------------------------------------+----------------------------------------------------------+ -| in_accel_y_calibbias | y-axis acceleration offset correction | +| in_accel_y_calibbias | Calibration offset for the Y-axis accelerometer channel. | +---------------------------------------------------+----------------------------------------------------------+ | in_accel_y_raw | Raw Y-axis accelerometer channel value. | +---------------------------------------------------+----------------------------------------------------------+ @@ -112,9 +112,9 @@ apply the following formula: Where _offset and _scale are device attributes. If no _offset attribute is present, simply assume its value is 0. -The ADXL313 driver offers data for a single types of channels, the table below -shows the measurement units for the processed value, which are defined by the -IIO framework: +The ADXL313 driver offers data for multiple channels of a single type. +The table below shows the measurement units for the processed value, +which are defined by the IIO framework: +-------------------------------------+---------------------------+ | Channel type | Measurement unit | diff --git a/Documentation/iio/adxl345.rst b/Documentation/iio/adxl345.rst index 978f746a819852..0aa33a85241280 100644 --- a/Documentation/iio/adxl345.rst +++ b/Documentation/iio/adxl345.rst @@ -47,7 +47,7 @@ specific device folder path ``/sys/bus/iio/devices/iio:deviceX``. +-------------------------------------------+----------------------------------------------------------+ | in_accel_x_raw | Raw X-axis accelerometer channel value. | +-------------------------------------------+----------------------------------------------------------+ -| in_accel_y_calibbias | Y-axis acceleration offset correction | +| in_accel_y_calibbias | Calibration offset for the Y-axis accelerometer channel. | +-------------------------------------------+----------------------------------------------------------+ | in_accel_y_raw | Raw Y-axis accelerometer channel value. | +-------------------------------------------+----------------------------------------------------------+ diff --git a/Documentation/iio/adxl380.rst b/Documentation/iio/adxl380.rst index 61cafa2f98bf36..654d4c0e84a197 100644 --- a/Documentation/iio/adxl380.rst +++ b/Documentation/iio/adxl380.rst @@ -51,7 +51,7 @@ specific device folder path ``/sys/bus/iio/devices/iio:deviceX``. +---------------------------------------------------+----------------------------------------------------------+ | in_accel_x_raw | Raw X-axis accelerometer channel value. | +---------------------------------------------------+----------------------------------------------------------+ -| in_accel_y_calibbias | y-axis acceleration offset correction | +| in_accel_y_calibbias | Calibration offset for the Y-axis accelerometer channel. | +---------------------------------------------------+----------------------------------------------------------+ | in_accel_y_raw | Raw Y-axis accelerometer channel value. | +---------------------------------------------------+----------------------------------------------------------+ diff --git a/Documentation/iio/iio_devbuf.rst b/Documentation/iio/iio_devbuf.rst index dca1f0200b0dd8..e91730fa3cea4e 100644 --- a/Documentation/iio/iio_devbuf.rst +++ b/Documentation/iio/iio_devbuf.rst @@ -83,9 +83,10 @@ and the relevant _type attributes to establish the data storage format. Read-only attribute containing the description of the scan element data storage within the buffer and hence the form in which it is read from userspace. Format -is [be|le]:[s|u]bits/storagebits[Xrepeat][>>shift], where: +is [be|le]:[f|s|u]bits/storagebits[Xrepeat][>>shift], where: - **be** or **le** specifies big or little-endian. +- **f** specifies if floating-point. - **s** or **u** specifies if signed (2's complement) or unsigned. - **bits** is the number of valid data bits. - **storagebits** is the number of bits (after padding) that it occupies in the diff --git a/Documentation/iio/index.rst b/Documentation/iio/index.rst index ba3e609c6a13c9..007e0a1fcc5a27 100644 --- a/Documentation/iio/index.rst +++ b/Documentation/iio/index.rst @@ -23,6 +23,7 @@ Industrial I/O Kernel Drivers ad4000 ad4030 ad4062 + ad4691 ad4695 ad7191 ad7380 diff --git a/Documentation/infiniband/user_verbs.rst b/Documentation/infiniband/user_verbs.rst index 8ddc4b1cfef273..96bcd1bd37ad4b 100644 --- a/Documentation/infiniband/user_verbs.rst +++ b/Documentation/infiniband/user_verbs.rst @@ -2,7 +2,7 @@ Userspace verbs access ====================== - The ib_uverbs module, built by enabling CONFIG_INFINIBAND_USER_VERBS, + The ib_uverbs module, built by enabling CONFIG_INFINIBAND_USER_ACCESS, enables direct userspace access to IB hardware via "verbs," as described in chapter 11 of the InfiniBand Architecture Specification. diff --git a/Documentation/input/userio.rst b/Documentation/input/userio.rst index f780c77931fe08..7aaaa629bde064 100644 --- a/Documentation/input/userio.rst +++ b/Documentation/input/userio.rst @@ -5,7 +5,7 @@ The userio Protocol =================== -:Copyright: |copy| 2015 Stephen Chandler Paul +:Copyright: |copy| 2015 Lyude Paul Sponsored by Red Hat @@ -66,8 +66,27 @@ USERIO_CMD_SET_PORT_TYPE ~~~~~~~~~~~~~~~~~~~~~~~~ Sets the type of port we're emulating, where ``data`` is the port type being -set. Can be any of the macros from . For example: SERIO_8042 -would set the port type to be a normal PS/2 port. +set. Can be any of the serio type macros from . For example: +SERIO_8042 would set the port type to be a normal PS/2 port. + +USERIO_CMD_SET_PORT_PROTO +~~~~~~~~~~~~~~~~~~~~~~~~~ + +Sets the protocol of port we're emulating, where ``data`` is the protocol being +set. Can be any of the serio proto macros from . For example: +SERIO_IFORCE would set the port type to be an I-Force serial joystick. + +USERIO_CMD_SET_PORT_ID +~~~~~~~~~~~~~~~~~~~~~~ + +Sets the ``id`` value on the identification of port we're emulating, where +``data`` is the value being set. + +USERIO_CMD_SET_PORT_EXTRA +~~~~~~~~~~~~~~~~~~~~~~~~~ + +Sets the ``extra`` value on the identification of port we're emulating, where +``data`` is the value being set. USERIO_CMD_SEND_INTERRUPT ~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/Documentation/kbuild/kconfig.rst b/Documentation/kbuild/kconfig.rst index d213c4f599a40f..e35dd1d5f9d30d 100644 --- a/Documentation/kbuild/kconfig.rst +++ b/Documentation/kbuild/kconfig.rst @@ -59,6 +59,11 @@ Environment variables for ``*config``: This environment variable makes Kconfig warn about all unrecognized symbols in the config input. +``KCONFIG_WARN_CHANGED_INPUT`` + If set to a non-blank value, Kconfig prints optional warnings for + user-provided values that change after Kconfig resolves dependencies + or applies other constraints such as ranges. + ``KCONFIG_WERROR`` If set, Kconfig treats warnings as errors. diff --git a/Documentation/kbuild/makefiles.rst b/Documentation/kbuild/makefiles.rst index 24a4708d26e8ef..7521cae7d56f11 100644 --- a/Documentation/kbuild/makefiles.rst +++ b/Documentation/kbuild/makefiles.rst @@ -1285,8 +1285,39 @@ Example:: In this example, the file target maketools will be processed before descending down in the subdirectories. -See also chapter XXX-TODO that describes how kbuild supports -generating offset header files. +Generating offset header files +------------------------------ + +The ``include/generated/asm-offsets.h`` header exposes C structure +member offsets and other compile-time constants to assembly code. It +is generated from ``arch/$(SRCARCH)/kernel/asm-offsets.c``. + +The source file uses ``DEFINE()``, ``OFFSET()``, ``BLANK()`` and +``COMMENT()`` from ````. These emit marker strings +through inline asm that Kbuild extracts from the compiled assembly +output. + +Example:: + + #include + #include + + int main(void) + { + OFFSET(TSK_ACTIVE_MM, task_struct, active_mm); + DEFINE(THREAD_SIZE, THREAD_SIZE); + BLANK(); + return 0; + } + +The rules are defined in the top-level ``Kbuild`` and +``scripts/Makefile.lib``. The header is built during Kbuild's +``prepare`` phase, after ``archprepare`` and before descending into +subdirectories. + +The same mechanism generates ``include/generated/bounds.h`` from +``kernel/bounds.c`` and ``include/generated/rq-offsets.h`` from +``kernel/sched/rq-offsets.c``. List directories to visit when descending ----------------------------------------- @@ -1690,9 +1721,3 @@ Credits - Updates by Kai Germaschewski - Updates by Sam Ravnborg - Language QA by Jan Engelhardt - -TODO -==== - -- Generating offset header files. -- Add more variables to chapters 7 or 9? diff --git a/Documentation/kernel-hacking/locking.rst b/Documentation/kernel-hacking/locking.rst index dff0646a717bff..c969c76ef7cb4d 100644 --- a/Documentation/kernel-hacking/locking.rst +++ b/Documentation/kernel-hacking/locking.rst @@ -442,7 +442,7 @@ to protect the cache and all the objects within it. Here's the code:: { struct object *obj; - if ((obj = kmalloc(sizeof(*obj), GFP_KERNEL)) == NULL) + if ((obj = kmalloc_obj(*obj)) == NULL) return -ENOMEM; strscpy(obj->name, name, sizeof(obj->name)); @@ -517,7 +517,7 @@ which are taken away, and the ``+`` are lines which are added. struct object *obj; + unsigned long flags; - if ((obj = kmalloc(sizeof(*obj), GFP_KERNEL)) == NULL) + if ((obj = kmalloc_obj(*obj)) == NULL) return -ENOMEM; @@ -63,30 +64,33 @@ obj->id = id; diff --git a/Documentation/leds/index.rst b/Documentation/leds/index.rst index bebf440042787a..23fa9ff7aaf4b0 100644 --- a/Documentation/leds/index.rst +++ b/Documentation/leds/index.rst @@ -28,6 +28,7 @@ LEDs leds-lp5812 leds-mlxcpld leds-mt6370-rgb + leds-s2m-rgb leds-sc27xx leds-st1202 leds-qcom-lpg diff --git a/Documentation/leds/leds-class-multicolor.rst b/Documentation/leds/leds-class-multicolor.rst index c6b47b4093c473..68340644f80b43 100644 --- a/Documentation/leds/leds-class-multicolor.rst +++ b/Documentation/leds/leds-class-multicolor.rst @@ -25,10 +25,14 @@ color name to indexed value. The ``multi_index`` file is an array that contains the string list of the colors as they are defined in each ``multi_*`` array file. -The ``multi_intensity`` is an array that can be read or written to for the +The ``multi_intensity`` file is an array that can be read or written to for the individual color intensities. All elements within this array must be written in order for the color LED intensities to be updated. +The ``multi_max_intensity`` file is an array that contains the maximum intensity +value supported by each color intensity. Intensity values above this will be +automatically clamped into the supported range. + Directory Layout Example ======================== .. code-block:: console @@ -38,6 +42,7 @@ Directory Layout Example -r--r--r-- 1 root root 4096 Oct 19 16:16 max_brightness -r--r--r-- 1 root root 4096 Oct 19 16:16 multi_index -rw-r--r-- 1 root root 4096 Oct 19 16:16 multi_intensity + -r--r--r-- 1 root root 4096 Oct 19 16:16 multi_max_intensity .. @@ -104,3 +109,17 @@ the color LED group. 128 .. + +Writing intensity values larger than the maximum specified in ``multi_max_intensity`` +will result in those values being clamped into the supported range. + +.. code-block:: console + + # cat /sys/class/leds/multicolor:status/multi_max_intensity + 255 255 255 + + # echo 512 512 512 > /sys/class/leds/multicolor:status/multi_intensity + # cat /sys/class/leds/multicolor:status/multi_intensity + 255 255 255 + +.. diff --git a/Documentation/leds/leds-class.rst b/Documentation/leds/leds-class.rst index 5db620ed27aa2e..3913966cfdac04 100644 --- a/Documentation/leds/leds-class.rst +++ b/Documentation/leds/leds-class.rst @@ -116,6 +116,69 @@ above leaves scope for further attributes should they be needed. If sections of the name don't apply, just leave that section blank. +Keyboard backlight control LED Device Naming +============================================ + +For backlit keyboards with a single brightness / color settings a single +(multicolor) LED class device should be used to allow userspace to change +the backlight brightness (and if possible the color). This LED class device +must use "kbd_backlight" for the function part of the LED class device name. +IOW the name must end with ":kbd_backlight". + +For backlit keyboards with multiple control zones, one (multicolor) LED class +device should be used per zone. These LED class devices' name must follow: + + "::kbd_zoned_backlight-" + +and must be the same for all zones of the same keyboard. + + should be descriptive of which part of the keyboard backlight +the zone covers and should be suitable for userspace to show to an end user +in an UI for controlling the zones. + +Where possible should be a value already used by other +zoned keyboards with a similar or identical zone layout, e.g.: + +::kbd_zoned_backlight-right +::kbd_zoned_backlight-middle +::kbd_zoned_backlight-left +::kbd_zoned_backlight-corners +::kbd_zoned_backlight-wasd + +or: + +::kbd_zoned_backlight-main +::kbd_zoned_backlight-cursor +::kbd_zoned_backlight-numpad +::kbd_zoned_backlight-corners +::kbd_zoned_backlight-wasd + +Note that this is intended for keyboards with a limited number of zones, +keyboards with per key addressable backlighting must not use LED class devices +since the sysfs API is not suitable for rapidly change multiple LEDs in one +"commit" as is necessary to do animations / special effects on such keyboards. + +An exception to the rule that all zones must follow: + + "::kbd_zoned_backlight-" + +is made for the special case where there is a single big zone which controls +the backlighting of almost all of the keyboard and there are some small areas +with separate control, like just the 4 cursor keys, or the WASD keys. In this +case the main zone should use 'kbd_backlight' for the function part of the name +for compatibility with (older) userspace code which is not aware of +the "kbd_zoned_backlight-" function naming scheme. + +While the smaller zones should use the new zoned naming scheme. Such a setup +would result in e.g.: + +::kbd_backlight +::kbd_zoned_backlight-wasd + +"kbd_zoned_backlight-" aware userspace should be aware of this +exception and check for a main zone with a "kbd_backlight" function-name. + + Brightness setting API ====================== diff --git a/Documentation/leds/leds-lp55xx.rst b/Documentation/leds/leds-lp55xx.rst index 632e41cec0b591..f60c7ec3981634 100644 --- a/Documentation/leds/leds-lp55xx.rst +++ b/Documentation/leds/leds-lp55xx.rst @@ -18,7 +18,7 @@ The LP55xx common driver provides these features using exported functions. lp55xx_init_device() / lp55xx_deinit_device() lp55xx_register_leds() / lp55xx_unregister_leds() - lp55xx_regsister_sysfs() / lp55xx_unregister_sysfs() + lp55xx_register_sysfs() / lp55xx_unregister_sysfs() ( Driver Structure Data ) diff --git a/Documentation/leds/leds-lp5812.rst b/Documentation/leds/leds-lp5812.rst index c2a6368d514938..12e757d45c3a25 100644 --- a/Documentation/leds/leds-lp5812.rst +++ b/Documentation/leds/leds-lp5812.rst @@ -20,7 +20,7 @@ Sysfs Interface =============== This driver uses the standard multicolor LED class interfaces defined -in Documentation/ABI/testing/sysfs-class-led-multicolor.rst. +in Documentation/ABI/testing/sysfs-class-led-multicolor. Each LP5812 LED output appears under ``/sys/class/leds/`` with its assigned label (for example ``LED_A``). diff --git a/Documentation/leds/leds-s2m-rgb.rst b/Documentation/leds/leds-s2m-rgb.rst new file mode 100644 index 00000000000000..4f89a8c89ea86a --- /dev/null +++ b/Documentation/leds/leds-s2m-rgb.rst @@ -0,0 +1,60 @@ +.. SPDX-License-Identifier: GPL-2.0 + +====================================== +Samsung S2M Series PMIC RGB LED Driver +====================================== + +Description +----------- + +The RGB LED on the S2M series PMIC hardware features a three-channel LED that +is grouped together as a single device. Furthermore, it supports 8-bit +brightness control for each channel. This LED is typically used as a status +indicator in mobile devices. It also supports various parameters for hardware +patterns. + +The hardware pattern can be programmed using the "pattern" trigger, using the +hw_pattern attribute. + +/sys/class/leds//repeat +---------------------------- + +The hardware supports only indefinitely repeating patterns. The repeat +attribute must be set to -1 for hardware patterns to function. + +/sys/class/leds//hw_pattern +-------------------------------- + +Specify a hardware pattern for the RGB LEDs. + +The pattern is a series of brightness levels and durations in milliseconds. +There should be only one non-zero brightness level. Unlike the results +described in leds-trigger-pattern, the transitions between on and off states +are smoothed out by the hardware. + +Simple pattern:: + + "255 3000 0 1000" + + 255 -+ ''''''-. .-'''''''-. + | '. .' '. + | \ / \ + | '. .' '. + | '-.......-' '- + 0 -+-------+-------+-------+-------+-------+-------+--> time (s) + 0 1 2 3 4 5 6 + +As described in leds-trigger-pattern, it is also possible to use zero-length +entries to disable the ramping mechanism. + +On-Off pattern:: + + "255 1000 255 0 0 1000 0 0" + + 255 -+ ------+ +-------+ +-------+ + | | | | | | + | | | | | | + | | | | | | + | +-------+ +-------+ +------- + 0 -+-------+-------+-------+-------+-------+-------+--> time (s) + 0 1 2 3 4 5 6 diff --git a/Documentation/locking/locktypes.rst b/Documentation/locking/locktypes.rst index 37b6a5670c2fa1..ac1ad722a9e7ef 100644 --- a/Documentation/locking/locktypes.rst +++ b/Documentation/locking/locktypes.rst @@ -498,7 +498,7 @@ allocating memory. Thus, on a non-PREEMPT_RT kernel the following code works perfectly:: raw_spin_lock(&lock); - p = kmalloc(sizeof(*p), GFP_ATOMIC); + p = kmalloc_obj(*p, GFP_ATOMIC); But this code fails on PREEMPT_RT kernels because the memory allocator is fully preemptible and therefore cannot be invoked from truly atomic @@ -507,7 +507,7 @@ while holding normal non-raw spinlocks because they do not disable preemption on PREEMPT_RT kernels:: spin_lock(&lock); - p = kmalloc(sizeof(*p), GFP_ATOMIC); + p = kmalloc_obj(*p, GFP_ATOMIC); bit spinlocks diff --git a/Documentation/locking/robust-futex-ABI.rst b/Documentation/locking/robust-futex-ABI.rst index f24904f1c16fb3..5e6a0665b8ba89 100644 --- a/Documentation/locking/robust-futex-ABI.rst +++ b/Documentation/locking/robust-futex-ABI.rst @@ -153,6 +153,9 @@ On removal: 3) release the futex lock, and 4) clear the 'lock_op_pending' word. +Please note that the removal of a robust futex purely in userspace is +racy. Refer to the next chapter to learn more and how to avoid this. + On exit, the kernel will consider the address stored in 'list_op_pending' and the address of each 'lock word' found by walking the list starting at 'head'. For each such address, if the bottom 30 @@ -182,3 +185,44 @@ any point: When the kernel sees a list entry whose 'lock word' doesn't have the current threads TID in the lower 30 bits, it does nothing with that entry, and goes on to the next entry. + +Robust release is racy +---------------------- + +The removal of a robust futex from the list is racy when doing it solely in +userspace. Quoting Thomas Gleixner for the explanation: + + The robust futex unlock mechanism is racy in respect to the clearing of the + robust_list_head::list_op_pending pointer because unlock and clearing the + pointer are not atomic. The race window is between the unlock and clearing + the pending op pointer. If the task is forced to exit in this window, exit + will access a potentially invalid pending op pointer when cleaning up the + robust list. That happens if another task manages to unmap the object + containing the lock before the cleanup, which results in an UAF. In the + worst case this UAF can lead to memory corruption when unrelated content + has been mapped to the same address by the time the access happens. + +A full in-depth analysis can be read at +https://lore.kernel.org/lkml/20260316162316.356674433@kernel.org/ + +To overcome that, the kernel needs to participate in the lock release operation. +This ensures that the release happens "atomically" with regard to releasing +the lock and removing the address from ``list_op_pending``. If the release is +interrupted by a signal, the kernel will also verify if it interrupted the +release operation. + +For the contended unlock case, where other threads are waiting for the lock +release, there's the ``FUTEX_ROBUST_UNLOCK`` operation feature flag for the +``futex()`` system call, which must be used with one of the following +operations: ``FUTEX_WAKE``, ``FUTEX_WAKE_BITSET`` or ``FUTEX_UNLOCK_PI``. +The kernel will release the lock (set the futex word to zero), clean the +``list_op_pending`` field. Then, it will proceed with the normal wake path. + +For the non-contended path, there's still a race between checking the futex word +and clearing the ``list_op_pending`` field. To solve this without the need of a +complete system call, userspace should call the virtual syscall +``__vdso_futex_robust_listXX_try_unlock()`` (where XX is either 32 or 64, +depending on the size of the pointer). If the vDSO call succeeds, it means that +it released the lock and cleared ``list_op_pending``. If it fails, that means +that there are waiters for this lock and a call to ``futex()`` syscall with +``FUTEX_ROBUST_UNLOCK`` is needed. diff --git a/Documentation/locking/robust-futexes.rst b/Documentation/locking/robust-futexes.rst index 6361fb01c9c1e8..1423f53ea2f46d 100644 --- a/Documentation/locking/robust-futexes.rst +++ b/Documentation/locking/robust-futexes.rst @@ -94,7 +94,7 @@ time, the kernel checks this user-space list: are there any robust futex locks to be cleaned up? In the common case, at do_exit() time, there is no list registered, so -the cost of robust futexes is just a simple current->robust_list != NULL +the cost of robust futexes is just a current->futex.robust_list != NULL comparison. If the thread has registered a list, then normally the list is empty. If the thread/process crashed or terminated in some incorrect way then the list might be non-empty: in this case the kernel carefully @@ -178,9 +178,9 @@ one to query the registered list pointer:: size_t __user *len_ptr); List registration is very fast: the pointer is simply stored in -current->robust_list. [Note that in the future, if robust futexes become -widespread, we could extend sys_clone() to register a robust-list head -for new threads, without the need of another syscall.] +current->futex.robust_list. [Note that in the future, if robust futexes +become widespread, we could extend sys_clone() to register a robust-list +head for new threads, without the need of another syscall.] So there is virtually zero overhead for tasks not using robust futexes, and even for robust futex users, there is only one extra syscall per diff --git a/Documentation/maintainer/maintainer-entry-profile.rst b/Documentation/maintainer/maintainer-entry-profile.rst index 6020d188e13de1..58e2af333692dc 100644 --- a/Documentation/maintainer/maintainer-entry-profile.rst +++ b/Documentation/maintainer/maintainer-entry-profile.rst @@ -92,24 +92,8 @@ full series, or privately send a reminder email. This section might also list how review works for this code area and methods to get feedback that are not directly from the maintainer. -Existing profiles ------------------ - -For now, existing maintainer profiles are listed here; we will likely want -to do something different in the near future. - -.. toctree:: - :maxdepth: 1 - - ../doc-guide/maintainer-profile - ../nvdimm/maintainer-entry-profile - ../arch/riscv/patch-acceptance - ../process/maintainer-soc - ../process/maintainer-soc-clean-dts - ../driver-api/media/maintainer-entry-profile - ../process/maintainer-netdev - ../driver-api/vfio-pci-device-specific-driver-acceptance - ../nvme/feature-and-quirk-policy - ../filesystems/nfs/nfsd-maintainer-entry-profile - ../filesystems/xfs/xfs-maintainer-entry-profile - ../mm/damon/maintainer-profile +Maintainer Handbooks +-------------------- + +For examples of other subsystem handbooks see +Documentation/process/maintainer-handbooks.rst. diff --git a/Documentation/misc-devices/apds990x.rst b/Documentation/misc-devices/apds990x.rst deleted file mode 100644 index e2f75577f731ba..00000000000000 --- a/Documentation/misc-devices/apds990x.rst +++ /dev/null @@ -1,128 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -====================== -Kernel driver apds990x -====================== - -Supported chips: -Avago APDS990X - -Data sheet: -Not freely available - -Author: -Samu Onkalo - -Description ------------ - -APDS990x is a combined ambient light and proximity sensor. ALS and proximity -functionality are highly connected. ALS measurement path must be running -while the proximity functionality is enabled. - -ALS produces raw measurement values for two channels: Clear channel -(infrared + visible light) and IR only. However, threshold comparisons happen -using clear channel only. Lux value and the threshold level on the HW -might vary quite much depending the spectrum of the light source. - -Driver makes necessary conversions to both directions so that user handles -only lux values. Lux value is calculated using information from the both -channels. HW threshold level is calculated from the given lux value to match -with current type of the lightning. Sometimes inaccuracy of the estimations -lead to false interrupt, but that doesn't harm. - -ALS contains 4 different gain steps. Driver automatically -selects suitable gain step. After each measurement, reliability of the results -is estimated and new measurement is triggered if necessary. - -Platform data can provide tuned values to the conversion formulas if -values are known. Otherwise plain sensor default values are used. - -Proximity side is little bit simpler. There is no need for complex conversions. -It produces directly usable values. - -Driver controls chip operational state using pm_runtime framework. -Voltage regulators are controlled based on chip operational state. - -SYSFS ------ - - -chip_id - RO - shows detected chip type and version - -power_state - RW - enable / disable chip. Uses counting logic - - 1 enables the chip - 0 disables the chip -lux0_input - RO - measured lux value - - sysfs_notify called when threshold interrupt occurs - -lux0_sensor_range - RO - lux0_input max value. - - Actually never reaches since sensor tends - to saturate much before that. Real max value varies depending - on the light spectrum etc. - -lux0_rate - RW - measurement rate in Hz - -lux0_rate_avail - RO - supported measurement rates - -lux0_calibscale - RW - calibration value. - - Set to neutral value by default. - Output results are multiplied with calibscale / calibscale_default - value. - -lux0_calibscale_default - RO - neutral calibration value - -lux0_thresh_above_value - RW - HI level threshold value. - - All results above the value - trigs an interrupt. 65535 (i.e. sensor_range) disables the above - interrupt. - -lux0_thresh_below_value - RW - LO level threshold value. - - All results below the value - trigs an interrupt. 0 disables the below interrupt. - -prox0_raw - RO - measured proximity value - - sysfs_notify called when threshold interrupt occurs - -prox0_sensor_range - RO - prox0_raw max value (1023) - -prox0_raw_en - RW - enable / disable proximity - uses counting logic - - - 1 enables the proximity - - 0 disables the proximity - -prox0_reporting_mode - RW - trigger / periodic. - - In "trigger" mode the driver tells two possible - values: 0 or prox0_sensor_range value. 0 means no proximity, - 1023 means proximity. This causes minimal number of interrupts. - In "periodic" mode the driver reports all values above - prox0_thresh_above. This causes more interrupts, but it can give - _rough_ estimate about the distance. - -prox0_reporting_mode_avail - RO - accepted values to prox0_reporting_mode (trigger, periodic) - -prox0_thresh_above_value - RW - threshold level which trigs proximity events. diff --git a/Documentation/misc-devices/index.rst b/Documentation/misc-devices/index.rst index 081e79415e3869..f911edaecbfad6 100644 --- a/Documentation/misc-devices/index.rst +++ b/Documentation/misc-devices/index.rst @@ -13,7 +13,6 @@ fit into other categories. ad525x_dpot amd-sbi - apds990x bh1770glc c2port dw-xdata-pcie diff --git a/Documentation/mm/damon/design.rst b/Documentation/mm/damon/design.rst index afc7d52bda2f7f..2da7ca0d3d17a4 100644 --- a/Documentation/mm/damon/design.rst +++ b/Documentation/mm/damon/design.rst @@ -19,6 +19,13 @@ types of monitoring. To know how user-space can do the configurations and start/stop DAMON, refer to :ref:`DAMON sysfs interface ` documentation. +Users can also request each context execution to be paused and resumed. When +it is paused, the kdamond does nothing other than applying online parameter +update. + +To know how user-space can pause/resume each context, refer to :ref:`DAMON +sysfs context ` usage documentation. + Overall Architecture ==================== @@ -140,7 +147,7 @@ as Idle page tracking does. Address Unit ------------ -DAMON core layer uses ``unsinged long`` type for monitoring target address +DAMON core layer uses ``unsigned long`` type for monitoring target address ranges. In some cases, the address space for a given operations set could be too large to be handled with the type. ARM (32-bit) with large physical address extension is an example. For such cases, a per-operations set @@ -269,6 +276,45 @@ interval``, DAMON checks if the region's size and access frequency (``nr_accesses``) has significantly changed. If so, the counter is reset to zero. Otherwise, the counter is increased. +.. _damon_design_data_attrs_monitoring: + +Data Attributes Monitoring +~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Data access pattern is only one type of data attributes. In some use cases, +users need to know more data attributes information. For example, users may +need to know how much of a given hot or cold memory region is backed by +anonymous pages, or belong to a specific cgroup. For such use case, data +attributes monitoring feature is provided. + +Using the feature, users can register data attributes of their interest to the +DAMON :ref:`context `. The +registration is made by specifying a probe per attribute. Each of the probe +specifies a rule to determine if a given memory region has the related +attribute. The rule is constructed with multiple filters. The filters work +same to :ref:`DAMOS filters ` except the supported +filter types. Currently only ``anon`` and ``memcg`` filter types are supported +for data attributes monitoring. + +If such probes are registered, DAMON executes the probes for each region's +sampling memory when it does the access :ref:`sampling +`. The number of samples that identified +as having the data attribute (hitting the probe) per :ref:`aggregation interval +` is accounted in a per-region per-probe counter. +Users can therefore know how much of a given DAMON region has a specific data +attribute by reading the per-region per-probe probe hits counter after each +aggregation interval. + +This is a sampling based mechanism. Hence, it is lightweight but the output +may include some measurement errors. The output should be used with good +understanding of statistics. + +Another way to do this for higher accuracy is using :ref:`DAMOS filter +` with ``stat`` :ref:`action +` and ``sz_ops_filter_passed`` :ref:`stat +`. This approach provides the data attributes +information in page level. But, because it is operated in page level, the +overhead is proportional to the size of the memory. Dynamic Target Space Updates Handling ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -371,7 +417,7 @@ with theoretical maximum ``nr_accesses``, which can be calculated as ``aggregation interval / sampling interval``. The mechanism calculates the ratio of access events for ``aggrs`` aggregations, -and increases or decrease the ``sampleing interval`` and ``aggregation +and increases or decrease the ``sampling interval`` and ``aggregation interval`` in same ratio, if the observed access ratio is lower or higher than the target, respectively. The ratio of the intervals change is decided in proportion to the distance between current samples ratio and the target ratio. @@ -387,7 +433,7 @@ The tuning is turned off by default, and need to be set explicitly by the user. As a rule of thumbs and the Parreto principle, 4% access samples ratio target is recommended. Note that Parreto principle (80/20 rule) has applied twice. That is, assumes 4% (20% of 20%) DAMON-observed access events ratio (source) -to capture 64% (80% multipled by 80%) real access events (outcomes). +to capture 64% (80% multiplied by 80%) real access events (outcomes). To know how user-space can use this feature via :ref:`DAMON sysfs interface `, refer to :ref:`intervals_goal @@ -474,6 +520,10 @@ that supports each action are as below. Supported by ``vaddr`` and ``fvaddr`` operations set. When TRANSPARENT_HUGEPAGE is disabled, the application of the action will just fail. + - ``collapse``: Call ``madvise()`` for the region with ``MADV_COLLAPSE``. + Supported by ``vaddr`` and ``fvaddr`` operations set. When + TRANSPARENT_HUGEPAGE is disabled, the application of the action will just + fail. - ``lru_prio``: Prioritize the region on its LRU lists. Supported by ``paddr`` operations set. - ``lru_deprio``: Deprioritize the region on its LRU lists. @@ -565,6 +615,28 @@ interface `, refer to :ref:`weights ` part of the documentation. +.. _damon_design_damos_quotas_failed_memory_charging_ratio: + +Action-failed Memory Charging Ratio +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +DAMOS action to a given region can fail for some subsets of the memory of the +region. For example, if the action is ``pageout`` and the region has some +unreclaimable pages, applying the action to the pages will fail. The amount of +system resource that is taken for such failed action applications is usually +different from that for successful action applications. For such cases, users +can set different charging ratio for such failed memory. The ratio can be +specified using ``fail_charge_num`` and ``fail_charge_denom`` parameters. The +two parameters represent the numerator and denominator of the ratio. The +feature is enabled only if ``fail_charge_denom`` is not zero. + +For example, let's suppose a DAMOS action is applied to a region of 1,000 MiB +size. The action is successfully applied to only 700 MiB of the region. +``fail_charge_num`` and ``fail_charge_denom`` are set to ``1`` and ``1024``, +respectively. Then only 700 MiB and 300 KiB of size (``700 MiB + 300 MiB * 1 / +1024``) will be charged. + + .. _damon_design_damos_quotas_auto_tuning: Aim-oriented Feedback-driven Auto-tuning diff --git a/Documentation/mm/damon/maintainer-profile.rst b/Documentation/mm/damon/maintainer-profile.rst index bcb9798a27a86f..fb2fa00cc9aa1b 100644 --- a/Documentation/mm/damon/maintainer-profile.rst +++ b/Documentation/mm/damon/maintainer-profile.rst @@ -100,3 +100,24 @@ There is also a public Google `calendar `_ that has the events. Anyone can subscribe to it. DAMON maintainer will also provide periodic reminders to the mailing list (damon@lists.linux.dev). + +AI Review +--------- + +For patches that are publicly posted to DAMON mailing list +(damon@lists.linux.dev), AI reviews of the patches will be available at +sashiko.dev. The reviews could also be sent as mails to the author of the +patch. + +Patch authors are encouraged to check the AI reviews and share their opinions. +The sharing could be done as a reply to the mail thread. Consider reducing the +recipients list for such sharing, since some people are not really interested +in AI reviews. As a rule of thumb, drop stable@vger.kernel.org and individuals +except DAMON maintainer. + +`hkml` also provides a `feature +`_ +for such sharing. Please feel free to use the feature. + +It is only an optional recommendation. DAMON maintainer could also ask any +question about the AI reviews, though. diff --git a/Documentation/mm/index.rst b/Documentation/mm/index.rst index 7aa2a888690832..13a79f5d092c0e 100644 --- a/Documentation/mm/index.rst +++ b/Documentation/mm/index.rst @@ -7,6 +7,19 @@ of Linux. If you are looking for advice on simply allocating memory, see the :ref:`memory_allocation`. For controlling and tuning guides, see the :doc:`admin guide <../admin-guide/mm/index>`. +.. note:: + + Unfortunately, parts of this guide are still incomplete or missing. + While we appreciate contributions, documentation in this area is hard + to get right and requires a lot of attention to detail. New contributors + should reach out to the relevant maintainers early. + + This guide is expected to reflect reality, which requires contributors + to have a detailed understanding. Documentation generated with LLMs + by contributors unfamiliar with these details shifts the real work onto + reviewers, which is why such contributions will be rejected without + further comment. + .. toctree:: :maxdepth: 1 diff --git a/Documentation/mm/memfd_preservation.rst b/Documentation/mm/memfd_preservation.rst index a8a5b476afd306..c908a12dffa7c0 100644 --- a/Documentation/mm/memfd_preservation.rst +++ b/Documentation/mm/memfd_preservation.rst @@ -11,7 +11,7 @@ Memfd Preservation ABI ====================== .. kernel-doc:: include/linux/kho/abi/memfd.h - :doc: DOC: memfd Live Update ABI + :doc: memfd Live Update ABI .. kernel-doc:: include/linux/kho/abi/memfd.h :internal: diff --git a/Documentation/mm/process_addrs.rst b/Documentation/mm/process_addrs.rst index 851680ead45fa1..042d64d72421b6 100644 --- a/Documentation/mm/process_addrs.rst +++ b/Documentation/mm/process_addrs.rst @@ -775,7 +775,7 @@ lock, releasing or downgrading the mmap write lock also releases the VMA write lock so there is no :c:func:`!vma_end_write` function. Note that when write-locking a VMA lock, the :c:member:`!vma.vm_refcnt` is temporarily -modified so that readers can detect the presense of a writer. The reference counter is +modified so that readers can detect the presence of a writer. The reference counter is restored once the vma sequence number used for serialisation is updated. This ensures the semantics we require - VMA write locks provide exclusive write diff --git a/Documentation/netlink/specs/devlink.yaml b/Documentation/netlink/specs/devlink.yaml index 247b147d689fa7..52ad1e7805d198 100644 --- a/Documentation/netlink/specs/devlink.yaml +++ b/Documentation/netlink/specs/devlink.yaml @@ -234,6 +234,10 @@ definitions: value: 10 - name: binary + - + name: u64-array + value: 129 + - name: rate-tc-index-max type: const diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml index 40465a3d7fc203..2bf83f6732ab0d 100644 --- a/Documentation/netlink/specs/dpll.yaml +++ b/Documentation/netlink/specs/dpll.yaml @@ -138,6 +138,9 @@ definitions: - name: eec doc: dpll drives the Ethernet Equipment Clock + - + name: generic + doc: generic dpll type for devices outside PPS/EEC classes render-max: true - type: enum @@ -212,6 +215,27 @@ definitions: name: selectable doc: pin enabled for automatic input selection render-max: true + - + type: enum + name: pin-operstate + doc: | + defines possible operational states of a pin with respect to its + parent DPLL device, valid values for DPLL_A_PIN_OPERSTATE attribute + entries: + - + name: active + doc: pin is qualified and actively used by the DPLL + value: 1 + - + name: standby + doc: pin is qualified but not actively used by the DPLL + - + name: no-signal + doc: pin does not have a valid signal + - + name: qual-failed + doc: pin signal failed qualification (e.g. frequency or phase monitor) + render-max: true - type: flags name: pin-capabilities @@ -427,12 +451,14 @@ attribute-sets: name: fractional-frequency-offset type: sint doc: | - The FFO (Fractional Frequency Offset) between the RX and TX - symbol rate on the media associated with the pin: - (rx_frequency-tx_frequency)/rx_frequency + The FFO (Fractional Frequency Offset) of the pin. + At top level this represents the RX vs TX symbol rate + offset on the media associated with the pin. Inside + the pin-parent-device nest it represents the frequency + offset between the pin and its parent DPLL device. Value is in PPM (parts per million). - This may be implemented for example for pin of type - PIN_TYPE_SYNCE_ETH_PORT. + This is a lower-precision version of + fractional-frequency-offset-ppt. - name: esync-frequency type: u64 @@ -471,12 +497,14 @@ attribute-sets: name: fractional-frequency-offset-ppt type: sint doc: | - The FFO (Fractional Frequency Offset) of the pin with respect to - the nominal frequency. - Value = (frequency_measured - frequency_nominal) / frequency_nominal + The FFO (Fractional Frequency Offset) of the pin. + At top level this represents the RX vs TX symbol rate + offset on the media associated with the pin. Inside + the pin-parent-device nest it represents the frequency + offset between the pin and its parent DPLL device. Value is in PPT (parts per trillion, 10^-12). - Note: This attribute provides higher resolution than the standard - fractional-frequency-offset (which is in PPM). + This is a higher-precision version of + fractional-frequency-offset. - name: measured-frequency type: u64 @@ -488,6 +516,14 @@ attribute-sets: Value of (DPLL_A_PIN_MEASURED_FREQUENCY % DPLL_PIN_MEASURED_FREQUENCY_DIVIDER) is a fractional part of a measured frequency value. + - + name: operstate + type: u32 + enum: pin-operstate + doc: | + Operational state of the pin with respect to its parent DPLL + device. Unlike state (which reflects the administrative intent), + operstate reflects the actual hardware status. - name: pin-parent-device @@ -501,8 +537,14 @@ attribute-sets: name: prio - name: state + - + name: operstate - name: phase-offset + - + name: fractional-frequency-offset + - + name: fractional-frequency-offset-ppt - name: pin-parent-pin subset-of: pin diff --git a/Documentation/netlink/specs/drm_ras.yaml b/Documentation/netlink/specs/drm_ras.yaml index 79af25dac3c57f..e113056f8c016c 100644 --- a/Documentation/netlink/specs/drm_ras.yaml +++ b/Documentation/netlink/specs/drm_ras.yaml @@ -99,7 +99,7 @@ operations: flags: [admin-perm] do: request: - attributes: + attributes: &id-attrs - node-id - error-id reply: @@ -113,3 +113,14 @@ operations: - node-id reply: attributes: *errorinfo + - + name: clear-error-counter + doc: >- + Clear error counter for a given node. + The request includes the error-id and node-id of the + counter to be cleared. + attribute-set: error-counter-attrs + flags: [admin-perm] + do: + request: + attributes: *id-attrs diff --git a/Documentation/netlink/specs/handshake.yaml b/Documentation/netlink/specs/handshake.yaml index 1024297b38513a..ffec12b467597d 100644 --- a/Documentation/netlink/specs/handshake.yaml +++ b/Documentation/netlink/specs/handshake.yaml @@ -125,6 +125,7 @@ operations: name: done doc: Handler reports handshake completion attribute-set: done + flags: [admin-perm] do: request: attributes: diff --git a/Documentation/netlink/specs/netdev.yaml b/Documentation/netlink/specs/netdev.yaml index b93beb247a112c..5f143da7458cfb 100644 --- a/Documentation/netlink/specs/netdev.yaml +++ b/Documentation/netlink/specs/netdev.yaml @@ -127,7 +127,14 @@ attribute-sets: enum: xsk-flags - name: io-uring-provider-info - attributes: [] + attributes: + - + name: rx-buf-len + type: uint + doc: | + RX buffer length in bytes for this io_uring memory provider. + Reflects the rx_buf_len passed at io_uring zerocopy rx + registration time. - name: page-pool attributes: @@ -649,6 +656,9 @@ operations: - dmabuf - io-uring dump: + request: + attributes: + - ifindex reply: *pp-reply config-cond: page-pool - @@ -692,6 +702,9 @@ operations: - recycle-ring-full - recycle-released-refcnt dump: + request: + attributes: + - info reply: *pp-stats-reply config-cond: page-pool-stats - @@ -792,7 +805,7 @@ operations: name: bind-rx doc: Bind dmabuf to netdev attribute-set: dmabuf - flags: [admin-perm] + flags: [uns-admin-perm] do: request: attributes: diff --git a/Documentation/netlink/specs/nfsd.yaml b/Documentation/netlink/specs/nfsd.yaml index 8ab43c8253b2e8..8f36fadd68f75b 100644 --- a/Documentation/netlink/specs/nfsd.yaml +++ b/Documentation/netlink/specs/nfsd.yaml @@ -6,7 +6,51 @@ uapi-header: linux/nfsd_netlink.h doc: NFSD configuration over generic netlink. +definitions: + - + type: flags + name: cache-type + entries: [svc_export, expkey] + - + type: flags + name: export-flags + doc: These flags are ordered to match the NFSEXP_* flags in include/linux/nfsd/export.h + entries: + - readonly + - insecure-port + - rootsquash + - allsquash + - async + - gathered-writes + - noreaddirplus + - security-label + - sign-fh + - nohide + - nosubtreecheck + - noauthnlm + - msnfs + - fsid + - crossmount + - noacl + - v4root + - pnfs + - + type: flags + name: xprtsec-mode + doc: These flags are ordered to match the NFSEXP_XPRTSEC_* flags in include/linux/nfsd/export.h + entries: + - none + - tls + - mtls + attribute-sets: + - + name: cache-notify + attributes: + - + name: cache-type + type: u32 + enum: cache-type - name: rpc-status attributes: @@ -132,6 +176,160 @@ attribute-sets: - name: npools type: u32 + - + name: fslocation + attributes: + - + name: host + type: string + - + name: path + type: string + - + name: fslocations + attributes: + - + name: location + type: nest + nested-attributes: fslocation + multi-attr: true + - + name: auth-flavor + attributes: + - + name: pseudoflavor + type: u32 + - + name: flags + type: u32 + enum: export-flags + enum-as-flags: true + - + name: svc-export + attributes: + - + name: seqno + type: u64 + - + name: client + type: string + - + name: path + type: string + - + name: negative + type: flag + - + name: expiry + type: u64 + - + name: anon-uid + type: u32 + - + name: anon-gid + type: u32 + - + name: fslocations + type: nest + nested-attributes: fslocations + - + name: uuid + type: binary + - + name: secinfo + type: nest + nested-attributes: auth-flavor + multi-attr: true + - + name: xprtsec + type: u32 + enum: xprtsec-mode + multi-attr: true + - + name: flags + type: u32 + enum: export-flags + enum-as-flags: true + - + name: fsid + type: s32 + - + name: svc-export-reqs + attributes: + - + name: requests + type: nest + nested-attributes: svc-export + multi-attr: true + - + name: expkey + attributes: + - + name: seqno + type: u64 + - + name: client + type: string + - + name: fsidtype + type: u8 + - + name: fsid + type: binary + - + name: negative + type: flag + - + name: expiry + type: u64 + - + name: path + type: string + - + name: expkey-reqs + attributes: + - + name: requests + type: nest + nested-attributes: expkey + multi-attr: true + - + name: cache-flush + attributes: + - + name: mask + type: u32 + enum: cache-type + enum-as-flags: true + - + name: unlock-ip + attributes: + - + name: address + type: binary + doc: struct sockaddr_in or struct sockaddr_in6. + checks: + min-len: 16 + - + name: unlock-filesystem + attributes: + - + name: path + type: string + doc: Filesystem path whose state should be released. + - + name: unlock-export + attributes: + - + name: path + type: string + doc: >- + Export path whose NFSv4 state should be revoked. + All state (opens, locks, delegations, layouts) acquired + through any export of this path is revoked, regardless + of which client holds the state. Intended for use after + all clients have been unexported from a given path, + enabling the underlying filesystem to be unmounted. operations: list: @@ -233,3 +431,95 @@ operations: attributes: - mode - npools + - + name: cache-notify + doc: Notification that there are cache requests that need servicing + attribute-set: cache-notify + mcgrp: exportd + event: + attributes: + - cache-type + - + name: svc-export-get-reqs + doc: Dump all pending svc_export requests + attribute-set: svc-export-reqs + flags: [admin-perm] + dump: + reply: + attributes: + - requests + - + name: svc-export-set-reqs + doc: Respond to one or more svc_export requests + attribute-set: svc-export-reqs + flags: [admin-perm] + do: + request: + attributes: + - requests + - + name: expkey-get-reqs + doc: Dump all pending expkey requests + attribute-set: expkey-reqs + flags: [admin-perm] + dump: + reply: + attributes: + - requests + - + name: expkey-set-reqs + doc: Respond to one or more expkey requests + attribute-set: expkey-reqs + flags: [admin-perm] + do: + request: + attributes: + - requests + - + name: cache-flush + doc: Flush nfsd caches (svc_export and/or expkey) + attribute-set: cache-flush + flags: [admin-perm] + do: + request: + attributes: + - mask + - + name: unlock-ip + doc: release NLM locks held by an IP address + attribute-set: unlock-ip + flags: [admin-perm] + do: + request: + attributes: + - address + - + name: unlock-filesystem + doc: revoke NFS state under a filesystem path + attribute-set: unlock-filesystem + flags: [admin-perm] + do: + request: + attributes: + - path + - + name: unlock-export + doc: >- + Revoke NFSv4 state acquired through exports of a given path. + Unlike unlock-filesystem, which operates at superblock granularity, + this command targets only state associated with a specific export + path. Userspace (exportfs -u) sends this after removing the last + client for a path so the underlying filesystem can be unmounted. + attribute-set: unlock-export + flags: [admin-perm] + do: + request: + attributes: + - path + +mcast-groups: + list: + - + name: none + - + name: exportd diff --git a/Documentation/netlink/specs/ovs_packet.yaml b/Documentation/netlink/specs/ovs_packet.yaml new file mode 100644 index 00000000000000..e4c5f24b3b01eb --- /dev/null +++ b/Documentation/netlink/specs/ovs_packet.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) +--- +name: ovs_packet +version: 1 +protocol: genetlink-legacy +uapi-header: linux/openvswitch.h + +doc: | + OVS packet execution over generic netlink. + + Only OVS_PACKET_CMD_EXECUTE is exposed as a genl operation. + OVS_PACKET_CMD_MISS and OVS_PACKET_CMD_ACTION are kernel-to-userspace + upcalls sent via genlmsg_unicast() to the vport's upcall_pid and have + no associated genl_ops or multicast group. + + Several attributes in the attribute set (userdata, egress-tun-key, len) + exist for the upcall path and are not used by the EXECUTE operation. + For EXECUTE, packet, key, and actions are mandatory (kernel returns + -EINVAL without them). + +definitions: + - + name: ovs-header + type: struct + members: + - + name: dp-ifindex + type: u32 + +attribute-sets: + - + name: packet + name-prefix: ovs-packet-attr- + enum-name: ovs-packet-attr + attributes: + - + name: packet + type: binary + doc: Packet data, from the start of the Ethernet header. + checks: + min-len: 14 + - + name: key + type: binary + doc: | + Nested OVS_KEY_ATTR_* attributes, extracted flow key. + Defined as binary because the key attribute-set belongs to the + ovs_flow family spec; cross-spec references are not supported. + - + name: actions + type: binary + doc: | + Nested OVS_ACTION_ATTR_* attributes. + Defined as binary for the same reason as key. + - + name: userdata + type: binary + doc: Opaque userspace cookie from OVS_USERSPACE_ATTR_USERDATA. + - + name: egress-tun-key + type: binary + doc: Nested OVS_TUNNEL_KEY_ATTR_* for output tunnel metadata. + - + name: unused1 + type: unused + - + name: unused2 + type: unused + - + name: probe + type: flag + doc: Packet operation is a feature probe, error logging suppressed. + - + name: mru + type: u16 + doc: Maximum received IP fragment size. + - + name: len + type: u32 + doc: Packet size before truncation. + - + name: hash + type: u64 + doc: Packet hash, low 32 bits are skb hash, upper bits are flags. + - + name: upcall-pid + type: u32 + doc: Netlink PID to use for upcalls during EXECUTE processing. + +operations: + fixed-header: ovs-header + name-prefix: ovs-packet-cmd- + list: + - + name: miss + doc: Notify userspace of a flow table miss for a received packet. + value: 1 + attribute-set: packet + event: + attributes: &event-attrs + - packet + - key + - userdata + - actions + - egress-tun-key + - mru + - len + - hash + - + name: action + doc: Notify userspace as requested by an OVS_ACTION_ATTR_USERSPACE action. + value: 2 + attribute-set: packet + event: + attributes: *event-attrs + - + name: execute + doc: Apply actions to a packet. + value: 3 + attribute-set: packet + do: + request: + attributes: + - packet + - key + - actions + - probe + - mru + - hash + - upcall-pid diff --git a/Documentation/netlink/specs/psp.yaml b/Documentation/netlink/specs/psp.yaml index bfcd6e4ecb850e..e9c2ee7e28e026 100644 --- a/Documentation/netlink/specs/psp.yaml +++ b/Documentation/netlink/specs/psp.yaml @@ -13,6 +13,17 @@ definitions: hdr0-aes-gmac-128, hdr0-aes-gmac-256] attribute-sets: + - + name: assoc-dev-info + attributes: + - + name: ifindex + doc: ifindex of an associated network device. + type: u32 + - + name: nsid + doc: Network namespace ID of the associated device. + type: s32 - name: dev attributes: @@ -24,7 +35,9 @@ attribute-sets: min: 1 - name: ifindex - doc: ifindex of the main netdevice linked to the PSP device. + doc: | + ifindex of the main netdevice linked to the PSP device, + or the ifindex to associate with the PSP device. type: u32 - name: psp-versions-cap @@ -38,6 +51,28 @@ attribute-sets: type: u32 enum: version enum-as-flags: true + - + name: assoc-list + doc: List of associated virtual devices. + type: nest + nested-attributes: assoc-dev-info + multi-attr: true + - + name: nsid + doc: | + Network namespace ID for the device to associate/disassociate. + Optional for dev-assoc and dev-disassoc; if not present, the + device is looked up in the caller's network namespace. + type: s32 + - + name: by-association + doc: | + Flag indicating the PSP device is an associated device from a + different network namespace. + Present when in associated namespace, absent when in primary/host + namespace. + type: flag + - name: assoc attributes: @@ -170,6 +205,8 @@ operations: - ifindex - psp-versions-cap - psp-versions-ena + - assoc-list + - by-association pre: psp-device-get-locked post: psp-device-unlock dump: @@ -196,7 +233,7 @@ operations: - psp-versions-ena reply: attributes: [] - pre: psp-device-get-locked + pre: psp-device-get-locked-admin post: psp-device-unlock - name: dev-change-ntf @@ -216,7 +253,7 @@ operations: reply: attributes: - id - pre: psp-device-get-locked + pre: psp-device-get-locked-admin post: psp-device-unlock - name: key-rotate-ntf @@ -281,6 +318,36 @@ operations: post: psp-device-unlock dump: reply: *stats-all + - + name: dev-assoc + doc: Associate a network device with a PSP device. + attribute-set: dev + flags: [admin-perm] + do: + request: + attributes: + - id + - ifindex + - nsid + reply: + attributes: [] + pre: psp-device-get-locked-dev-assoc + post: psp-device-unlock + - + name: dev-disassoc + doc: Disassociate a network device from a PSP device. + attribute-set: dev + flags: [admin-perm] + do: + request: + attributes: + - id + - ifindex + - nsid + reply: + attributes: [] + pre: psp-device-get-locked + post: psp-device-unlock mcast-groups: list: diff --git a/Documentation/netlink/specs/rt-link.yaml b/Documentation/netlink/specs/rt-link.yaml index f23aa5f229c500..892979da098ed1 100644 --- a/Documentation/netlink/specs/rt-link.yaml +++ b/Documentation/netlink/specs/rt-link.yaml @@ -880,19 +880,21 @@ attribute-sets: struct: rtnl-link-stats - name: cost - type: string + type: unused - name: priority - type: string + type: unused - name: master type: u32 - name: wireless - type: string + type: binary + doc: struct iw_event - name: protinfo - type: string + type: binary + doc: A nest of ifla6-attrs or linkinfo-brport-attrs - name: txqlen type: u32 @@ -1351,6 +1353,12 @@ attribute-sets: - name: coupled-control type: u8 + - + name: broadcast-neigh + type: u8 + - + name: lacp-strict + type: u8 - name: bond-ad-info-attrs name-prefix: ifla-bond-ad-info- @@ -1700,6 +1708,9 @@ attribute-sets: - name: backup-nhid type: u32 + - + name: neigh-forward-grat + type: u8 - name: linkinfo-gre-attrs name-prefix: ifla-gre- @@ -1936,6 +1947,15 @@ attribute-sets: - name: gro-hint type: flag + - + name: local + type: u32 + byte-order: big-endian + display-hint: ipv4 + - + name: local6 + type: binary + display-hint: ipv6 - name: linkinfo-hsr-attrs name-prefix: ifla-hsr- diff --git a/Documentation/netlink/specs/sunrpc_cache.yaml b/Documentation/netlink/specs/sunrpc_cache.yaml new file mode 100644 index 00000000000000..f22ff22b9418fa --- /dev/null +++ b/Documentation/netlink/specs/sunrpc_cache.yaml @@ -0,0 +1,149 @@ +# SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) +--- +name: sunrpc +protocol: genetlink +uapi-header: linux/sunrpc_netlink.h + +doc: SUNRPC cache upcall support over generic netlink. + +definitions: + - + type: flags + name: cache-type + entries: [ip_map, unix_gid] + +attribute-sets: + - + name: cache-notify + attributes: + - + name: cache-type + type: u32 + enum: cache-type + - + name: ip-map + attributes: + - + name: seqno + type: u64 + - + name: class + type: string + - + name: addr + type: string + - + name: domain + type: string + - + name: negative + type: flag + - + name: expiry + type: u64 + - + name: ip-map-reqs + attributes: + - + name: requests + type: nest + nested-attributes: ip-map + multi-attr: true + - + name: unix-gid + attributes: + - + name: seqno + type: u64 + - + name: uid + type: u32 + - + name: gids + type: u32 + multi-attr: true + - + name: negative + type: flag + - + name: expiry + type: u64 + - + name: unix-gid-reqs + attributes: + - + name: requests + type: nest + nested-attributes: unix-gid + multi-attr: true + - + name: cache-flush + attributes: + - + name: mask + type: u32 + enum: cache-type + enum-as-flags: true + +operations: + list: + - + name: cache-notify + doc: Notification that there are cache requests that need servicing + attribute-set: cache-notify + mcgrp: exportd + event: + attributes: + - cache-type + - + name: ip-map-get-reqs + doc: Dump all pending ip_map requests + attribute-set: ip-map-reqs + flags: [admin-perm] + dump: + reply: + attributes: + - requests + - + name: ip-map-set-reqs + doc: Respond to one or more ip_map requests + attribute-set: ip-map-reqs + flags: [admin-perm] + do: + request: + attributes: + - requests + - + name: unix-gid-get-reqs + doc: Dump all pending unix_gid requests + attribute-set: unix-gid-reqs + flags: [admin-perm] + dump: + reply: + attributes: + - requests + - + name: unix-gid-set-reqs + doc: Respond to one or more unix_gid requests + attribute-set: unix-gid-reqs + flags: [admin-perm] + do: + request: + attributes: + - requests + - + name: cache-flush + doc: Flush sunrpc caches (ip_map and/or unix_gid) + attribute-set: cache-flush + flags: [admin-perm] + do: + request: + attributes: + - mask + +mcast-groups: + list: + - + name: none + - + name: exportd diff --git a/Documentation/networking/arcnet-hardware.rst b/Documentation/networking/arcnet-hardware.rst index 20e5075d0d0e7d..37c016cee35366 100644 --- a/Documentation/networking/arcnet-hardware.rst +++ b/Documentation/networking/arcnet-hardware.rst @@ -8,16 +8,13 @@ ARCnet Hardware .. note:: - 1) This file is a supplement to arcnet.rst. Please read that for general - driver configuration help. - 2) This file is no longer Linux-specific. It should probably be moved out - of the kernel sources. Ideas? + This file is a supplement to arcnet.rst. Please read that for general + driver configuration help. Because so many people (myself included) seem to have obtained ARCnet cards -without manuals, this file contains a quick introduction to ARCnet hardware, -some cabling tips, and a listing of all jumper settings I can find. If you -have any settings for your particular card, and/or any other information you -have, do not hesitate to :ref:`email to netdev `. +without manuals, this file contains a quick introduction to ARCnet hardware +and some cabling tips. If you have any other information, do not hesitate to +:ref:`send an email to netdev `. Introduction to ARCnet @@ -135,13 +132,11 @@ And now to the cabling. What you can connect together: network. 2. A card to a passive hub. Remember that all unused connectors on the hub - must be properly terminated with 93 Ohm (or something else if you don't - have the right ones) terminators. + must be properly terminated with 93 Ohm terminators (or something else if you + don't have the right ones), although the network may work without + terminators. - (Avery's note: oops, I didn't know that. Mine (TV cable) works - anyway, though.) - -3. A card to an active hub. Here is no need to terminate the unused +3. A card to an active hub. Here there is no need to terminate the unused connectors except some kind of aesthetic feeling. But, there may not be more than eleven active hubs between any two computers. That of course doesn't limit the number of active hubs on the network. @@ -151,7 +146,7 @@ And now to the cabling. What you can connect together: 5. An active hub to passive hub. Remember that you cannot connect two passive hubs together. The power loss -implied by such a connection is too high for the net to operate reliably. +implied by such a connection is too high for the network to operate reliably. An example of a typical ARCnet network:: @@ -164,8 +159,8 @@ An example of a typical ARCnet network:: | S -The BUS topology is very similar to the one used by Ethernet. The only -difference is in cable and terminators: they should be 93 Ohm. Ethernet +The BUS topology is very similar to the one used by 10BASE2 Ethernet. The only +difference is in cable and terminators: they should be 93 Ohm. 10BASE2 Ethernet uses 50 Ohm impedance. You use T connectors to put the computers on a single line of cable, the bus. You have to put terminators at both ends of the cable. A typical BUS ARCnet network looks like:: @@ -178,7 +173,7 @@ cable. A typical BUS ARCnet network looks like:: T - T connector But that is not all! The two types can be connected together. According to -the official documentation the only way of connecting them is using an active +the official documentation, the only way of connecting them is using an active hub:: A------T------T------TR @@ -187,7 +182,7 @@ hub:: | S -The official docs also state that you can use STAR cards at the ends of +The official docs also state that you can use STAR cards at the ends of a BUS network in place of a BUS card and a terminator:: S------T------T------S @@ -212,7 +207,7 @@ example:: | | S------T----H---S | S S B R S -A basically different cabling scheme is used with Twisted Pair cabling. Each +A completely different cabling scheme is used with Twisted Pair cabling. Each of the TP cards has two RJ (phone-cord style) connectors. The cards are then daisy-chained together using a cable connecting every two neighboring cards. The ends are terminated with RJ 93 Ohm terminators which plug into @@ -264,95 +259,13 @@ of a TP cable between two cards/hubs is 650 meters. Setting the Jumpers =================== -All ARCnet cards should have a total of four or five different settings: - - - the I/O address: this is the "port" your ARCnet card is on. Probed - values in the Linux ARCnet driver are only from 0x200 through 0x3F0. (If - your card has additional ones, which is possible, please tell me.) This - should not be the same as any other device on your system. According to - a doc I got from Novell, MS Windows prefers values of 0x300 or more, - eating net connections on my system (at least) otherwise. My guess is - this may be because, if your card is at 0x2E0, probing for a serial port - at 0x2E8 will reset the card and probably mess things up royally. - - - Avery's favourite: 0x300. - - - the IRQ: on 8-bit cards, it might be 2 (9), 3, 4, 5, or 7. - on 16-bit cards, it might be 2 (9), 3, 4, 5, 7, or 10-15. - - Make sure this is different from any other card on your system. Note - that IRQ2 is the same as IRQ9, as far as Linux is concerned. You can - "cat /proc/interrupts" for a somewhat complete list of which ones are in - use at any given time. Here is a list of common usages from Vojtech - Pavlik : - - ("Not on bus" means there is no way for a card to generate this - interrupt) - - ====== ========================================================= - IRQ 0 Timer 0 (Not on bus) - IRQ 1 Keyboard (Not on bus) - IRQ 2 IRQ Controller 2 (Not on bus, nor does interrupt the CPU) - IRQ 3 COM2 - IRQ 4 COM1 - IRQ 5 FREE (LPT2 if you have it; sometimes COM3; maybe PLIP) - IRQ 6 Floppy disk controller - IRQ 7 FREE (LPT1 if you don't use the polling driver; PLIP) - IRQ 8 Realtime Clock Interrupt (Not on bus) - IRQ 9 FREE (VGA vertical sync interrupt if enabled) - IRQ 10 FREE - IRQ 11 FREE - IRQ 12 FREE - IRQ 13 Numeric Coprocessor (Not on bus) - IRQ 14 Fixed Disk Controller - IRQ 15 FREE (Fixed Disk Controller 2 if you have it) - ====== ========================================================= - - - .. note:: - - IRQ 9 is used on some video cards for the "vertical retrace" - interrupt. This interrupt would have been handy for things like - video games, as it occurs exactly once per screen refresh, but - unfortunately IBM cancelled this feature starting with the original - VGA and thus many VGA/SVGA cards do not support it. For this - reason, no modern software uses this interrupt and it can almost - always be safely disabled, if your video card supports it at all. - - If your card for some reason CANNOT disable this IRQ (usually there - is a jumper), one solution would be to clip the printed circuit - contact on the board: it's the fourth contact from the left on the - back side. I take no responsibility if you try this. - - - Avery's favourite: IRQ2 (actually IRQ9). Watch that VGA, though. - - - the memory address: Unlike most cards, ARCnets use "shared memory" for - copying buffers around. Make SURE it doesn't conflict with any other - used memory in your system! - - :: - - A0000 - VGA graphics memory (ok if you don't have VGA) - B0000 - Monochrome text mode - C0000 \ One of these is your VGA BIOS - usually C0000. - E0000 / - F0000 - System BIOS - - Anything less than 0xA0000 is, well, a BAD idea since it isn't above - 640k. - - - Avery's favourite: 0xD0000 - - - the station address: Every ARCnet card has its own "unique" network - address from 0 to 255. Unlike Ethernet, you can set this address - yourself with a jumper or switch (or on some cards, with special - software). Since it's only 8 bits, you can only have 254 ARCnet cards - on a network. DON'T use 0 or 255, since these are reserved (although - neat stuff will probably happen if you DO use them). By the way, if you - haven't already guessed, don't set this the same as any other ARCnet on - your network! - - - Avery's favourite: 3 and 4. Not that it matters. + - Every ARCnet card has its own "unique" network address from 0 to 255. + Unlike Ethernet, you can set this address yourself with a jumper or switch + (or on some cards, with special software). Since it's only 8 bits, you can + only have 254 ARCnet cards on a network. DON'T use 0 or 255, since these + are reserved (although neat stuff will probably happen if you DO use them). + By the way, if you haven't already guessed, don't set this the same as any + other ARCnet device on your network! - There may be ETS1 and ETS2 settings. These may or may not make a difference on your card (many manuals call them "reserved"), but are @@ -375,11 +288,13 @@ All ARCnet cards should have a total of four or five different settings: Make sure you set ETS1 and ETS2 to the SAME VALUE for all cards on your network. -Also, on many cards (not mine, though) there are red and green LED's. -Vojtech Pavlik tells me this is what they mean: +LED Indicators +============== + +Many cards have red and green LEDs, which have the following meanings: =============== =============== ===================================== - GREEN RED Status + Green Red Status =============== =============== ===================================== OFF OFF Power off OFF Short flashes Cabling problems (broken cable or not @@ -390,2843 +305,3 @@ Vojtech Pavlik tells me this is what they mean: ON Long flashes Data transfer ON OFF Never happens (maybe when wrong ID) =============== =============== ===================================== - - -The following is all the specific information people have sent me about -their own particular ARCnet cards. It is officially a mess, and contains -huge amounts of duplicated information. I have no time to fix it. If you -want to, PLEASE DO! Just send me a 'diff -u' of all your changes. - -The model # is listed right above specifics for that card, so you should be -able to use your text viewer's "search" function to find the entry you want. -If you don't KNOW what kind of card you have, try looking through the -various diagrams to see if you can tell. - -If your model isn't listed and/or has different settings, PLEASE PLEASE -tell me. I had to figure mine out without the manual, and it WASN'T FUN! - -Even if your ARCnet model isn't listed, but has the same jumpers as another -model that is, please e-mail me to say so. - -Cards Listed in this file (in this order, mostly): - - =============== ======================= ==== - Manufacturer Model # Bits - =============== ======================= ==== - SMC PC100 8 - SMC PC110 8 - SMC PC120 8 - SMC PC130 8 - SMC PC270E 8 - SMC PC500 16 - SMC PC500Longboard 16 - SMC PC550Longboard 16 - SMC PC600 16 - SMC PC710 8 - SMC? LCS-8830(-T) 8/16 - Puredata PDI507 8 - CNet Tech CN120-Series 8 - CNet Tech CN160-Series 16 - Lantech? UM9065L chipset 8 - Acer 5210-003 8 - Datapoint? LAN-ARC-8 8 - Topware TA-ARC/10 8 - Thomas-Conrad 500-6242-0097 REV A 8 - Waterloo? (C)1985 Waterloo Micro. 8 - No Name -- 8/16 - No Name Taiwan R.O.C? 8 - No Name Model 9058 8 - Tiara Tiara Lancard? 8 - =============== ======================= ==== - - -* SMC = Standard Microsystems Corp. -* CNet Tech = CNet Technology, Inc. - -Unclassified Stuff -================== - - - Please send any other information you can find. - - - And some other stuff (more info is welcome!):: - - From: root@ultraworld.xs4all.nl (Timo Hilbrink) - To: apenwarr@foxnet.net (Avery Pennarun) - Date: Wed, 26 Oct 1994 02:10:32 +0000 (GMT) - Reply-To: timoh@xs4all.nl - - [...parts deleted...] - - About the jumpers: On my PC130 there is one more jumper, located near the - cable-connector and it's for changing to star or bus topology; - closed: star - open: bus - On the PC500 are some more jumper-pins, one block labeled with RX,PDN,TXI - and another with ALE,LA17,LA18,LA19 these are undocumented.. - - [...more parts deleted...] - - --- CUT --- - -Standard Microsystems Corp (SMC) -================================ - -PC100, PC110, PC120, PC130 (8-bit cards) and PC500, PC600 (16-bit cards) ------------------------------------------------------------------------- - - - mainly from Avery Pennarun . Values depicted - are from Avery's setup. - - special thanks to Timo Hilbrink for noting that PC120, - 130, 500, and 600 all have the same switches as Avery's PC100. - PC500/600 have several extra, undocumented pins though. (?) - - PC110 settings were verified by Stephen A. Wood - - Also, the JP- and S-numbers probably don't match your card exactly. Try - to find jumpers/switches with the same number of settings - it's - probably more reliable. - -:: - - JP5 [|] : : : : - (IRQ Setting) IRQ2 IRQ3 IRQ4 IRQ5 IRQ7 - Put exactly one jumper on exactly one set of pins. - - - 1 2 3 4 5 6 7 8 9 10 - S1 /----------------------------------\ - (I/O and Memory | 1 1 * 0 0 0 0 * 1 1 0 1 | - addresses) \----------------------------------/ - |--| |--------| |--------| - (a) (b) (m) - - WARNING. It's very important when setting these which way - you're holding the card, and which way you think is '1'! - - If you suspect that your settings are not being made - correctly, try reversing the direction or inverting the - switch positions. - - a: The first digit of the I/O address. - Setting Value - ------- ----- - 00 0 - 01 1 - 10 2 - 11 3 - - b: The second digit of the I/O address. - Setting Value - ------- ----- - 0000 0 - 0001 1 - 0010 2 - ... ... - 1110 E - 1111 F - - The I/O address is in the form ab0. For example, if - a is 0x2 and b is 0xE, the address will be 0x2E0. - - DO NOT SET THIS LESS THAN 0x200!!!!! - - - m: The first digit of the memory address. - Setting Value - ------- ----- - 0000 0 - 0001 1 - 0010 2 - ... ... - 1110 E - 1111 F - - The memory address is in the form m0000. For example, if - m is D, the address will be 0xD0000. - - DO NOT SET THIS TO C0000, F0000, OR LESS THAN A0000! - - 1 2 3 4 5 6 7 8 - S2 /--------------------------\ - (Station Address) | 1 1 0 0 0 0 0 0 | - \--------------------------/ - - Setting Value - ------- ----- - 00000000 00 - 10000000 01 - 01000000 02 - ... - 01111111 FE - 11111111 FF - - Note that this is binary with the digits reversed! - - DO NOT SET THIS TO 0 OR 255 (0xFF)! - - -PC130E/PC270E (8-bit cards) ---------------------------- - - - from Juergen Seifert - -This description has been written by Juergen Seifert -using information from the following Original SMC Manual - - "Configuration Guide for ARCNET(R)-PC130E/PC270 Network - Controller Boards Pub. # 900.044A June, 1989" - -ARCNET is a registered trademark of the Datapoint Corporation -SMC is a registered trademark of the Standard Microsystems Corporation - -The PC130E is an enhanced version of the PC130 board, is equipped with a -standard BNC female connector for connection to RG-62/U coax cable. -Since this board is designed both for point-to-point connection in star -networks and for connection to bus networks, it is downwardly compatible -with all the other standard boards designed for coax networks (that is, -the PC120, PC110 and PC100 star topology boards and the PC220, PC210 and -PC200 bus topology boards). - -The PC270E is an enhanced version of the PC260 board, is equipped with two -modular RJ11-type jacks for connection to twisted pair wiring. -It can be used in a star or a daisy-chained network. - -:: - - 8 7 6 5 4 3 2 1 - ________________________________________________________________ - | | S1 | | - | |_________________| | - | Offs|Base |I/O Addr | - | RAM Addr | ___| - | ___ ___ CR3 |___| - | | \/ | CR4 |___| - | | PROM | ___| - | | | N | | 8 - | | SOCKET | o | | 7 - | |________| d | | 6 - | ___________________ e | | 5 - | | | A | S | 4 - | |oo| EXT2 | | d | 2 | 3 - | |oo| EXT1 | SMC | d | | 2 - | |oo| ROM | 90C63 | r |___| 1 - | |oo| IRQ7 | | |o| _____| - | |oo| IRQ5 | | |o| | J1 | - | |oo| IRQ4 | | STAR |_____| - | |oo| IRQ3 | | | J2 | - | |oo| IRQ2 |___________________| |_____| - |___ ______________| - | | - |_____________________________________________| - -Legend:: - - SMC 90C63 ARCNET Controller / Transceiver /Logic - S1 1-3: I/O Base Address Select - 4-6: Memory Base Address Select - 7-8: RAM Offset Select - S2 1-8: Node ID Select - EXT Extended Timeout Select - ROM ROM Enable Select - STAR Selected - Star Topology (PC130E only) - Deselected - Bus Topology (PC130E only) - CR3/CR4 Diagnostic LEDs - J1 BNC RG62/U Connector (PC130E only) - J1 6-position Telephone Jack (PC270E only) - J2 6-position Telephone Jack (PC270E only) - -Setting one of the switches to Off/Open means "1", On/Closed means "0". - - -Setting the Node ID -^^^^^^^^^^^^^^^^^^^ - -The eight switches in group S2 are used to set the node ID. -These switches work in a way similar to the PC100-series cards; see that -entry for more information. - - -Setting the I/O Base Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The first three switches in switch group S1 are used to select one -of eight possible I/O Base addresses using the following table:: - - - Switch | Hex I/O - 1 2 3 | Address - -------|-------- - 0 0 0 | 260 - 0 0 1 | 290 - 0 1 0 | 2E0 (Manufacturer's default) - 0 1 1 | 2F0 - 1 0 0 | 300 - 1 0 1 | 350 - 1 1 0 | 380 - 1 1 1 | 3E0 - - -Setting the Base Memory (RAM) buffer Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The memory buffer requires 2K of a 16K block of RAM. The base of this -16K block can be located in any of eight positions. -Switches 4-6 of switch group S1 select the Base of the 16K block. -Within that 16K address space, the buffer may be assigned any one of four -positions, determined by the offset, switches 7 and 8 of group S1. - -:: - - Switch | Hex RAM | Hex ROM - 4 5 6 7 8 | Address | Address *) - -----------|---------|----------- - 0 0 0 0 0 | C0000 | C2000 - 0 0 0 0 1 | C0800 | C2000 - 0 0 0 1 0 | C1000 | C2000 - 0 0 0 1 1 | C1800 | C2000 - | | - 0 0 1 0 0 | C4000 | C6000 - 0 0 1 0 1 | C4800 | C6000 - 0 0 1 1 0 | C5000 | C6000 - 0 0 1 1 1 | C5800 | C6000 - | | - 0 1 0 0 0 | CC000 | CE000 - 0 1 0 0 1 | CC800 | CE000 - 0 1 0 1 0 | CD000 | CE000 - 0 1 0 1 1 | CD800 | CE000 - | | - 0 1 1 0 0 | D0000 | D2000 (Manufacturer's default) - 0 1 1 0 1 | D0800 | D2000 - 0 1 1 1 0 | D1000 | D2000 - 0 1 1 1 1 | D1800 | D2000 - | | - 1 0 0 0 0 | D4000 | D6000 - 1 0 0 0 1 | D4800 | D6000 - 1 0 0 1 0 | D5000 | D6000 - 1 0 0 1 1 | D5800 | D6000 - | | - 1 0 1 0 0 | D8000 | DA000 - 1 0 1 0 1 | D8800 | DA000 - 1 0 1 1 0 | D9000 | DA000 - 1 0 1 1 1 | D9800 | DA000 - | | - 1 1 0 0 0 | DC000 | DE000 - 1 1 0 0 1 | DC800 | DE000 - 1 1 0 1 0 | DD000 | DE000 - 1 1 0 1 1 | DD800 | DE000 - | | - 1 1 1 0 0 | E0000 | E2000 - 1 1 1 0 1 | E0800 | E2000 - 1 1 1 1 0 | E1000 | E2000 - 1 1 1 1 1 | E1800 | E2000 - - *) To enable the 8K Boot PROM install the jumper ROM. - The default is jumper ROM not installed. - - -Setting the Timeouts and Interrupt -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The jumpers labeled EXT1 and EXT2 are used to determine the timeout -parameters. These two jumpers are normally left open. - -To select a hardware interrupt level set one (only one!) of the jumpers -IRQ2, IRQ3, IRQ4, IRQ5, IRQ7. The Manufacturer's default is IRQ2. - - -Configuring the PC130E for Star or Bus Topology -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The single jumper labeled STAR is used to configure the PC130E board for -star or bus topology. -When the jumper is installed, the board may be used in a star network, when -it is removed, the board can be used in a bus topology. - - -Diagnostic LEDs -^^^^^^^^^^^^^^^ - -Two diagnostic LEDs are visible on the rear bracket of the board. -The green LED monitors the network activity: the red one shows the -board activity:: - - Green | Status Red | Status - -------|------------------- ---------|------------------- - on | normal activity flash/on | data transfer - blink | reconfiguration off | no data transfer; - off | defective board or | incorrect memory or - | node ID is zero | I/O address - - -PC500/PC550 Longboard (16-bit cards) ------------------------------------- - - - from Juergen Seifert - - - .. note:: - - There is another Version of the PC500 called Short Version, which - is different in hard- and software! The most important differences - are: - - - The long board has no Shared memory. - - On the long board the selection of the interrupt is done by binary - coded switch, on the short board directly by jumper. - -[Avery's note: pay special attention to that: the long board HAS NO SHARED -MEMORY. This means the current Linux-ARCnet driver can't use these cards. -I have obtained a PC500Longboard and will be doing some experiments on it in -the future, but don't hold your breath. Thanks again to Juergen Seifert for -his advice about this!] - -This description has been written by Juergen Seifert -using information from the following Original SMC Manual - - "Configuration Guide for SMC ARCNET-PC500/PC550 - Series Network Controller Boards Pub. # 900.033 Rev. A - November, 1989" - -ARCNET is a registered trademark of the Datapoint Corporation -SMC is a registered trademark of the Standard Microsystems Corporation - -The PC500 is equipped with a standard BNC female connector for connection -to RG-62/U coax cable. -The board is designed both for point-to-point connection in star networks -and for connection to bus networks. - -The PC550 is equipped with two modular RJ11-type jacks for connection -to twisted pair wiring. -It can be used in a star or a daisy-chained (BUS) network. - -:: - - 1 - 0 9 8 7 6 5 4 3 2 1 6 5 4 3 2 1 - ____________________________________________________________________ - < | SW1 | | SW2 | | - > |_____________________| |_____________| | - < IRQ |I/O Addr | - > ___| - < CR4 |___| - > CR3 |___| - < ___| - > N | | 8 - < o | | 7 - > d | S | 6 - < e | W | 5 - > A | 3 | 4 - < d | | 3 - > d | | 2 - < r |___| 1 - > |o| _____| - < |o| | J1 | - > 3 1 JP6 |_____| - < |o|o| JP2 | J2 | - > |o|o| |_____| - < 4 2__ ______________| - > | | | - <____| |_____________________________________________| - -Legend:: - - SW1 1-6: I/O Base Address Select - 7-10: Interrupt Select - SW2 1-6: Reserved for Future Use - SW3 1-8: Node ID Select - JP2 1-4: Extended Timeout Select - JP6 Selected - Star Topology (PC500 only) - Deselected - Bus Topology (PC500 only) - CR3 Green Monitors Network Activity - CR4 Red Monitors Board Activity - J1 BNC RG62/U Connector (PC500 only) - J1 6-position Telephone Jack (PC550 only) - J2 6-position Telephone Jack (PC550 only) - -Setting one of the switches to Off/Open means "1", On/Closed means "0". - - -Setting the Node ID -^^^^^^^^^^^^^^^^^^^ - -The eight switches in group SW3 are used to set the node ID. Each node -attached to the network must have an unique node ID which must be -different from 0. -Switch 1 serves as the least significant bit (LSB). - -The node ID is the sum of the values of all switches set to "1" -These values are:: - - Switch | Value - -------|------- - 1 | 1 - 2 | 2 - 3 | 4 - 4 | 8 - 5 | 16 - 6 | 32 - 7 | 64 - 8 | 128 - -Some Examples:: - - Switch | Hex | Decimal - 8 7 6 5 4 3 2 1 | Node ID | Node ID - ----------------|---------|--------- - 0 0 0 0 0 0 0 0 | not allowed - 0 0 0 0 0 0 0 1 | 1 | 1 - 0 0 0 0 0 0 1 0 | 2 | 2 - 0 0 0 0 0 0 1 1 | 3 | 3 - . . . | | - 0 1 0 1 0 1 0 1 | 55 | 85 - . . . | | - 1 0 1 0 1 0 1 0 | AA | 170 - . . . | | - 1 1 1 1 1 1 0 1 | FD | 253 - 1 1 1 1 1 1 1 0 | FE | 254 - 1 1 1 1 1 1 1 1 | FF | 255 - - -Setting the I/O Base Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The first six switches in switch group SW1 are used to select one -of 32 possible I/O Base addresses using the following table:: - - Switch | Hex I/O - 6 5 4 3 2 1 | Address - -------------|-------- - 0 1 0 0 0 0 | 200 - 0 1 0 0 0 1 | 210 - 0 1 0 0 1 0 | 220 - 0 1 0 0 1 1 | 230 - 0 1 0 1 0 0 | 240 - 0 1 0 1 0 1 | 250 - 0 1 0 1 1 0 | 260 - 0 1 0 1 1 1 | 270 - 0 1 1 0 0 0 | 280 - 0 1 1 0 0 1 | 290 - 0 1 1 0 1 0 | 2A0 - 0 1 1 0 1 1 | 2B0 - 0 1 1 1 0 0 | 2C0 - 0 1 1 1 0 1 | 2D0 - 0 1 1 1 1 0 | 2E0 (Manufacturer's default) - 0 1 1 1 1 1 | 2F0 - 1 1 0 0 0 0 | 300 - 1 1 0 0 0 1 | 310 - 1 1 0 0 1 0 | 320 - 1 1 0 0 1 1 | 330 - 1 1 0 1 0 0 | 340 - 1 1 0 1 0 1 | 350 - 1 1 0 1 1 0 | 360 - 1 1 0 1 1 1 | 370 - 1 1 1 0 0 0 | 380 - 1 1 1 0 0 1 | 390 - 1 1 1 0 1 0 | 3A0 - 1 1 1 0 1 1 | 3B0 - 1 1 1 1 0 0 | 3C0 - 1 1 1 1 0 1 | 3D0 - 1 1 1 1 1 0 | 3E0 - 1 1 1 1 1 1 | 3F0 - - -Setting the Interrupt -^^^^^^^^^^^^^^^^^^^^^ - -Switches seven through ten of switch group SW1 are used to select the -interrupt level. The interrupt level is binary coded, so selections -from 0 to 15 would be possible, but only the following eight values will -be supported: 3, 4, 5, 7, 9, 10, 11, 12. - -:: - - Switch | IRQ - 10 9 8 7 | - ---------|-------- - 0 0 1 1 | 3 - 0 1 0 0 | 4 - 0 1 0 1 | 5 - 0 1 1 1 | 7 - 1 0 0 1 | 9 (=2) (default) - 1 0 1 0 | 10 - 1 0 1 1 | 11 - 1 1 0 0 | 12 - - -Setting the Timeouts -^^^^^^^^^^^^^^^^^^^^ - -The two jumpers JP2 (1-4) are used to determine the timeout parameters. -These two jumpers are normally left open. -Refer to the COM9026 Data Sheet for alternate configurations. - - -Configuring the PC500 for Star or Bus Topology -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The single jumper labeled JP6 is used to configure the PC500 board for -star or bus topology. -When the jumper is installed, the board may be used in a star network, when -it is removed, the board can be used in a bus topology. - - -Diagnostic LEDs -^^^^^^^^^^^^^^^ - -Two diagnostic LEDs are visible on the rear bracket of the board. -The green LED monitors the network activity: the red one shows the -board activity:: - - Green | Status Red | Status - -------|------------------- ---------|------------------- - on | normal activity flash/on | data transfer - blink | reconfiguration off | no data transfer; - off | defective board or | incorrect memory or - | node ID is zero | I/O address - - -PC710 (8-bit card) ------------------- - - - from J.S. van Oosten - -Note: this data is gathered by experimenting and looking at info of other -cards. However, I'm sure I got 99% of the settings right. - -The SMC710 card resembles the PC270 card, but is much more basic (i.e. no -LEDs, RJ11 jacks, etc.) and 8 bit. Here's a little drawing:: - - _______________________________________ - | +---------+ +---------+ |____ - | | S2 | | S1 | | - | +---------+ +---------+ | - | | - | +===+ __ | - | | R | | | X-tal ###___ - | | O | |__| ####__'| - | | M | || ### - | +===+ | - | | - | .. JP1 +----------+ | - | .. | big chip | | - | .. | 90C63 | | - | .. | | | - | .. +----------+ | - ------- ----------- - ||||||||||||||||||||| - -The row of jumpers at JP1 actually consists of 8 jumpers, (sometimes -labelled) the same as on the PC270, from top to bottom: EXT2, EXT1, ROM, -IRQ7, IRQ5, IRQ4, IRQ3, IRQ2 (gee, wonder what they would do? :-) ) - -S1 and S2 perform the same function as on the PC270, only their numbers -are swapped (S1 is the nodeaddress, S2 sets IO- and RAM-address). - -I know it works when connected to a PC110 type ARCnet board. - - -***************************************************************************** - -Possibly SMC -============ - -LCS-8830(-T) (8 and 16-bit cards) ---------------------------------- - - - from Mathias Katzer - - Marek Michalkiewicz says the - LCS-8830 is slightly different from LCS-8830-T. These are 8 bit, BUS - only (the JP0 jumper is hardwired), and BNC only. - -This is a LCS-8830-T made by SMC, I think ('SMC' only appears on one PLCC, -nowhere else, not even on the few Xeroxed sheets from the manual). - -SMC ARCnet Board Type LCS-8830-T:: - - ------------------------------------ - | | - | JP3 88 8 JP2 | - | ##### | \ | - | ##### ET1 ET2 ###| - | 8 ###| - | U3 SW 1 JP0 ###| Phone Jacks - | -- ###| - | | | | - | | | SW2 | - | | | | - | | | ##### | - | -- ##### #### BNC Connector - | #### - | 888888 JP1 | - | 234567 | - -- ------- - ||||||||||||||||||||||||||| - -------------------------- - - - SW1: DIP-Switches for Station Address - SW2: DIP-Switches for Memory Base and I/O Base addresses - - JP0: If closed, internal termination on (default open) - JP1: IRQ Jumpers - JP2: Boot-ROM enabled if closed - JP3: Jumpers for response timeout - - U3: Boot-ROM Socket - - - ET1 ET2 Response Time Idle Time Reconfiguration Time - - 78 86 840 - X 285 316 1680 - X 563 624 1680 - X X 1130 1237 1680 - - (X means closed jumper) - - (DIP-Switch downwards means "0") - -The station address is binary-coded with SW1. - -The I/O base address is coded with DIP-Switches 6,7 and 8 of SW2: - -======== ======== -Switches Base -678 Address -======== ======== -000 260-26f -100 290-29f -010 2e0-2ef -110 2f0-2ff -001 300-30f -101 350-35f -011 380-38f -111 3e0-3ef -======== ======== - - -DIP Switches 1-5 of SW2 encode the RAM and ROM Address Range: - -======== ============= ================ -Switches RAM ROM -12345 Address Range Address Range -======== ============= ================ -00000 C:0000-C:07ff C:2000-C:3fff -10000 C:0800-C:0fff -01000 C:1000-C:17ff -11000 C:1800-C:1fff -00100 C:4000-C:47ff C:6000-C:7fff -10100 C:4800-C:4fff -01100 C:5000-C:57ff -11100 C:5800-C:5fff -00010 C:C000-C:C7ff C:E000-C:ffff -10010 C:C800-C:Cfff -01010 C:D000-C:D7ff -11010 C:D800-C:Dfff -00110 D:0000-D:07ff D:2000-D:3fff -10110 D:0800-D:0fff -01110 D:1000-D:17ff -11110 D:1800-D:1fff -00001 D:4000-D:47ff D:6000-D:7fff -10001 D:4800-D:4fff -01001 D:5000-D:57ff -11001 D:5800-D:5fff -00101 D:8000-D:87ff D:A000-D:bfff -10101 D:8800-D:8fff -01101 D:9000-D:97ff -11101 D:9800-D:9fff -00011 D:C000-D:c7ff D:E000-D:ffff -10011 D:C800-D:cfff -01011 D:D000-D:d7ff -11011 D:D800-D:dfff -00111 E:0000-E:07ff E:2000-E:3fff -10111 E:0800-E:0fff -01111 E:1000-E:17ff -11111 E:1800-E:1fff -======== ============= ================ - - -PureData Corp -============= - -PDI507 (8-bit card) --------------------- - - - from Mark Rejhon (slight modifications by Avery) - - Avery's note: I think PDI508 cards (but definitely NOT PDI508Plus cards) - are mostly the same as this. PDI508Plus cards appear to be mainly - software-configured. - -Jumpers: - - There is a jumper array at the bottom of the card, near the edge - connector. This array is labelled J1. They control the IRQs and - something else. Put only one jumper on the IRQ pins. - - ETS1, ETS2 are for timing on very long distance networks. See the - more general information near the top of this file. - - There is a J2 jumper on two pins. A jumper should be put on them, - since it was already there when I got the card. I don't know what - this jumper is for though. - - There is a two-jumper array for J3. I don't know what it is for, - but there were already two jumpers on it when I got the card. It's - a six pin grid in a two-by-three fashion. The jumpers were - configured as follows:: - - .-------. - o | o o | - :-------: ------> Accessible end of card with connectors - o | o o | in this direction -------> - `-------' - -Carl de Billy explains J3 and J4: - - J3 Diagram:: - - .-------. - o | o o | - :-------: TWIST Technology - o | o o | - `-------' - .-------. - | o o | o - :-------: COAX Technology - | o o | o - `-------' - - - If using coax cable in a bus topology the J4 jumper must be removed; - place it on one pin. - - - If using bus topology with twisted pair wiring move the J3 - jumpers so they connect the middle pin and the pins closest to the RJ11 - Connectors. Also the J4 jumper must be removed; place it on one pin of - J4 jumper for storage. - - - If using star topology with twisted pair wiring move the J3 - jumpers so they connect the middle pin and the pins closest to the RJ11 - connectors. - - -DIP Switches: - - The DIP switches accessible on the accessible end of the card while - it is installed, is used to set the ARCnet address. There are 8 - switches. Use an address from 1 to 254 - - ========== ========================= - Switch No. ARCnet address - 12345678 - ========== ========================= - 00000000 FF (Don't use this!) - 00000001 FE - 00000010 FD - ... - 11111101 2 - 11111110 1 - 11111111 0 (Don't use this!) - ========== ========================= - - There is another array of eight DIP switches at the top of the - card. There are five labelled MS0-MS4 which seem to control the - memory address, and another three labelled IO0-IO2 which seem to - control the base I/O address of the card. - - This was difficult to test by trial and error, and the I/O addresses - are in a weird order. This was tested by setting the DIP switches, - rebooting the computer, and attempting to load ARCETHER at various - addresses (mostly between 0x200 and 0x400). The address that caused - the red transmit LED to blink, is the one that I thought works. - - Also, the address 0x3D0 seem to have a special meaning, since the - ARCETHER packet driver loaded fine, but without the red LED - blinking. I don't know what 0x3D0 is for though. I recommend using - an address of 0x300 since Windows may not like addresses below - 0x300. - - ============= =========== - IO Switch No. I/O address - 210 - ============= =========== - 111 0x260 - 110 0x290 - 101 0x2E0 - 100 0x2F0 - 011 0x300 - 010 0x350 - 001 0x380 - 000 0x3E0 - ============= =========== - - The memory switches set a reserved address space of 0x1000 bytes - (0x100 segment units, or 4k). For example if I set an address of - 0xD000, it will use up addresses 0xD000 to 0xD100. - - The memory switches were tested by booting using QEMM386 stealth, - and using LOADHI to see what address automatically became excluded - from the upper memory regions, and then attempting to load ARCETHER - using these addresses. - - I recommend using an ARCnet memory address of 0xD000, and putting - the EMS page frame at 0xC000 while using QEMM stealth mode. That - way, you get contiguous high memory from 0xD100 almost all the way - the end of the megabyte. - - Memory Switch 0 (MS0) didn't seem to work properly when set to OFF - on my card. It could be malfunctioning on my card. Experiment with - it ON first, and if it doesn't work, set it to OFF. (It may be a - modifier for the 0x200 bit?) - - ============= ============================================ - MS Switch No. - 43210 Memory address - ============= ============================================ - 00001 0xE100 (guessed - was not detected by QEMM) - 00011 0xE000 (guessed - was not detected by QEMM) - 00101 0xDD00 - 00111 0xDC00 - 01001 0xD900 - 01011 0xD800 - 01101 0xD500 - 01111 0xD400 - 10001 0xD100 - 10011 0xD000 - 10101 0xCD00 - 10111 0xCC00 - 11001 0xC900 (guessed - crashes tested system) - 11011 0xC800 (guessed - crashes tested system) - 11101 0xC500 (guessed - crashes tested system) - 11111 0xC400 (guessed - crashes tested system) - ============= ============================================ - -CNet Technology Inc. (8-bit cards) -================================== - -120 Series (8-bit cards) ------------------------- - - from Juergen Seifert - -This description has been written by Juergen Seifert -using information from the following Original CNet Manual - - "ARCNET USER'S MANUAL for - CN120A - CN120AB - CN120TP - CN120ST - CN120SBT - P/N:12-01-0007 - Revision 3.00" - -ARCNET is a registered trademark of the Datapoint Corporation - -- P/N 120A ARCNET 8 bit XT/AT Star -- P/N 120AB ARCNET 8 bit XT/AT Bus -- P/N 120TP ARCNET 8 bit XT/AT Twisted Pair -- P/N 120ST ARCNET 8 bit XT/AT Star, Twisted Pair -- P/N 120SBT ARCNET 8 bit XT/AT Star, Bus, Twisted Pair - -:: - - __________________________________________________________________ - | | - | ___| - | LED |___| - | ___| - | N | | ID7 - | o | | ID6 - | d | S | ID5 - | e | W | ID4 - | ___________________ A | 2 | ID3 - | | | d | | ID2 - | | | 1 2 3 4 5 6 7 8 d | | ID1 - | | | _________________ r |___| ID0 - | | 90C65 || SW1 | ____| - | JP 8 7 | ||_________________| | | - | |o|o| JP1 | | | J2 | - | |o|o| |oo| | | JP 1 1 1 | | - | ______________ | | 0 1 2 |____| - | | PROM | |___________________| |o|o|o| _____| - | > SOCKET | JP 6 5 4 3 2 |o|o|o| | J1 | - | |______________| |o|o|o|o|o| |o|o|o| |_____| - |_____ |o|o|o|o|o| ______________| - | | - |_____________________________________________| - -Legend:: - - 90C65 ARCNET Probe - S1 1-5: Base Memory Address Select - 6-8: Base I/O Address Select - S2 1-8: Node ID Select (ID0-ID7) - JP1 ROM Enable Select - JP2 IRQ2 - JP3 IRQ3 - JP4 IRQ4 - JP5 IRQ5 - JP6 IRQ7 - JP7/JP8 ET1, ET2 Timeout Parameters - JP10/JP11 Coax / Twisted Pair Select (CN120ST/SBT only) - JP12 Terminator Select (CN120AB/ST/SBT only) - J1 BNC RG62/U Connector (all except CN120TP) - J2 Two 6-position Telephone Jack (CN120TP/ST/SBT only) - -Setting one of the switches to Off means "1", On means "0". - - -Setting the Node ID -^^^^^^^^^^^^^^^^^^^ - -The eight switches in SW2 are used to set the node ID. Each node attached -to the network must have an unique node ID which must be different from 0. -Switch 1 (ID0) serves as the least significant bit (LSB). - -The node ID is the sum of the values of all switches set to "1" -These values are: - - ======= ====== ===== - Switch Label Value - ======= ====== ===== - 1 ID0 1 - 2 ID1 2 - 3 ID2 4 - 4 ID3 8 - 5 ID4 16 - 6 ID5 32 - 7 ID6 64 - 8 ID7 128 - ======= ====== ===== - -Some Examples:: - - Switch | Hex | Decimal - 8 7 6 5 4 3 2 1 | Node ID | Node ID - ----------------|---------|--------- - 0 0 0 0 0 0 0 0 | not allowed - 0 0 0 0 0 0 0 1 | 1 | 1 - 0 0 0 0 0 0 1 0 | 2 | 2 - 0 0 0 0 0 0 1 1 | 3 | 3 - . . . | | - 0 1 0 1 0 1 0 1 | 55 | 85 - . . . | | - 1 0 1 0 1 0 1 0 | AA | 170 - . . . | | - 1 1 1 1 1 1 0 1 | FD | 253 - 1 1 1 1 1 1 1 0 | FE | 254 - 1 1 1 1 1 1 1 1 | FF | 255 - - -Setting the I/O Base Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The last three switches in switch block SW1 are used to select one -of eight possible I/O Base addresses using the following table:: - - - Switch | Hex I/O - 6 7 8 | Address - ------------|-------- - ON ON ON | 260 - OFF ON ON | 290 - ON OFF ON | 2E0 (Manufacturer's default) - OFF OFF ON | 2F0 - ON ON OFF | 300 - OFF ON OFF | 350 - ON OFF OFF | 380 - OFF OFF OFF | 3E0 - - -Setting the Base Memory (RAM) buffer Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The memory buffer (RAM) requires 2K. The base of this buffer can be -located in any of eight positions. The address of the Boot Prom is -memory base + 8K or memory base + 0x2000. -Switches 1-5 of switch block SW1 select the Memory Base address. - -:: - - Switch | Hex RAM | Hex ROM - 1 2 3 4 5 | Address | Address *) - --------------------|---------|----------- - ON ON ON ON ON | C0000 | C2000 - ON ON OFF ON ON | C4000 | C6000 - ON ON ON OFF ON | CC000 | CE000 - ON ON OFF OFF ON | D0000 | D2000 (Manufacturer's default) - ON ON ON ON OFF | D4000 | D6000 - ON ON OFF ON OFF | D8000 | DA000 - ON ON ON OFF OFF | DC000 | DE000 - ON ON OFF OFF OFF | E0000 | E2000 - - *) To enable the Boot ROM install the jumper JP1 - -.. note:: - - Since the switches 1 and 2 are always set to ON it may be possible - that they can be used to add an offset of 2K, 4K or 6K to the base - address, but this feature is not documented in the manual and I - haven't tested it yet. - - -Setting the Interrupt Line -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -To select a hardware interrupt level install one (only one!) of the jumpers -JP2, JP3, JP4, JP5, JP6. JP2 is the default:: - - Jumper | IRQ - -------|----- - 2 | 2 - 3 | 3 - 4 | 4 - 5 | 5 - 6 | 7 - - -Setting the Internal Terminator on CN120AB/TP/SBT -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The jumper JP12 is used to enable the internal terminator:: - - ----- - 0 | 0 | - ----- ON | | ON - | 0 | | 0 | - | | OFF ----- OFF - | 0 | 0 - ----- - Terminator Terminator - disabled enabled - - -Selecting the Connector Type on CN120ST/SBT -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -:: - - JP10 JP11 JP10 JP11 - ----- ----- - 0 0 | 0 | | 0 | - ----- ----- | | | | - | 0 | | 0 | | 0 | | 0 | - | | | | ----- ----- - | 0 | | 0 | 0 0 - ----- ----- - Coaxial Cable Twisted Pair Cable - (Default) - - -Setting the Timeout Parameters -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The jumpers labeled EXT1 and EXT2 are used to determine the timeout -parameters. These two jumpers are normally left open. - - -CNet Technology Inc. (16-bit cards) -=================================== - -160 Series (16-bit cards) -------------------------- - - from Juergen Seifert - -This description has been written by Juergen Seifert -using information from the following Original CNet Manual - - "ARCNET USER'S MANUAL for - CN160A CN160AB CN160TP - P/N:12-01-0006 Revision 3.00" - -ARCNET is a registered trademark of the Datapoint Corporation - -- P/N 160A ARCNET 16 bit XT/AT Star -- P/N 160AB ARCNET 16 bit XT/AT Bus -- P/N 160TP ARCNET 16 bit XT/AT Twisted Pair - -:: - - ___________________________________________________________________ - < _________________________ ___| - > |oo| JP2 | | LED |___| - < |oo| JP1 | 9026 | LED |___| - > |_________________________| ___| - < N | | ID7 - > 1 o | | ID6 - < 1 2 3 4 5 6 7 8 9 0 d | S | ID5 - > _______________ _____________________ e | W | ID4 - < | PROM | | SW1 | A | 2 | ID3 - > > SOCKET | |_____________________| d | | ID2 - < |_______________| | IO-Base | MEM | d | | ID1 - > r |___| ID0 - < ____| - > | | - < | J1 | - > | | - < |____| - > 1 1 1 1 | - < 3 4 5 6 7 JP 8 9 0 1 2 3 | - > |o|o|o|o|o| |o|o|o|o|o|o| | - < |o|o|o|o|o| __ |o|o|o|o|o|o| ___________| - > | | | - <____________| |_______________________________________| - -Legend:: - - 9026 ARCNET Probe - SW1 1-6: Base I/O Address Select - 7-10: Base Memory Address Select - SW2 1-8: Node ID Select (ID0-ID7) - JP1/JP2 ET1, ET2 Timeout Parameters - JP3-JP13 Interrupt Select - J1 BNC RG62/U Connector (CN160A/AB only) - J1 Two 6-position Telephone Jack (CN160TP only) - LED - -Setting one of the switches to Off means "1", On means "0". - - -Setting the Node ID -^^^^^^^^^^^^^^^^^^^ - -The eight switches in SW2 are used to set the node ID. Each node attached -to the network must have an unique node ID which must be different from 0. -Switch 1 (ID0) serves as the least significant bit (LSB). - -The node ID is the sum of the values of all switches set to "1" -These values are:: - - Switch | Label | Value - -------|-------|------- - 1 | ID0 | 1 - 2 | ID1 | 2 - 3 | ID2 | 4 - 4 | ID3 | 8 - 5 | ID4 | 16 - 6 | ID5 | 32 - 7 | ID6 | 64 - 8 | ID7 | 128 - -Some Examples:: - - Switch | Hex | Decimal - 8 7 6 5 4 3 2 1 | Node ID | Node ID - ----------------|---------|--------- - 0 0 0 0 0 0 0 0 | not allowed - 0 0 0 0 0 0 0 1 | 1 | 1 - 0 0 0 0 0 0 1 0 | 2 | 2 - 0 0 0 0 0 0 1 1 | 3 | 3 - . . . | | - 0 1 0 1 0 1 0 1 | 55 | 85 - . . . | | - 1 0 1 0 1 0 1 0 | AA | 170 - . . . | | - 1 1 1 1 1 1 0 1 | FD | 253 - 1 1 1 1 1 1 1 0 | FE | 254 - 1 1 1 1 1 1 1 1 | FF | 255 - - -Setting the I/O Base Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The first six switches in switch block SW1 are used to select the I/O Base -address using the following table:: - - Switch | Hex I/O - 1 2 3 4 5 6 | Address - ------------------------|-------- - OFF ON ON OFF OFF ON | 260 - OFF ON OFF ON ON OFF | 290 - OFF ON OFF OFF OFF ON | 2E0 (Manufacturer's default) - OFF ON OFF OFF OFF OFF | 2F0 - OFF OFF ON ON ON ON | 300 - OFF OFF ON OFF ON OFF | 350 - OFF OFF OFF ON ON ON | 380 - OFF OFF OFF OFF OFF ON | 3E0 - -Note: Other IO-Base addresses seem to be selectable, but only the above - combinations are documented. - - -Setting the Base Memory (RAM) buffer Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The switches 7-10 of switch block SW1 are used to select the Memory -Base address of the RAM (2K) and the PROM:: - - Switch | Hex RAM | Hex ROM - 7 8 9 10 | Address | Address - ----------------|---------|----------- - OFF OFF ON ON | C0000 | C8000 - OFF OFF ON OFF | D0000 | D8000 (Default) - OFF OFF OFF ON | E0000 | E8000 - -.. note:: - - Other MEM-Base addresses seem to be selectable, but only the above - combinations are documented. - - -Setting the Interrupt Line -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -To select a hardware interrupt level install one (only one!) of the jumpers -JP3 through JP13 using the following table:: - - Jumper | IRQ - -------|----------------- - 3 | 14 - 4 | 15 - 5 | 12 - 6 | 11 - 7 | 10 - 8 | 3 - 9 | 4 - 10 | 5 - 11 | 6 - 12 | 7 - 13 | 2 (=9) Default! - -.. note:: - - - Do not use JP11=IRQ6, it may conflict with your Floppy Disk - Controller - - Use JP3=IRQ14 only, if you don't have an IDE-, MFM-, or RLL- - Hard Disk, it may conflict with their controllers - - -Setting the Timeout Parameters ------------------------------- - -The jumpers labeled JP1 and JP2 are used to determine the timeout -parameters. These two jumpers are normally left open. - - -Lantech -======= - -8-bit card, unknown model -------------------------- - - from Vlad Lungu - his e-mail address seemed broken at - the time I tried to reach him. Sorry Vlad, if you didn't get my reply. - -:: - - ________________________________________________________________ - | 1 8 | - | ___________ __| - | | SW1 | LED |__| - | |__________| | - | ___| - | _____________________ |S | 8 - | | | |W | - | | | |2 | - | | | |__| 1 - | | UM9065L | |o| JP4 ____|____ - | | | |o| | CN | - | | | |________| - | | | | - | |___________________| | - | | - | | - | _____________ | - | | | | - | | PROM | |ooooo| JP6 | - | |____________| |ooooo| | - |_____________ _ _| - |____________________________________________| |__| - - -UM9065L : ARCnet Controller - -SW 1 : Shared Memory Address and I/O Base - -:: - - ON=0 - - 12345|Memory Address - -----|-------------- - 00001| D4000 - 00010| CC000 - 00110| D0000 - 01110| D1000 - 01101| D9000 - 10010| CC800 - 10011| DC800 - 11110| D1800 - -It seems that the bits are considered in reverse order. Also, you must -observe that some of those addresses are unusual and I didn't probe them; I -used a memory dump in DOS to identify them. For the 00000 configuration and -some others that I didn't write here the card seems to conflict with the -video card (an S3 GENDAC). I leave the full decoding of those addresses to -you. - -:: - - 678| I/O Address - ---|------------ - 000| 260 - 001| failed probe - 010| 2E0 - 011| 380 - 100| 290 - 101| 350 - 110| failed probe - 111| 3E0 - - SW 2 : Node ID (binary coded) - - JP 4 : Boot PROM enable CLOSE - enabled - OPEN - disabled - - JP 6 : IRQ set (ONLY ONE jumper on 1-5 for IRQ 2-6) - - -Acer -==== - -8-bit card, Model 5210-003 --------------------------- - - - from Vojtech Pavlik using portions of the existing - arcnet-hardware file. - -This is a 90C26 based card. Its configuration seems similar to the SMC -PC100, but has some additional jumpers I don't know the meaning of. - -:: - - __ - | | - ___________|__|_________________________ - | | | | - | | BNC | | - | |______| ___| - | _____________________ |___ - | | | | - | | Hybrid IC | | - | | | o|o J1 | - | |_____________________| 8|8 | - | 8|8 J5 | - | o|o | - | 8|8 | - |__ 8|8 | - (|__| LED o|o | - | 8|8 | - | 8|8 J15 | - | | - | _____ | - | | | _____ | - | | | | | ___| - | | | | | | - | _____ | ROM | | UFS | | - | | | | | | | | - | | | ___ | | | | | - | | | | | |__.__| |__.__| | - | | NCR | |XTL| _____ _____ | - | | | |___| | | | | | - | |90C26| | | | | | - | | | | RAM | | UFS | | - | | | J17 o|o | | | | | - | | | J16 o|o | | | | | - | |__.__| |__.__| |__.__| | - | ___ | - | | |8 | - | |SW2| | - | | | | - | |___|1 | - | ___ | - | | |10 J18 o|o | - | | | o|o | - | |SW1| o|o | - | | | J21 o|o | - | |___|1 | - | | - |____________________________________| - - -Legend:: - - 90C26 ARCNET Chip - XTL 20 MHz Crystal - SW1 1-6 Base I/O Address Select - 7-10 Memory Address Select - SW2 1-8 Node ID Select (ID0-ID7) - J1-J5 IRQ Select - J6-J21 Unknown (Probably extra timeouts & ROM enable ...) - LED1 Activity LED - BNC Coax connector (STAR ARCnet) - RAM 2k of SRAM - ROM Boot ROM socket - UFS Unidentified Flying Sockets - - -Setting the Node ID -^^^^^^^^^^^^^^^^^^^ - -The eight switches in SW2 are used to set the node ID. Each node attached -to the network must have an unique node ID which must not be 0. -Switch 1 (ID0) serves as the least significant bit (LSB). - -Setting one of the switches to OFF means "1", ON means "0". - -The node ID is the sum of the values of all switches set to "1" -These values are:: - - Switch | Value - -------|------- - 1 | 1 - 2 | 2 - 3 | 4 - 4 | 8 - 5 | 16 - 6 | 32 - 7 | 64 - 8 | 128 - -Don't set this to 0 or 255; these values are reserved. - - -Setting the I/O Base Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The switches 1 to 6 of switch block SW1 are used to select one -of 32 possible I/O Base addresses using the following tables:: - - | Hex - Switch | Value - -------|------- - 1 | 200 - 2 | 100 - 3 | 80 - 4 | 40 - 5 | 20 - 6 | 10 - -The I/O address is sum of all switches set to "1". Remember that -the I/O address space below 0x200 is RESERVED for mainboard, so -switch 1 should be ALWAYS SET TO OFF. - - -Setting the Base Memory (RAM) buffer Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The memory buffer (RAM) requires 2K. The base of this buffer can be -located in any of sixteen positions. However, the addresses below -A0000 are likely to cause system hang because there's main RAM. - -Jumpers 7-10 of switch block SW1 select the Memory Base address:: - - Switch | Hex RAM - 7 8 9 10 | Address - ----------------|--------- - OFF OFF OFF OFF | F0000 (conflicts with main BIOS) - OFF OFF OFF ON | E0000 - OFF OFF ON OFF | D0000 - OFF OFF ON ON | C0000 (conflicts with video BIOS) - OFF ON OFF OFF | B0000 (conflicts with mono video) - OFF ON OFF ON | A0000 (conflicts with graphics) - - -Setting the Interrupt Line -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Jumpers 1-5 of the jumper block J1 control the IRQ level. ON means -shorted, OFF means open:: - - Jumper | IRQ - 1 2 3 4 5 | - ---------------------------- - ON OFF OFF OFF OFF | 7 - OFF ON OFF OFF OFF | 5 - OFF OFF ON OFF OFF | 4 - OFF OFF OFF ON OFF | 3 - OFF OFF OFF OFF ON | 2 - - -Unknown jumpers & sockets -^^^^^^^^^^^^^^^^^^^^^^^^^ - -I know nothing about these. I just guess that J16&J17 are timeout -jumpers and maybe one of J18-J21 selects ROM. Also J6-J10 and -J11-J15 are connecting IRQ2-7 to some pins on the UFSs. I can't -guess the purpose. - -Datapoint? -========== - -LAN-ARC-8, an 8-bit card ------------------------- - - - from Vojtech Pavlik - -This is another SMC 90C65-based ARCnet card. I couldn't identify the -manufacturer, but it might be DataPoint, because the card has the -original arcNet logo in its upper right corner. - -:: - - _______________________________________________________ - | _________ | - | | SW2 | ON arcNet | - | |_________| OFF ___| - | _____________ 1 ______ 8 | | 8 - | | | SW1 | XTAL | ____________ | S | - | > RAM (2k) | |______|| | | W | - | |_____________| | H | | 3 | - | _________|_____ y | |___| 1 - | _________ | | |b | | - | |_________| | | |r | | - | | SMC | |i | | - | | 90C65| |d | | - | _________ | | | | | - | | SW1 | ON | | |I | | - | |_________| OFF |_________|_____/C | _____| - | 1 8 | | | |___ - | ______________ | | | BNC |___| - | | | |____________| |_____| - | > EPROM SOCKET | _____________ | - | |______________| |_____________| | - | ______________| - | | - |________________________________________| - -Legend:: - - 90C65 ARCNET Chip - SW1 1-5: Base Memory Address Select - 6-8: Base I/O Address Select - SW2 1-8: Node ID Select - SW3 1-5: IRQ Select - 6-7: Extra Timeout - 8 : ROM Enable - BNC Coax connector - XTAL 20 MHz Crystal - - -Setting the Node ID -^^^^^^^^^^^^^^^^^^^ - -The eight switches in SW3 are used to set the node ID. Each node attached -to the network must have an unique node ID which must not be 0. -Switch 1 serves as the least significant bit (LSB). - -Setting one of the switches to Off means "1", On means "0". - -The node ID is the sum of the values of all switches set to "1" -These values are:: - - Switch | Value - -------|------- - 1 | 1 - 2 | 2 - 3 | 4 - 4 | 8 - 5 | 16 - 6 | 32 - 7 | 64 - 8 | 128 - - -Setting the I/O Base Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The last three switches in switch block SW1 are used to select one -of eight possible I/O Base addresses using the following table:: - - - Switch | Hex I/O - 6 7 8 | Address - ------------|-------- - ON ON ON | 260 - OFF ON ON | 290 - ON OFF ON | 2E0 (Manufacturer's default) - OFF OFF ON | 2F0 - ON ON OFF | 300 - OFF ON OFF | 350 - ON OFF OFF | 380 - OFF OFF OFF | 3E0 - - -Setting the Base Memory (RAM) buffer Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The memory buffer (RAM) requires 2K. The base of this buffer can be -located in any of eight positions. The address of the Boot Prom is -memory base + 0x2000. - -Jumpers 3-5 of switch block SW1 select the Memory Base address. - -:: - - Switch | Hex RAM | Hex ROM - 1 2 3 4 5 | Address | Address *) - --------------------|---------|----------- - ON ON ON ON ON | C0000 | C2000 - ON ON OFF ON ON | C4000 | C6000 - ON ON ON OFF ON | CC000 | CE000 - ON ON OFF OFF ON | D0000 | D2000 (Manufacturer's default) - ON ON ON ON OFF | D4000 | D6000 - ON ON OFF ON OFF | D8000 | DA000 - ON ON ON OFF OFF | DC000 | DE000 - ON ON OFF OFF OFF | E0000 | E2000 - - *) To enable the Boot ROM set the switch 8 of switch block SW3 to position ON. - -The switches 1 and 2 probably add 0x0800 and 0x1000 to RAM base address. - - -Setting the Interrupt Line -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Switches 1-5 of the switch block SW3 control the IRQ level:: - - Jumper | IRQ - 1 2 3 4 5 | - ---------------------------- - ON OFF OFF OFF OFF | 3 - OFF ON OFF OFF OFF | 4 - OFF OFF ON OFF OFF | 5 - OFF OFF OFF ON OFF | 7 - OFF OFF OFF OFF ON | 2 - - -Setting the Timeout Parameters -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The switches 6-7 of the switch block SW3 are used to determine the timeout -parameters. These two switches are normally left in the OFF position. - - -Topware -======= - -8-bit card, TA-ARC/10 ---------------------- - - - from Vojtech Pavlik - -This is another very similar 90C65 card. Most of the switches and jumpers -are the same as on other clones. - -:: - - _____________________________________________________________________ - | ___________ | | ______ | - | |SW2 NODE ID| | | | XTAL | | - | |___________| | Hybrid IC | |______| | - | ___________ | | __| - | |SW1 MEM+I/O| |_________________________| LED1|__|) - | |___________| 1 2 | - | J3 |o|o| TIMEOUT ______| - | ______________ |o|o| | | - | | | ___________________ | RJ | - | > EPROM SOCKET | | \ |------| - |J2 |______________| | | | | - ||o| | | |______| - ||o| ROM ENABLE | SMC | _________ | - | _____________ | 90C65 | |_________| _____| - | | | | | | |___ - | > RAM (2k) | | | | BNC |___| - | |_____________| | | |_____| - | |____________________| | - | ________ IRQ 2 3 4 5 7 ___________ | - ||________| |o|o|o|o|o| |___________| | - |________ J1|o|o|o|o|o| ______________| - | | - |_____________________________________________| - -Legend:: - - 90C65 ARCNET Chip - XTAL 20 MHz Crystal - SW1 1-5 Base Memory Address Select - 6-8 Base I/O Address Select - SW2 1-8 Node ID Select (ID0-ID7) - J1 IRQ Select - J2 ROM Enable - J3 Extra Timeout - LED1 Activity LED - BNC Coax connector (BUS ARCnet) - RJ Twisted Pair Connector (daisy chain) - - -Setting the Node ID -^^^^^^^^^^^^^^^^^^^ - -The eight switches in SW2 are used to set the node ID. Each node attached to -the network must have an unique node ID which must not be 0. Switch 1 (ID0) -serves as the least significant bit (LSB). - -Setting one of the switches to Off means "1", On means "0". - -The node ID is the sum of the values of all switches set to "1" -These values are:: - - Switch | Label | Value - -------|-------|------- - 1 | ID0 | 1 - 2 | ID1 | 2 - 3 | ID2 | 4 - 4 | ID3 | 8 - 5 | ID4 | 16 - 6 | ID5 | 32 - 7 | ID6 | 64 - 8 | ID7 | 128 - -Setting the I/O Base Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The last three switches in switch block SW1 are used to select one -of eight possible I/O Base addresses using the following table:: - - - Switch | Hex I/O - 6 7 8 | Address - ------------|-------- - ON ON ON | 260 (Manufacturer's default) - OFF ON ON | 290 - ON OFF ON | 2E0 - OFF OFF ON | 2F0 - ON ON OFF | 300 - OFF ON OFF | 350 - ON OFF OFF | 380 - OFF OFF OFF | 3E0 - - -Setting the Base Memory (RAM) buffer Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The memory buffer (RAM) requires 2K. The base of this buffer can be -located in any of eight positions. The address of the Boot Prom is -memory base + 0x2000. - -Jumpers 3-5 of switch block SW1 select the Memory Base address. - -:: - - Switch | Hex RAM | Hex ROM - 1 2 3 4 5 | Address | Address *) - --------------------|---------|----------- - ON ON ON ON ON | C0000 | C2000 - ON ON OFF ON ON | C4000 | C6000 (Manufacturer's default) - ON ON ON OFF ON | CC000 | CE000 - ON ON OFF OFF ON | D0000 | D2000 - ON ON ON ON OFF | D4000 | D6000 - ON ON OFF ON OFF | D8000 | DA000 - ON ON ON OFF OFF | DC000 | DE000 - ON ON OFF OFF OFF | E0000 | E2000 - - *) To enable the Boot ROM short the jumper J2. - -The jumpers 1 and 2 probably add 0x0800 and 0x1000 to RAM address. - - -Setting the Interrupt Line -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Jumpers 1-5 of the jumper block J1 control the IRQ level. ON means -shorted, OFF means open:: - - Jumper | IRQ - 1 2 3 4 5 | - ---------------------------- - ON OFF OFF OFF OFF | 2 - OFF ON OFF OFF OFF | 3 - OFF OFF ON OFF OFF | 4 - OFF OFF OFF ON OFF | 5 - OFF OFF OFF OFF ON | 7 - - -Setting the Timeout Parameters -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The jumpers J3 are used to set the timeout parameters. These two -jumpers are normally left open. - -Thomas-Conrad -============= - -Model #500-6242-0097 REV A (8-bit card) ---------------------------------------- - - - from Lars Karlsson <100617.3473@compuserve.com> - -:: - - ________________________________________________________ - | ________ ________ |_____ - | |........| |........| | - | |________| |________| ___| - | SW 3 SW 1 | | - | Base I/O Base Addr. Station | | - | address | | - | ______ switch | | - | | | | | - | | | |___| - | | | ______ |___._ - | |______| |______| ____| BNC - | Jumper- _____| Connector - | Main chip block _ __| ' - | | | | RJ Connector - | |_| | with 110 Ohm - | |__ Terminator - | ___________ __| - | |...........| | RJ-jack - | |...........| _____ | (unused) - | |___________| |_____| |__ - | Boot PROM socket IRQ-jumpers |_ Diagnostic - |________ __ _| LED (red) - | | | | | | | | | | | | | | | | | | | | | | - | | | | | | | | | | | | | | | | | | | | |________| - | - | - -And here are the settings for some of the switches and jumpers on the cards. - -:: - - I/O - - 1 2 3 4 5 6 7 8 - - 2E0----- 0 0 0 1 0 0 0 1 - 2F0----- 0 0 0 1 0 0 0 0 - 300----- 0 0 0 0 1 1 1 1 - 350----- 0 0 0 0 1 1 1 0 - -"0" in the above example means switch is off "1" means that it is on. - -:: - - ShMem address. - - 1 2 3 4 5 6 7 8 - - CX00--0 0 1 1 | | | - DX00--0 0 1 0 | - X000--------- 1 1 | - X400--------- 1 0 | - X800--------- 0 1 | - XC00--------- 0 0 - ENHANCED----------- 1 - COMPATIBLE--------- 0 - -:: - - IRQ - - - 3 4 5 7 2 - . . . . . - . . . . . - - -There is a DIP-switch with 8 switches, used to set the shared memory address -to be used. The first 6 switches set the address, the 7th doesn't have any -function, and the 8th switch is used to select "compatible" or "enhanced". -When I got my two cards, one of them had this switch set to "enhanced". That -card didn't work at all, it wasn't even recognized by the driver. The other -card had this switch set to "compatible" and it behaved absolutely normally. I -guess that the switch on one of the cards, must have been changed accidentally -when the card was taken out of its former host. The question remains -unanswered, what is the purpose of the "enhanced" position? - -[Avery's note: "enhanced" probably either disables shared memory (use IO -ports instead) or disables IO ports (use memory addresses instead). This -varies by the type of card involved. I fail to see how either of these -enhance anything. Send me more detailed information about this mode, or -just use "compatible" mode instead.] - -Waterloo Microsystems Inc. ?? -============================= - -8-bit card (C) 1985 -------------------- - - from Robert Michael Best - -[Avery's note: these don't work with my driver for some reason. These cards -SEEM to have settings similar to the PDI508Plus, which is -software-configured and doesn't work with my driver either. The "Waterloo -chip" is a boot PROM, probably designed specifically for the University of -Waterloo. If you have any further information about this card, please -e-mail me.] - -The probe has not been able to detect the card on any of the J2 settings, -and I tried them again with the "Waterloo" chip removed. - -:: - - _____________________________________________________________________ - | \/ \/ ___ __ __ | - | C4 C4 |^| | M || ^ ||^| | - | -- -- |_| | 5 || || | C3 | - | \/ \/ C10 |___|| ||_| | - | C4 C4 _ _ | | ?? | - | -- -- | \/ || | | - | | || | | - | | || C1 | | - | | || | \/ _____| - | | C6 || | C9 | |___ - | | || | -- | BNC |___| - | | || | >C7| |_____| - | | || | | - | __ __ |____||_____| 1 2 3 6 | - || ^ | >C4| |o|o|o|o|o|o| J2 >C4| | - || | |o|o|o|o|o|o| | - || C2 | >C4| >C4| | - || | >C8| | - || | 2 3 4 5 6 7 IRQ >C4| | - ||_____| |o|o|o|o|o|o| J3 | - |_______ |o|o|o|o|o|o| _______________| - | | - |_____________________________________________| - - C1 -- "COM9026 - SMC 8638" - In a chip socket. - - C2 -- "@Copyright - Waterloo Microsystems Inc. - 1985" - In a chip Socket with info printed on a label covering a round window - showing the circuit inside. (The window indicates it is an EPROM chip.) - - C3 -- "COM9032 - SMC 8643" - In a chip socket. - - C4 -- "74LS" - 9 total no sockets. - - M5 -- "50006-136 - 20.000000 MHZ - MTQ-T1-S3 - 0 M-TRON 86-40" - Metallic case with 4 pins, no socket. - - C6 -- "MOSTEK@TC8643 - MK6116N-20 - MALAYSIA" - No socket. - - C7 -- No stamp or label but in a 20 pin chip socket. - - C8 -- "PAL10L8CN - 8623" - In a 20 pin socket. - - C9 -- "PAl16R4A-2CN - 8641" - In a 20 pin socket. - - C10 -- "M8640 - NMC - 9306N" - In an 8 pin socket. - - ?? -- Some components on a smaller board and attached with 20 pins all - along the side closest to the BNC connector. The are coated in a dark - resin. - -On the board there are two jumper banks labeled J2 and J3. The -manufacturer didn't put a J1 on the board. The two boards I have both -came with a jumper box for each bank. - -:: - - J2 -- Numbered 1 2 3 4 5 6. - 4 and 5 are not stamped due to solder points. - - J3 -- IRQ 2 3 4 5 6 7 - -The board itself has a maple leaf stamped just above the irq jumpers -and "-2 46-86" beside C2. Between C1 and C6 "ASS 'Y 300163" and "@1986 -CORMAN CUSTOM ELECTRONICS CORP." stamped just below the BNC connector. -Below that "MADE IN CANADA" - -No Name -======= - -8-bit cards, 16-bit cards -------------------------- - - - from Juergen Seifert - -I have named this ARCnet card "NONAME", since there is no name of any -manufacturer on the Installation manual nor on the shipping box. The only -hint to the existence of a manufacturer at all is written in copper, -it is "Made in Taiwan" - -This description has been written by Juergen Seifert -using information from the Original - - "ARCnet Installation Manual" - -:: - - ________________________________________________________________ - | |STAR| BUS| T/P| | - | |____|____|____| | - | _____________________ | - | | | | - | | | | - | | | | - | | SMC | | - | | | | - | | COM90C65 | | - | | | | - | | | | - | |__________-__________| | - | _____| - | _______________ | CN | - | | PROM | |_____| - | > SOCKET | | - | |_______________| 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 | - | _______________ _______________ | - | |o|o|o|o|o|o|o|o| | SW1 || SW2 || - | |o|o|o|o|o|o|o|o| |_______________||_______________|| - |___ 2 3 4 5 7 E E R Node ID IOB__|__MEM____| - | \ IRQ / T T O | - |__________________1_2_M______________________| - -Legend:: - - COM90C65: ARCnet Probe - S1 1-8: Node ID Select - S2 1-3: I/O Base Address Select - 4-6: Memory Base Address Select - 7-8: RAM Offset Select - ET1, ET2 Extended Timeout Select - ROM ROM Enable Select - CN RG62 Coax Connector - STAR| BUS | T/P Three fields for placing a sign (colored circle) - indicating the topology of the card - -Setting one of the switches to Off means "1", On means "0". - - -Setting the Node ID -^^^^^^^^^^^^^^^^^^^ - -The eight switches in group SW1 are used to set the node ID. -Each node attached to the network must have an unique node ID which -must be different from 0. -Switch 8 serves as the least significant bit (LSB). - -The node ID is the sum of the values of all switches set to "1" -These values are:: - - Switch | Value - -------|------- - 8 | 1 - 7 | 2 - 6 | 4 - 5 | 8 - 4 | 16 - 3 | 32 - 2 | 64 - 1 | 128 - -Some Examples:: - - Switch | Hex | Decimal - 1 2 3 4 5 6 7 8 | Node ID | Node ID - ----------------|---------|--------- - 0 0 0 0 0 0 0 0 | not allowed - 0 0 0 0 0 0 0 1 | 1 | 1 - 0 0 0 0 0 0 1 0 | 2 | 2 - 0 0 0 0 0 0 1 1 | 3 | 3 - . . . | | - 0 1 0 1 0 1 0 1 | 55 | 85 - . . . | | - 1 0 1 0 1 0 1 0 | AA | 170 - . . . | | - 1 1 1 1 1 1 0 1 | FD | 253 - 1 1 1 1 1 1 1 0 | FE | 254 - 1 1 1 1 1 1 1 1 | FF | 255 - - -Setting the I/O Base Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The first three switches in switch group SW2 are used to select one -of eight possible I/O Base addresses using the following table:: - - Switch | Hex I/O - 1 2 3 | Address - ------------|-------- - ON ON ON | 260 - ON ON OFF | 290 - ON OFF ON | 2E0 (Manufacturer's default) - ON OFF OFF | 2F0 - OFF ON ON | 300 - OFF ON OFF | 350 - OFF OFF ON | 380 - OFF OFF OFF | 3E0 - - -Setting the Base Memory (RAM) buffer Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The memory buffer requires 2K of a 16K block of RAM. The base of this -16K block can be located in any of eight positions. -Switches 4-6 of switch group SW2 select the Base of the 16K block. -Within that 16K address space, the buffer may be assigned any one of four -positions, determined by the offset, switches 7 and 8 of group SW2. - -:: - - Switch | Hex RAM | Hex ROM - 4 5 6 7 8 | Address | Address *) - -----------|---------|----------- - 0 0 0 0 0 | C0000 | C2000 - 0 0 0 0 1 | C0800 | C2000 - 0 0 0 1 0 | C1000 | C2000 - 0 0 0 1 1 | C1800 | C2000 - | | - 0 0 1 0 0 | C4000 | C6000 - 0 0 1 0 1 | C4800 | C6000 - 0 0 1 1 0 | C5000 | C6000 - 0 0 1 1 1 | C5800 | C6000 - | | - 0 1 0 0 0 | CC000 | CE000 - 0 1 0 0 1 | CC800 | CE000 - 0 1 0 1 0 | CD000 | CE000 - 0 1 0 1 1 | CD800 | CE000 - | | - 0 1 1 0 0 | D0000 | D2000 (Manufacturer's default) - 0 1 1 0 1 | D0800 | D2000 - 0 1 1 1 0 | D1000 | D2000 - 0 1 1 1 1 | D1800 | D2000 - | | - 1 0 0 0 0 | D4000 | D6000 - 1 0 0 0 1 | D4800 | D6000 - 1 0 0 1 0 | D5000 | D6000 - 1 0 0 1 1 | D5800 | D6000 - | | - 1 0 1 0 0 | D8000 | DA000 - 1 0 1 0 1 | D8800 | DA000 - 1 0 1 1 0 | D9000 | DA000 - 1 0 1 1 1 | D9800 | DA000 - | | - 1 1 0 0 0 | DC000 | DE000 - 1 1 0 0 1 | DC800 | DE000 - 1 1 0 1 0 | DD000 | DE000 - 1 1 0 1 1 | DD800 | DE000 - | | - 1 1 1 0 0 | E0000 | E2000 - 1 1 1 0 1 | E0800 | E2000 - 1 1 1 1 0 | E1000 | E2000 - 1 1 1 1 1 | E1800 | E2000 - - *) To enable the 8K Boot PROM install the jumper ROM. - The default is jumper ROM not installed. - - -Setting Interrupt Request Lines (IRQ) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -To select a hardware interrupt level set one (only one!) of the jumpers -IRQ2, IRQ3, IRQ4, IRQ5 or IRQ7. The manufacturer's default is IRQ2. - - -Setting the Timeouts -^^^^^^^^^^^^^^^^^^^^ - -The two jumpers labeled ET1 and ET2 are used to determine the timeout -parameters (response and reconfiguration time). Every node in a network -must be set to the same timeout values. - -:: - - ET1 ET2 | Response Time (us) | Reconfiguration Time (ms) - --------|--------------------|-------------------------- - Off Off | 78 | 840 (Default) - Off On | 285 | 1680 - On Off | 563 | 1680 - On On | 1130 | 1680 - -On means jumper installed, Off means jumper not installed - - -16-BIT ARCNET -------------- - -The manual of my 8-Bit NONAME ARCnet Card contains another description -of a 16-Bit Coax / Twisted Pair Card. This description is incomplete, -because there are missing two pages in the manual booklet. (The table -of contents reports pages ... 2-9, 2-11, 2-12, 3-1, ... but inside -the booklet there is a different way of counting ... 2-9, 2-10, A-1, -(empty page), 3-1, ..., 3-18, A-1 (again), A-2) -Also the picture of the board layout is not as good as the picture of -8-Bit card, because there isn't any letter like "SW1" written to the -picture. - -Should somebody have such a board, please feel free to complete this -description or to send a mail to me! - -This description has been written by Juergen Seifert -using information from the Original - - "ARCnet Installation Manual" - -:: - - ___________________________________________________________________ - < _________________ _________________ | - > | SW? || SW? | | - < |_________________||_________________| | - > ____________________ | - < | | | - > | | | - < | | | - > | | | - < | | | - > | | | - < | | | - > |____________________| | - < ____| - > ____________________ | | - < | | | J1 | - > | < | | - < |____________________| ? ? ? ? ? ? |____| - > |o|o|o|o|o|o| | - < |o|o|o|o|o|o| | - > | - < __ ___________| - > | | | - <____________| |_______________________________________| - - -Setting one of the switches to Off means "1", On means "0". - - -Setting the Node ID -^^^^^^^^^^^^^^^^^^^ - -The eight switches in group SW2 are used to set the node ID. -Each node attached to the network must have an unique node ID which -must be different from 0. -Switch 8 serves as the least significant bit (LSB). - -The node ID is the sum of the values of all switches set to "1" -These values are:: - - Switch | Value - -------|------- - 8 | 1 - 7 | 2 - 6 | 4 - 5 | 8 - 4 | 16 - 3 | 32 - 2 | 64 - 1 | 128 - -Some Examples:: - - Switch | Hex | Decimal - 1 2 3 4 5 6 7 8 | Node ID | Node ID - ----------------|---------|--------- - 0 0 0 0 0 0 0 0 | not allowed - 0 0 0 0 0 0 0 1 | 1 | 1 - 0 0 0 0 0 0 1 0 | 2 | 2 - 0 0 0 0 0 0 1 1 | 3 | 3 - . . . | | - 0 1 0 1 0 1 0 1 | 55 | 85 - . . . | | - 1 0 1 0 1 0 1 0 | AA | 170 - . . . | | - 1 1 1 1 1 1 0 1 | FD | 253 - 1 1 1 1 1 1 1 0 | FE | 254 - 1 1 1 1 1 1 1 1 | FF | 255 - - -Setting the I/O Base Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The first three switches in switch group SW1 are used to select one -of eight possible I/O Base addresses using the following table:: - - Switch | Hex I/O - 3 2 1 | Address - ------------|-------- - ON ON ON | 260 - ON ON OFF | 290 - ON OFF ON | 2E0 (Manufacturer's default) - ON OFF OFF | 2F0 - OFF ON ON | 300 - OFF ON OFF | 350 - OFF OFF ON | 380 - OFF OFF OFF | 3E0 - - -Setting the Base Memory (RAM) buffer Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The memory buffer requires 2K of a 16K block of RAM. The base of this -16K block can be located in any of eight positions. -Switches 6-8 of switch group SW1 select the Base of the 16K block. -Within that 16K address space, the buffer may be assigned any one of four -positions, determined by the offset, switches 4 and 5 of group SW1:: - - Switch | Hex RAM | Hex ROM - 8 7 6 5 4 | Address | Address - -----------|---------|----------- - 0 0 0 0 0 | C0000 | C2000 - 0 0 0 0 1 | C0800 | C2000 - 0 0 0 1 0 | C1000 | C2000 - 0 0 0 1 1 | C1800 | C2000 - | | - 0 0 1 0 0 | C4000 | C6000 - 0 0 1 0 1 | C4800 | C6000 - 0 0 1 1 0 | C5000 | C6000 - 0 0 1 1 1 | C5800 | C6000 - | | - 0 1 0 0 0 | CC000 | CE000 - 0 1 0 0 1 | CC800 | CE000 - 0 1 0 1 0 | CD000 | CE000 - 0 1 0 1 1 | CD800 | CE000 - | | - 0 1 1 0 0 | D0000 | D2000 (Manufacturer's default) - 0 1 1 0 1 | D0800 | D2000 - 0 1 1 1 0 | D1000 | D2000 - 0 1 1 1 1 | D1800 | D2000 - | | - 1 0 0 0 0 | D4000 | D6000 - 1 0 0 0 1 | D4800 | D6000 - 1 0 0 1 0 | D5000 | D6000 - 1 0 0 1 1 | D5800 | D6000 - | | - 1 0 1 0 0 | D8000 | DA000 - 1 0 1 0 1 | D8800 | DA000 - 1 0 1 1 0 | D9000 | DA000 - 1 0 1 1 1 | D9800 | DA000 - | | - 1 1 0 0 0 | DC000 | DE000 - 1 1 0 0 1 | DC800 | DE000 - 1 1 0 1 0 | DD000 | DE000 - 1 1 0 1 1 | DD800 | DE000 - | | - 1 1 1 0 0 | E0000 | E2000 - 1 1 1 0 1 | E0800 | E2000 - 1 1 1 1 0 | E1000 | E2000 - 1 1 1 1 1 | E1800 | E2000 - - -Setting Interrupt Request Lines (IRQ) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -?????????????????????????????????????? - - -Setting the Timeouts -^^^^^^^^^^^^^^^^^^^^ - -?????????????????????????????????????? - - -8-bit cards ("Made in Taiwan R.O.C.") -------------------------------------- - - - from Vojtech Pavlik - -I have named this ARCnet card "NONAME", since I got only the card with -no manual at all and the only text identifying the manufacturer is -"MADE IN TAIWAN R.O.C" printed on the card. - -:: - - ____________________________________________________________ - | 1 2 3 4 5 6 7 8 | - | |o|o| JP1 o|o|o|o|o|o|o|o| ON | - | + o|o|o|o|o|o|o|o| ___| - | _____________ o|o|o|o|o|o|o|o| OFF _____ | | ID7 - | | | SW1 | | | | ID6 - | > RAM (2k) | ____________________ | H | | S | ID5 - | |_____________| | || y | | W | ID4 - | | || b | | 2 | ID3 - | | || r | | | ID2 - | | || i | | | ID1 - | | 90C65 || d | |___| ID0 - | SW3 | || | | - | |o|o|o|o|o|o|o|o| ON | || I | | - | |o|o|o|o|o|o|o|o| | || C | | - | |o|o|o|o|o|o|o|o| OFF |____________________|| | _____| - | 1 2 3 4 5 6 7 8 | | | |___ - | ______________ | | | BNC |___| - | | | |_____| |_____| - | > EPROM SOCKET | | - | |______________| | - | ______________| - | | - |_____________________________________________| - -Legend:: - - 90C65 ARCNET Chip - SW1 1-5: Base Memory Address Select - 6-8: Base I/O Address Select - SW2 1-8: Node ID Select (ID0-ID7) - SW3 1-5: IRQ Select - 6-7: Extra Timeout - 8 : ROM Enable - JP1 Led connector - BNC Coax connector - -Although the jumpers SW1 and SW3 are marked SW, not JP, they are jumpers, not -switches. - -Setting the jumpers to ON means connecting the upper two pins, off the bottom -two - or - in case of IRQ setting, connecting none of them at all. - -Setting the Node ID -^^^^^^^^^^^^^^^^^^^ - -The eight switches in SW2 are used to set the node ID. Each node attached -to the network must have an unique node ID which must not be 0. -Switch 1 (ID0) serves as the least significant bit (LSB). - -Setting one of the switches to Off means "1", On means "0". - -The node ID is the sum of the values of all switches set to "1" -These values are:: - - Switch | Label | Value - -------|-------|------- - 1 | ID0 | 1 - 2 | ID1 | 2 - 3 | ID2 | 4 - 4 | ID3 | 8 - 5 | ID4 | 16 - 6 | ID5 | 32 - 7 | ID6 | 64 - 8 | ID7 | 128 - -Some Examples:: - - Switch | Hex | Decimal - 8 7 6 5 4 3 2 1 | Node ID | Node ID - ----------------|---------|--------- - 0 0 0 0 0 0 0 0 | not allowed - 0 0 0 0 0 0 0 1 | 1 | 1 - 0 0 0 0 0 0 1 0 | 2 | 2 - 0 0 0 0 0 0 1 1 | 3 | 3 - . . . | | - 0 1 0 1 0 1 0 1 | 55 | 85 - . . . | | - 1 0 1 0 1 0 1 0 | AA | 170 - . . . | | - 1 1 1 1 1 1 0 1 | FD | 253 - 1 1 1 1 1 1 1 0 | FE | 254 - 1 1 1 1 1 1 1 1 | FF | 255 - - -Setting the I/O Base Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The last three switches in switch block SW1 are used to select one -of eight possible I/O Base addresses using the following table:: - - - Switch | Hex I/O - 6 7 8 | Address - ------------|-------- - ON ON ON | 260 - OFF ON ON | 290 - ON OFF ON | 2E0 (Manufacturer's default) - OFF OFF ON | 2F0 - ON ON OFF | 300 - OFF ON OFF | 350 - ON OFF OFF | 380 - OFF OFF OFF | 3E0 - - -Setting the Base Memory (RAM) buffer Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The memory buffer (RAM) requires 2K. The base of this buffer can be -located in any of eight positions. The address of the Boot Prom is -memory base + 0x2000. - -Jumpers 3-5 of jumper block SW1 select the Memory Base address. - -:: - - Switch | Hex RAM | Hex ROM - 1 2 3 4 5 | Address | Address *) - --------------------|---------|----------- - ON ON ON ON ON | C0000 | C2000 - ON ON OFF ON ON | C4000 | C6000 - ON ON ON OFF ON | CC000 | CE000 - ON ON OFF OFF ON | D0000 | D2000 (Manufacturer's default) - ON ON ON ON OFF | D4000 | D6000 - ON ON OFF ON OFF | D8000 | DA000 - ON ON ON OFF OFF | DC000 | DE000 - ON ON OFF OFF OFF | E0000 | E2000 - - *) To enable the Boot ROM set the jumper 8 of jumper block SW3 to position ON. - -The jumpers 1 and 2 probably add 0x0800, 0x1000 and 0x1800 to RAM adders. - -Setting the Interrupt Line -^^^^^^^^^^^^^^^^^^^^^^^^^^ - -Jumpers 1-5 of the jumper block SW3 control the IRQ level:: - - Jumper | IRQ - 1 2 3 4 5 | - ---------------------------- - ON OFF OFF OFF OFF | 2 - OFF ON OFF OFF OFF | 3 - OFF OFF ON OFF OFF | 4 - OFF OFF OFF ON OFF | 5 - OFF OFF OFF OFF ON | 7 - - -Setting the Timeout Parameters -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The jumpers 6-7 of the jumper block SW3 are used to determine the timeout -parameters. These two jumpers are normally left in the OFF position. - - - -(Generic Model 9058) --------------------- - - from Andrew J. Kroll - - Sorry this sat in my to-do box for so long, Andrew! (yikes - over a - year!) - -:: - - _____ - | < - | .---' - ________________________________________________________________ | | - | | SW2 | | | - | ___________ |_____________| | | - | | | 1 2 3 4 5 6 ___| | - | > 6116 RAM | _________ 8 | | | - | |___________| |20MHzXtal| 7 | | | - | |_________| __________ 6 | S | | - | 74LS373 | |- 5 | W | | - | _________ | E |- 4 | | | - | >_______| ______________|..... P |- 3 | 3 | | - | | | : O |- 2 | | | - | | | : X |- 1 |___| | - | ________________ | | : Y |- | | - | | SW1 | | SL90C65 | : |- | | - | |________________| | | : B |- | | - | 1 2 3 4 5 6 7 8 | | : O |- | | - | |_________o____|..../ A |- _______| | - | ____________________ | R |- | |------, - | | | | D |- | BNC | # | - | > 2764 PROM SOCKET | |__________|- |_______|------' - | |____________________| _________ | | - | >________| <- 74LS245 | | - | | | - |___ ______________| | - |H H H H H H H H H H H H H H H H H H H H H H H| | | - |U_U_U_U_U_U_U_U_U_U_U_U_U_U_U_U_U_U_U_U_U_U_U| | | - \| - -Legend:: - - SL90C65 ARCNET Controller / Transceiver /Logic - SW1 1-5: IRQ Select - 6: ET1 - 7: ET2 - 8: ROM ENABLE - SW2 1-3: Memory Buffer/PROM Address - 3-6: I/O Address Map - SW3 1-8: Node ID Select - BNC BNC RG62/U Connection - *I* have had success using RG59B/U with *NO* terminators! - What gives?! - -SW1: Timeouts, Interrupt and ROM -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -To select a hardware interrupt level set one (only one!) of the dip switches -up (on) SW1...(switches 1-5) -IRQ3, IRQ4, IRQ5, IRQ7, IRQ2. The Manufacturer's default is IRQ2. - -The switches on SW1 labeled EXT1 (switch 6) and EXT2 (switch 7) -are used to determine the timeout parameters. These two dip switches -are normally left off (down). - - To enable the 8K Boot PROM position SW1 switch 8 on (UP) labeled ROM. - The default is jumper ROM not installed. - - -Setting the I/O Base Address -^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The last three switches in switch group SW2 are used to select one -of eight possible I/O Base addresses using the following table:: - - - Switch | Hex I/O - 4 5 6 | Address - -------|-------- - 0 0 0 | 260 - 0 0 1 | 290 - 0 1 0 | 2E0 (Manufacturer's default) - 0 1 1 | 2F0 - 1 0 0 | 300 - 1 0 1 | 350 - 1 1 0 | 380 - 1 1 1 | 3E0 - - -Setting the Base Memory Address (RAM & ROM) -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The memory buffer requires 2K of a 16K block of RAM. The base of this -16K block can be located in any of eight positions. -Switches 1-3 of switch group SW2 select the Base of the 16K block. -(0 = DOWN, 1 = UP) -I could, however, only verify two settings... - - -:: - - Switch| Hex RAM | Hex ROM - 1 2 3 | Address | Address - ------|---------|----------- - 0 0 0 | E0000 | E2000 - 0 0 1 | D0000 | D2000 (Manufacturer's default) - 0 1 0 | ????? | ????? - 0 1 1 | ????? | ????? - 1 0 0 | ????? | ????? - 1 0 1 | ????? | ????? - 1 1 0 | ????? | ????? - 1 1 1 | ????? | ????? - - -Setting the Node ID -^^^^^^^^^^^^^^^^^^^ - -The eight switches in group SW3 are used to set the node ID. -Each node attached to the network must have an unique node ID which -must be different from 0. -Switch 1 serves as the least significant bit (LSB). -switches in the DOWN position are OFF (0) and in the UP position are ON (1) - -The node ID is the sum of the values of all switches set to "1" -These values are:: - - Switch | Value - -------|------- - 1 | 1 - 2 | 2 - 3 | 4 - 4 | 8 - 5 | 16 - 6 | 32 - 7 | 64 - 8 | 128 - -Some Examples:: - - Switch# | Hex | Decimal - 8 7 6 5 4 3 2 1 | Node ID | Node ID - ----------------|---------|--------- - 0 0 0 0 0 0 0 0 | not allowed <-. - 0 0 0 0 0 0 0 1 | 1 | 1 | - 0 0 0 0 0 0 1 0 | 2 | 2 | - 0 0 0 0 0 0 1 1 | 3 | 3 | - . . . | | | - 0 1 0 1 0 1 0 1 | 55 | 85 | - . . . | | + Don't use 0 or 255! - 1 0 1 0 1 0 1 0 | AA | 170 | - . . . | | | - 1 1 1 1 1 1 0 1 | FD | 253 | - 1 1 1 1 1 1 1 0 | FE | 254 | - 1 1 1 1 1 1 1 1 | FF | 255 <-' - - -Tiara -===== - -(model unknown) ---------------- - - - from Christoph Lameter - - -Here is information about my card as far as I could figure it out:: - - - ----------------------------------------------- tiara - Tiara LanCard of Tiara Computer Systems. - - +----------------------------------------------+ - ! ! Transmitter Unit ! ! - ! +------------------+ ------- - ! MEM Coax Connector - ! ROM 7654321 <- I/O ------- - ! : : +--------+ ! - ! : : ! 90C66LJ! +++ - ! : : ! ! !D Switch to set - ! : : ! ! !I the Nodenumber - ! : : +--------+ !P - ! !++ - ! 234567 <- IRQ ! - +------------!!!!!!!!!!!!!!!!!!!!!!!!--------+ - !!!!!!!!!!!!!!!!!!!!!!!! - -- 0 = Jumper Installed -- 1 = Open - -Top Jumper line Bit 7 = ROM Enable 654=Memory location 321=I/O - -Settings for Memory Location (Top Jumper Line) - -=== ================ -456 Address selected -=== ================ -000 C0000 -001 C4000 -010 CC000 -011 D0000 -100 D4000 -101 D8000 -110 DC000 -111 E0000 -=== ================ - -Settings for I/O Address (Top Jumper Line) - -=== ==== -123 Port -=== ==== -000 260 -001 290 -010 2E0 -011 2F0 -100 300 -101 350 -110 380 -111 3E0 -=== ==== - -Settings for IRQ Selection (Lower Jumper Line) - -====== ===== -234567 -====== ===== -011111 IRQ 2 -101111 IRQ 3 -110111 IRQ 4 -111011 IRQ 5 -111110 IRQ 7 -====== ===== - -Other Cards -=========== - -I have no information on other models of ARCnet cards at the moment. - -Thanks. diff --git a/Documentation/networking/arcnet.rst b/Documentation/networking/arcnet.rst index cd43a18ad1494b..4e541aa44aec60 100644 --- a/Documentation/networking/arcnet.rst +++ b/Documentation/networking/arcnet.rst @@ -8,30 +8,10 @@ ARCnet .. note:: - See also arcnet-hardware.txt in this directory for jumper-setting + See also arcnet-hardware.rst in this directory for jumper-setting and cabling information if you're like many of us and didn't happen to get a manual with your ARCnet card. -Since no one seems to listen to me otherwise, perhaps a poem will get your -attention:: - - This driver's getting fat and beefy, - But my cat is still named Fifi. - -Hmm, I think I'm allowed to call that a poem, even though it's only two -lines. Hey, I'm in Computer Science, not English. Give me a break. - -The point is: I REALLY REALLY REALLY REALLY REALLY want to hear from you if -you test this and get it working. Or if you don't. Or anything. - -ARCnet 0.32 ALPHA first made it into the Linux kernel 1.1.80 - this was -nice, but after that even FEWER people started writing to me because they -didn't even have to install the patch. - -Come on, be a sport! Send me a success report! - -(hey, that was even better than my original poem... this is getting bad!) - ---- These are the ARCnet drivers for Linux. @@ -62,183 +42,47 @@ netdev@vger.kernel.org and make sure to Cc: maintainer listed in Other Drivers and Info ---------------------- -You can try my ARCNET page on the World Wide Web at: - - http://www.qis.net/~jschmitz/arcnet/ - -Also, SMC (one of the companies that makes ARCnet cards) has a WWW site you -might be interested in, which includes several drivers for various cards -including ARCnet. Try: - - http://www.smc.com/ - -Performance Technologies makes various network software that supports -ARCnet: - - http://www.perftech.com/ or ftp to ftp.perftech.com. - -Novell makes a networking stack for DOS which includes ARCnet drivers. Try -FTPing to ftp.novell.com. - -You can get the Crynwr packet driver collection (including arcether.com, the -one you'll want to use with ARCnet cards) from -oak.oakland.edu:/simtel/msdos/pktdrvr. It won't work perfectly on a 386+ -without patches, though, and also doesn't like several cards. Fixed -versions are available on my WWW page, or via e-mail if you don't have WWW -access. +You can try JoAnne Schmitz's ARCNET page on the World Wide Web at: + https://www.qis.net/~jschmitz/arcnet/ -Installing the Driver ---------------------- -All you will need to do in order to install the driver is:: +Supported Hardware +------------------ - make config - (be sure to choose ARCnet in the network devices - and at least one chipset driver.) - make clean - make zImage +Only PCI and PCI Express devices based on the COM20020 chipset are supported. +This is the newest chipset from SMC with support for promiscuous mode (packet +sniffing), extra diagnostic information, etc. These devices use the com20020_pci +driver. -If you obtained this ARCnet package as an upgrade to the ARCnet driver in -your current kernel, you will need to first copy arcnet.c over the one in -the linux/drivers/net directory. +Support for older chipsets and ISA and PCMCIA devices was previously available +but has been removed. -You will know the driver is installed properly if you get some ARCnet -messages when you reboot into the new Linux kernel. -There are four chipset options: - - 1. Standard ARCnet COM90xx chipset. - -This is the normal ARCnet card, which you've probably got. This is the only -chipset driver which will autoprobe if not told where the card is. -It following options on the command line:: - - com90xx=[[,[,]]][,] | - -If you load the chipset support as a module, the options are:: - - io= irq= shmem= device= - -To disable the autoprobe, just specify "com90xx=" on the kernel command line. -To specify the name alone, but allow autoprobe, just put "com90xx=" - - 2. ARCnet COM20020 chipset. +Configuring the Driver +---------------------- -This is the new chipset from SMC with support for promiscuous mode (packet -sniffing), extra diagnostic information, etc. Unfortunately, there is no -sensible method of autoprobing for these cards. You must specify the I/O -address on the kernel command line. +The COM20020 driver will be loaded automatically at boot if a supported card is +detected. -The command line options are:: +If the com20020_pci driver was compiled as a loadable module, the options are:: - com20020=[,[,[,backplane[,CKP[,timeout]]]]][,name] + node= backplane= clockp= clockm= + timeout= device= -If you load the chipset support as a module, the options are:: +If the driver was compiled into the kernel, the same options can be specified on +the kernel command line by prefixing them with `com20020_pci.`, as in the +following example:: - io= irq= node= backplane= clock= - timeout= device= + com20020_pci.device=eth1 The COM20020 chipset allows you to set the node ID in software, overriding the default which is still set in DIP switches on the card. If you don't have the -COM20020 data sheets, and you don't know what the other three options refer +COM20020 data sheets, and you don't know what the other options refer to, then they won't interest you - forget them. - 3. ARCnet COM90xx chipset in IO-mapped mode. - -This will also work with the normal ARCnet cards, but doesn't use the shared -memory. It performs less well than the above driver, but is provided in case -you have a card which doesn't support shared memory, or (strangely) in case -you have so many ARCnet cards in your machine that you run out of shmem slots. -If you don't give the IO address on the kernel command line, then the driver -will not find the card. - -The command line options are:: - - com90io=[,][,] - -If you load the chipset support as a module, the options are: - io= irq= device= - - 4. ARCnet RIM I cards. - -These are COM90xx chips which are _completely_ memory mapped. The support for -these is not tested. If you have one, please mail the author with a success -report. All options must be specified, except the device name. -Command line options:: - - arcrimi=,,[,] - -If you load the chipset support as a module, the options are:: - - shmem= irq= node= device= - - -Loadable Module Support ------------------------ - -Configure and rebuild Linux. When asked, answer 'm' to "Generic ARCnet -support" and to support for your ARCnet chipset if you want to use the -loadable module. You can also say 'y' to "Generic ARCnet support" and 'm' -to the chipset support if you wish. - -:: - - make config - make clean - make zImage - make modules - -If you're using a loadable module, you need to use insmod to load it, and -you can specify various characteristics of your card on the command -line. (In recent versions of the driver, autoprobing is much more reliable -and works as a module, so most of this is now unnecessary.) - -For example:: - - cd /usr/src/linux/modules - insmod arcnet.o - insmod com90xx.o - insmod com20020.o io=0x2e0 device=eth1 - - -Using the Driver ----------------- - -If you build your kernel with ARCnet COM90xx support included, it should -probe for your card automatically when you boot. If you use a different -chipset driver complied into the kernel, you must give the necessary options -on the kernel command line, as detailed above. - -Go read the NET-2-HOWTO and ETHERNET-HOWTO for Linux; they should be -available where you picked up this driver. Think of your ARCnet as a -souped-up (or down, as the case may be) Ethernet card. - -By the way, be sure to change all references from "eth0" to "arc0" in the -HOWTOs. Remember that ARCnet isn't a "true" Ethernet, and the device name -is DIFFERENT. - - -Multiple Cards in One Computer ------------------------------- - -Linux has pretty good support for this now, but since I've been busy, the -ARCnet driver has somewhat suffered in this respect. COM90xx support, if -compiled into the kernel, will (try to) autodetect all the installed cards. - -If you have other cards, with support compiled into the kernel, then you can -just repeat the options on the kernel command line, e.g.:: - - LILO: linux com20020=0x2e0 com20020=0x380 com90io=0x260 - -If you have the chipset support built as a loadable module, then you need to -do something like this:: - - insmod -o arc0 com90xx - insmod -o arc1 com20020 io=0x2e0 - insmod -o arc2 com90xx - -The ARCnet drivers will now sort out their names automatically. +Otherwise, ARCnet can be configured in a similar way to Ethernet, with the +exception that ARCnet interface names begin with `arc`. How do I get it to work with...? @@ -276,9 +120,8 @@ LAN Manager and Windows for Workgroups: are incompatible with the Internet standard. They try to pretend the cards are Ethernet, and confuse everyone else on the network. - However, v2.00 and higher of the Linux ARCnet driver supports this - protocol via the 'arc0e' device. See the section on "Multiprotocol - Support" for more information. + The Linux ARCnet driver supports this protocol via the 'arc0e' device. + See the section on "Multiprotocol Support" for more information. Using the freeware Samba server and clients for Linux, you can now interface quite nicely with TCP/IP-based WfWg or Lan Manager @@ -313,7 +156,7 @@ NetBSD/AmiTCP: Using Multiprotocol ARCnet -------------------------- -The ARCnet driver v2.10 ALPHA supports three protocols, each on its own +The ARCnet driver supports three protocols, each on its own "virtual network device": ====== =============================================================== @@ -505,7 +348,7 @@ can set up your network then: It works: what now? ------------------- -Send mail following :ref:`arcnet-netdev`. Describe your setup, preferably +:ref:`Send an email to netdev `. Describe your setup, preferably including driver version, kernel version, ARCnet card model, CPU type, number of systems on your network, and list of software in use. @@ -524,10 +367,6 @@ first! D_DURING displays 4-5 lines for each packet sent or received. D_TX, D_RX, and D_SKB actually DISPLAY each packet as it is sent or received, which is obviously quite big. -Starting with v2.40 ALPHA, the autoprobe routines have changed -significantly. In particular, they won't tell you why the card was not -found unless you turn on the D_INIT_REASONS debugging flag. - Once the driver is running, you can run the arcdump shell script (available from me or in the full ARCnet package, if you have it) as root to list the contents of the arcnet buffers at any time. To make any sense at all out of @@ -548,21 +387,13 @@ out which bytes are being used by a packet. You can change the debug level without recompiling the kernel by typing:: ifconfig arc0 down metric 1xxx - /etc/rc.d/rc.inet1 + ifconfig arc0 up where "xxx" is the debug level you want. For example, "metric 1015" would put you at debug level 15. Debug level 7 is currently the default. -Note that the debug level is (starting with v1.90 ALPHA) a binary -combination of different debug flags; so debug level 7 is really 1+2+4 or -D_NORMAL+D_EXTRA+D_INIT. To include D_DURING, you would add 16 to this, -resulting in debug level 23. +Note that the debug level is a binary combination of different debug flags; +debug level 7 is really 1+2+4 or D_NORMAL+D_EXTRA+D_INIT. To include D_DURING, +you would add 16 to this, resulting in debug level 23. If you don't understand that, you probably don't want to know anyway. -E-mail me about your problem. - - -I want to send money: what now? -------------------------------- - -Go take a nap or something. You'll feel better in the morning. diff --git a/Documentation/networking/bonding.rst b/Documentation/networking/bonding.rst index e700bf1d095c35..33ca5afafdf6dd 100644 --- a/Documentation/networking/bonding.rst +++ b/Documentation/networking/bonding.rst @@ -619,6 +619,29 @@ min_links aggregator cannot be active without at least one available link, setting this option to 0 or to 1 has the exact same effect. +lacp_strict + + Specifies the fallback behavior of a bonding when LACP negotiation + fails on all slave links, i.e. when no slave is in the + Collecting_Distributing state, while at least `min_links` link still + reports carrier up. + + This option is only applicable to 802.3ad mode (mode 4). + + Valid values are: + + off or 0 + One interface of the bond is selected to be active, in order to + facilitate communication with peer devices that do not implement + LACP. + + on or 1 + Interfaces are only permitted to be made active if they have an + active LACP partner and have successfully reached + Collecting_Distributing state. + + The default value is 0 (off). + mode Specifies one of the bonding policies. The default is diff --git a/Documentation/networking/checksum-offloads.rst b/Documentation/networking/checksum-offloads.rst index 69b23cf6879e7b..d4ded890011b2d 100644 --- a/Documentation/networking/checksum-offloads.rst +++ b/Documentation/networking/checksum-offloads.rst @@ -19,17 +19,14 @@ The following technologies are described: Things that should be documented here but aren't yet: -* RX Checksum Offload * CHECKSUM_UNNECESSARY conversion TX Checksum Offload =================== -The interface for offloading a transmit checksum to a device is explained in -detail in comments near the top of include/linux/skbuff.h. - -In brief, it allows to request the device fill in a single ones-complement +In brief, Tx checksum offload allows to request the device fill in a single +ones-complement checksum defined by the sk_buff fields skb->csum_start and skb->csum_offset. The device should compute the 16-bit ones-complement checksum (i.e. the 'IP-style' checksum) from csum_start to the end of the packet, and fill in the @@ -45,9 +42,10 @@ encapsulation is used, the packet may have multiple checksum fields in different header layers, and the rest will have to be handled by another mechanism such as LCO or RCO. -CRC32c can also be offloaded using this interface, by means of filling -skb->csum_start and skb->csum_offset as described above, and setting -skb->csum_not_inet: see skbuff.h comment (section 'D') for more details. +SCTP CRC32c can also be offloaded using this interface, by means of filling +skb->csum_start and skb->csum_offset as described above, setting +skb->csum_not_inet, and advertising NETIF_F_SCTP_CRC. Drivers must not treat +ordinary IP checksum offload as SCTP CRC32c support. No offloading of the IP header checksum is performed; it is always done in software. This is OK because when we build the IP header, we obviously have it @@ -55,18 +53,15 @@ in cache, so summing it isn't expensive. It's also rather short. The requirements for GSO are more complicated, because when segmenting an encapsulated packet both the inner and outer checksums may need to be edited or -recomputed for each resulting segment. See the skbuff.h comment (section 'E') -for more details. +recomputed for each resulting segment. A driver declares its offload capabilities in netdev->hw_features; see -Documentation/networking/netdev-features.rst for more. Note that a device -which only advertises NETIF_F_IP[V6]_CSUM must still obey the csum_start and -csum_offset given in the SKB; if it tries to deduce these itself in hardware -(as some NICs do) the driver should check that the values in the SKB match -those which the hardware will deduce, and if not, fall back to checksumming in -software instead (with skb_csum_hwoffload_help() or one of the -skb_checksum_help() / skb_crc32c_csum_help functions, as mentioned in -include/linux/skbuff.h). +Documentation/networking/netdev-features.rst for more. NETIF_F_IP_CSUM and +NETIF_F_IPV6_CSUM are restricted legacy features and are being deprecated in +favor of NETIF_F_HW_CSUM. New devices should use NETIF_F_HW_CSUM to advertise +generic checksum offload. The skb_csum_hwoffload_help() helper can resolve +CHECKSUM_PARTIAL according to the device's advertised checksum capabilities, +falling back to software when needed. The stack should, for the most part, assume that checksum offload is supported by the underlying device. The only place that should check is @@ -108,11 +103,9 @@ LCO is performed by the stack when constructing an outer UDP header for an encapsulation such as VXLAN or GENEVE, in udp_set_csum(). Similarly for the IPv6 equivalents, in udp6_set_csum(). -It is also performed when constructing an IPv4 GRE header, in -net/ipv4/ip_gre.c:build_header(). It is *not* currently performed when -constructing an IPv6 GRE header; the GRE checksum is computed over the whole -packet in net/ipv6/ip6_gre.c:ip6gre_xmit2(), but it should be possible to use -LCO here as IPv6 GRE still uses an IP-style checksum. +It is also performed when constructing GRE headers with the shared +gre_build_header() helper in include/net/gre.h, which is used by both IPv4 and +IPv6 GRE. All of the LCO implementations use a helper function lco_csum(), in include/linux/skbuff.h. @@ -138,6 +131,28 @@ RCO is detailed in the following Internet-Drafts: * https://tools.ietf.org/html/draft-herbert-vxlan-rco-00 In Linux, RCO is implemented individually in each encapsulation protocol, and -most tunnel types have flags controlling its use. For instance, VXLAN has the -flag VXLAN_F_REMCSUM_TX (per struct vxlan_rdst) to indicate that RCO should be -used when transmitting to a given remote destination. +most tunnel types have flags controlling its use. For instance, VXLAN has the +configuration flag VXLAN_F_REMCSUM_TX to indicate that RCO should be used when +transmitting. + + +RX Checksum Offload +=================== + +RX checksum offload is controlled via NETIF_F_RXCSUM. When disabled the driver +must not set skb->ip_summed on ingress packets. As mentioned, IPv4 checksum +is not offloaded, the RXCSUM feature controls the offload of verification of +transport layer checksums. + +Note that packets with bad TCP/UDP checksums must still be passed +to the stack. skb->ip_summed of such packets can be set to ``CHECKSUM_COMPLETE`` +or left at ``CHECKSUM_NONE``. Drivers **must not discard** packets with +bad TCP/UDP checksum and must not configure the device to drop them. +Checksum validation is relatively inexpensive and having bad packets reflected +in SNMP counters is crucial for network monitoring. + +skb checksum documentation +========================== + +.. kernel-doc:: include/linux/skbuff.h + :doc: skb checksums diff --git a/Documentation/networking/device_drivers/ethernet/cirrus/cs89x0.rst b/Documentation/networking/device_drivers/ethernet/cirrus/cs89x0.rst deleted file mode 100644 index e5c283940ac54c..00000000000000 --- a/Documentation/networking/device_drivers/ethernet/cirrus/cs89x0.rst +++ /dev/null @@ -1,647 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -================================================ -Cirrus Logic LAN CS8900/CS8920 Ethernet Adapters -================================================ - -.. note:: - - This document was contributed by Cirrus Logic for kernel 2.2.5. This version - has been updated for 2.3.48 by Andrew Morton. - - Still, this is too outdated! A major cleanup is needed here. - -Cirrus make a copy of this driver available at their website, as -described below. In general, you should use the driver version which -comes with your Linux distribution. - - -Linux Network Interface Driver ver. 2.00 - - -.. TABLE OF CONTENTS - - 1.0 CIRRUS LOGIC LAN CS8900/CS8920 ETHERNET ADAPTERS - 1.1 Product Overview - 1.2 Driver Description - 1.2.1 Driver Name - 1.2.2 File in the Driver Package - 1.3 System Requirements - 1.4 Licensing Information - - 2.0 ADAPTER INSTALLATION and CONFIGURATION - 2.1 CS8900-based Adapter Configuration - 2.2 CS8920-based Adapter Configuration - - 3.0 LOADING THE DRIVER AS A MODULE - - 4.0 COMPILING THE DRIVER - 4.1 Compiling the Driver as a Loadable Module - 4.2 Compiling the driver to support memory mode - 4.3 Compiling the driver to support Rx DMA - - 5.0 TESTING AND TROUBLESHOOTING - 5.1 Known Defects and Limitations - 5.2 Testing the Adapter - 5.2.1 Diagnostic Self-Test - 5.2.2 Diagnostic Network Test - 5.3 Using the Adapter's LEDs - 5.4 Resolving I/O Conflicts - - 6.0 TECHNICAL SUPPORT - 6.1 Contacting Cirrus Logic's Technical Support - 6.2 Information Required Before Contacting Technical Support - 6.3 Obtaining the Latest Driver Version - 6.4 Current maintainer - 6.5 Kernel boot parameters - - -1. Cirrus Logic LAN CS8900/CS8920 Ethernet Adapters -=================================================== - - -1.1. Product Overview -===================== - -The CS8900-based ISA Ethernet Adapters from Cirrus Logic follow -IEEE 802.3 standards and support half or full-duplex operation in ISA bus -computers on 10 Mbps Ethernet networks. The adapters are designed for operation -in 16-bit ISA or EISA bus expansion slots and are available in -10BaseT-only or 3-media configurations (10BaseT, 10Base2, and AUI for 10Base-5 -or fiber networks). - -CS8920-based adapters are similar to the CS8900-based adapter with additional -features for Plug and Play (PnP) support and Wakeup Frame recognition. As -such, the configuration procedures differ somewhat between the two types of -adapters. Refer to the "Adapter Configuration" section for details on -configuring both types of adapters. - - -1.2. Driver Description -======================= - -The CS8900/CS8920 Ethernet Adapter driver for Linux supports the Linux -v2.3.48 or greater kernel. It can be compiled directly into the kernel -or loaded at run-time as a device driver module. - -1.2.1 Driver Name: cs89x0 - -1.2.2 Files in the Driver Archive: - -The files in the driver at Cirrus' website include: - - =================== ==================================================== - readme.txt this file - build batch file to compile cs89x0.c. - cs89x0.c driver C code - cs89x0.h driver header file - cs89x0.o pre-compiled module (for v2.2.5 kernel) - config/Config.in sample file to include cs89x0 driver in the kernel. - config/Makefile sample file to include cs89x0 driver in the kernel. - config/Space.c sample file to include cs89x0 driver in the kernel. - =================== ==================================================== - - - -1.3. System Requirements ------------------------- - -The following hardware is required: - - * Cirrus Logic LAN (CS8900/20-based) Ethernet ISA Adapter - - * IBM or IBM-compatible PC with: - * An 80386 or higher processor - * 16 bytes of contiguous IO space available between 210h - 370h - * One available IRQ (5,10,11,or 12 for the CS8900, 3-7,9-15 for CS8920). - - * Appropriate cable (and connector for AUI, 10BASE-2) for your network - topology. - -The following software is required: - -* LINUX kernel version 2.3.48 or higher - - * CS8900/20 Setup Utility (DOS-based) - - * LINUX kernel sources for your kernel (if compiling into kernel) - - * GNU Toolkit (gcc and make) v2.6 or above (if compiling into kernel - or a module) - - - -1.4. Licensing Information --------------------------- - -This program is free software; you can redistribute it and/or modify it under -the terms of the GNU General Public License as published by the Free Software -Foundation, version 1. - -This program is distributed in the hope that it will be useful, but WITHOUT -ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for -more details. - -For a full copy of the GNU General Public License, write to the Free Software -Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. - - - -2. Adapter Installation and Configuration -========================================= - -Both the CS8900 and CS8920-based adapters can be configured using parameters -stored in an on-board EEPROM. You must use the DOS-based CS8900/20 Setup -Utility if you want to change the adapter's configuration in EEPROM. - -When loading the driver as a module, you can specify many of the adapter's -configuration parameters on the command-line to override the EEPROM's settings -or for interface configuration when an EEPROM is not used. (CS8920-based -adapters must use an EEPROM.) See Section 3.0 LOADING THE DRIVER AS A MODULE. - -Since the CS8900/20 Setup Utility is a DOS-based application, you must install -and configure the adapter in a DOS-based system using the CS8900/20 Setup -Utility before installation in the target LINUX system. (Not required if -installing a CS8900-based adapter and the default configuration is acceptable.) - - -2.1. CS8900-based Adapter Configuration ---------------------------------------- - -CS8900-based adapters shipped from Cirrus Logic have been configured -with the following "default" settings:: - - Operation Mode: Memory Mode - IRQ: 10 - Base I/O Address: 300 - Memory Base Address: D0000 - Optimization: DOS Client - Transmission Mode: Half-duplex - BootProm: None - Media Type: Autodetect (3-media cards) or - 10BASE-T (10BASE-T only adapter) - -You should only change the default configuration settings if conflicts with -another adapter exists. To change the adapter's configuration, run the -CS8900/20 Setup Utility. - - -2.2. CS8920-based Adapter Configuration ---------------------------------------- - -CS8920-based adapters are shipped from Cirrus Logic configured as Plug -and Play (PnP) enabled. However, since the cs89x0 driver does NOT -support PnP, you must install the CS8920 adapter in a DOS-based PC and -run the CS8900/20 Setup Utility to disable PnP and configure the -adapter before installation in the target Linux system. Failure to do -this will leave the adapter inactive and the driver will be unable to -communicate with the adapter. - -:: - - **************************************************************** - * CS8920-BASED ADAPTERS: * - * * - * CS8920-BASED ADAPTERS ARE PLUG and PLAY ENABLED BY DEFAULT. * - * THE CS89X0 DRIVER DOES NOT SUPPORT PnP. THEREFORE, YOU MUST * - * RUN THE CS8900/20 SETUP UTILITY TO DISABLE PnP SUPPORT AND * - * TO ACTIVATE THE ADAPTER. * - **************************************************************** - - - - -3. Loading the Driver as a Module -================================= - -If the driver is compiled as a loadable module, you can load the driver module -with the 'modprobe' command. Many of the adapter's configuration parameters can -be specified as command-line arguments to the load command. This facility -provides a means to override the EEPROM's settings or for interface -configuration when an EEPROM is not used. - -Example:: - - insmod cs89x0.o io=0x200 irq=0xA media=aui - -This example loads the module and configures the adapter to use an IO port base -address of 200h, interrupt 10, and use the AUI media connection. The following -configuration options are available on the command line:: - - io=### - specify IO address (200h-360h) - irq=## - specify interrupt level - use_dma=1 - Enable DMA - dma=# - specify dma channel (Driver is compiled to support - Rx DMA only) - dmasize=# (16 or 64) - DMA size 16K or 64K. Default value is set to 16. - media=rj45 - specify media type - or media=bnc - or media=aui - or media=auto - duplex=full - specify forced half/full/autonegotiate duplex - or duplex=half - or duplex=auto - debug=# - debug level (only available if the driver was compiled - for debugging) - -**Notes:** - -a) If an EEPROM is present, any specified command-line parameter - will override the corresponding configuration value stored in - EEPROM. - -b) The "io" parameter must be specified on the command-line. - -c) The driver's hardware probe routine is designed to avoid - writing to I/O space until it knows that there is a cs89x0 - card at the written addresses. This could cause problems - with device probing. To avoid this behaviour, add one - to the ``io=`` module parameter. This doesn't actually change - the I/O address, but it is a flag to tell the driver - to partially initialise the hardware before trying to - identify the card. This could be dangerous if you are - not sure that there is a cs89x0 card at the provided address. - - For example, to scan for an adapter located at IO base 0x300, - specify an IO address of 0x301. - -d) The "duplex=auto" parameter is only supported for the CS8920. - -e) The minimum command-line configuration required if an EEPROM is - not present is: - - io - irq - media type (no autodetect) - -f) The following additional parameters are CS89XX defaults (values - used with no EEPROM or command-line argument). - - * DMA Burst = enabled - * IOCHRDY Enabled = enabled - * UseSA = enabled - * CS8900 defaults to half-duplex if not specified on command-line - * CS8920 defaults to autoneg if not specified on command-line - * Use reset defaults for other config parameters - * dma_mode = 0 - -g) You can use ifconfig to set the adapter's Ethernet address. - -h) Many Linux distributions use the 'modprobe' command to load - modules. This program uses the '/etc/conf.modules' file to - determine configuration information which is passed to a driver - module when it is loaded. All the configuration options which are - described above may be placed within /etc/conf.modules. - - For example:: - - > cat /etc/conf.modules - ... - alias eth0 cs89x0 - options cs89x0 io=0x0200 dma=5 use_dma=1 - ... - - In this example we are telling the module system that the - ethernet driver for this machine should use the cs89x0 driver. We - are asking 'modprobe' to pass the 'io', 'dma' and 'use_dma' - arguments to the driver when it is loaded. - -i) Cirrus recommend that the cs89x0 use the ISA DMA channels 5, 6 or - 7. You will probably find that other DMA channels will not work. - -j) The cs89x0 supports DMA for receiving only. DMA mode is - significantly more efficient. Flooding a 400 MHz Celeron machine - with large ping packets consumes 82% of its CPU capacity in non-DMA - mode. With DMA this is reduced to 45%. - -k) If your Linux kernel was compiled with inbuilt plug-and-play - support you will be able to find information about the cs89x0 card - with the command:: - - cat /proc/isapnp - -l) If during DMA operation you find erratic behavior or network data - corruption you should use your PC's BIOS to slow the EISA bus clock. - -m) If the cs89x0 driver is compiled directly into the kernel - (non-modular) then its I/O address is automatically determined by - ISA bus probing. The IRQ number, media options, etc are determined - from the card's EEPROM. - -n) If the cs89x0 driver is compiled directly into the kernel, DMA - mode may be selected by providing the kernel with a boot option - 'cs89x0_dma=N' where 'N' is the desired DMA channel number (5, 6 or 7). - - Kernel boot options may be provided on the LILO command line:: - - LILO boot: linux cs89x0_dma=5 - - or they may be placed in /etc/lilo.conf:: - - image=/boot/bzImage-2.3.48 - append="cs89x0_dma=5" - label=linux - root=/dev/hda5 - read-only - - The DMA Rx buffer size is hardwired to 16 kbytes in this mode. - (64k mode is not available). - - -4. Compiling the Driver -======================= - -The cs89x0 driver can be compiled directly into the kernel or compiled into -a loadable device driver module. - -Just use the standard way to configure the driver and compile the Kernel. - - -4.1. Compiling the Driver to Support Rx DMA -------------------------------------------- - -The compile-time optionality for DMA was removed in the 2.3 kernel -series. DMA support is now unconditionally part of the driver. It is -enabled by the 'use_dma=1' module option. - - -5. Testing and Troubleshooting -============================== - -5.1. Known Defects and Limitations ----------------------------------- - -Refer to the RELEASE.TXT file distributed as part of this archive for a list of -known defects, driver limitations, and work arounds. - - -5.2. Testing the Adapter ------------------------- - -Once the adapter has been installed and configured, the diagnostic option of -the CS8900/20 Setup Utility can be used to test the functionality of the -adapter and its network connection. Use the diagnostics 'Self Test' option to -test the functionality of the adapter with the hardware configuration you have -assigned. You can use the diagnostics 'Network Test' to test the ability of the -adapter to communicate across the Ethernet with another PC equipped with a -CS8900/20-based adapter card (it must also be running the CS8900/20 Setup -Utility). - -.. note:: - - The Setup Utility's diagnostics are designed to run in a - DOS-only operating system environment. DO NOT run the diagnostics - from a DOS or command prompt session under Windows 95, Windows NT, - OS/2, or other operating system. - -To run the diagnostics tests on the CS8900/20 adapter: - - 1. Boot DOS on the PC and start the CS8900/20 Setup Utility. - - 2. The adapter's current configuration is displayed. Hit the ENTER key to - get to the main menu. - - 4. Select 'Diagnostics' (ALT-G) from the main menu. - * Select 'Self-Test' to test the adapter's basic functionality. - * Select 'Network Test' to test the network connection and cabling. - - -5.2.1. Diagnostic Self-test -^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The diagnostic self-test checks the adapter's basic functionality as well as -its ability to communicate across the ISA bus based on the system resources -assigned during hardware configuration. The following tests are performed: - - * IO Register Read/Write Test - - The IO Register Read/Write test insures that the CS8900/20 can be - accessed in IO mode, and that the IO base address is correct. - - * Shared Memory Test - - The Shared Memory test insures the CS8900/20 can be accessed in memory - mode and that the range of memory addresses assigned does not conflict - with other devices in the system. - - * Interrupt Test - - The Interrupt test insures there are no conflicts with the assigned IRQ - signal. - - * EEPROM Test - - The EEPROM test insures the EEPROM can be read. - - * Chip RAM Test - - The Chip RAM test insures the 4K of memory internal to the CS8900/20 is - working properly. - - * Internal Loop-back Test - - The Internal Loop Back test insures the adapter's transmitter and - receiver are operating properly. If this test fails, make sure the - adapter's cable is connected to the network (check for LED activity for - example). - - * Boot PROM Test - - The Boot PROM test insures the Boot PROM is present, and can be read. - Failure indicates the Boot PROM was not successfully read due to a - hardware problem or due to a conflicts on the Boot PROM address - assignment. (Test only applies if the adapter is configured to use the - Boot PROM option.) - -Failure of a test item indicates a possible system resource conflict with -another device on the ISA bus. In this case, you should use the Manual Setup -option to reconfigure the adapter by selecting a different value for the system -resource that failed. - - -5.2.2. Diagnostic Network Test -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ - -The Diagnostic Network Test verifies a working network connection by -transferring data between two CS8900/20 adapters installed in different PCs -on the same network. (Note: the diagnostic network test should not be run -between two nodes across a router.) - -This test requires that each of the two PCs have a CS8900/20-based adapter -installed and have the CS8900/20 Setup Utility running. The first PC is -configured as a Responder and the other PC is configured as an Initiator. -Once the Initiator is started, it sends data frames to the Responder which -returns the frames to the Initiator. - -The total number of frames received and transmitted are displayed on the -Initiator's display, along with a count of the number of frames received and -transmitted OK or in error. The test can be terminated anytime by the user at -either PC. - -To setup the Diagnostic Network Test: - - 1. Select a PC with a CS8900/20-based adapter and a known working network - connection to act as the Responder. Run the CS8900/20 Setup Utility - and select 'Diagnostics -> Network Test -> Responder' from the main - menu. Hit ENTER to start the Responder. - - 2. Return to the PC with the CS8900/20-based adapter you want to test and - start the CS8900/20 Setup Utility. - - 3. From the main menu, Select 'Diagnostic -> Network Test -> Initiator'. - Hit ENTER to start the test. - -You may stop the test on the Initiator at any time while allowing the Responder -to continue running. In this manner, you can move to additional PCs and test -them by starting the Initiator on another PC without having to stop/start the -Responder. - - - -5.3. Using the Adapter's LEDs ------------------------------ - -The 2 and 3-media adapters have two LEDs visible on the back end of the board -located near the 10Base-T connector. - -Link Integrity LED: A "steady" ON of the green LED indicates a valid 10Base-T -connection. (Only applies to 10Base-T. The green LED has no significance for -a 10Base-2 or AUI connection.) - -TX/RX LED: The yellow LED lights briefly each time the adapter transmits or -receives data. (The yellow LED will appear to "flicker" on a typical network.) - - -5.4. Resolving I/O Conflicts ----------------------------- - -An IO conflict occurs when two or more adapter use the same ISA resource (IO -address, memory address or IRQ). You can usually detect an IO conflict in one -of four ways after installing and or configuring the CS8900/20-based adapter: - - 1. The system does not boot properly (or at all). - - 2. The driver cannot communicate with the adapter, reporting an "Adapter - not found" error message. - - 3. You cannot connect to the network or the driver will not load. - - 4. If you have configured the adapter to run in memory mode but the driver - reports it is using IO mode when loading, this is an indication of a - memory address conflict. - -If an IO conflict occurs, run the CS8900/20 Setup Utility and perform a -diagnostic self-test. Normally, the ISA resource in conflict will fail the -self-test. If so, reconfigure the adapter selecting another choice for the -resource in conflict. Run the diagnostics again to check for further IO -conflicts. - -In some cases, such as when the PC will not boot, it may be necessary to remove -the adapter and reconfigure it by installing it in another PC to run the -CS8900/20 Setup Utility. Once reinstalled in the target system, run the -diagnostics self-test to ensure the new configuration is free of conflicts -before loading the driver again. - -When manually configuring the adapter, keep in mind the typical ISA system -resource usage as indicated in the tables below. - -:: - - I/O Address Device IRQ Device - ----------- -------- --- -------- - 200-20F Game I/O adapter 3 COM2, Bus Mouse - 230-23F Bus Mouse 4 COM1 - 270-27F LPT3: third parallel port 5 LPT2 - 2F0-2FF COM2: second serial port 6 Floppy Disk controller - 320-32F Fixed disk controller 7 LPT1 - 8 Real-time Clock - 9 EGA/VGA display adapter - 12 Mouse (PS/2) - Memory Address Device 13 Math Coprocessor - -------------- --------------------- 14 Hard Disk controller - A000-BFFF EGA Graphics Adapter - A000-C7FF VGA Graphics Adapter - B000-BFFF Mono Graphics Adapter - B800-BFFF Color Graphics Adapter - E000-FFFF AT BIOS - - - - -6. Technical Support -==================== - -6.1. Contacting Cirrus Logic's Technical Support ------------------------------------------------- - -Cirrus Logic's CS89XX Technical Application Support can be reached at:: - - Telephone :(800) 888-5016 (from inside U.S. and Canada) - :(512) 442-7555 (from outside the U.S. and Canada) - Fax :(512) 912-3871 - Email :ethernet@crystal.cirrus.com - WWW :http://www.cirrus.com - - -6.2. Information Required before Contacting Technical Support -------------------------------------------------------------- - -Before contacting Cirrus Logic for technical support, be prepared to provide as -Much of the following information as possible. - -1.) Adapter type (CRD8900, CDB8900, CDB8920, etc.) - -2.) Adapter configuration - - * IO Base, Memory Base, IO or memory mode enabled, IRQ, DMA channel - * Plug and Play enabled/disabled (CS8920-based adapters only) - * Configured for media auto-detect or specific media type (which type). - -3.) PC System's Configuration - - * Plug and Play system (yes/no) - * BIOS (make and version) - * System make and model - * CPU (type and speed) - * System RAM - * SCSI Adapter - -4.) Software - - * CS89XX driver and version - * Your network operating system and version - * Your system's OS version - * Version of all protocol support files - -5.) Any Error Message displayed. - - - -6.3 Obtaining the Latest Driver Version ---------------------------------------- - -You can obtain the latest CS89XX drivers and support software from Cirrus Logic's -Web site. You can also contact Cirrus Logic's Technical Support (email: -ethernet@crystal.cirrus.com) and request that you be registered for automatic -software-update notification. - -Cirrus Logic maintains a web page at http://www.cirrus.com with the -latest drivers and technical publications. - - -6.4. Current maintainer ------------------------ - -In February 2000 the maintenance of this driver was assumed by Andrew -Morton. - -6.5 Kernel module parameters ----------------------------- - -For use in embedded environments with no cs89x0 EEPROM, the kernel boot -parameter ``cs89x0_media=`` has been implemented. Usage is:: - - cs89x0_media=rj45 or - cs89x0_media=aui or - cs89x0_media=bnc diff --git a/Documentation/networking/device_drivers/ethernet/index.rst b/Documentation/networking/device_drivers/ethernet/index.rst index 1d25be493ae9d4..786a23c84b901c 100644 --- a/Documentation/networking/device_drivers/ethernet/index.rst +++ b/Documentation/networking/device_drivers/ethernet/index.rst @@ -19,7 +19,6 @@ Contents: amd/pds_vfio_pci aquantia/atlantic chelsio/cxgb - cirrus/cs89x0 dlink/dl2k davicom/dm9000 dec/dmfe diff --git a/Documentation/networking/devlink/devlink-health.rst b/Documentation/networking/devlink/devlink-health.rst index 4d10536377ab70..bedac58a2f36d1 100644 --- a/Documentation/networking/devlink/devlink-health.rst +++ b/Documentation/networking/devlink/devlink-health.rst @@ -33,7 +33,9 @@ Device driver can provide specific callbacks for each "health reporter", e.g.: * Recovery procedures * Diagnostics procedures * Object dump procedures - * Out Of Box initial parameters + +Drivers also provide default values for generic reporter parameters when +creating a health reporter. Different parts of the driver can register different types of health reporters with different handlers. @@ -45,8 +47,9 @@ Once an error is reported, devlink health will perform the following actions: * A log is being send to the kernel trace events buffer * Health status and statistics are being updated for the reporter instance - * Object dump is being taken and saved at the reporter instance (as long as - auto-dump is set and there is no other dump which is already stored) + * Object dump is being taken and saved at the reporter instance. This is + best effort and skipped when recovery is aborted, auto-dump is disabled, + no dump callback is registered, or a dump is already stored. * Auto recovery attempt is being done. Depends on: - Auto-recovery configuration @@ -75,7 +78,8 @@ User Interface ============== User can access/change each reporter's parameters and driver specific callbacks -via ``devlink``, e.g per error type (per health reporter): +via ``devlink``, e.g. per error type (per health reporter). Reporters may be +registered for the whole devlink instance or for a specific devlink port. * Configure reporter's generic parameters (like: disable/enable auto recovery) * Invoke recovery procedure diff --git a/Documentation/networking/devlink/devlink-params.rst b/Documentation/networking/devlink/devlink-params.rst index ea17756dcda6d3..ca19ee3e63c86f 100644 --- a/Documentation/networking/devlink/devlink-params.rst +++ b/Documentation/networking/devlink/devlink-params.rst @@ -122,7 +122,7 @@ own name. * - ``enable_iwarp`` - Boolean - Enable handling of iWARP traffic in the device. - * - ``internal_err_reset`` + * - ``internal_error_reset`` - Boolean - When enabled, the device driver will reset the device on internal errors. diff --git a/Documentation/networking/devlink/devlink-port.rst b/Documentation/networking/devlink/devlink-port.rst index 5e397798a40224..9374ebe70f485e 100644 --- a/Documentation/networking/devlink/devlink-port.rst +++ b/Documentation/networking/devlink/devlink-port.rst @@ -38,7 +38,7 @@ Devlink port flavours are described below. - This indicates an eswitch port representing a port of PCI subfunction (SF). * - ``DEVLINK_PORT_FLAVOUR_VIRTUAL`` - - This indicates a virtual port for the PCI virtual function. + - Any virtual port facing the user. Devlink port can have a different type based on the link layer described below. @@ -134,6 +134,9 @@ Users may also set the IPsec crypto capability of the function using Users may also set the IPsec packet capability of the function using `devlink port function set ipsec_packet` command. +The ``migratable`` attribute may be set only on ports with +``DEVLINK_PORT_FLAVOUR_PCI_VF``. + Users may also set the maximum IO event queues of the function using `devlink port function set max_io_eqs` command. diff --git a/Documentation/networking/devlink/devlink-trap.rst b/Documentation/networking/devlink/devlink-trap.rst index 5885e21e221257..ac5bf9337198c5 100644 --- a/Documentation/networking/devlink/devlink-trap.rst +++ b/Documentation/networking/devlink/devlink-trap.rst @@ -516,9 +516,11 @@ Generic Packet Trap Groups Generic packet trap groups are used to aggregate logically related packet traps. These groups allow the user to batch operations such as setting the trap -action of all member traps. In addition, ``devlink-trap`` can report aggregated -per-group packets and bytes statistics, in case per-trap statistics are too -narrow. The description of these groups must be added to the following table: +action of all member drop traps whose action may legally change. Exception and +control traps remain unchanged. In addition, ``devlink-trap`` can report +aggregated per-group packets and bytes statistics, in case per-trap statistics +are too narrow. The description of these groups must be added to the following +table: .. list-table:: List of Generic Packet Trap Groups :widths: 10 90 diff --git a/Documentation/networking/devlink/index.rst b/Documentation/networking/devlink/index.rst index f7ba7dcf477d05..32f70879ddd06d 100644 --- a/Documentation/networking/devlink/index.rst +++ b/Documentation/networking/devlink/index.rst @@ -13,8 +13,8 @@ new APIs prefixed by ``devl_*``. The older APIs handle all the locking in devlink core, but don't allow registration of most sub-objects once the main devlink object is itself registered. The newer ``devl_*`` APIs assume the devlink instance lock is already held. Drivers can take the instance -lock by calling ``devl_lock()``. It is also held all callbacks of devlink -netlink commands. +lock by calling ``devl_lock()``. It is also held across all callbacks of +devlink netlink commands. Drivers are encouraged to use the devlink instance lock for their own needs. @@ -33,11 +33,11 @@ sure to respect following rules: lock of both nested and parent instances at the same time, devlink instance lock of the parent instance should be taken first, only then instance lock of the nested instance could be taken. - - Driver should use object-specific helpers to setup the - nested relationship: + - Driver should use object-specific helpers to setup the nested relationship + before registering the nested devlink instance: - ``devl_nested_devlink_set()`` - called to setup devlink -> nested - devlink relationship (could be user for multiple nested instances. + devlink relationship (could be used for multiple nested instances). - ``devl_port_fn_devlink_set()`` - called to setup port function -> nested devlink relationship. - ``devlink_linecard_nested_dl_set()`` - called to setup linecard -> diff --git a/Documentation/networking/devlink/stmmac.rst b/Documentation/networking/devlink/stmmac.rst index 47e3ff10bc0825..fbaa81ea782d50 100644 --- a/Documentation/networking/devlink/stmmac.rst +++ b/Documentation/networking/devlink/stmmac.rst @@ -24,7 +24,7 @@ The ``stmmac`` driver implements the following driver-specific parameters. - runtime - Enable the Coarse timestamping mode, as defined in the DWMAC TRM. A detailed explanation of this timestamping mode can be found in the - Socfpga Functionnal Description [1]. + Socfpga Functional Description [1]. In Coarse mode, the ptp clock is expected to be fed by a high-precision clock that is externally adjusted, and the subsecond increment used for diff --git a/Documentation/networking/devmem.rst b/Documentation/networking/devmem.rst index a6cd7236bfbd20..6a3f3c2ac19c42 100644 --- a/Documentation/networking/devmem.rst +++ b/Documentation/networking/devmem.rst @@ -103,24 +103,22 @@ The user must bind a dmabuf to any number of RX queues on a given NIC using the netlink API:: /* Bind dmabuf to NIC RX queue 15 */ - struct netdev_queue *queues; - queues = malloc(sizeof(*queues) * 1); + struct netdev_queue_id *queues; - queues[0]._present.type = 1; - queues[0]._present.idx = 1; - queues[0].type = NETDEV_RX_QUEUE_TYPE_RX; - queues[0].idx = 15; + queues = netdev_queue_id_alloc(1); + netdev_queue_id_set_type(&queues[0], NETDEV_QUEUE_TYPE_RX); + netdev_queue_id_set_id(&queues[0], 15); *ys = ynl_sock_create(&ynl_netdev_family, &yerr); req = netdev_bind_rx_req_alloc(); netdev_bind_rx_req_set_ifindex(req, 1 /* ifindex */); - netdev_bind_rx_req_set_dmabuf_fd(req, dmabuf_fd); - __netdev_bind_rx_req_set_queues(req, queues, n_queue_index); + netdev_bind_rx_req_set_fd(req, dmabuf_fd); + __netdev_bind_rx_req_set_queues(req, queues, 1); rsp = netdev_bind_rx(*ys, req); - dmabuf_id = rsp->dmabuf_id; + dmabuf_id = rsp->id; The netlink API returns a dmabuf_id: a unique ID that refers to this dmabuf @@ -302,13 +300,12 @@ The user should create a msghdr where, * iov_base is set to the offset into the dmabuf to start sending from * iov_len is set to the number of bytes to be sent from the dmabuf -The user passes the dma-buf id to send from via the dmabuf_tx_cmsg.dmabuf_id. +The user passes the dma-buf id to send from as a u32 cmsg payload. The example below sends 1024 bytes from offset 100 into the dmabuf, and 2048 from offset 2000 into the dmabuf. The dmabuf to send from is tx_dmabuf_id:: - char ctrl_data[CMSG_SPACE(sizeof(struct dmabuf_tx_cmsg))]; - struct dmabuf_tx_cmsg ddmabuf; + char ctrl_data[CMSG_SPACE(sizeof(__u32))]; struct msghdr msg = {}; struct cmsghdr *cmsg; struct iovec iov[2]; @@ -327,11 +324,9 @@ from offset 2000 into the dmabuf. The dmabuf to send from is tx_dmabuf_id:: cmsg = CMSG_FIRSTHDR(&msg); cmsg->cmsg_level = SOL_SOCKET; cmsg->cmsg_type = SCM_DEVMEM_DMABUF; - cmsg->cmsg_len = CMSG_LEN(sizeof(struct dmabuf_tx_cmsg)); + cmsg->cmsg_len = CMSG_LEN(sizeof(__u32)); - ddmabuf.dmabuf_id = tx_dmabuf_id; - - *((struct dmabuf_tx_cmsg *)CMSG_DATA(cmsg)) = ddmabuf; + *((__u32 *)CMSG_DATA(cmsg)) = tx_dmabuf_id; sendmsg(socket_fd, &msg, MSG_ZEROCOPY); diff --git a/Documentation/networking/driver.rst b/Documentation/networking/driver.rst index 4f5dfa9c022eca..920c0ec987594a 100644 --- a/Documentation/networking/driver.rst +++ b/Documentation/networking/driver.rst @@ -51,7 +51,7 @@ for a driver implementing scatter-gather this means: { u32 used = READ_ONCE(dr->prod) - READ_ONCE(dr->cons); - return dr->tx_ring_size - (used & bp->tx_ring_mask); + return dr->tx_ring_size - (used & dr->tx_ring_mask); } static netdev_tx_t drv_hard_start_xmit(struct sk_buff *skb, @@ -69,7 +69,7 @@ for a driver implementing scatter-gather this means: //... /* This should be a very rare race - log it. */ if (drv_tx_avail(dr) <= skb_shinfo(skb)->nr_frags + 1) { - netif_stop_queue(dev); + netif_tx_stop_queue(txq); netdev_warn(dev, "Tx Ring full when queue awake!\n"); return NETDEV_TX_BUSY; } @@ -103,6 +103,9 @@ Lockless queue stop / wake helper macros .. kernel-doc:: include/net/netdev_queues.h :doc: Lockless queue stopping / waking helpers. +The standard macros like netif_txq_maybe_stop(), netif_txq_try_stop() etc. +are well tested, prefer them over local synchronization schemes. + No exclusive ownership ---------------------- @@ -125,3 +128,16 @@ to be freed up. If you return NETDEV_TX_BUSY from the ndo_start_xmit method, you must not keep any reference to that SKB and you must not attempt to free it up. + +Error message reporting +======================= + +A number of driver configuration interfaces pass a Netlink extended ACK +(``extack``) object to the driver (either directly as an argument or +as a member of a parameter struct). The drivers should try to report +most errors via the ``extack`` object. System level exceptions, +indicating that system or device is misbehaving or is in bad state, +should continue to be reported to system logs. + +Messages should be passed **either** via ``extack`` **or** to system logs. +Drivers should not try to report the same information to both. diff --git a/Documentation/networking/dsa/dsa.rst b/Documentation/networking/dsa/dsa.rst index fd3c254ced1dca..42a99f5dfa2e2b 100644 --- a/Documentation/networking/dsa/dsa.rst +++ b/Documentation/networking/dsa/dsa.rst @@ -509,7 +509,7 @@ Device Tree ----------- DSA features a standardized binding which is documented in -``Documentation/devicetree/bindings/net/dsa/dsa.txt``. PHY/MDIO library helper +``Documentation/devicetree/bindings/net/dsa/dsa.yaml``. PHY/MDIO library helper functions such as ``of_get_phy_mode()``, ``of_phy_connect()`` are also used to query per-port PHY specific details: interface connection, MDIO bus location, etc. diff --git a/Documentation/networking/dsa/lan9303.rst b/Documentation/networking/dsa/lan9303.rst index ab81b4e0139e34..776572be265e1a 100644 --- a/Documentation/networking/dsa/lan9303.rst +++ b/Documentation/networking/dsa/lan9303.rst @@ -12,7 +12,7 @@ Driver details The driver is implemented as a DSA driver, see ``Documentation/networking/dsa/dsa.rst``. -See ``Documentation/devicetree/bindings/net/dsa/lan9303.txt`` for device tree +See ``Documentation/devicetree/bindings/net/dsa/smsc,lan9303.yaml`` for device tree binding. The LAN9303 can be managed both via MDIO and I2C, both supported by this driver. diff --git a/Documentation/networking/ip-sysctl.rst b/Documentation/networking/ip-sysctl.rst index 2e3a746fcc6da9..208f46967ee59b 100644 --- a/Documentation/networking/ip-sysctl.rst +++ b/Documentation/networking/ip-sysctl.rst @@ -489,7 +489,7 @@ tcp_ecn - INTEGER tcp_ecn_option - INTEGER Control Accurate ECN (AccECN) option sending when AccECN has been successfully negotiated during handshake. Send logic inhibits - sending AccECN options regarless of this setting when no AccECN + sending AccECN options regardless of this setting when no AccECN option has been seen for the reverse direction. Possible values are: @@ -2444,7 +2444,11 @@ fib_multipath_hash_policy - INTEGER Possible values: - - 0 - Layer 3 (source and destination addresses plus flow label) + - 0 - Layer 3 (source and destination addresses plus flow label). + For IPv6 TCP, the local ECMP path is selected from the socket + txhash rather than the flow label, and may change after a TCP + rehash event (such as a retransmission timeout) to recover from + path failure. The on-wire flow label is unaffected. - 1 - Layer 4 (standard 5-tuple) - 2 - Layer 3 or inner Layer 3 if present - 3 - Custom multipath hash. Fields used for multipath hash calculation diff --git a/Documentation/networking/ipvs-sysctl.rst b/Documentation/networking/ipvs-sysctl.rst index a556439f8be7b8..fe36f4fcd3a00d 100644 --- a/Documentation/networking/ipvs-sysctl.rst +++ b/Documentation/networking/ipvs-sysctl.rst @@ -56,6 +56,50 @@ conn_lfactor - INTEGER -4: grow if load goes above 6% (buckets = nodes * 16) 2: grow if load goes above 400% (buckets = nodes / 4) +conn_max - INTEGER + Limit for number of connections, per netns. + + Controls the soft and hard limit for number of connections. + Initially, the platform specific limit is assigned for init_net. + The value can be changed and later the soft limit propagated + to other networking namespaces. + + Privileged admin can change both limits up to the value of the + platform limit while the unprivileged admin can change only the + soft limit up to the value of the hard limit. + + For setups using conntrack=1 (CONFIG_IP_VS_NFCT for + Netfilter connection tracking) the connections can be + limited also by nf_conntrack_max. + + Limits for init_net: + + ======================= =============== ============= + \ soft limit hard limit + ======================= =============== ============= + create netns platform platform + priv admin 0 .. platform 0 .. platform + ======================= =============== ============= + + Limits for new netns: + + ======================= =============== ============= + \ soft limit hard limit + ======================= =============== ============= + create netns init_net:soft init_net:soft + priv admin 0 .. platform 0 .. platform + unpriv admin 0 .. hard N/A + ======================= =============== ============= + + Limits per platform: + + - 1,073,741,824 (2^30 for 64-bit) + - 16,777,216 (2^24 for 32-bit) + + Possible values: 0 .. platform limit + + Default: platform limit + conn_reuse_mode - INTEGER 1 - default diff --git a/Documentation/networking/mptcp-sysctl.rst b/Documentation/networking/mptcp-sysctl.rst index 1eb6af26b4a7ac..b9b5f58e06257c 100644 --- a/Documentation/networking/mptcp-sysctl.rst +++ b/Documentation/networking/mptcp-sysctl.rst @@ -21,6 +21,19 @@ add_addr_timeout - INTEGER (seconds) Default: 120 +add_addr_v6_port_drop_ts - BOOLEAN + Control whether preparing an ADD_ADDR with an IPv6 address and a port + should drop the TCP timestamps option to have enough option space to + send the signal. + + If there is not enough option space, and the TCP timestamps option + cannot be dropped, the signal cannot be sent. Note that dropping the TCP + timestamps option for one packet of the connection could disrupt some + middleboxes: even if it should be unlikely, they could drop the packet + or block the connection. This is a per-namespace sysctl. + + Default: 1 (enabled) + allow_join_initial_addr_port - BOOLEAN Allow peers to send join requests to the IP address and port number used by the initial subflow if the value is 1. This controls a flag that is diff --git a/Documentation/networking/napi.rst b/Documentation/networking/napi.rst index 4e008efebb352a..c719924f36ce90 100644 --- a/Documentation/networking/napi.rst +++ b/Documentation/networking/napi.rst @@ -49,7 +49,11 @@ instance to be released. The control APIs are not idempotent. Control API calls are safe against concurrent use of datapath APIs but an incorrect sequence of control API calls may result in crashes, deadlocks, or race conditions. For example, -calling napi_disable() multiple times in a row will deadlock. +calling napi_disable() multiple times in a row will hang waiting for +ownership of the NAPI instance to be released. + +Drivers using the netdev instance lock may need to use the ``_locked()`` +variants of the control APIs when that lock is already held. Datapath API ------------ @@ -190,7 +194,8 @@ User API ======== User interactions with NAPI depend on NAPI instance ID. The instance IDs -are only visible to the user thru the ``SO_INCOMING_NAPI_ID`` socket option. +are visible to the user through the ``SO_INCOMING_NAPI_ID`` socket option +and the netdev Netlink API. Users can query NAPI IDs for a device or device queue using netlink. This can be done programmatically in a user application or by using a script included in @@ -371,7 +376,7 @@ To use this mechanism: the application has stalled. This value should be chosen so that it covers the amount of time the user application needs to process data from its call to epoll_wait, noting that applications can control how much data - they retrieve by setting ``max_events`` when calling epoll_wait. + they retrieve by setting ``maxevents`` when calling epoll_wait. 2. The sysfs parameter or per-NAPI config parameters ``gro_flush_timeout`` and ``napi_defer_hard_irqs`` can be set to low values. They will be used diff --git a/Documentation/networking/net_cachelines/net_device.rst b/Documentation/networking/net_cachelines/net_device.rst index 1c19bb7705dfac..512f6d6fa3d8f8 100644 --- a/Documentation/networking/net_cachelines/net_device.rst +++ b/Documentation/networking/net_cachelines/net_device.rst @@ -10,7 +10,7 @@ Type Name fastpath_tx_acce =================================== =========================== =================== =================== =================================================================================== unsigned_long:32 priv_flags read_mostly __dev_queue_xmit(tx) unsigned_long:1 lltx read_mostly HARD_TX_LOCK,HARD_TX_TRYLOCK,HARD_TX_UNLOCK(tx) -unsigned long:1 netmem_tx:1; read_mostly +unsigned_long:2 netmem_tx:2; read_mostly char name[16] struct netdev_name_node* name_node struct dev_ifalias* ifalias @@ -90,8 +90,6 @@ struct inet6_dev* ip6_ptr read_mostly struct vlan_info* vlan_info struct dsa_port* dsa_ptr struct tipc_bearer* tipc_ptr -void* atalk_ptr -void* ax25_ptr struct wireless_dev* ieee80211_ptr struct wpan_dev* ieee802154_ptr struct mpls_dev* mpls_ptr diff --git a/Documentation/networking/net_cachelines/tcp_sock.rst b/Documentation/networking/net_cachelines/tcp_sock.rst index fecf61166a54ee..0f6088c4ab8bb8 100644 --- a/Documentation/networking/net_cachelines/tcp_sock.rst +++ b/Documentation/networking/net_cachelines/tcp_sock.rst @@ -13,16 +13,16 @@ u16 tcp_header_len read_mostly read_m u16 gso_segs read_mostly tcp_xmit_size_goal __be32 pred_flags read_write read_mostly tcp_select_window(tx);tcp_rcv_established(rx) u64 bytes_received read_write tcp_rcv_nxt_update(rx) -u32 segs_in read_write tcp_v6_rcv(rx) +u32 segs_in read_write read_write tcp_segs_in(),tcp_v6_rcv(rx),tcp_v4_rcv() u32 data_segs_in read_write tcp_v6_rcv(rx) u32 rcv_nxt read_mostly read_write tcp_cleanup_rbuf,tcp_send_ack,tcp_inq_hint,tcp_transmit_skb,tcp_receive_window(tx);tcp_v6_do_rcv,tcp_rcv_established,tcp_data_queue,tcp_receive_window,tcp_rcv_nxt_update(write)(rx) u32 copied_seq read_mostly tcp_cleanup_rbuf,tcp_rcv_space_adjust,tcp_inq_hint u32 rcv_wup read_write __tcp_cleanup_rbuf,tcp_receive_window,tcp_receive_established u32 snd_nxt read_write read_mostly tcp_rate_check_app_limited,__tcp_transmit_skb,tcp_event_new_data_sent(write)(tx);tcp_rcv_established,tcp_ack,tcp_clean_rtx_queue(rx) -u32 segs_out read_write __tcp_transmit_skb +u32 segs_out read_write read_write __tcp_transmit_skb u32 data_segs_out read_write __tcp_transmit_skb,tcp_update_skb_after_send u64 bytes_sent read_write __tcp_transmit_skb -u64 bytes_acked read_write tcp_snd_una_update/tcp_ack +u64 bytes_acked read_write tcp_snd_una_update/tcp_ack u32 dsack_dups u32 snd_una read_mostly read_write tcp_wnd_end,tcp_urg_mode,tcp_minshall_check,tcp_cwnd_validate(tx);tcp_ack,tcp_may_update_window,tcp_clean_rtx_queue(write),tcp_ack_tstamp(rx) u32 snd_sml read_write tcp_minshall_check,tcp_minshall_update @@ -99,8 +99,8 @@ u32 snd_cwnd_stamp u32 prior_cwnd u32 prr_delivered u32 prr_out read_mostly read_mostly tcp_rate_skb_sent,tcp_newly_delivered(tx);tcp_ack,tcp_rate_gen,tcp_clean_rtx_queue(rx) -u32 delivered read_mostly read_write tcp_rate_skb_sent, tcp_newly_delivered(tx);tcp_ack, tcp_rate_gen, tcp_clean_rtx_queue (rx) -u32 delivered_ce read_mostly read_write tcp_rate_skb_sent(tx);tcp_rate_gen(rx) +u32 delivered read_write tcp_rate_skb_sent, tcp_newly_delivered(tx);tcp_ack, tcp_rate_gen, tcp_clean_rtx_queue (rx) +u32 delivered_ce read_write tcp_rate_skb_sent(tx);tcp_rate_gen(rx) u32 received_ce read_mostly read_write u32[3] received_ecn_bytes read_mostly read_write u8:4 received_ce_pending read_mostly read_write diff --git a/Documentation/networking/netdev-features.rst b/Documentation/networking/netdev-features.rst index 02bd7536fc0ca2..f9e1f3921f537d 100644 --- a/Documentation/networking/netdev-features.rst +++ b/Documentation/networking/netdev-features.rst @@ -18,29 +18,38 @@ that relieve an OS of various tasks like generating and checking checksums, splitting packets, classifying them. Those capabilities and their state are commonly referred to as netdev features in Linux kernel world. -There are currently three sets of features relevant to the driver, and -one used internally by network core: +There are currently three main sets of features on each netdevice, +first and second are initialized by the driver: 1. netdev->hw_features set contains features whose state may possibly be changed (enabled or disabled) for a particular device by user's - request. This set should be initialized in ndo_init callback and not - changed later. + request. Drivers normally initialize this set before registration or + in the ndo_init callback. Changes after registration should be made + very carefully as other parts of the code may assume hw_features are + static. At the very least changes must be made under rtnl_lock and + the netdev instance lock, and followed by netdev_update_features(). 2. netdev->features set contains features which are currently enabled for a device. This should be changed only by network core or in error paths of ndo_set_features callback. - 3. netdev->vlan_features set contains features whose state is inherited - by child VLAN devices (limits netdev->features set). This is currently - used for all VLAN devices whether tags are stripped or inserted in - hardware or software. - - 4. netdev->wanted_features set contains feature set requested by user. + 3. netdev->wanted_features set contains feature set requested by user. This set is filtered by ndo_fix_features callback whenever it or some device-specific conditions change. This set is internal to networking core and should not be referenced in drivers. +On top of those three main sets, each netdev has: + + 1. Sets which control features inherited by child devices (VLAN, MPLS, + hw_enc for L3/L4 tunnels). These sets allow the driver to limit which + netdev->features are propagated, in case HW cannot perform the offloads + with the extra headers present. + + 2. netdev->mangleid_features, TSO features which are supported only when + IP ID field can be mangled (constant instead of incrementing) during TSO. + 3. netdev->gso_partial_features, additional TSO features which HW can + support via NETIF_F_GSO_PARTIAL. Part II: Controlling enabled features ===================================== @@ -62,11 +71,22 @@ ndo_*_features callbacks are called with rtnl_lock held. Missing callbacks are treated as always returning success. A driver that wants to trigger recalculation must do so by calling -netdev_update_features() while holding rtnl_lock. This should not be done -from ndo_*_features callbacks. netdev->features should not be modified by -driver except by means of ndo_fix_features callback. - - +netdev_update_features() while holding rtnl_lock. If the device uses the +netdev instance lock, that lock must be held as well. This should not be +done from ndo_*_features callbacks. netdev->features should not be modified +by driver except by means of ndo_fix_features callback. + +For "ops locked" drivers (see Documentation/networking/netdevices.rst), +ethtool callbacks that may end up invoking netdev_update_features() must +opt back into rtnl_lock by setting the matching ETHTOOL_OP_NEEDS_RTNL_* +bit in ``ethtool_ops::op_needs_rtnl``. The ethtool core then keeps +rtnl_lock held across those SET callbacks so the contract above still +holds. + +ndo_features_check is called for each skb before that skb is passed to +ndo_start_xmit. Driver may perform any non-trivial checks (e.g. exact +header geometry / length) and withdraw features like HW_CSUM or TSO, +requesting the networking stack to fall back to the software implementation. Part III: Implementation hints ============================== @@ -83,8 +103,9 @@ stateless). It can be called multiple times between successive ndo_set_features calls. Callback must not alter features contained in NETIF_F_SOFT_FEATURES or -NETIF_F_NEVER_CHANGE sets. The exception is NETIF_F_VLAN_CHALLENGED but -care must be taken as the change won't affect already configured VLANs. +NETIF_F_NEVER_CHANGE, except that NETIF_F_VLAN_CHALLENGED may be changed. +Care must be taken as changes to NETIF_F_VLAN_CHALLENGED won't affect already +configured VLANs. * ndo_set_features: @@ -186,10 +207,14 @@ Redundancy) frames from one port to another in hardware. * hsr-dup-offload This should be set for devices which duplicate outgoing HSR (High-availability -Seamless Redundancy) or PRP (Parallel Redundancy Protocol) tags automatically -frames in hardware. +Seamless Redundancy) or PRP (Parallel Redundancy Protocol) frames +automatically in hardware. + +Part V: Related device flags +============================ -* netmem-tx +* netdev->netmem_tx -This should be set for devices which support netmem TX. See -Documentation/networking/netmem.rst +This is not a netdev feature bit. Drivers support netmem TX by setting +netdev->netmem_tx to one of the values in enum netmem_tx_mode. +See Documentation/networking/netmem.rst. diff --git a/Documentation/networking/netdevices.rst b/Documentation/networking/netdevices.rst index 93e06e8d51a9ca..d2a238f8cc8b91 100644 --- a/Documentation/networking/netdevices.rst +++ b/Documentation/networking/netdevices.rst @@ -21,13 +21,14 @@ by free_netdev(). This is required to handle the pathological case cleanly alloc_netdev_mqs() / alloc_netdev() reserve extra space for driver private data which gets freed when the network device is freed. If separately allocated data is attached to the network device -(netdev_priv()) then it is up to the module exit handler to free that. +(extra pointers stored in the device private struct) then it is up +to the module exit handler to free that. There are two groups of APIs for registering struct net_device. First group can be used in normal contexts where ``rtnl_lock`` is not already held: register_netdev(), unregister_netdev(). Second group can be used when ``rtnl_lock`` is already held: -register_netdevice(), unregister_netdevice(), free_netdevice(). +register_netdevice(), unregister_netdevice(), free_netdev(). Simple drivers -------------- @@ -58,6 +59,7 @@ the register_netdev(), and unregister_netdev() functions: goto err_undo; /* net_device is visible to the user! */ + return 0; err_undo: /* ... undo the device setup ... */ @@ -73,7 +75,7 @@ the register_netdev(), and unregister_netdev() functions: Note that after calling register_netdev() the device is visible in the system. Users can open it and start sending / receiving traffic immediately, -or run any other callback, so all initialization must be done prior to +or run any other callback, so all initialization must be **complete** prior to registration. unregister_netdev() closes the device and waits for all users to be done @@ -157,7 +159,7 @@ register_netdevice() fails. The callback may be invoked with or without There is no explicit constructor callback, driver "constructs" the private netdev state after allocating it and before registration. -Setting struct net_device.needs_free_netdev makes core call free_netdevice() +Setting struct net_device.needs_free_netdev makes core call free_netdev() automatically after unregister_netdevice() when all references to the device are gone. It only takes effect after a successful call to register_netdevice() so if register_netdevice() fails driver is responsible for calling @@ -256,7 +258,7 @@ ndo_eth_ioctl: lock if the driver implements queue management or shaper API. Context: process -ndo_get_stats: +ndo_get_stats / ndo_get_stats64: Synchronization: RCU (can be called concurrently with the stats update path). Context: atomic (can't sleep under RCU) @@ -264,12 +266,9 @@ ndo_get_stats: ndo_start_xmit: Synchronization: __netif_tx_lock spinlock. - When the driver sets dev->lltx this will be - called without holding netif_tx_lock. In this case the driver - has to lock by itself when needed. - The locking there should also properly protect against - set_rx_mode. WARNING: use of dev->lltx is deprecated. - Don't use it for new drivers. + When the driver sets dev->lltx this will be called without holding + netif_tx_lock. dev->lltx is meant for software drivers only, since + they often have no per-queue state. Context: Process with BHs disabled or BH (timer), will be called with interrupts disabled by netconsole. @@ -304,11 +303,15 @@ ndo_change_rx_flags: lock if the driver implements queue management or shaper API. ndo_setup_tc: - ``TC_SETUP_BLOCK`` and ``TC_SETUP_FT`` are running under NFT locks - (i.e. no ``rtnl_lock`` and no device instance lock). The rest of - ``tc_setup_type`` types run under netdev instance lock if the driver + Locking depends on ``tc_setup_type``. For most types the callback + is invoked under ``rtnl_lock`` and netdev instance lock if the driver implements queue management or shaper API. + For ``TC_SETUP_BLOCK`` and ``TC_SETUP_FT`` ``rtnl_lock`` may or + may not be held, and the netdev instance lock is not held. + ``TC_SETUP_BLOCK`` runs under ``block->cb_lock`` and ``TC_SETUP_FT`` + runs under ``flowtable->flow_block_lock``. + Most ndo callbacks not specified in the list above are running under ``rtnl_lock``. In addition, netdev instance lock is taken as well if the driver implements queue management or shaper API. @@ -348,10 +351,6 @@ virtual and the physical device. To prevent deadlocks, the virtual device's lock must always be acquired before the physical device's (see ``netdev_nl_queue_create_doit``). -In the future, there will be an option for individual -drivers to opt out of using ``rtnl_lock`` and instead perform their control -operations directly under the netdev instance lock. - Device drivers are encouraged to rely on the instance lock where possible. For the (mostly software) drivers that need to interact with the core stack, @@ -372,9 +371,16 @@ the instance lock. struct ethtool_ops ------------------ -Similarly to ``ndos`` the instance lock is only held for select drivers. -For "ops locked" drivers all ethtool ops without exceptions should -be called under the instance lock. +For non-"ops locked" drivers ethtool_ops are executed under ``rtnl_lock``. + +For "ops locked" drivers, ``ethtool_ops``, unlike ``ndos``, run under +the instance lock **only**. Drivers may request that ``rtnl_lock`` +is held around specific operations (both SET and GET) by setting +appropriate bits in ``ethtool_ops::op_needs_rtnl`` (if the necessary +``ETHTOOL_OP_NEEDS_RTNL_*`` bit doesn't exist, just add it). +Commonly used core helpers which force drivers to selectively opt-in to +``rtnl_lock`` protection include ``netdev_update_features()``, +``netif_set_real_num_tx_queues()``, and phylink helpers. struct netdev_stat_ops ---------------------- @@ -412,6 +418,7 @@ The following netdev notifiers are always run under the instance lock: For devices with locked ops, currently only the following notifiers are running under the lock: * ``NETDEV_CHANGE`` +* ``NETDEV_CHANGENAME`` * ``NETDEV_REGISTER`` * ``NETDEV_UP`` @@ -426,6 +433,8 @@ exceptions) notifiers run under the instance lock. Please extend this documentation whenever you make explicit assumption about lock being held from a notifier. +Drivers **must not** generate nested notifications of the ops-locked types. + NETDEV_INTERNAL symbol namespace ================================ diff --git a/Documentation/networking/netmem.rst b/Documentation/networking/netmem.rst index b63aded4633707..217869d1108dd9 100644 --- a/Documentation/networking/netmem.rst +++ b/Documentation/networking/netmem.rst @@ -95,4 +95,10 @@ Driver TX Requirements netdev@, or reach out to the maintainers and/or almasrymina@google.com for help adding the netmem API. -2. Driver should declare support by setting `netdev->netmem_tx = true` +2. Driver should declare support by setting `netdev->netmem_tx` to the + appropriate mode: + + - `NETMEM_TX_DMA`: for physical devices that perform DMA. + + - `NETMEM_TX_NO_DMA`: for virtual or passthrough devices that do + not DMA, but still support handling of netmem-backed skbs. diff --git a/Documentation/networking/page_pool.rst b/Documentation/networking/page_pool.rst index 9d958128a57cbc..817f8b78d24604 100644 --- a/Documentation/networking/page_pool.rst +++ b/Documentation/networking/page_pool.rst @@ -43,18 +43,32 @@ Architecture overview Monitoring ========== -Information about page pools on the system can be accessed via the netdev -genetlink family (see Documentation/netlink/specs/netdev.yaml). +Information about allocated page pools, their memory use, recycling statistics +etc. can be accessed via the netdev genetlink family +(see Documentation/netlink/specs/netdev.yaml). + +Statistics +---------- + +.. kernel-doc:: include/net/page_pool/types.h + :identifiers: struct page_pool_recycle_stats + struct page_pool_alloc_stats + struct page_pool_stats API interface ============= -The number of pools created **must** match the number of hardware queues +The number of pools created **must** match the number of NAPI contexts / queues unless hardware restrictions make that impossible. This would otherwise beat the purpose of page pool, which is allocate pages fast from cache without locking. This lockless guarantee naturally comes from running under a NAPI softirq. The protection doesn't strictly have to be NAPI, any guarantee that allocating a page will cause no race conditions is enough. +If ``params.napi`` is set, the NAPI instance must be the sole consumer +context for pages allocated from the pool. In other words, when running in +that NAPI context, the page pool may safely access consumer-side resources +**without any additional locking**. + .. kernel-doc:: net/core/page_pool.c :identifiers: page_pool_create @@ -69,7 +83,7 @@ a page will cause no race conditions is enough. page_pool_get_dma_addr page_pool_get_dma_dir .. kernel-doc:: net/core/page_pool.c - :identifiers: page_pool_put_page_bulk page_pool_get_stats + :identifiers: page_pool_put_page_bulk DMA sync -------- @@ -98,29 +112,12 @@ If in doubt set ``offset`` to 0, ``max_len`` to ``PAGE_SIZE`` and pass -1 as ``dma_sync_size``. That combination of arguments is always correct. -Note that the syncing parameters are for the entire page. -This is important to remember when using fragments (``PP_FLAG_PAGE_FRAG``), -where allocated buffers may be smaller than a full page. +Note that the syncing parameters are for the **entire page**, even if +the driver allocates fragments (e.g. via ``page_pool_dev_alloc_frag()``). Unless the driver author really understands page pool internals it's recommended to always use ``offset = 0``, ``max_len = PAGE_SIZE`` with fragmented page pools. -Stats API and structures ------------------------- -If the kernel is configured with ``CONFIG_PAGE_POOL_STATS=y``, the API -page_pool_get_stats() and structures described below are available. -It takes a pointer to a ``struct page_pool`` and a pointer to a struct -page_pool_stats allocated by the caller. - -Older drivers expose page pool statistics via ethtool or debugfs. -The same statistics are accessible via the netlink netdev family -in a driver-independent fashion. - -.. kernel-doc:: include/net/page_pool/types.h - :identifiers: struct page_pool_recycle_stats - struct page_pool_alloc_stats - struct page_pool_stats - Coding examples =============== @@ -140,7 +137,7 @@ Registration pp_params.pool_size = DESC_NUM; pp_params.nid = NUMA_NO_NODE; pp_params.dev = priv->dev; - pp_params.napi = napi; /* only if locking is tied to NAPI */ + pp_params.napi = napi; /* only if this NAPI is the sole consumer, see above */ pp_params.dma_dir = xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE; page_pool = page_pool_create(&pp_params); @@ -174,21 +171,6 @@ NAPI poller } } -Stats ------ - -.. code-block:: c - - #ifdef CONFIG_PAGE_POOL_STATS - /* retrieve stats */ - struct page_pool_stats stats = { 0 }; - if (page_pool_get_stats(page_pool, &stats)) { - /* perhaps the driver reports statistics with ethool */ - ethtool_print_allocation_stats(&stats.alloc_stats); - ethtool_print_recycle_stats(&stats.recycle_stats); - } - #endif - Driver unload ------------- diff --git a/Documentation/networking/segmentation-offloads.rst b/Documentation/networking/segmentation-offloads.rst index 72f69b22b28c58..25a8b7eca847a5 100644 --- a/Documentation/networking/segmentation-offloads.rst +++ b/Documentation/networking/segmentation-offloads.rst @@ -14,10 +14,13 @@ to take advantage of segmentation offload capabilities of various NICs. The following technologies are described: * TCP Segmentation Offload - TSO * UDP Fragmentation Offload - UFO + * UDP Segmentation Offload - USO * IPIP, SIT, GRE, and UDP Tunnel Offloads * Generic Segmentation Offload - GSO * Generic Receive Offload - GRO * Partial Generic Segmentation Offload - GSO_PARTIAL + * ESP Segmentation Offload + * Fraglist Generic Segmentation Offload - GSO_FRAGLIST * SCTP acceleration with GSO - GSO_BY_FRAGS @@ -38,7 +41,8 @@ In order to support TCP segmentation offload it is necessary to populate the network and transport header offsets of the skbuff so that the device drivers will be able determine the offsets of the IP or IPv6 header and the TCP header. In addition as CHECKSUM_PARTIAL is required csum_start should -also point to the TCP header of the packet. +also point to the TCP header of the packet, or to the inner transport header +for encapsulated TSO. For IPv4 segmentation we support one of two types in terms of the IP ID. The default behavior is to increment the IP ID with every segment. If the @@ -57,6 +61,10 @@ DF bit is not set on the outer header, in which case the device driver must guarantee that the IP ID field is incremented in the outer header with every segment. +SKB_GSO_TCP_ACCECN is a modifier used with TCP segmentation offload for +AccECN packets where the CWR bit must not be cleared during segmentation. +Devices advertise support for this using NETIF_F_GSO_ACCECN. + UDP Fragmentation Offload ========================= @@ -71,6 +79,16 @@ still receive them from tuntap and similar devices. Offload of UDP-based tunnel protocols is still supported. +UDP Segmentation Offload +======================== + +UDP segmentation offload allows a device to segment a large UDP packet into +multiple UDP datagrams. Unlike UFO, these are not IP fragments. The payload +size of each datagram is specified in skb_shinfo()->gso_size and the GSO type +is SKB_GSO_UDP_L4. Devices advertise support for this using +NETIF_F_GSO_UDP_L4. + + IPIP, SIT, GRE, UDP Tunnel, and Remote Checksum Offloads ======================================================== @@ -154,6 +172,23 @@ that the IPv4 ID field is incremented in the case that a given header does not have the DF bit set. +ESP Segmentation Offload +======================== + +ESP segmentation offload uses SKB_GSO_ESP to mark packets that require +IPsec ESP segmentation. This type is set by the XFRM output path for GSO +packets handled by ESP hardware offload. + + +Fraglist Generic Segmentation Offload +===================================== + +Fraglist GSO uses SKB_GSO_FRAGLIST to mark packets whose segments are +already arranged as a list of skbs. The segmentation path splits the skb +based on that list rather than by creating segments of skb_shinfo()->gso_size +bytes from the linear and page-fragment data. + + SCTP acceleration with GSO =========================== diff --git a/Documentation/networking/skbuff.rst b/Documentation/networking/skbuff.rst index 5b74275a73a3b8..94681523e345ff 100644 --- a/Documentation/networking/skbuff.rst +++ b/Documentation/networking/skbuff.rst @@ -29,9 +29,3 @@ dataref and headerless skbs .. kernel-doc:: include/linux/skbuff.h :doc: dataref and headerless skbs - -Checksum information --------------------- - -.. kernel-doc:: include/linux/skbuff.h - :doc: skb checksums diff --git a/Documentation/networking/smc-sysctl.rst b/Documentation/networking/smc-sysctl.rst index a8b4f357174efb..93cc6244f6c85d 100644 --- a/Documentation/networking/smc-sysctl.rst +++ b/Documentation/networking/smc-sysctl.rst @@ -86,7 +86,7 @@ smcr_max_send_wr - INTEGER Please be aware that all the buffers need to be allocated as a physically continuous array in which each element is a single buffer and has the size of SMC_WR_BUF_SIZE (48) bytes. If the allocation fails, we keep retrying - with half of the buffer count until it is ether successful or (unlikely) + with half of the buffer count until it is either successful or (unlikely) we dip below the old hard coded value which is 16 where we give up much like before having this control. @@ -100,14 +100,14 @@ smcr_max_recv_wr - INTEGER depending on the workload it can be a bottleneck in a sense that threads have to wait for work request buffers to become available. Before the introduction of this control the maximal number of work request buffers - available on the receive path used to be hard coded to 16. With this control + available on the receive path used to be hard coded to 48. With this control it becomes configurable. The acceptable range is between 2 and 2048. Please be aware that all the buffers need to be allocated as a physically continuous array in which each element is a single buffer and has the size of SMC_WR_BUF_SIZE (48) bytes. If the allocation fails, we keep retrying - with half of the buffer count until it is ether successful or (unlikely) - we dip below the old hard coded value which is 16 where we give up much + with half of the buffer count until it is either successful or (unlikely) + we dip below the old hard coded value which is 48 where we give up much like before having this control. Default: 48 diff --git a/Documentation/networking/statistics.rst b/Documentation/networking/statistics.rst index 66b0ef941457c8..824ebc54938395 100644 --- a/Documentation/networking/statistics.rst +++ b/Documentation/networking/statistics.rst @@ -231,8 +231,19 @@ Kernel-internal data structures ------------------------------- The following structures are internal to the kernel, their members are -translated to netlink attributes when dumped. Drivers must not overwrite -the statistics they don't report with 0. - -- ethtool_pause_stats() -- ethtool_fec_stats() +translated to netlink attributes when dumped. Fields are pre-initialized +to ``ETHTOOL_STAT_NOT_SET`` (by ``ethtool_stats_init()``); drivers must +leave fields they do not report at that value rather than overwriting +them with 0. + +- ``struct ethtool_eth_ctrl_stats`` +- ``struct ethtool_eth_mac_stats`` +- ``struct ethtool_eth_phy_stats`` +- ``struct ethtool_fec_hist`` +- ``struct ethtool_fec_stats`` +- ``struct ethtool_link_ext_stats`` +- ``struct ethtool_mm_stats`` +- ``struct ethtool_pause_stats`` +- ``struct ethtool_phy_stats`` +- ``struct ethtool_rmon_stats`` +- ``struct ethtool_ts_stats`` diff --git a/Documentation/networking/strparser.rst b/Documentation/networking/strparser.rst index 8dc6bb04c710be..372106b61e6512 100644 --- a/Documentation/networking/strparser.rst +++ b/Documentation/networking/strparser.rst @@ -40,8 +40,8 @@ Functions :: - strp_init(struct strparser *strp, struct sock *sk, - const struct strp_callbacks *cb) + int strp_init(struct strparser *strp, struct sock *sk, + const struct strp_callbacks *cb) Called to initialize a stream parser. strp is a struct of type strparser that is allocated by the upper layer. sk is the TCP @@ -95,7 +95,7 @@ Functions void strp_data_ready(struct strparser *strp); - The upper layer calls strp_tcp_data_ready when data is ready on + The upper layer calls strp_data_ready when data is ready on the lower socket for strparser to process. This should be called from a data_ready callback that is set on the socket. Note that maximum messages size is the limit of the receive socket @@ -123,9 +123,9 @@ There are seven callbacks: should parse the sk_buff as containing the headers for the next application layer message in the stream. - The skb->cb in the input skb is a struct strp_msg. Only - the offset field is relevant in parse_msg and gives the offset - where the message starts in the skb. + The strparser metadata in the input skb can be accessed with + strp_msg(skb). Only the offset field is relevant in parse_msg and + gives the offset where the message starts in the skb. The return values of this function are: @@ -176,11 +176,11 @@ There are seven callbacks: received in rcv_msg (see strp_pause above). This callback must be set. - The skb->cb in the input skb is a struct strp_msg. This - struct contains two fields: offset and full_len. Offset is - where the message starts in the skb, and full_len is the - the length of the message. skb->len - offset may be greater - than full_len since strparser does not trim the skb. + The strparser metadata in the input skb can be accessed with + strp_msg(skb). This struct contains two fields: offset and full_len. + Offset is where the message starts in the skb, and full_len is + the length of the message. skb->len - offset may be greater than + full_len since strparser does not trim the skb. :: diff --git a/Documentation/networking/tcp_ao.rst b/Documentation/networking/tcp_ao.rst index d5b6d0df63c351..55304037aa814c 100644 --- a/Documentation/networking/tcp_ao.rst +++ b/Documentation/networking/tcp_ao.rst @@ -7,9 +7,9 @@ TCP Authentication Option Linux implementation (RFC5925) TCP Authentication Option (TCP-AO) provides a TCP extension aimed at verifying segments between trusted peers. It adds a new TCP header option with a Message Authentication Code (MAC). MACs are produced from the content -of a TCP segment using a hashing function with a password known to both peers. +of a TCP segment using a key known to both peers. The intent of TCP-AO is to deprecate TCP-MD5 providing better security, -key rotation and support for a variety of hashing algorithms. +key rotation and support for a variety of MAC algorithms. 1. Introduction =============== @@ -19,16 +19,18 @@ key rotation and support for a variety of hashing algorithms. +----------------------+------------------------+-----------------------+ | | TCP-MD5 | TCP-AO | +======================+========================+=======================+ - |Supported hashing |MD5 |Must support HMAC-SHA1 | - |algorithms |(cryptographically weak)|(chosen-prefix attacks)| - | | |and CMAC-AES-128 (only | - | | |side-channel attacks). | - | | |May support any hashing| - | | |algorithm. | + |Supported MAC |MD5 of data and key |HMAC-SHA-1-96 and | + |algorithms |(cryptographically weak)|AES-128-CMAC-96. | + | | |Implementations are | + | | |permitted to support | + | | |additional algorithms. | +----------------------+------------------------+-----------------------+ - |Length of MACs (bytes)|16 |Typically 12-16. | - | | |Other variants that fit| - | | |TCP header permitted. | + |Length of MACs (bytes)|16 |12 for HMAC-SHA-1-96 | + | | |and AES-128-CMAC-96. | + | | |Implementations are | + | | |permitted to support | + | | |any MAC length that | + | | |fits in the TCP header.| +----------------------+------------------------+-----------------------+ |Number of keys per |1 |Many | |TCP connection | | | @@ -296,6 +298,20 @@ userspace manage TCP-AO on a per-socket basis. In order to add/delete MKTs It is not allowed to add a key on an established non-TCP-AO connection as well as to remove the last key from TCP-AO connection. +``TCP_AO_ADD_KEY`` allows the MAC algorithm and MAC length to be selected. +Linux supports the mandatory-to-implement algorithms HMAC-SHA-1-96 and +AES-128-CMAC-96. In addition, as Linux extensions, it supports: + +- HMAC-SHA256. Linux uses HMAC-SHA256 in the same way as HMAC-SHA1; this + includes omitting an explicit entropy extraction step. To work around the + missing entropy extraction, users should provide keys with full entropy. The + implementation is interoperable with other implementations of HMAC-SHA256 for + TCP-AO only when they have implemented the key derivation the same way (and + also the same MAC length is selected on each side). + +- Any MAC length for any of the supported MAC algorithms, provided it fits in + the TCP header and is at least 4 bytes. + ``setsockopt(TCP_AO_DEL_KEY)`` command may specify ``tcp_ao_del::current_key`` + ``tcp_ao_del::set_current`` and/or ``tcp_ao_del::rnext`` + ``tcp_ao_del::set_rnext`` which makes such delete "forced": it diff --git a/Documentation/networking/tls-offload.rst b/Documentation/networking/tls-offload.rst index c173f537bf4dd4..e5802bcd4d22de 100644 --- a/Documentation/networking/tls-offload.rst +++ b/Documentation/networking/tls-offload.rst @@ -13,7 +13,7 @@ Layer Protocol (ULP) and install the cryptographic connection state. For details regarding the user-facing interface refer to the TLS documentation in :ref:`Documentation/networking/tls.rst `. -``ktls`` can operate in three modes: +``ktls`` can operate in two modes: * Software crypto mode (``TLS_SW``) - CPU handles the cryptography. In most basic cases only crypto operations synchronous with the CPU @@ -26,11 +26,6 @@ documentation in :ref:`Documentation/networking/tls.rst `. This mode integrates best with the kernel stack and is described in detail in the remaining part of this document (``ethtool`` flags ``tls-hw-tx-offload`` and ``tls-hw-rx-offload``). - * Full TCP NIC offload mode (``TLS_HW_RECORD``) - mode of operation where - NIC driver and firmware replace the kernel networking stack - with its own TCP handling, it is not usable in production environments - making use of the Linux networking stack for example any firewalling - abilities or QoS and packet scheduling (``ethtool`` flag ``tls-hw-record``). The operation mode is selected automatically based on device configuration, offload opt-in or opt-out on per-connection basis is not currently supported. @@ -104,6 +99,29 @@ at the end of kernel structures (see :c:member:`driver_state` members in ``include/net/tls.h``) to avoid additional allocations and pointer dereferences. +When the offloaded connection is destroyed the core calls +the :c:member:`tls_dev_del` callback so the driver can release per-direction +state: + +.. code-block:: c + + void (*tls_dev_del)(struct net_device *netdev, + struct tls_context *ctx, + enum tls_offload_ctx_dir direction); + +``tls_dev_del`` is mandatory whenever ``tls_dev_add`` is provided. + +The third TLS device callback is :c:member:`tls_dev_resync`, called by the core +to synchronize the TCP stream with the record boundaries: + +.. code-block:: c + + int (*tls_dev_resync)(struct net_device *netdev, + struct sock *sk, u32 seq, u8 *rcd_sn, + enum tls_offload_ctx_dir direction); + +See the `Resync handling`_ section for details. + TX -- @@ -255,9 +273,9 @@ Following helper should be used to test if resync is complete: bool tls_offload_tx_resync_pending(struct sock *sk) Next time ``ktls`` pushes a record it will first send its TCP sequence number -and TLS record number to the driver. Stack will also make sure that -the new record will start on a segment boundary (like it does when -the connection is initially added). +and TLS record number to the driver via the ``tls_dev_resync`` callback. +The stack will also make sure that the new record will start on a segment +boundary (like it does when the connection is initially added). RX -- @@ -349,9 +367,10 @@ all TLS record headers that have been logged since the resync request started. The kernel confirms the guessed location was correct and tells the device -the record sequence number. Meanwhile, the device had been parsing -and counting all records since the just-confirmed one, it adds the number -of records it had seen to the record number provided by the kernel. +the record sequence number via the ``tls_dev_resync`` callback. Meanwhile, +the device had been parsing and counting all records since the just-confirmed +one, it adds the number of records it had seen to the record number provided +by the kernel. At this point the device is in sync and can resume decryption at next segment boundary. @@ -375,12 +394,19 @@ schedules resynchronization after it has received two completely encrypted records. The stack waits for the socket to drain and informs the device about -the next expected record number and its TCP sequence number. If the +the next expected record number and its TCP sequence number via the +``tls_dev_resync`` callback. If the records continue to be received fully encrypted stack retries the synchronization with an exponential back off (first after 2 encrypted records, then after 4 records, after 8, after 16... up until every 128 records). +Rekey +===== + +Offload does not currently support TLS 1.3, therefore key rotation +is not a concern for offloaded connections at this point. + Error handling ============== diff --git a/Documentation/networking/xdp-rx-metadata.rst b/Documentation/networking/xdp-rx-metadata.rst index ce96f4c9950541..efdf5eeb49e782 100644 --- a/Documentation/networking/xdp-rx-metadata.rst +++ b/Documentation/networking/xdp-rx-metadata.rst @@ -36,7 +36,7 @@ metadata available in which case the driver returns ``-ENODATA``. Not all kfuncs have to be implemented by the device driver; when not implemented, the default ones that return ``-EOPNOTSUPP`` will be used -to indicate the device driver have not implemented this kfunc. +to indicate the device driver has not implemented this kfunc. Within an XDP frame, the metadata layout (accessed via ``xdp_buff``) is diff --git a/Documentation/networking/xfrm/index.rst b/Documentation/networking/xfrm/index.rst index 7d866da836fe76..90191848f8db90 100644 --- a/Documentation/networking/xfrm/index.rst +++ b/Documentation/networking/xfrm/index.rst @@ -9,5 +9,6 @@ XFRM Framework xfrm_device xfrm_proc + xfrm_migrate_state xfrm_sync xfrm_sysctl diff --git a/Documentation/networking/xfrm/xfrm_migrate_state.rst b/Documentation/networking/xfrm/xfrm_migrate_state.rst new file mode 100644 index 00000000000000..9d53cb22b00752 --- /dev/null +++ b/Documentation/networking/xfrm/xfrm_migrate_state.rst @@ -0,0 +1,274 @@ +.. SPDX-License-Identifier: GPL-2.0 + +===================== +XFRM SA Migrate State +===================== + +Overview +======== + +``XFRM_MSG_MIGRATE_STATE`` migrates a single SA, looked up using SPI and +mark, without involving policies. Unlike ``XFRM_MSG_MIGRATE``, which couples +SA and policy migration and allows migrating multiple SAs in one call, this +interface identifies the SA unambiguously via SPI and supports changing +the reqid, addresses, encapsulation, selector, and offload. + +Because IKE daemons can manage policies independently of +the kernel, this interface allows precise per-SA migration without +requiring policy involvement. Optional netlink attributes follow an +omit-to-inherit model: omitting an attribute preserves the value from +the old SA. The ``flags`` field controls two exceptions: hardware offload +is inherited by default and can be suppressed with +``XFRM_MIGRATE_STATE_CLEAR_OFFLOAD`` or overridden with ``XFRMA_OFFLOAD_DEV``; +the new selector is taken from ``new_sel`` by default and can instead be +derived from the new addresses with ``XFRM_MIGRATE_STATE_UPDATE_H2H_SEL``. + +SA Identification +================= + +The struct is defined in ``include/uapi/linux/xfrm.h``. The SA is looked +up using ``xfrm_state_lookup()`` with ``id.spi``, +``id.daddr``, ``id.proto``, ``id.family``, and +``old_mark.v & old_mark.m`` as the mark key:: + + struct xfrm_user_migrate_state { + struct xfrm_usersa_id id; /* spi, daddr, proto, family */ + xfrm_address_t new_daddr; + xfrm_address_t new_saddr; + struct xfrm_mark old_mark; /* SA lookup: key = v & m */ + struct xfrm_selector new_sel; /* new selector (see Flags) */ + __u32 new_reqid; + __u32 flags; /* XFRM_MIGRATE_STATE_* */ + __u16 new_family; + __u16 reserved; /* must be zero */ + }; + +The ``reserved`` field must be set to zero; the kernel rejects any +other value with ``-EINVAL``. + +Supported Attributes +==================== + +The following fields in ``xfrm_user_migrate_state`` are always explicit +and are not inherited from the existing SA. Passing zero is not equivalent +to "keep unchanged" — zero is used as-is: + +- ``new_daddr`` - new destination address +- ``new_saddr`` - new source address +- ``new_family`` - new address family +- ``new_reqid`` - new reqid (0 = no reqid) +- ``new_sel`` - new selector; used when ``XFRM_MIGRATE_STATE_UPDATE_H2H_SEL`` is + not set (see `Flags`_ below) +- ``flags`` - bitmask of ``XFRM_MIGRATE_STATE_*`` flags (see `Flags`_ below) + +The following netlink attributes are also accepted. Omitting an attribute +inherits the value from the existing SA (omit-to-inherit). + +.. list-table:: + :widths: 30 70 + :header-rows: 1 + + * - Attribute + - Description + * - ``XFRMA_MARK`` + - Mark on the migrated SA (``struct xfrm_mark``). Absent inherits + ``old_mark``. To use no mark on the new SA, send ``XFRMA_MARK`` + with ``{0, 0}``. + * - ``XFRMA_ENCAP`` + - UDP encapsulation template; only ``UDP_ENCAP_ESPINUDP`` is supported. + Set ``encap_type=0`` to remove encap. + * - ``XFRMA_OFFLOAD_DEV`` + - Hardware offload configuration (``struct xfrm_user_offload``). Absent + copies offload from the existing SA. When + ``XFRM_MIGRATE_STATE_CLEAR_OFFLOAD`` is set in ``flags``, the new SA has + no offload; this flag is mutually exclusive with ``XFRMA_OFFLOAD_DEV`` + and sending both returns ``-EINVAL``. + * - ``XFRMA_SET_MARK`` + - Output mark on the migrated SA; pair with ``XFRMA_SET_MARK_MASK``. + Send 0 to clear. + * - ``XFRMA_NAT_KEEPALIVE_INTERVAL`` + - NAT keepalive interval in seconds. Requires encap. Send 0 to clear. + Automatically cleared when encap is removed; setting a non-zero + value without encap returns ``-EINVAL``. + * - ``XFRMA_MTIMER_THRESH`` + - Mapping maxage threshold. Only valid on input SAs; setting on an + output SA returns ``-EINVAL``. Requires encap. Send 0 to clear. + Automatically cleared when encap is removed; setting a non-zero + value without encap returns ``-EINVAL``. + +The following SA properties are immutable and cannot be changed via +``XFRM_MSG_MIGRATE_STATE``: algorithms (``XFRMA_ALG_*``), replay state, +direction (``XFRMA_SA_DIR``), and security context (``XFRMA_SEC_CTX``). + +Flags +===== + +The ``flags`` field in ``xfrm_user_migrate_state`` controls optional +migration behaviour. Unknown flag bits are rejected with ``-EINVAL``; the +extended ACK message identifies the unrecognised bits (e.g. ``"Unknown flags: +0x4"``). Userspace can use ``XFRM_MIGRATE_STATE_KNOWN_FLAGS`` (defined in +````) to validate flags before sending; note that this constant +reflects the flags known to the header version userspace was compiled against, +which may differ from what the running kernel accepts. + +.. list-table:: + :widths: 40 60 + :header-rows: 1 + + * - Flag + - Description + * - ``XFRM_MIGRATE_STATE_CLEAR_OFFLOAD`` + - When set, the new SA has no hardware offload even when + ``XFRMA_OFFLOAD_DEV`` is absent. Without this flag, omitting + ``XFRMA_OFFLOAD_DEV`` copies the existing offload to the new SA. + Mutually exclusive with ``XFRMA_OFFLOAD_DEV``; sending both + returns ``-EINVAL``. + * - ``XFRM_MIGRATE_STATE_UPDATE_H2H_SEL`` + - When set, the kernel validates that the existing SA selector is a + single-host entry matching the SA addresses (``prefixlen_s == + prefixlen_d`` equal to 32 for IPv4 or 128 for IPv6, and addresses + matching ``id.daddr`` and ``props.saddr``). If the check passes, + the new selector is derived from ``new_daddr`` and ``new_saddr`` + with the single-host mask for ``new_family``. A mismatch returns + ``-EINVAL``. When this flag is not set, ``new_sel`` is used as-is + for the migrated SA. + +Migration Steps +=============== + +Outgoing SA +----------- + +To prevent cleartext traffic leaks, install a block policy before +migrating: + +#. Install a block policy to drop traffic on the affected selector. +#. Remove the old policy. +#. Call ``XFRM_MSG_MIGRATE_STATE`` for each SA. +#. Reinstall the policies. +#. Remove the block policy. + +If AES-GCM is in use, the block policy also prevents IV reuse during +the migration window. For other AEADs this step is not required for +IV safety, but skipping it allows a brief cleartext window. + +Incoming SA +----------- + +No block policy is needed. ``XFRM_MSG_MIGRATE_STATE`` atomically +transfers the sequence number and replay window from the old SA to +the new SA, so the new SA continues replay protection without a gap. +Call ``XFRM_MSG_MIGRATE_STATE`` for each SA directly. + +When accepting incoming traffic, be liberal during the migration +window: packets sent by the remote peer before it completed its own +migration may arrive out of order or slightly late. Dropping them +unnecessarily causes packet loss. A generous replay window reduces +the impact of reordering during migration. + +Block Policy and IV Safety +-------------------------- + +AES-GCM IV uniqueness is critical: reusing a (key, IV) pair allows +an attacker to recover the authentication subkey and forge +authentication tags, breaking both confidentiality and integrity. +This concern applies to outgoing SAs only — the remote peer controls +IV generation on incoming traffic. + +``XFRM_MSG_MIGRATE_STATE`` atomically copies the sequence number and +replay window from the old SA to the new SA and deletes the old SA. +The block policy serves two purposes: it prevents cleartext traffic +leaks during the migration window, and for AES-GCM it prevents IV +reuse by ensuring no outgoing packets are sent under the same key. +The atomic copy of the sequence number and replay window complements +this — together they eliminate both risks during migration. +The atomic copy also serves incoming SAs, ensuring replay protection +continues without a gap across the migration. + +Feature Detection +================= + +Userspace can probe for kernel support by sending a minimal +``XFRM_MSG_MIGRATE_STATE`` message with a non-zero non-existent SPI: + +- ``-EINVAL``: kernel predates ``XFRM_MSG_MIGRATE_STATE``; message type + is out of range +- ``-ENOPROTOOPT``: message type is known but ``CONFIG_XFRM_MIGRATE`` + is not enabled +- ``-ESRCH``: supported (SPI not found) + +Userspace Notification on Success +================================= + +On successful migration the kernel multicasts an +``XFRM_MSG_MIGRATE_STATE`` message to the ``XFRMNLGRP_MIGRATE`` group. +The fixed header is ``struct xfrm_user_migrate_state`` copied from the +request, followed by the same set of netlink attributes that are +accepted as input, with the differences noted below. + +Differences from the request +----------------------------- + +.. list-table:: + :widths: 25 75 + :header-rows: 1 + + * - Field / Attribute + - Difference + * - ``new_sel`` + - Contains the actual selector of the newly installed SA, not the + ``new_sel`` from the request. When + ``XFRM_MIGRATE_STATE_UPDATE_H2H_SEL`` is set the kernel derives the + selector from ``new_daddr`` / ``new_saddr``; the caller's + ``new_sel`` field is ignored in that case. The notification + always carries the real selector of the new SA. + * - ``XFRMA_SA_DIR`` + - Present in the notification (set from the direction of the new + SA) but **not accepted as input** — direction is immutable. + * - ``flags`` + - Echoed back as-is. ``XFRM_MIGRATE_STATE_CLEAR_OFFLOAD`` and + ``XFRM_MIGRATE_STATE_UPDATE_H2H_SEL`` describe the request that was + made, not a property of the resulting SA. + +Attributes in the notification +------------------------------- + +.. list-table:: + :widths: 30 70 + :header-rows: 1 + + * - Attribute + - Description + * - ``XFRMA_ENCAP`` + - UDP encapsulation template, if configured on the new SA. + * - ``XFRMA_OFFLOAD_DEV`` + - Hardware offload configuration, if active on the new SA. + * - ``XFRMA_MARK`` + - Mark on the new SA, if set. + * - ``XFRMA_SET_MARK`` + - Output mark on the new SA, if set. + * - ``XFRMA_SET_MARK_MASK`` + - Output mark mask, present together with ``XFRMA_SET_MARK``. + * - ``XFRMA_MTIMER_THRESH`` + - Mapping maxage threshold, if non-zero. + * - ``XFRMA_NAT_KEEPALIVE_INTERVAL`` + - NAT keepalive interval, if non-zero. + * - ``XFRMA_SA_DIR`` + - Direction of the new SA. + +Error Handling +============== + +If the target SA tuple (new daddr, SPI, proto, new family) is already +occupied, the operation returns ``-EEXIST`` before the migration begins. +The old SA remains intact and the operation is safe to retry after +resolving the conflict. + +If the target SA is deleted before the migration completes, the operation +returns ``-ESRCH``. No new SA is installed. Userspace should verify the +current SA state before retrying. + +If the multicast notification (``XFRMNLGRP_MIGRATE``) fails to send, +the migration itself has already completed successfully and the new SA +is installed. The operation returns success, 0, with an extack warning, +but listeners will not receive the migration event. diff --git a/Documentation/networking/xsk-tx-metadata.rst b/Documentation/networking/xsk-tx-metadata.rst index df53a10ccac34b..f240930ca1df68 100644 --- a/Documentation/networking/xsk-tx-metadata.rst +++ b/Documentation/networking/xsk-tx-metadata.rst @@ -14,9 +14,9 @@ General Design The headroom for the metadata is reserved via ``tx_metadata_len`` and ``XDP_UMEM_TX_METADATA_LEN`` flag in ``struct xdp_umem_reg``. The metadata length is therefore the same for every socket that shares the same umem. -The metadata layout is a fixed UAPI, refer to ``union xsk_tx_metadata`` in +The metadata layout is a fixed UAPI, refer to ``struct xsk_tx_metadata`` in ``include/uapi/linux/if_xdp.h``. Thus, generally, the ``tx_metadata_len`` -field above should contain ``sizeof(union xsk_tx_metadata)``. +field above should contain ``sizeof(struct xsk_tx_metadata)``. Note that in the original implementation the ``XDP_UMEM_TX_METADATA_LEN`` flag was not required. Applications might attempt to create a umem @@ -45,15 +45,16 @@ the metadata area is ignored by the kernel as well. The flags field enables the particular offload: - ``XDP_TXMD_FLAGS_TIMESTAMP``: requests the device to put transmission - timestamp into ``tx_timestamp`` field of ``union xsk_tx_metadata``. + timestamp into ``completion.tx_timestamp`` field of + ``struct xsk_tx_metadata``. - ``XDP_TXMD_FLAGS_CHECKSUM``: requests the device to calculate L4 - checksum. ``csum_start`` specifies byte offset of where the checksumming - should start and ``csum_offset`` specifies byte offset where the - device should store the computed checksum. + checksum. ``request.csum_start`` specifies byte offset of where the + checksumming should start and ``request.csum_offset`` specifies byte offset + where the device should store the computed checksum. - ``XDP_TXMD_FLAGS_LAUNCH_TIME``: requests the device to schedule the packet for transmission at a pre-determined time called launch time. The - value of launch time is indicated by ``launch_time`` field of - ``union xsk_tx_metadata``. + value of launch time is indicated by ``request.launch_time`` field of + ``struct xsk_tx_metadata``. Besides the flags above, in order to trigger the offloads, the first packet's ``struct xdp_desc`` descriptor should set ``XDP_TX_METADATA`` @@ -63,9 +64,9 @@ only the first chunk should carry the metadata. Software TX Checksum ==================== -For development and testing purposes its possible to pass +For development and testing purposes it's possible to pass ``XDP_UMEM_TX_SW_CSUM`` flag to ``XDP_UMEM_REG`` UMEM registration call. -In this case, when running in ``XDK_COPY`` mode, the TX checksum +In this case, when running in ``XDP_COPY`` mode, the TX checksum is calculated on the CPU. Do not enable this option in production because it will negatively affect performance. @@ -118,7 +119,7 @@ schedule with a 1-second cycle time, with all Tx Queues open at all times. The value of the launch time that is programmed in the Advanced Transmit Context Descriptor is a relative offset to the starting time of the Qbv -transmission window of the queue. The Frst flag of the descriptor can be +transmission window of the queue. The First flag of the descriptor can be set to schedule the packet for the next Qbv cycle. Therefore, the horizon of the launch time for i225 and i226 is the ending time of the next cycle of the Qbv transmission window of the queue. For example, when the Qbv @@ -129,9 +130,10 @@ running. Querying Device Capabilities ============================ -Every devices exports its offloads capabilities via netlink netdev family. -Refer to ``xsk-flags`` features bitmask in -``Documentation/netlink/specs/netdev.yaml``. +Every device exports its offload capabilities via the Netlink netdev family. +Query the ``xsk-features`` attribute in +``Documentation/netlink/specs/netdev.yaml``. Its bits are defined by the +``xsk-flags`` enum. - ``tx-timestamp``: device supports ``XDP_TXMD_FLAGS_TIMESTAMP`` - ``tx-checksum``: device supports ``XDP_TXMD_FLAGS_CHECKSUM`` diff --git a/Documentation/process/changes.rst b/Documentation/process/changes.rst index 9a99037270ff27..1ca8c5f73ad004 100644 --- a/Documentation/process/changes.rst +++ b/Documentation/process/changes.rst @@ -36,7 +36,7 @@ bindgen (optional) 0.71.1 bindgen --version binutils 2.30 ld -v bison 2.0 bison --version btrfs-progs 0.18 btrfs --version -Clang/LLVM (optional) 15.0.0 clang --version +Clang/LLVM (optional) 17.0.1 clang --version e2fsprogs 1.41.4 e2fsck -V flex 2.5.35 flex --version gdb 7.2 gdb --version @@ -53,7 +53,7 @@ mcelog 0.6 mcelog --version mkimage (optional) 2017.01 mkimage --version nfs-utils 1.0.5 showmount --version openssl & libcrypto 1.0.0 openssl version -pahole 1.22 pahole --version +pahole 1.26 pahole --version pcmciautils 004 pccardctl -V PPP 2.4.0 pppd --version procps 3.2.0 ps --version @@ -147,6 +147,11 @@ Since Linux 5.2, if CONFIG_DEBUG_INFO_BTF is selected, the build system generates BTF (BPF Type Format) from DWARF in vmlinux, a bit later from kernel modules as well. This requires pahole v1.22 or later. +Since Linux 7.0, kfuncs annotated with KF_IMPLICIT_ARGS require pahole v1.26 +or later. Without it, such kfuncs will have incorrect BTF prototypes in +vmlinux, causing BPF programs to fail to load with a "func_proto incompatible +with vmlinux" error. Many sched_ext kfuncs are affected. + It is found in the 'dwarves' or 'pahole' distro packages or from https://fedorapeople.org/~acme/dwarves/. diff --git a/Documentation/process/coding-style.rst b/Documentation/process/coding-style.rst index 35b381230f6e48..a8336582f60bfa 100644 --- a/Documentation/process/coding-style.rst +++ b/Documentation/process/coding-style.rst @@ -936,7 +936,7 @@ used. --------------------- The kernel provides the following general purpose memory allocators: -kmalloc(), kzalloc(), kmalloc_array(), kcalloc(), vmalloc(), and +kmalloc(), kzalloc(), kmalloc_objs(), kzalloc_objs(), vmalloc(), and vzalloc(). Please refer to the API documentation for further information about them. :ref:`Documentation/core-api/memory-allocation.rst ` @@ -945,7 +945,7 @@ The preferred form for passing a size of a struct is the following: .. code-block:: c - p = kmalloc(sizeof(*p), ...); + p = kmalloc_obj(*p, ...); The alternative form where struct name is spelled out hurts readability and introduces an opportunity for a bug when the pointer variable type is changed @@ -959,13 +959,13 @@ The preferred form for allocating an array is the following: .. code-block:: c - p = kmalloc_array(n, sizeof(...), ...); + p = kmalloc_objs(*p, n, ...); The preferred form for allocating a zeroed array is the following: .. code-block:: c - p = kcalloc(n, sizeof(...), ...); + p = kzalloc_objs(*p, n, ...); Both forms check for overflow on the allocation size n * sizeof(...), and return NULL if that occurred. diff --git a/Documentation/process/debugging/kgdb.rst b/Documentation/process/debugging/kgdb.rst index dd6a103073fafc..316b1d74e9c865 100644 --- a/Documentation/process/debugging/kgdb.rst +++ b/Documentation/process/debugging/kgdb.rst @@ -513,7 +513,7 @@ unregister all the kernel hook points. All kgdb I/O drivers can be reconfigured at run time, if ``CONFIG_SYSFS`` and ``CONFIG_MODULES`` are enabled, by echo'ing a new -config string to ``/sys/module//parameter/