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System Design with HDLs

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Name		Name	Last commit message	Last commit date
Assignment 1		Assignment 1
Assignment 2		Assignment 2
Assignment 3		Assignment 3
Assignment 3b		Assignment 3b
Assignment 4		Assignment 4
Lab 1		Lab 1
Lab 2		Lab 2
alu.vhd		alu.vhd
memory.vhd		memory.vhd
registers.vhd		registers.vhd
scheduler.vhd		scheduler.vhd
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System Design with HDLs

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