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RISC V 32 bit Base ISA Implementation.

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Tethorax: A RISC-V 32-bit Base ISA Implementation.

About the Project

The design and the implementation of this RV32I ISA was the subject of my Integrated Master's Degree Thesis at Computer Science and Engineering (University of Ioannina). The project began at mid-January and finished at June of the same year (2019). My work was supervised by professor Aristides Efthymiou.

For a detailed and complete analysis and report of my work, read the "Documentation.pdf"

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