Skip to content
Merged
Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
28 commits
Select commit Hold shift + click to select a range
492d9d9
Make MemAccess a sum type of fetch, read and write
kristinas Oct 21, 2026
060ea3a
Drop the secure core: remove the Access layer and its parameter f
kristinas Oct 21, 2026
ad49c6e
Rename memWriteWord to memWrite
kristinas Oct 21, 2026
2769b0f
Rename the stall reason MemoryBusBusy to NoInstruction
kristinas Oct 21, 2026
2d16bae
Put the address first in memWrite and write
kristinas Oct 21, 2026
3a2b6f9
Carry the halt resume address in the result registers
kristinas Oct 22, 2026
1195db5
Move the solver modules into proof/, keeping them behind the smt-proo…
kristinas Oct 23, 2026
e1684fb
Move ideal memory into src as Memory.Ideal
kristinas Oct 23, 2026
025c3c7
Move the ISA, instructions and register file into src/Core
kristinas Oct 27, 2026
8daeb79
Cache work on the insecure core (WIP, squashed)
kristinas Oct 21, 2026
e28d87b
Make the CPU input a single Maybe Word
kristinas Oct 21, 2026
e198e58
WIP: prefix the cache operations with cache, server rewrite in progress
kristinas Oct 21, 2026
174d82a
Rename memWriteWord to memWrite in the cache files, prefix Cache4K's …
kristinas Oct 21, 2026
6eeac41
Pass the address first to memWrite in the cache server
kristinas Oct 21, 2026
5ede056
Rename execute' to executeFresh, like the other stage bodies
kristinas Oct 21, 2026
3d878ef
Pass the address first to memWrite in the cache tests
kristinas Oct 21, 2026
dfbd94d
Move coherentAt from the cache to the server proof
kristinas Oct 21, 2026
ad365a2
Replace the load-in-flight state flag by a writeback control line
kristinas Oct 21, 2026
6c22564
Drop stateHaltNextPc from the cache proof and tests
kristinas Oct 22, 2026
6916e64
Group the core's proofs under Proof.Core.Functional and Proof.Core.Le…
kristinas Oct 23, 2026
6840c6d
Split the cache's hop into a driver and a machine, as for the core
kristinas Oct 23, 2026
699cbec
Prove the core behind the cache refines the core behind ideal memory
kristinas Oct 26, 2026
7baae65
Keep the full build green: register link 2, unlist the old cache modules
kristinas Oct 26, 2026
fbb49b2
Freeze the pipeline whenever memory has not answered
kristinas Oct 26, 2026
f6449ea
Reset the control lines at the end of every cycle as well
kristinas Oct 26, 2026
b87cb3a
Take link 2 out of the build; the coherent cache moves to the cache p…
kristinas Oct 26, 2026
533fa96
Make the cache's proof standalone, with a contract between core and c…
kristinas Oct 27, 2026
fe86ce1
State that the core's invariant gives the ISA the core's flushed state
kristinas Oct 27, 2026
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
72 changes: 19 additions & 53 deletions app/Main.hs
Original file line number Diff line number Diff line change
@@ -1,20 +1,18 @@
module Main (main) where

import Access
import Clash.Prelude hiding (Log, Ordering (..), Word, break, def, init, lift, log, resize)
import Control.Exception (catch)
import Control.Monad (when)
import Control.Monad.IO.Class (MonadIO, liftIO)
import qualified Core as Core
import Data.Functor.Identity
import Data.IORef
import Elf.ElfLoader
import Elf.Syscall (ProgramExitException (..), handleSyscall)
import Memory.IO (IOMemT, SecureIOMemT, ioMemInitSP, loadProgram, loadSecureProgram, newIOMem, newSecureIOMem, runIOMemT, runSecureIOMemT, secureIOMemInitSP)
import Memory.IO (IOMemT, ioMemInitSP, loadProgram, newIOMem, runIOMemT)
import Memory.Types
import Numeric (showHex)
import Options.Applicative
import RegFile
import Core.RegFile
import Simulate
import System.Exit (ExitCode (..), exitWith)
import Types (Word)
Expand All @@ -25,7 +23,6 @@ import Prelude hiding (Ordering (..), Word, break, init, log, map, not, repeat,
-- | Command line options
data Options = Options
{ optVerbose :: Bool
, optSecureMemory :: Bool
, optExecutable :: String
} deriving (Show)

Expand All @@ -36,13 +33,6 @@ verboseParser = switch
<> short 'v'
<> help "Enable verbose output (shows PC and instruction trace)" )

-- | Parser for secure memory flag
secureMemoryParser :: Parser Bool
secureMemoryParser = switch
( long "secure-memory"
<> short 's'
<> help "Enable secure memory tracking (PubSec mode)" )

-- | Parser for executable argument
executableParser :: Parser String
executableParser = strArgument
Expand All @@ -53,7 +43,6 @@ executableParser = strArgument
optionsParser :: Parser Options
optionsParser = Options
<$> verboseParser
<*> secureMemoryParser
<*> executableParser

-- | Program info for help generation
Expand All @@ -64,14 +53,13 @@ programInfo = info (optionsParser <**> helper)
<> header "uc-risc-v - RISC-V Simulator"
<> footer "Examples:\n\
\ uc-risc-v benchmark/bench_chacha20\n\
\ uc-risc-v --verbose benchmark/bench_blake2b\n\
\ uc-risc-v --secure-memory benchmark/bench_secure_memory" )
\ uc-risc-v --verbose benchmark/bench_blake2b" )

-- | Called by 'runElf' whenever the core halts on a syscall: optionally log the
-- state, remember it as the final state, and service the syscall.
instrument ::
(Access f, Show (f Word), MonadIO m, MonadMemory m) =>
String -> Bool -> IORef (Maybe (Core.State f)) -> Instrument f m
(MonadIO m, MonadMemory m) =>
String -> Bool -> IORef (Maybe Core.State) -> Instrument m
instrument modeName shouldLog finalStateRef s = do
let pc = Core.stateExPc s

Expand All @@ -98,42 +86,20 @@ runExecutable Options{..} = do

when optVerbose $ do
putStrLn $ "Entry point: 0x" P.++ showHex entryOffset ""
if optSecureMemory
then putStrLn "Starting execution in SECURE MEMORY mode..."
else putStrLn "Starting execution in standard mode..."

if optSecureMemory
then do
secureIOMem <- newSecureIOMem elf
finalStateRef <- newIORef Nothing
runSecureIOMemT secureIOMem $ do
loadSecureProgram elf
runElf
(instrument "SECURE" optVerbose finalStateRef)
(simulator @PubSec @(SecureIOMemT IO))
{ circuitState =
Core.initAt
(fromIntegral entryOffset)
(modifyRF 2 (pure $ secureIOMemInitSP secureIOMem) (initRF @PubSec))
}
finalState <- readIORef finalStateRef
case finalState of
Just state | Core.stateHalt state == Just Core.SecurityViolation ->
putStrLn "Program aborted due to security violation"
_ -> pure ()
else do
mem <- newIOMem elf
finalStateRef <- newIORef Nothing
runIOMemT mem $ do
loadProgram elf
runElf
(instrument "STANDARD" optVerbose finalStateRef)
(simulator @Identity @(IOMemT IO))
{ circuitState =
Core.initAt
(fromIntegral entryOffset)
(modifyRF 2 (pure $ ioMemInitSP mem) (initRF @Identity))
}
putStrLn "Starting execution..."

mem <- newIOMem elf
finalStateRef <- newIORef Nothing
runIOMemT mem $ do
loadProgram elf
runElf
(instrument "STANDARD" optVerbose finalStateRef)
(simulator @(IOMemT IO))
{ circuitState =
Core.initAt
(fromIntegral entryOffset)
(modifyRF 2 (ioMemInitSP mem) initRF)
}

when optVerbose $ putStrLn "Execution completed successfully"

Expand Down
62 changes: 41 additions & 21 deletions package.yaml
Original file line number Diff line number Diff line change
Expand Up @@ -19,9 +19,9 @@ extra-source-files:
# common to point users to the README.md file.
description: Please see the README on GitHub at <https://github.com/githubuser/aimcore#readme>

# The modules under proof-smt/ discharge their properties through an SMT solver
# while GHC compiles them, so building them needs a solver on PATH and takes as
# long as the solver does. Pantomime goes through SBV, and SBV's Z3 backend is
# The modules listed under the smt-proof flag in the library discharge their
# properties through an SMT solver while GHC compiles them, so building them
# needs a solver on PATH and takes as long as the solver does. Pantomime goes through SBV, and SBV's Z3 backend is
# pointed at a different binary with SBV_Z3; Z3 itself does not finish these in
# useful time, while bitwuzla discharges each in under a minute:
#
Expand Down Expand Up @@ -107,39 +107,52 @@ library:
- proof
when:
- condition: flag(smt-proof)
source-dirs: proof-smt
exposed-modules:
- Proof.Functional.Induction
- Proof.Leakage.Induction
- Proof.SMT.Array
- Proof.Cache.Functional.Solver
- Proof.Core.Functional.Solver
- Proof.Core.Leakage.Solver
- Proof.SMT.Axioms
- Proof.Cache.SMT.Array
- Proof.Cache.SMT.Axioms
- Proof.Cache.SMT.Coherent
- Proof.SMT.Logged
- Proof.SMT.Sanity
- Proof.SMT.System
- Proof.Core.Functional.System
cpp-options: -DSMT_PROOF
# Listed explicitly, with no automatic discovery: the solver modules above
# live in proof/ too, and must only be built with the smt-proof flag.
other-modules: []
exposed-modules:
- Proof.Machine
- Proof.Functional.Driver
- Proof.Functional.Invariant
- Proof.Functional.Obligation
- Proof.Leakage.Model
- Proof.Leakage.Simulator
- Proof.Leakage.Driver
- Proof.Leakage.Invariant
- Proof.Leakage.Obligation
- Access
- Proof.Cache.Functional.Contract
- Proof.Cache.Functional.Driver
- Proof.Cache.Functional.Invariant
- Proof.Cache.Functional.Obligation
- Proof.Cache.SMT.Raw
- Proof.SMT.Array
- Proof.Core.Functional.Machine
- Proof.Core.Functional.Driver
- Proof.Core.Functional.Invariant
- Proof.Core.Functional.Obligation
- Proof.Core.Leakage.Model
- Proof.Core.Leakage.Simulator
- Proof.Core.Leakage.Driver
- Proof.Core.Leakage.Invariant
- Proof.Core.Leakage.Obligation
- Core
- Elf.ElfLoader
- Elf.Syscall
- HardwareSim
- Instruction
- ISA
- Core.Instruction
- Core.ISA
- Memory.Types
- Memory.Ideal
- Memory.Vec
- Memory.ST
- Memory.IO
- Memory.Cache4K
- Memory.Cache4KServer
- Pretty
- RegFile
- Core.RegFile
- Simulate
- Types
- Util
Expand All @@ -160,6 +173,13 @@ tests:
aimcore-test:
main: Spec.hs
source-dirs: test
# Listed explicitly: Cache4KSpec and CompositionSpec are still written
# against the cache's old interface and wait for the cache's leakage proof.
other-modules:
- BenchmarkSpec
- InstructionSpec
- IsaSpec
- ProofSpec
when:
- condition: flag(smt-proof)
cpp-options: -DSMT_PROOF
Expand Down
119 changes: 0 additions & 119 deletions proof-smt/Proof/Functional/Induction.hs

This file was deleted.

Loading
Loading