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Rename SimMemAccess to SimDataAccess - #28
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The simulator's memory stage holds only data accesses, so SimMemAccess read like a counterpart of Core.Pipeline.MemAccess, which includes fetches. SimNoAccess was also easy to confuse with the observation NoAccess, which means the bus shows nothing. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
The Boolean in SimCachedSys says whether the simulator is ready to receive an input. Describing it as "the cache answered in the previous cycle" needed a made-up justification for its initial value True, since nothing has answered before the start. The field is now simCachedReady, and the comments on the type, its initial state and its step describe it as readiness. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
…mments The invariant and driver of link 2's leakage half still described the flag as "the last cycle brought an answer". They now call it readiness to receive an input, as the simulator itself does. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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The simulator's memory stage holds only data accesses, so SimMemAccess read like a counterpart of Core.Pipeline.MemAccess, which includes fetches. SimNoAccess was also easy to confuse with the observation NoAccess, which means the bus shows nothing.