Traffic Light Controller for a Three-Road Intersection (Verilog)

A Verilog finite state machine that cycles green signals across three main roads at an intersection, simulated and fitted with Quartus Prime for an Intel Cyclone V FPGA.

Stack: Verilog HDL, Intel Quartus Prime (21.1.1 Lite), ModelSim simulation, Cyclone V (5CGXFC7C7F23C8).

Quick start

1. Open Hackathon.qpf in Quartus Prime. The top-level entity is Hackathon (Hackathon.qsf).
2. Compile the project (Processing > Start Compilation).
3. To simulate, open Waveform.vwf in Quartus Prime and run the simulator. Simulation outputs are in simulation/.

The RTL is in Hackathon.v. Hackathon.v.bak is a copy of the same code with the module named traffic_light_controller.

Student

Name : Rhudhresh

Aim: To design and simulate a traffic light controller for an intersection of three main roads, where each road has equal priority. The controller should regulate the traffic flow efficiently, ensuring safety and smooth movement of vehicles while diverting the traffic to path 1 direction and disabling control in other directions. Apparatus Required:

1. Hardware Description Language (HDL) simulation environment such as Verilog or VHDL.
2. Simulation software like ModelSim for testing and verification.
3. FPGA development board (optional) for hardware implementation. Procedure:
4. Define the State Machine
5. Implement the State Machine in HDL
6. Simulate the Design
7. Test the Design
8. Optimize and Refine

State Table : • To define the states, inputs, outputs, and state transitions. • Let's denote the three main roads as MR1, MR2, and MR3. • Each road can have three possible states for its traffic light: Red, Yellow, and Green. Here's the state table:

• Each row represents a state transition along with the corresponding outputs for each main road. • The "Counter" column indicates the counts for each state before transitioning to the next state. • The "Current State" column represents the current state of the state machine. • The "Next State" column indicates the state to transition to after completing the counts. • The "MR1", "MR2", and "MR3" columns specify the traffic light states for each main road in the current state. • "Red", "Yellow", and "Green" denote the states of the traffic lights. • The lab table lists the counter as 0 to 9. The RTL in Hackathon.v counts 0 to 5, so each state lasts six clock cycles. See Status. Code:

RTL Schematic View

Output Waveforms

Roadmap

• The design compiles and fits. The fitter summary reports success for 5CGXFC7C7F23C8, using 6 ALMs, 12 registers and 11 pins (output_files/Hackathon.fit.summary).
• Simulation files and a programming file (output_files/Hackathon.sof) are included. The repository does not document a run on the board.
• The RTL has no yellow phase. The yellow_MR1, yellow_MR2 and yellow_MR3 outputs are declared but never driven high.
• The lab table shows different light patterns from the RTL. For example, the table gives MR3 green in the S_RED row, while the RTL turns all of MR3's lights off in that state.
• The RTL counts 0 to 5, not 0 to 9 as the lab table states.

License

GPL-3.0. See LICENSE.txt.

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Built by Rhudhresh R