A simple, 32-bit, in order, 5-stage interlocking pipelined RISC-V core. It fully supports RV32I (RISC-V User Manual v2.2) and partially conforms to RISC-V Privileged Architecture v1.1. It has been written in Verilog and simulated using Icarus Verilog and ModelSim.
This work is done in partial fulfillment of requirements of B. Tech (Electronics and Communication), SASTRA Deemed to be University, India.