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Normalize tinyAVR 0/1-series ATDFs to one pack version #261

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7 changes: 7 additions & 0 deletions CHANGELOG.md
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Expand Up @@ -13,6 +13,13 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
- `ATtiny412`: Fixed `TCA0` missing and a bunch of incorrect register fields ([#260]).
- Fixed compilation with the Bazel build system ([#251]). There was a symlink
check in our build script which interferes with Bazel's source organization.
- Normalized all tinyAVR 0/1-series vendor ATDFs to a single Microchip pack
version (`ATtiny_DFP.3.4.278`). The previous set mixed versions: some
parts were older schema-0.3 files that encoded `TCA` as a `class="union"`
register-group, which `atdf2svd` cannot handle (leaving the generated PAC
without `TCA0`). The `.278` pack encodes `TCA` as an ordinary
register-group, so `TCA0` is generated correctly. `attiny1614` was
additionally a pre-release schema-0.3 file with wrong CCL pin data.

[#251]: https://github.com/Rahix/avr-device/pull/251
[#252]: https://github.com/Rahix/avr-device/pull/252
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5 changes: 5 additions & 0 deletions patch/attiny1606.yaml
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@@ -0,0 +1,5 @@
_svd: ../svd/attiny1606.svd

_include:
- common/attiny-xmega/common.yaml
- common/attiny-xmega/0-series.yaml
5 changes: 5 additions & 0 deletions patch/attiny1614.yaml
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@@ -0,0 +1,5 @@
_svd: ../svd/attiny1614.svd

_include:
- common/attiny-xmega/common.yaml
- common/attiny-xmega/1-series.yaml
48 changes: 3 additions & 45 deletions patch/attiny816.yaml
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@@ -1,45 +1,3 @@
CRCSCAN:
CTRLB:
SRC:
_replace_enum:
FLASH: [0, "CRC on entire flash"]
BOOTAPP: [1, "CRC on boot and appl section of flash"]
BOOT: [2, "CRC on boot section of flash"]
MODE:
_replace_enum:
PRIORITY: [0, "Priority to flash"]

NVMCTRL:
CTRLA:
CMD:
_replace_enum:
NONE: [0, "No command"]
WP: [1, "Write page"]
ER: [2, "Erase page"]
ERWP: [3, "Erase and write page"]
PBC: [4, "Page buffer clear"]
CHER: [5, "Chip erase"]
EEER: [6, "EEPROM erase"]
WFU: [7, "Write fuse (PDI only)"]

SLPCTRL:
CTRLA:
SMODE:
_replace_enum:
IDLE: [0, "Idle mode"]
STANDBY: [1, "Standby Mode"]
PDOWN: [2, "Power-down Mode"]

TCD0:
EVCTRL?:
CFG:
_replace_enum:
NEITHER: [0, "Neither Filter nor Asynchronous Event is enabled"]
FILTERON: [1, "Input Capture Noise Cancellation Filter enabled"]
ASYNCON: [2, "Asynchronous Event output qualification enabled"]

USART0:
STATUS:
_modify:
WFB:
access: write-only
_include:
- common/attiny-xmega/common.yaml
- common/attiny-xmega/1-series.yaml
30 changes: 18 additions & 12 deletions vendor/attiny1604.atdf
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Expand Up @@ -515,7 +515,7 @@
index="0"
pad="PB0"/>
<signal field="PORTMUX.CTRLC.TCA00"
function="TCA0_ALT"
function="TCA0_ALT1"
group="WO"
index="0"
pad="PB3"/>
Expand Down Expand Up @@ -604,19 +604,19 @@
group="XDIR"
pad="PB0"/>
<signal field="PORTMUX.CTRLB.USART0"
function="USART0_ALT"
function="USART0_ALT1"
group="RXD"
pad="PA2"/>
<signal field="PORTMUX.CTRLB.USART0"
function="USART0_ALT"
function="USART0_ALT1"
group="TXD"
pad="PA1"/>
<signal field="PORTMUX.CTRLB.USART0"
function="USART0_ALT"
function="USART0_ALT1"
group="XCK"
pad="PA3"/>
<signal field="PORTMUX.CTRLB.USART0"
function="USART0_ALT"
function="USART0_ALT1"
group="XDIR"
pad="PA4"/>
</signals>
Expand Down Expand Up @@ -902,7 +902,7 @@
offset="0x05"
rw="RW"
size="1">
<bitfield caption="Sample lenght" mask="0x1F" name="SAMPLEN" rw="RW"/>
<bitfield caption="Sample length" mask="0x1F" name="SAMPLEN" rw="RW"/>
</register>
<register caption="Positive mux input"
initval="0x00"
Expand Down Expand Up @@ -1253,7 +1253,8 @@
<bitfield caption="Clock Source Selection"
mask="0x40"
name="CLKSRC"
rw="RW"/>
rw="RW"
values="CCL_CLKSRC"/>
<bitfield caption="Edge Detection Enable"
mask="0x80"
name="EDGEDET"
Expand Down Expand Up @@ -1313,7 +1314,8 @@
<bitfield caption="Clock Source Selection"
mask="0x40"
name="CLKSRC"
rw="RW"/>
rw="RW"
values="CCL_CLKSRC"/>
<bitfield caption="Edge Detection Enable"
mask="0x80"
name="EDGEDET"
Expand Down Expand Up @@ -1358,6 +1360,10 @@
<bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
</register>
</register-group>
<value-group caption="Clock Source Selection" name="CCL_CLKSRC">
<value caption="CLK_PER is clocking the LUT" name="CLKPER" value="0x0"/>
<value caption="IN[2] is clocking the LUT" name="IN2" value="0x1"/>
</value-group>
<value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
<value caption="Edge detector is disabled" name="DIS" value="0x0"/>
<value caption="Edge detector is enabled" name="EN" value="0x1"/>
Expand Down Expand Up @@ -1449,7 +1455,7 @@
offset="0x02"
rw="RW"
size="1">
<bitfield caption="lock ebable" mask="0x01" name="LOCKEN" rw="RW"/>
<bitfield caption="Lock enable" mask="0x01" name="LOCKEN" rw="RW"/>
</register>
<register caption="MCLK Status"
initval="0x00"
Expand Down Expand Up @@ -1508,8 +1514,8 @@
</register>
</register-group>
<value-group caption="Clock select" name="CLKCTRL_CLKSEL">
<value caption="20MHz internal oscillator" name="OSC20M" value="0x00"/>
<value caption="32KHz internal Ultra Low Power oscillator"
<value caption="16/20MHz internal oscillator" name="OSC20M" value="0x00"/>
<value caption="32.768kHz internal ultra low-power oscillator"
name="OSCULP32K"
value="0x01"/>
<value caption="External clock" name="EXTCLK" value="0x03"/>
Expand Down Expand Up @@ -3251,7 +3257,7 @@
<register caption="Revision ID"
name="REVID"
offset="0x01"
rw="RW"
rw="R"
size="1"/>
<register caption="External Break"
initval="0x00"
Expand Down
50 changes: 28 additions & 22 deletions vendor/attiny1606.atdf
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Expand Up @@ -185,7 +185,7 @@
index="0"
pad="PA4"/>
<signal field="PORTMUX.CTRLA.LUT0"
function="CCL_ALT"
function="CCL_ALT1"
group="LUT0_OUT"
index="0"
pad="PB4"/>
Expand All @@ -195,7 +195,7 @@
index="0"
pad="PA7"/>
<signal field="PORTMUX.CTRLA.LUT1"
function="CCL_ALT"
function="CCL_ALT1"
group="LUT1_OUT"
index="0"
pad="PC1"/>
Expand Down Expand Up @@ -594,19 +594,19 @@
pad="PA3"/>
<signal field="PORTMUX.CTRLB.SPI0" function="SPI0" group="SS" pad="PA4"/>
<signal field="PORTMUX.CTRLB.SPI0"
function="SPI0_ALT"
function="SPI0_ALT1"
group="MISO"
pad="PC1"/>
<signal field="PORTMUX.CTRLB.SPI0"
function="SPI0_ALT"
function="SPI0_ALT1"
group="MOSI"
pad="PC2"/>
<signal field="PORTMUX.CTRLB.SPI0"
function="SPI0_ALT"
function="SPI0_ALT1"
group="SCK"
pad="PC0"/>
<signal field="PORTMUX.CTRLB.SPI0"
function="SPI0_ALT"
function="SPI0_ALT1"
group="SS"
pad="PC3"/>
</signals>
Expand Down Expand Up @@ -636,7 +636,7 @@
index="0"
pad="PB0"/>
<signal field="PORTMUX.CTRLC.TCA00"
function="TCA0_ALT"
function="TCA0_ALT1"
group="WO"
index="0"
pad="PB3"/>
Expand All @@ -646,7 +646,7 @@
index="1"
pad="PB1"/>
<signal field="PORTMUX.CTRLC.TCA01"
function="TCA0_ALT"
function="TCA0_ALT1"
group="WO"
index="1"
pad="PB4"/>
Expand All @@ -656,7 +656,7 @@
index="2"
pad="PB2"/>
<signal field="PORTMUX.CTRLC.TCA02"
function="TCA0_ALT"
function="TCA0_ALT1"
group="WO"
index="2"
pad="PB5"/>
Expand All @@ -666,7 +666,7 @@
index="3"
pad="PA3"/>
<signal field="PORTMUX.CTRLC.TCA03"
function="TCA0_ALT"
function="TCA0_ALT1"
group="WO"
index="3"
pad="PC3"/>
Expand Down Expand Up @@ -696,7 +696,7 @@
index="0"
pad="PA5"/>
<signal field="PORTMUX.CTRLD.TCB0"
function="TCB0_ALT"
function="TCB0_ALT1"
group="WO"
index="0"
pad="PC0"/>
Expand Down Expand Up @@ -745,19 +745,19 @@
group="XDIR"
pad="PB0"/>
<signal field="PORTMUX.CTRLB.USART0"
function="USART0_ALT"
function="USART0_ALT1"
group="RXD"
pad="PA2"/>
<signal field="PORTMUX.CTRLB.USART0"
function="USART0_ALT"
function="USART0_ALT1"
group="TXD"
pad="PA1"/>
<signal field="PORTMUX.CTRLB.USART0"
function="USART0_ALT"
function="USART0_ALT1"
group="XCK"
pad="PA3"/>
<signal field="PORTMUX.CTRLB.USART0"
function="USART0_ALT"
function="USART0_ALT1"
group="XDIR"
pad="PA4"/>
</signals>
Expand Down Expand Up @@ -1043,7 +1043,7 @@
offset="0x05"
rw="RW"
size="1">
<bitfield caption="Sample lenght" mask="0x1F" name="SAMPLEN" rw="RW"/>
<bitfield caption="Sample length" mask="0x1F" name="SAMPLEN" rw="RW"/>
</register>
<register caption="Positive mux input"
initval="0x00"
Expand Down Expand Up @@ -1394,7 +1394,8 @@
<bitfield caption="Clock Source Selection"
mask="0x40"
name="CLKSRC"
rw="RW"/>
rw="RW"
values="CCL_CLKSRC"/>
<bitfield caption="Edge Detection Enable"
mask="0x80"
name="EDGEDET"
Expand Down Expand Up @@ -1454,7 +1455,8 @@
<bitfield caption="Clock Source Selection"
mask="0x40"
name="CLKSRC"
rw="RW"/>
rw="RW"
values="CCL_CLKSRC"/>
<bitfield caption="Edge Detection Enable"
mask="0x80"
name="EDGEDET"
Expand Down Expand Up @@ -1499,6 +1501,10 @@
<bitfield caption="Truth Table" mask="0xFF" name="TRUTH" rw="RW"/>
</register>
</register-group>
<value-group caption="Clock Source Selection" name="CCL_CLKSRC">
<value caption="CLK_PER is clocking the LUT" name="CLKPER" value="0x0"/>
<value caption="IN[2] is clocking the LUT" name="IN2" value="0x1"/>
</value-group>
<value-group caption="Edge Detection Enable select" name="CCL_EDGEDET">
<value caption="Edge detector is disabled" name="DIS" value="0x0"/>
<value caption="Edge detector is enabled" name="EN" value="0x1"/>
Expand Down Expand Up @@ -1590,7 +1596,7 @@
offset="0x02"
rw="RW"
size="1">
<bitfield caption="lock ebable" mask="0x01" name="LOCKEN" rw="RW"/>
<bitfield caption="Lock enable" mask="0x01" name="LOCKEN" rw="RW"/>
</register>
<register caption="MCLK Status"
initval="0x00"
Expand Down Expand Up @@ -1649,8 +1655,8 @@
</register>
</register-group>
<value-group caption="Clock select" name="CLKCTRL_CLKSEL">
<value caption="20MHz internal oscillator" name="OSC20M" value="0x00"/>
<value caption="32KHz internal Ultra Low Power oscillator"
<value caption="16/20MHz internal oscillator" name="OSC20M" value="0x00"/>
<value caption="32.768kHz internal ultra low-power oscillator"
name="OSCULP32K"
value="0x01"/>
<value caption="External clock" name="EXTCLK" value="0x03"/>
Expand Down Expand Up @@ -3392,7 +3398,7 @@
<register caption="Revision ID"
name="REVID"
offset="0x01"
rw="RW"
rw="R"
size="1"/>
<register caption="External Break"
initval="0x00"
Expand Down
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