Strange and incorrect beautification

Found this happening, not sure why it's happening and not a lot of time to debug at the moment: 
```
entity asdf is
	port (

	);
end entity asdf;

​entity register is
port (
	A   : in  std_logic_vector(7 downto 0);
	clk : in  std_logic;
	clr : in  std_logic;
	B   : out std_logic_vector(7 downto 0)
);
end register;
```
Note that the port clause in the second entity isn't indenting