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LiteX SMP generator: enable CounterPlugin so utime is driven - #502
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vexRiscvConfig defaults withCounterPlugin to false, but still sets
CsrPlugin utimeAccess to READ_ONLY. Without a CounterPlugin, CsrPlugin
allocates its own utime input, and the clint binding only drives
CounterPlugin.time. SpinalHDL then rejects the cluster:
NO DRIVER ON (toplevel/cores_0_cpu_logic_cpu/utime : in UInt[64 bits])
VexRiscvLitexSmpClusterCmdGen is the generator LiteX runs. Pass
withCounterPlugin = true there, which is the behaviour from before the
flag existed. LiteX pins pythondata-cpu-vexriscv-smp to 217d23d
(enjoy-digital/litex@bfb3f8beb) until this lands.
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enjoy-digital
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Oct 14, 2026
Bring in SpinalHDL/VexRiscv#502: VexRiscvLitexSmpClusterCmdGen enables CounterPlugin again, so the CsrPlugin utime input is driven and the LiteX SMP cluster elaborates with the current SpinalHDL (90b7d8eee). Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
pu-cc
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Oct 15, 2026
The upstream generator now drives the CsrPlugin utime input again (SpinalHDL/VexRiscv#502) and the Ram_1w_1rs models accept the new rdLatency/rd_dataEn ports (pythondata-cpu-vexriscv_smp#12), so follow pythondata-cpu-vexriscv-smp master again. This reverts commit bfb3f8b. Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
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vexRiscvConfigdefaultswithCounterPluginto false, but still setsCsrPluginutimeAccesstoREAD_ONLY. Without aCounterPlugin,CsrPluginallocates its ownutimeinput, and the clint binding only drivesCounterPlugin.time. SpinalHDL then rejects the cluster before any netlist is written:VexRiscvLitexSmpClusterCmdGenis the generator LiteX runs for the SMP cluster. This passeswithCounterPlugin = truethere, which is the behaviour from before the flag existed. Nothing else changes: caches, ISA, debug, and the SWD option are untouched.This is why LiteX pins
pythondata-cpu-vexriscv-smpto217d23d(enjoy-digital/litex@bfb3f8beb, asked about on litex-hub/pythondata-cpu-vexriscv_smp#11). The pin can move once this is in a pythondata gitlink. The companion model update forrdLatency/rd_dataEnis separate; elaboration dies onutimebefore that Verilog check runs.