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Lower concrete BF16 GEMM to Grider ISA - #16
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SaibaWaipu
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codex/issue-8-bf16-f32-accumulator
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October 30, 2026 09:27
SaibaWaipu
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October 30, 2026 09:27
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Summary
Depends on #11 (FP32 BF16 MAC semantics). Adds a concrete 16x16 BF16 GEMM lowering using row/column lane masks, immediate loads, SIMD MACs, and final BF16 conversion. It includes a Python execution report (instruction count, cycle estimate, maximum error) and a utility to run the generated stream through the tile RTL testbench.
Scope
The current lowering embeds matrices in
MOVIimmediates because the ISA has no runtime global-memory load or program fetch. This is a complete fixed-input lowering path, not yet a reusable runtime GEMM kernel. Draft pending RTL/Python execution and reference-error comparison. No tests were run.