🧠 4-Bit Nano Processor (VHDL)

Semester 2 — Computer Organization & Digital Design

📌 Overview

This repository contains the complete implementation of a custom-designed 4-bit Nano Processor, developed as a team project for the CS1050 — Computer Organization & Digital Design module.

The processor was built using a modular VHDL design, simulated via Xilinx Vivado, and tested on a BASYS-3 FPGA board.

🧩 Instruction Set Architecture

The processor supports a compact 12-bit instruction format, enabling arithmetic, logic, data movement, and branching.

Instruction	Purpose	Format	Description
MOVI R, d	Load immediate	10 RRR 000 dddd	R ← d
ADD Ra, Rb	Add registers	00 RaRaRa RbRbRb 0000	Ra ← Ra + Rb
NEG R	2’s complement	01 RRR 0000000	R ← –R
JZR R, d	Jump if zero	11 RRR 0000 ddd	If R==0 → PC ← d

🔧 Major Components

• Program Counter (PC) — 3-bit, jump-enabled

• Program ROM — stores binary instructions

• Instruction Decoder — converts opcode → control signals

• Register Bank (8 × 4-bit)

• ALU (Add / Sub / NEG)

• Multiplexers (8×4-bit, 2×4-bit, 2×3-bit)

• Slow Clock Divider

• Top-Level Processor Integration

⚙️ Features

• 🟦 Modular VHDL Design — clean separation of components
• ⚡ Carry Lookahead ALU for faster operations
• 🔁 Full instruction cycle (Fetch → Decode → Execute → Writeback)
• 🧪 All modules testbench-verified with waveforms
• 💡 BASYS-3 FPGA implementation with LED & 7-segment output

🧪 Simulation & Testing

✔ Individual testbenches for PC, ROM, Register Bank, ALU, MUXes

✔ Elaborated schematics + timing diagrams

✔ Full CPU simulation testbench

✔ Real FPGA testing on BASYS-3 development board

🚀 How to Run

🔧 1. Open in Vivado

• Create a new Vivado project

• Add all .vhd files from src/

• Set NanoProcessor as the top module

▶️ 2. Run Simulation

• Add testbenches from sim/

• Run behavioral simulation

💡 3. FPGA Deployment

• Use the .xdc constraint file

• Generate bitstream

• Program FPGA