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RISC-V-CPU

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RISCV32I CPU homework written in verilog

cpu emulator verilog

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Name		Name	Last commit message	Last commit date
common		common
.gitignore		.gitignore
README.md		README.md
consts.v		consts.v
cpu.v		cpu.v
ex.v		ex.v
hci.v		hci.v
id.v		id.v
if.v		if.v
mem.v		mem.v
memctrl.v		memctrl.v
midregs.v		midregs.v
pc_reg.v		pc_reg.v
ram.v		ram.v
regs.v		regs.v
riscv_top.v		riscv_top.v
stallbus.v		stallbus.v

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RISC-V-CPU

Course MS108, a RISCV32I CPU homework written in verilog.

In this project, we implemented a 5-pipelined CPU according to our own design.

About

RISCV32I CPU homework written in verilog

cpu emulator verilog

5 stars

1 watching

Report repository

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