Issues

• ARM7: Register ROR by a nonzero multiple of 32 preserves the wrong carry

  chsasank/ARM7#19 · Filter by author canxin121 opened on Nov 6, 2026

• ARM7: Data cache declares 2 XOR addr_width entries instead of 2^addr_width

  chsasank/ARM7#18 · Filter by author canxin121 opened on Nov 6, 2026

• ARM7: Single-register transfers invert immediate and register offset selection

  chsasank/ARM7#17 · Filter by author canxin121 opened on Nov 6, 2026

• Immediate LSR/ASR with imm5=0 are interpreted as no shift

  chsasank/ARM7#8 · Filter by author canxin121 opened on Nov 2, 2026

• Register ASR of a negative operand by more than 32 does not sign-fill

  chsasank/ARM7#7 · Filter by author canxin121 opened on Nov 2, 2026

• LDRB drives the upper 24 result bits to Z instead of zero-extending

  chsasank/ARM7#6 · Filter by author canxin121 opened on Nov 2, 2026

• LS and LE condition predicates have incorrect Boolean expressions

  chsasank/ARM7#5 · Filter by author canxin121 opened on Nov 2, 2026

• Skipped and non-flag-setting instructions forward invalid NZCV to the next condition

  chsasank/ARM7#4 · Filter by author canxin121 opened on Nov 2, 2026

• Problem in fibonacci series result output

  chsasank/ARM7#2 · Filter by author nanahemal opened on Jan 10, 2024

• Issue with calculating overflow flag(v) in nzcv

  chsasank/ARM7#1 · Filter by author MohGanji opened on Jan 6, 2020
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