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- #136 · fabianschuiki opened
on May 2, 2020 - #233 · hunterzju opened
on Nov 12, 2021 2
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- Status: Open.#253 In fabianschuiki/moore;
- Status: Open.#251 In fabianschuiki/moore;
- Status: Open.#250 In fabianschuiki/moore;
- Status: Open.#248 In fabianschuiki/moore;
- Status: Open.#245 In fabianschuiki/moore;
- Status: Open.#244 In fabianschuiki/moore;
- Status: Open.#239 In fabianschuiki/moore;
Eliminate HIR in favor of AST-specific queries
A-hirArea: High-level Intermediate Representation.Area: High-level Intermediate Representation.L-vlogLanguage: Verilog and SystemVerilog.Language: Verilog and SystemVerilog.Status: Open.#237 In fabianschuiki/moore;Remove legacy LLHD crate codegen and dependency
A-codegenArea: Code generation.Area: Code generation.A-depsArea: Dependencies.Area: Dependencies.C-cleanupCategory: Clean up or refactor code.Category: Clean up or refactor code.Status: Open.#236 In fabianschuiki/moore;Add Moore MIR dialect and move codegen to CIRCT
A-codegenArea: Code generation.Area: Code generation.C-enhancementCategory: Adding or improving on features.Category: Adding or improving on features.L-vlogLanguage: Verilog and SystemVerilog.Language: Verilog and SystemVerilog.P-highPriority: High.Priority: High.Status: Open.#235 In fabianschuiki/moore;problems about ports when build in hierachy
A-mirArea: Mid-level Intermediate Representation.Area: Mid-level Intermediate Representation.C-bugCategory: This is a bug.Category: This is a bug.L-vlogLanguage: Verilog and SystemVerilog.Language: Verilog and SystemVerilog.P-highPriority: High.Priority: High.Status: Open.#231 In fabianschuiki/moore;Consider adding support for importing / exporting UHDM
C-enhancementCategory: Adding or improving on features.Category: Adding or improving on features.Status: Open.#229 In fabianschuiki/moore;