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chore(engine): license gateware under CERN-OHL-W-2.0 fpga-sim #38: Commit 1564868 pushed by felipebalbi
8m 50s master
master
8m 50s
ci: switch synth+release jobs to oss-cad-suite 2026-06-14 fpga-sim #37: Commit f2106b7 pushed by felipebalbi
8m 45s bitstream-verde-v0.2.0
bitstream-verde-v0.2.0
8m 45s
ci: switch synth+release jobs to oss-cad-suite 2026-06-14 release-bitstream #2: Commit f2106b7 pushed by felipebalbi
1m 49s bitstream-verde-v0.2.0
bitstream-verde-v0.2.0
1m 49s
ci: switch synth+release jobs to oss-cad-suite 2026-06-14 rust #30: Commit f2106b7 pushed by felipebalbi
51s bitstream-verde-v0.2.0
bitstream-verde-v0.2.0
51s
ci: switch synth+release jobs to oss-cad-suite 2026-06-14 fpga-sim #36: Commit f2106b7 pushed by felipebalbi
9m 21s master
master
9m 21s
ci: add release-bitstream workflow for tagged Mole Verde builds fpga-sim #35: Commit 25d41b2 pushed by felipebalbi
8m 48s bitstream-verde-v0.2.0
bitstream-verde-v0.2.0
8m 48s
ci: add release-bitstream workflow for tagged Mole Verde builds release-bitstream #1: Commit 25d41b2 pushed by felipebalbi
1m 31s bitstream-verde-v0.2.0
bitstream-verde-v0.2.0
1m 31s
ci: add release-bitstream workflow for tagged Mole Verde builds rust #29: Commit 25d41b2 pushed by felipebalbi
50s bitstream-verde-v0.2.0
bitstream-verde-v0.2.0
50s
chore(uart): switch Verde production default to 2 Mbaud x 8x oversample rust #28: Commit 1fe28cd pushed by felipebalbi
47s master
master
47s
chore(uart): switch Verde production default to 2 Mbaud x 8x oversample fpga-sim #34: Commit 1fe28cd pushed by felipebalbi
9m 15s master
master
9m 15s
build(engine): switch nextpnr default seed from 3 to 4 for v0.2 margin fpga-sim #33: Commit 007c2e5 pushed by felipebalbi
8m 50s master
master
8m 50s
rustfmt + scalafmt fpga-sim #32: Commit 20fe737 pushed by felipebalbi
8m 59s master
master
8m 59s
rustfmt + scalafmt rust #27: Commit 20fe737 pushed by felipebalbi
1m 12s master
master
1m 12s
rustfmt + scalafmt rust #26: Commit 20fe737 pushed by felipebalbi
46s v0.2
v0.2
46s
rustfmt + scalafmt fpga-sim #31: Commit 20fe737 pushed by felipebalbi
9m 31s v0.2
v0.2
9m 31s
docs(presentation): full v0.2 ISA sync across all chapters rust #25: Commit c382dd0 pushed by felipebalbi
53s v0.2
v0.2
53s
fix(engine): reset per-program state on engineStart rising edge fpga-sim #30: Commit 3937aec pushed by felipebalbi
8m 55s v0.2
v0.2
8m 55s
test(asm): tmp108-loop fixture for sustained-load regression rust #24: Commit 4d23821 pushed by felipebalbi
50s v0.2
v0.2
50s
test(asm): tmp108-loop fixture for sustained-load regression fpga-sim #29: Commit 4d23821 pushed by felipebalbi
8m 56s v0.2
v0.2
8m 56s
test(engine): update MoleIoBufUp5kSim PIN_TYPE assertion to 101001 fpga-sim #28: Commit cc10fe3 pushed by felipebalbi
6m 21s master
master
6m 21s
feat(engine)!: gate Q1->Q2 stretch guard on recent SCL drive fpga-sim #27: Commit 4338f24 pushed by felipebalbi
8m 41s v0.2
v0.2
8m 41s
feat(engine)!: gate Q1->Q2 stretch guard on recent SCL drive rust #23: Commit 4338f24 pushed by felipebalbi
38s v0.2
v0.2
38s
chore(engine): bump REVISION 0.1.0 -> 0.1.1 fpga-sim #26: Commit 9d66459 pushed by felipebalbi
7m 6s master
master
7m 6s
feat(asm,loader,engine)!: rewrite host↔FPGA wire format as [MAGIC|LEN… fpga-sim #25: Commit 4a3f088 pushed by felipebalbi
6m 17s v0.2
v0.2
6m 17s
feat(asm,loader,engine)!: rewrite host↔FPGA wire format as [MAGIC|LEN… rust #22: Commit 4a3f088 pushed by felipebalbi
42s v0.2
v0.2
42s