sunteng goog00

Hi, I'm Sun Teng 👋

I'm an open-source contributor focused on GPU/NPU compilers and heterogeneous runtimes.

My recent work spans the path from compiler IR to hardware execution:

IR analysis → transformation → GPU/NPU code generation → JIT runtime → hardware validation

I enjoy working on compiler semantics, compilation and runtime systems, tensor computation, and heterogeneous execution.

An MLIR-based compiler infrastructure for Ascend NPU.

My contributions include:

CustomOp 1:2 TileAndBind: extended dimension analysis and slice propagation for CustomOp / CustomMacroOp, using iterator_types and indexing_map to derive tiled operands while preserving reduction semantics
Added support for elementwise, broadcast, reduction, scalar-operand, and constrained multi-result cases, with conservative fallback for unsupported layouts, side effects, synchronization resources, and other unsafe cases
Added memory-effect modeling for bufferized CustomOps to preserve execution ordering through compiler transformations
Added MLIR/LIT and Ascend NPU E2E validation; 15 correctness cases passed, and 6 Softmax performance cases achieved approximately 1.99× speedup with 1:2 sub-block tiling on Ascend hardware

A Rust GPU DSL and asynchronous JIT runtime based on NVIDIA cuTile.

My contributions include:

Persistent Cubin cache for content-addressed, cross-process JIT reuse, with atomic publication, integrity validation, eviction, and automatic recovery from invalid entries
- Reduced GEMM preparation from 16.8 s to 98 ms on sm_89 and from 4.0 s to 54 ms on sm_120
Single-flight Kernel Cache and Meta Tensor warmup, eliminating duplicate compilation for the same specialization and moving JIT cost out of the first production launch
- Reduced a warmed first production launch from approximately 283 ms to 259 μs on RTX 4090
Custom CUDA Memory Pool with device ownership, asynchronous allocation, execution-context capture, and RAII lifetime management
Zero-copy Tensor views and reinterpretation using shared storage ownership with shape, byte-size, contiguity, alignment, and aliasing validation
BF16 support across the DSL, type system, and kernel execution path

An compiler that lowers Rust MIR directly to CUDA PTX.

My contributions include:

Implemented Rust MIR SetDiscriminant lowering for direct-tag and niche-encoded enums while preserving Rust layout semantics on GPU
Added 64-bit warp shuffle, redux.sync, lane-mask, and Hopper elect.sync intrinsics across the compiler pipeline
Added LLVM convergent semantics for cooperative warp and barrier operations to prevent invalid compiler optimizations
Added MIR, LLVM IR, and PTX code-generation tests for the new lowering and GPU primitives

A general-purpose programming language compiler with JIT and heterogeneous GPU support.

My contributions include:

Implemented LLVM-based NVPTX/AMDGPU code generation and CUDA/HIP runtime integration
Generated PTX directly through LLVM TargetMachine APIs instead of invoking an external llc
Unified NVIDIA and AMD GPU kernel launch paths
Contributed IR/Codegen refactoring, tests, documentation, and memory-lifetime fixes

A compilation framework for tensor computation and Tile-based programming.

My contributions include:

Implemented hardware-aware FP32 GEMM tiling based on cache hierarchy and SIMD characteristics
Derived MC, NC, and KC block sizes using a BLIS-inspired model
Improved single-core performance from 85–120 GFLOPS to stable 130+ GFLOPS, with a peak of 134 GFLOPS (~96% of theoretical peak) on AMD Threadripper Pro 3955WX
Contributed IR infrastructure, parameterized tests, memory-lifetime fixes, and CI support

Languages: Rust, C++, Python, Java
Compiler: MLIR, LLVM, Rust MIR, IR lowering and transformation, affine/indexing maps, NVPTX, AMDGPU
GPU Runtime: CUDA Driver API, PTX/NVVM, CUDA streams, memory pools, JIT compilation, HIP/ROCm
Platforms: NVIDIA GPU, Ascend NPU, AMD ROCm