feat(gpclk): prove GPCLK0 clock enable - #81
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Fail-closed CM_GP0 OSC+ENAB after GENET on a new unused block, with leftover restore. UART2 MMIO after GENET hung AXI — do not retry UART2-5. Co-authored-by: Cursor <cursoragent@cursor.com>
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Hi @infektyd - this PR hasn't had any activity in over 7 days. Please update it or close it if it's no longer needed. (No merge conflicts detected.) |
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Summary
05b39d20d01fd53bfd5f01fcf88e2e2f4f2685d8(feat(gpclk): prove GPCLK0 clock enable) onto PR feat(auxspi1): prove AUX SPI1 enable #80 tippr/auxspi1-v143@7eebe118e109e045c778239d9b30c1612c7d7768.kernel8.imgsha2568860802981d6b9d597c12791228434ffa108898ae2cca4583f57caf3dc57f47f; serialgpclk ok=1 version=144 clk=1 restore=1(verified this session from last-boot capture/tmp/aether-v144-gpclk.bin; TFTP image at~/aether-tftp/aether/kernel8.imgmatches the same sha256; live soak / last-boot serial is valid proof; iterate AND-gate miss is not a kernel miss).Test plan
gh pr view 80still tips7eebe118e109e045c778239d9b30c1612c7d7768and this PR bases onpr/auxspi1-v143.gpclk ok=1 version=144 clk=1 restore=1.tests/test_runtime_gpclk_v144_contract.pyis in the diff and Toolsets are not.Made with Cursor