f5low-fg

Frame generation host behind OptiScaler-NR's F5Low FG output. Our own pacer, gate and presenter, with pluggable frame generators:

generator	makes the frames	GPUs
own (XeFG Tensor)	our kernels (D3D12 command lists + NVAPI cubins); Intel's native modules, weights and root constants read from the player's libxess_fg.dll into memory at every start (nothing written to disk; no translation, no dxcompiler.dll)	NVIDIA
intel	Intel's libxess_fg.dll	any
dlssg	NVIDIA DLSS-G through a private, renamed copy of the player's Streamline (copied from OptiScaler's Streamline folder at run time); 2x to 6x on RTX 20 to 50: native on RTX 50, unlocked in memory on RTX 20/30/40 (src/unlock/); never falls back to another generator	NVIDIA RTX 20+
fsr	AMD FidelityFX frame generation	any

Every vendor library is loaded at runtime from the player's PC. This repo holds only our own code.

Status: being set up (private). Layout planned:

src/core/        XeFG-API surface OptiScaler drives, pacer, gate, presenter, interop, log/ini/version
src/generators/  own, dlssg (+ stubs for intel, fsr)
src/sink/        the present sink and logging DXGI proxies (dlssg now, intel later)
src/unlock/      OptiScaler's MFG unlock families (structural locators, patch transaction, RTX 20 PTX rewrite), applied in memory to f5low's own DLSS-G copy
tools/           recipe builder, audit, harness

Rule: no vendor content

Never commit a vendor binary (libxess_fg.dll, Streamline, nvngx_*, FidelityFX DLLs) or anything derived from one: extracted or translated shaders (DXBC, DXIL, PTX made from them), zstd dictionaries, weights, captured buffers, disassembly, RVAs or byte patterns. ("Byte patterns" means sequences copied from a vendor binary; the generic instruction encodings our scans recognise, such as mov [rsp+disp], imm, are not.) Intel modules are referred to by SHA-256 only. The audit in tools/ enforces this in CI.

Recipe (own generator's graph pack)

recipe/i0/ is our half of the own generator's pack: manifest.tmpl (the manifest, generated file names as @name) and parts.json (how each file is made; the nested hdr/ pack alike). tools/kernels/ holds our generators and HLSL templates. Intel modules appear only as SHA-256 of the decoded module, weights as upload ordinal + size + SHA-256. At run time f5low.dll rebuilds the pack from the player's libxess_fg.dll (decode, find modules by hash, weights and root constants from the file) in memory, on a background thread, at every start: nothing Intel-derived is ever written to disk, and the game's thread does not wait for it (f5lowGetStatus says 0, "building its frame generator in the background", while the frames pass through). The pack-less pack runs on the D3D12 path only (docs/PACKLESS.md). tools/recipe/build_pack.py recombines the recipe with the Intel parts of a local libxess_fg.dll and a weight capture offline (a dev pack with PTX twins, both paths); compare_pack.py checks a built pack against a reference (--packless for the runtime one); classify.py derives a recipe from a finished pack (dev tool, needs the old libxess-weights checkout). Built packs are Intel-derived and stay out of the repo.

Licence

GPL-3.0, the same as OptiScaler (see LICENSE), with an additional permission under section 7 (LICENSE-EXCEPTION.md): f5low may be combined and conveyed with Intel's XeSS libraries (libxess_fg.dll, libxell.dll, libxess.dll) and NVIDIA / AMD vendor runtime libraries without those libraries falling under the GPL. Vendor libraries are never part of this repo; they are loaded at runtime from the player's PC and keep their own licences. tools/make_kit.ps1 builds the release kit (f5low.dll + Intel's libxess_fg.dll + both licences).

Credits

src/unlock/ is OptiScaler-NR's MFG unlock (OptiScaler/framegen/mfgunlock, GPL-3.0 like this repo), ported file by file; each header says which OptiScaler-NR commit it comes from and what differs. Its sl.dlss_g frame-count clamp and software-pacing approach is adapted from KleberMotta/OptiScaler-DLSS5-MFG-RTX40 (MIT), which adapted the MFG Unlock ReShade addon by Dreamt and mavismmg: the MIT notice is in licenses/MFGUnlock_LICENSE.txt. The x64 length decoder in src/unlock/hde/ is Hacker Disassembler Engine 64 C by Vyacheslav Patkov (its licence text is in the files).

Exports

Besides Intel's xefgSwapChain* API: f5lowGetStatus (which generator runs and why), xefgCudaXellCountsRenderedOnly and xefgCudaDriverMultipliesReflexCap; see docs/GENERATORS.md.