Timing feedback for the next design iteration.

Documentation · RustEDA · Benchmarks · Apache-2.0

RustSTA analyzes gate-level Verilog, Liberty, SDC and SPEF with persistent multi-corner timing results, bounded queries and incremental updates.

Part of RustEDA, infrastructure for chip-design recursive self-improvement. Native tools shorten the work between inference steps; verified results guide the next iteration.

Latest development · 2026-11-01

The source now includes mixed standard-cell/SRAM Liberty conventions, explicit global early/late timing derates and driving-cell waveforms on extracted and propagated-clock paths. RC preparation runs independent nodes within each graph level on a bounded rayon pool, then commits results in topological order. The memory estimate includes an additional 184 bytes per node for jobs/results.

Current source and qualification · Latest complete-flow evidence

Quick start

Install Rust with rustup and Git. The checkout pins Rust 1.97.1. The default build needs no GPU or Python runtime.

$ git clone https://github.com/lab-emi/RustSTA.git
$ cd RustSTA
$ cargo build --locked --release -p rusteda-cli -p ruststa-cli

Add the built binaries to your shell path, then confirm the CPU build:

export PATH="$PWD/target/release:$PATH"

$ ruststa --version
ruststa 0.4.3 (backends: cpu)

From the repository root, analyze the bundled eight-cell chain in a fresh workspace:

FIX=verification/fixtures/synthetic/sta
WS=.work/first-timing

rusteda init --workspace "$WS" --format json
rusteda import --workspace "$WS" --base-rev rev0 \
  --lib "$FIX/lib/wt_15.lib" \
  --netlist "$FIX/net/chain_8.v" \
  --sdc "$FIX/sdc/chain_8.sdc" --format json
ruststa run --workspace "$WS" --base-rev rev1 \
  --threads 2 --max-paths 5 --max-state-gib 1 --format json
ruststa report --workspace "$WS" --rev rev2 --section summary --format json
ruststa path --workspace "$WS" --rev rev2 --target path1 --format json
ruststa check --workspace "$WS" --base-rev rev2 --method both --format json

The synthetic library is a test fixture. This flow creates rev0 → rev1 → rev2 → rev3; queries read rev2, and checking adds sta_check.json in rev3. A successful operation, timing closure and a verification verdict are separate results. Inspect corner, wire model and unconstrained endpoints alongside slack.

The complete quickstart explains reports and artifacts. For your own design, follow the timing workflow.

A workspace you can inspect

Command	Result
rusteda init / import	Create a workspace and import Verilog, Liberty, SDC and SPEF
ruststa run / update	Analyze a revision and persist sta.rbin
ruststa path / inspect / report	Read timing paths, pins, endpoints and summaries
ruststa check	Compare saved timing with an independent checker, a full rerun, or both
rusteda show / log / diff / export	Inspect revisions and export structural Verilog

Updates to an existing workspace require an explicit --base-rev revN. A stale revision fails with REVISION_CONFLICT (exit 4). Queries accept --rev; handles such as path1 belong to the selected revision. Initialization creates rev0 and takes no base revision.

Agent integration · Commands and exit codes · JSON reports and artifacts

Timing scope

Available now	Current boundary
Multi-corner 1D/2D/3D Liberty NLDM tables	No CCS/ECSM or sign-off accuracy claim
Setup/hold, latch borrowing, recovery/removal, gating checks	Ideal and explicit propagated primary clocks; generated clocks and CPPR remain outside scope
Constants and supported -from/-to timing exceptions	Ordered -through exception hops are rejected by the engine
Ideal, lumped wire-load and detailed SPEF RC networks, including resistor loops	Moment-matched pi, effective load and driver waveforms; disconnected components emit T0151; no crosstalk/CCS claim
CPU f64 and optional CUDA f64/f32 propagation	Metal/Accelerate is not a shipped backend
Incremental TimingSession Rust API	The CLI ruststa update currently reports full recomputation

Unsupported semantic constructs produce diagnostics. See the complete support table, backend guide and scope.

Verification and performance

The test infrastructure includes hand-derived timing cases, a separately implemented ruststa-check, full-vs-incremental consistency checks, and pinned SkyWater sky130_fd_sc_hd and GlobalFoundries gf180mcu_fd_sc_mcu7t5v0 / gf180mcu_fd_sc_mcu9t5v0 Liberty libraries.

$ cargo xtask pdk fetch
$ cargo xtask verify pdk --profile pr --require

Coverage and limits are explicit: the independent checker can return undecided on bounded large exception cases; a missing external tool or device is unverified. No numerical RustSTA-vs-OpenSTA speedup is claimed by this release. Compare pinned reference executables as black boxes and report complete command wall time, peak memory, timing scope and numerical agreement together.

In the RustEDA Ibex flow on IHP SG13G2 / EZ130 (two real SRAMs), RustSTA drives the frontend and post-route repairs and signs off TT/SS extracted timing beside OpenSTA. In run16 (2026-10-30) the two agreed within 0.806 ps on identical SPEF, against a 1 ps gate. The whole-flow comparison with LibreLane is on the RustEDA benchmarks page.

Verification scope · Dual-PDK suite · Performance and memory

Documentation

• Get started and install from source.
• Timing manual, CLI manual, and formal specifications.
• Architecture, requirements and evidence, and RustEDA brand.
• Build and publish the documentation.

Contributing

See CONTRIBUTING.md for specification-first development, clean-room boundaries, independent verification and memory budgets. Development checks cover layout, formatting, shared crates, fixtures and tests. Everyone participating follows the Code of Conduct.

Report vulnerabilities according to SECURITY.md. RustSTA is licensed under Apache-2.0; see NOTICE and REUSE.toml.

Extracted RC timing

rusteda import --spef routed.spef.gz --spef-corner tt --base-rev rev1 -w work imports a bounded detailed RC extraction for a previously imported netlist and corner. It can also be combined with --lib, --netlist and --sdc in one transaction. Run the usual ruststa run and ruststa check --method full on the returned revisions. The scope reports spef_rc, spef and nldm_ceff_ramp; missing extraction and a different corner are errors. Resistor loops are solved on the nodal conductance system, and a part of a net without a resistor path to its driver joins the driver with warning T0151.

Plain text and gzip are accepted under the same encoded/decoded byte cap. CRC errors, missing annotation and budget overruns fail explicitly without committing a partial revision. This uses moment-matched pi loads, charge-matched effective capacitance, a finite-ramp Thevenin driver and RC threshold/slew propagation, with factor-one grounded coupling. Explicit propagated primary clocks are supported; crosstalk and CCS current tables are not. The independent checker currently reports extracted RC as undecided; use full recomputation and the measured dual-PDK black-box suite. See the SPEF workflow, parasitic timing and the verification report.