USB4/Thunderbolt and Type-C display support

Documentation/devicetree/bindings/iommu/apple,dart.yaml

@@ -28,6 +28,11 @@ properties:
           - apple,t8103-usb4-dart
           - apple,t8110-dart
           - apple,t6000-dart
+      - items:
+          - enum:
+              - apple,t6000-dart
+              - apple,t8112-dart
+          - const: apple,t8110-dart
       - items:
           - enum:
               - apple,t6020-dart
@@ -46,20 +51,63 @@ properties:
       Optional since not all IOMMUs are attached to a clock gate.
 
   '#iommu-cells':
-    const: 1
+    enum: [1, 5]
     description:
-      Has to be one. The single cell describes the stream id emitted by
-      a master to the IOMMU.
+      Usually one cell describing the stream id emitted by a master. The
+      T6020 NHI DART uses five cells to describe a stream range and its
+      device-visible DMA window.
 
   power-domains:
     maxItems: 1
 
+  apple,dma-range:
+    $ref: /schemas/types.yaml#/definitions/uint64-array
+    minItems: 2
+    maxItems: 2
+    description: >
+      Inclusive device-visible DMA aperture, encoded as a start address and
+      size. The IOMMU DMA allocator restricts mappings to this range.
+
+  apple,dma-offset:
+    $ref: /schemas/types.yaml#/definitions/uint64
+    description: >
+      Offset added to device-visible DMA addresses when indexing the DART page
+      tables. This models host bridges which alias a low PCI bus aperture into
+      a high DART translation window.
+
+  apple,tunable:
+    $ref: /schemas/types.yaml#/definitions/uint32-matrix
+    items:
+      items:
+        - description: Register offset
+        - description: Mask to be applied to the register value
+        - description: Bits to be set after applying the mask
+    description: >
+      List of (register offset, mask, value) tuples copied from Apple's Device
+      Tree by the bootloader and required to initialize dynamically powered
+      DART instances.
+
 required:
   - compatible
   - reg
   - '#iommu-cells'
   - interrupts
 
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: apple,t6020-dart
+    then:
+      properties:
+        '#iommu-cells':
+          enum: [1, 5]
+    else:
+      properties:
+        '#iommu-cells':
+          const: 1
+
 additionalProperties: false
 
 examples:

Documentation/devicetree/bindings/pci/apple,pcie.yaml

@@ -21,6 +21,10 @@ description: |
   separate from the port registers. In that case, there is one PHY
   register range per port register range.
 
+  The PCIe-C variant connects a single root port to a USB4 router instead of
+  a physical PCIe link. It has no external PHY or PERST# GPIO and follows the
+  router's cable-controlled power lifetime.
+
   All root ports share a single ECAM space, but separate GPIOs are
   used to take the PCI devices on those ports out of reset.  Therefore
   the standard "reset-gpios" and "max-link-speed" properties appear on
@@ -45,28 +49,23 @@ properties:
           - const: apple,t8122-pcie
           - const: apple,t6020-pcie
       - const: apple,t6020-pcie
+      - const: apple,t8103-pciec
+      - items:
+          - const: apple,t8112-pciec
+          - const: apple,t8103-pciec
+      - const: apple,t6000-pciec
 
   reg:
     minItems: 3
     maxItems: 10
 
   reg-names:
     minItems: 3
-    items:
-      - const: config
-      - const: rc
-      - const: port0
-      - const: port1
-      - const: port2
-      - const: port3
-      - const: phy0
-      - const: phy1
-      - const: phy2
-      - const: phy3
+    maxItems: 10
 
   ranges:
     minItems: 2
-    maxItems: 2
+    maxItems: 3
 
   interrupts:
     description:
@@ -85,6 +84,8 @@ properties:
   power-domains:
     maxItems: 1
 
+  dma-coherent: true
+
 patternProperties:
   "^pci@":
     $ref: /schemas/pci/pci-bus.yaml#
@@ -99,13 +100,16 @@ patternProperties:
         description: Optional GPIO to power on the device
         maxItems: 1
 
+      interrupt-controller: true
+
     required:
-      - reset-gpios
       - interrupt-controller
       - "#interrupt-cells"
       - interrupt-map-mask
       - interrupt-map
 
+    unevaluatedProperties: false
+
 required:
   - compatible
   - reg
@@ -141,6 +145,60 @@ allOf:
       properties:
         reg-names:
           minItems: 10
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - apple,t8103-pciec
+              - apple,t6000-pciec
+    then:
+      properties:
+        reg:
+          minItems: 5
+          maxItems: 7
+        reg-names:
+          oneOf:
+            - items:
+                - const: config
+                - const: rc
+                - const: port0
+                - const: fabric
+                - const: debug
+            - items:
+                - const: config
+                - const: rc
+                - const: port0
+                - const: fabric
+                - const: debug
+                - const: ltssm
+                - const: intr2axi
+        interrupts:
+          maxItems: 1
+        ranges:
+          minItems: 3
+          maxItems: 3
+    else:
+      properties:
+        reg-names:
+          minItems: 3
+          items:
+            - const: config
+            - const: rc
+            - const: port0
+            - const: port1
+            - const: port2
+            - const: port3
+            - const: phy0
+            - const: phy1
+            - const: phy2
+            - const: phy3
+        ranges:
+          maxItems: 2
+      patternProperties:
+        "^pci@":
+          required:
+            - reset-gpios
 
 examples:
   - |

Documentation/devicetree/bindings/thunderbolt/apple,t8103-usb4-acio.yaml

@@ -60,10 +60,20 @@ properties:
 
   power-domains:
     minItems: 3
-    maxItems: 3
+    maxItems: 4
+    description: |
+      The first three domains power the ACIO co-processor complex. When
+      apple,pcie-tunnel is present, the fourth domain powers its PCIe-C
+      controller and is enabled only after the USB4 PCIe tunnel is active.
 
   thunderbolt-switch: true
 
+  apple,pcie-tunnel:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      PCIe-C tunnel container populated after the USB4 router has enabled its
+      PCIe adapter.
+
   apple,tunable-rc:
     $ref: /schemas/types.yaml#/definitions/uint32-matrix
     items:
@@ -162,7 +172,8 @@ examples:
             mboxes = <&usb4_1_mbox>;
             power-domains = <&ps_atc1_cio>,
                             <&ps_atc1_cio_pcie>,
-                            <&ps_atc1_cio_usb>;
+                            <&ps_atc1_cio_usb>,
+                            <&ps_atc1_pcie>;
             resets = <&cio_reset 1>;
             thunderbolt-switch;
             pinctrl-0 = <&acio1_pins>;

arch/arm64/boot/dts/apple/t6001.dtsi

@@ -20,6 +20,8 @@
 # define GPU_REPEAT(x) <x x x x>
 #endif
 
+#define APPLE_T600X_NON_ULTRA
+
 #include "t600x-common.dtsi"
 
 / {
@@ -45,6 +47,7 @@
 &{/soc} {
 	#include "t600x-die0.dtsi"
 	#include "t600x-dieX.dtsi"
+	#include "t600x-pciec.dtsi"
 	#include "t600x-nvme.dtsi"
 };
 

arch/arm64/boot/dts/apple/t600x-dieX.dtsi

@@ -466,6 +466,7 @@
 	};
 	*/
 
+#ifdef APPLE_T600X_NON_ULTRA
 	DIE_NODE(usb4_0_mbox): mailbox@701100000 {
 		compatible = "apple,t6000-m3-mailbox",
 			"apple,m3-mailbox-v2";
@@ -491,7 +492,8 @@
 
 		power-domains = <&DIE_NODE(ps_atc0_cio)>,
 				<&DIE_NODE(ps_atc0_cio_pcie)>,
-				<&DIE_NODE(ps_atc0_cio_usb)>;
+				<&DIE_NODE(ps_atc0_cio_usb)>,
+				<&DIE_NODE(ps_atc0_pcie)>;
 
 		thunderbolt-switch;
 
@@ -557,6 +559,7 @@
 			apple,thunderbolt-drom = [00];
 		};
 	};
+#endif
 
 	DIE_NODE(dwc3_0): usb@702280000 {
 		compatible = "apple,t6000-dwc3", "apple,t8103-dwc3";
@@ -619,6 +622,7 @@
 		status = "disabled";
 	};
 
+#ifdef APPLE_T600X_NON_ULTRA
 	DIE_NODE(usb4_1_mbox): mailbox@b01100000 {
 		compatible = "apple,t6000-m3-mailbox",
 			"apple,m3-mailbox-v2";
@@ -644,7 +648,8 @@
 
 		power-domains = <&DIE_NODE(ps_atc1_cio)>,
 				<&DIE_NODE(ps_atc1_cio_pcie)>,
-				<&DIE_NODE(ps_atc1_cio_usb)>;
+				<&DIE_NODE(ps_atc1_cio_usb)>,
+				<&DIE_NODE(ps_atc1_pcie)>;
 
 		thunderbolt-switch;
 
@@ -710,6 +715,7 @@
 			apple,thunderbolt-drom = [00];
 		};
 	};
+#endif
 
 	DIE_NODE(dwc3_1): usb@b02280000 {
 		compatible = "apple,t6000-dwc3", "apple,t8103-dwc3";
@@ -772,6 +778,7 @@
 		status = "disabled";
 	};
 
+#ifdef APPLE_T600X_NON_ULTRA
 	DIE_NODE(usb4_2_mbox): mailbox@f01100000 {
 		compatible = "apple,t6000-m3-mailbox",
 			"apple,m3-mailbox-v2";
@@ -797,7 +804,8 @@
 
 		power-domains = <&DIE_NODE(ps_atc2_cio)>,
 				<&DIE_NODE(ps_atc2_cio_pcie)>,
-				<&DIE_NODE(ps_atc2_cio_usb)>;
+				<&DIE_NODE(ps_atc2_cio_usb)>,
+				<&DIE_NODE(ps_atc2_pcie)>;
 
 		thunderbolt-switch;
 
@@ -863,6 +871,7 @@
 			apple,thunderbolt-drom = [00];
 		};
 	};
+#endif
 
 	DIE_NODE(dwc3_2): usb@f02280000 {
 		compatible = "apple,t6000-dwc3", "apple,t8103-dwc3";
@@ -925,6 +934,7 @@
 		status = "disabled";
 	};
 
+#ifdef APPLE_T600X_NON_ULTRA
 	DIE_NODE(usb4_3_mbox): mailbox@1301100000 {
 		compatible = "apple,t6000-m3-mailbox",
 			"apple,m3-mailbox-v2";
@@ -1016,6 +1026,7 @@
 			apple,thunderbolt-drom = [00];
 		};
 	};
+#endif
 
 	DIE_NODE(dwc3_3): usb@1302280000 {
 		compatible = "apple,t6000-dwc3", "apple,t8103-dwc3";