To enable our software-defined devices we need some hardware support. This should be use-case driven. Currently I have thought of:
SPI
In SPI the master generates a clock signal, often up to 10MHz, and clocks out the data over the MOSI pin, at the same time the (previous) response from the slave arrives on the MISO pin. To do something like this we probably want GPIO blocks that can shift out a byte together with a clock signal. Also something that can shift IN a byte together with an external clock signal.
Ethernet
To support ethernet we need to use the MDIO protocol to talk to an external Ethernet PHY. FOr GigE this is 8bit wide and clocked at 125MHz. This might be too much for us. But to even manage 10/100Mbps we probably want something where you can write a 32bit word to the GPIO block and then the hardware shifts out byte after byte together with a clock signal.
To enable our software-defined devices we need some hardware support. This should be use-case driven. Currently I have thought of:
SPI
In SPI the master generates a clock signal, often up to 10MHz, and clocks out the data over the MOSI pin, at the same time the (previous) response from the slave arrives on the MISO pin. To do something like this we probably want GPIO blocks that can shift out a byte together with a clock signal. Also something that can shift IN a byte together with an external clock signal.
Ethernet
To support ethernet we need to use the MDIO protocol to talk to an external Ethernet PHY. FOr GigE this is 8bit wide and clocked at 125MHz. This might be too much for us. But to even manage 10/100Mbps we probably want something where you can write a 32bit word to the GPIO block and then the hardware shifts out byte after byte together with a clock signal.