hw/arm/rk3588: peripheral models, Rock 5B+ boot and PCIe network path - #33
Conversation
![chatgpt-codex-connector[bot]](https://avatars.githubusercontent.com/in/1144995?s=60&v=4){kind=small}
There was a problem hiding this comment.
💡 Codex Review
Here are some automated review suggestions for this pull request.
Reviewed commit: 0b484a7d09
ℹ️ About Codex in GitHub
Your team has set up Codex to review pull requests in this repo. Reviews are triggered when you
- Open a pull request for review
- Mark a draft as ready
- Comment "@codex review".
If Codex has suggestions, it will comment; otherwise it will react with 👍.
Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".
|
Review round resolved. New commits on top of the original 11:
All five Codex review findings are addressed, each with a dedicated commit and a reply on the corresponding review thread. qtests: 16/16 pass. Guest boot, reboot cycle, apt update and the e1000e NIC are verified end-to-end. |
There was a problem hiding this comment.
💡 Codex Review
Here are some automated review suggestions for this pull request.
Reviewed commit: fa53d6c0b2
ℹ️ About Codex in GitHub
Your team has set up Codex to review pull requests in this repo. Reviews are triggered when you
- Open a pull request for review
- Mark a draft as ready
- Comment "@codex review".
If Codex has suggestions, it will comment; otherwise it will react with 👍.
Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".
fa53d6c to
cc49ef6
Compare
There was a problem hiding this comment.
💡 Codex Review
Here are some automated review suggestions for this pull request.
Reviewed commit: cc49ef653f
ℹ️ About Codex in GitHub
Your team has set up Codex to review pull requests in this repo. Reviews are triggered when you
- Open a pull request for review
- Mark a draft as ready
- Comment "@codex review".
If Codex has suggestions, it will comment; otherwise it will react with 👍.
Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".
cc49ef6 to
b0e2b6c
Compare
There was a problem hiding this comment.
💡 Codex Review
Here are some automated review suggestions for this pull request.
Reviewed commit: b0e2b6c322
ℹ️ About Codex in GitHub
Your team has set up Codex to review pull requests in this repo. Reviews are triggered when you
- Open a pull request for review
- Mark a draft as ready
- Comment "@codex review".
If Codex has suggestions, it will comment; otherwise it will react with 👍.
Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".
There was a problem hiding this comment.
💡 Codex Review
Here are some automated review suggestions for this pull request.
Reviewed commit: 904e8199a1
ℹ️ About Codex in GitHub
Your team has set up Codex to review pull requests in this repo. Reviews are triggered when you
- Open a pull request for review
- Mark a draft as ready
- Comment "@codex review".
If Codex has suggestions, it will comment; otherwise it will react with 👍.
Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".
904e819 to
5858fe6
Compare
There was a problem hiding this comment.
💡 Codex Review
Here are some automated review suggestions for this pull request.
Reviewed commit: 5858fe6153
ℹ️ About Codex in GitHub
Your team has set up Codex to review pull requests in this repo. Reviews are triggered when you
- Open a pull request for review
- Mark a draft as ready
- Comment "@codex review".
If Codex has suggestions, it will comment; otherwise it will react with 👍.
Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".
There was a problem hiding this comment.
💡 Codex Review
Here are some automated review suggestions for this pull request.
Reviewed commit: 8164cc2838
ℹ️ About Codex in GitHub
Your team has set up Codex to review pull requests in this repo. Reviews are triggered when you
- Open a pull request for review
- Mark a draft as ready
- Comment "@codex review".
If Codex has suggestions, it will comment; otherwise it will react with 👍.
Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".
There was a problem hiding this comment.
💡 Codex Review
Here are some automated review suggestions for this pull request.
Reviewed commit: ecd27d47d5
ℹ️ About Codex in GitHub
Your team has set up Codex to review pull requests in this repo. Reviews are triggered when you
- Open a pull request for review
- Mark a draft as ready
- Comment "@codex review".
If Codex has suggestions, it will comment; otherwise it will react with 👍.
Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".
There was a problem hiding this comment.
💡 Codex Review
Here are some automated review suggestions for this pull request.
Reviewed commit: 567f57e83c
ℹ️ About Codex in GitHub
Your team has set up Codex to review pull requests in this repo. Reviews are triggered when you
- Open a pull request for review
- Mark a draft as ready
- Comment "@codex review".
If Codex has suggestions, it will comment; otherwise it will react with 👍.
Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".
There was a problem hiding this comment.
💡 Codex Review
Here are some automated review suggestions for this pull request.
Reviewed commit: 692d2aee80
ℹ️ About Codex in GitHub
Your team has set up Codex to review pull requests in this repo. Reviews are triggered when you
- Open a pull request for review
- Mark a draft as ready
- Comment "@codex review".
If Codex has suggestions, it will comment; otherwise it will react with 👍.
Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".
There was a problem hiding this comment.
💡 Codex Review
Here are some automated review suggestions for this pull request.
Reviewed commit: 24cb818668
ℹ️ About Codex in GitHub
Your team has set up Codex to review pull requests in this repo. Reviews are triggered when you
- Open a pull request for review
- Mark a draft as ready
- Comment "@codex review".
If Codex has suggestions, it will comment; otherwise it will react with 👍.
Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".
There was a problem hiding this comment.
💡 Codex Review
Here are some automated review suggestions for this pull request.
Reviewed commit: 1481be246b
ℹ️ About Codex in GitHub
Your team has set up Codex to review pull requests in this repo. Reviews are triggered when you
- Open a pull request for review
- Mark a draft as ready
- Comment "@codex review".
If Codex has suggestions, it will comment; otherwise it will react with 👍.
Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".
| value = (ROCKCHIP_SFC_FIFO_DEPTH << ROCKCHIP_SFC_FSR_TXLV_SHIFT) | | ||
| (rx_level << ROCKCHIP_SFC_FSR_RXLV_SHIFT); |
There was a problem hiding this comment.
The fresh evidence after the earlier FIFO finding is that the final fix now hard-codes ROCKCHIP_SFC_FIFO_DEPTH (32), but TXLV is a five-bit field (ROCKCHIP_SFC_FSR_TXLV_MASK is 0x1f << 8). Shifting 32 places a bit outside that field, so Linux masks the value to zero and its PIO write loop sees no available FIFO entries, potentially stalling every non-DMA flash write. Report the maximum representable level (31), or adjust the modeled depth/encoding to match the hardware contract.
Useful? React with 👍 / 👎.
| if (words > ROCKCHIP_SPI_FIFO_DEPTH) { | ||
| words = ROCKCHIP_SPI_FIFO_DEPTH; | ||
| } |
There was a problem hiding this comment.
For a read-only transfer longer than 32 bytes, this truncates the requested count to one FIFO's capacity and discards the remaining count. After Linux drains those 32 bytes, no later RXDR access or status update generates the remaining clocks, so RX_FULL deasserts while the driver still has unread bytes and the transfer can wait indefinitely. Track the outstanding word count and refill the RX FIFO as space becomes available.
Useful? React with 👍 / 👎.
| qemu_fdt_setprop_string(fdt, rtc, "compatible", "haoyu,hym8563"); | ||
| qemu_fdt_setprop_cell(fdt, rtc, "reg", 0x51); | ||
| qemu_fdt_setprop_string(fdt, rtc, "status", "okay"); |
There was a problem hiding this comment.
On direct -kernel boots using the generated DTB, the HYM8563 node has no interrupt-parent or interrupts property even though the modeled INT output is wired to GPIO0_B0. Consequently the RTC driver cannot request the line and alarm/timer wakeups implemented by the device never reach the guest on this boot path; allocate a phandle for GPIO0 and describe pin 8 as the active-low RTC interrupt.
Useful? React with 👍 / 👎.
Model the RK3588 SPI flash controller register interface used by the Linux rockchip-sfc driver (JEDEC/SFDP discovery, PIO and DMA transfers, DMA interrupt). Add a Winbond w25q128 SFDP table (JESD216A, 16 MiB) and attach the flash on the SoC SFC bus; an optional -drive if=mtd,index=0 backs it. A qtest programs the flash through the SFC registers and verifies the DMA interrupt path. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Model the rockchip-spi register interface in TX/RX modes and the RK806 PMIC SPI frame protocol, wired together on SPI2 chip-select 0, so the vendor kernel PMIC probe and regulator setup succeed and the MMC/PCIe probe chains stop deferring on missing regulators. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Return stable in-range ADC codes for the rockchip-thermal driver so the kernel thermal framework boots without critical-trip shutdowns. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Provide entropy to the rockchip-trngv1 driver so the kernel CRNG seeds early and getrandom() does not block during boot. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
RAM-backed DMAC1 window so the pl330 driver binds and registers the DT DMA provider; SPI consumers stop deferring dma_request_chan(). Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Model pcie2x1l0/pcie2x1l2 (domains 2/4, buses 0x20/0x40) with FDT nodes, serial PHY syscons, and ITS0 MSI routing. Links stay down while U-Boot runs and come up on the kernel's first PSCI call so the vendor dw-pcie probe sees the hosts. A qtest attaches virtio-net-pci on the pcie2x1l0 root bridge secondary bus and drives ATU config reads, BAR assignment, MSI-X table access, and full RX/TX over a socket netdev. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Add a firmware-bootargs machine property. U-Boot's booti rewrites /chosen/bootargs from its environment right before entering the kernel, so the model keeps the value patched in place (a same-length store in the existing property slot, dropping the androidboot.fwver tail) until the kernel entry PC is observed, then leaves the DTB untouched. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
The vendor ttyFIQ0 console probe calls rockchip_sip; report success for SIP_SHARE_MEM and UARTDBG_CFG calls and hand out a shared page so the console driver binds and UART2 stays usable. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
The vendor DTB pstore window at 0x110000 is read at probe; provide RAM backing so the pstore driver does not abort on an unmapped page. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Verify the eMMC controller answers CMD1 with the OCR the vendor MMC stack expects during card power-up. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Cover the SFC/w25q128 flash, SPI2+RK806, TRNG, TSADC, DMAC stub, ramoops window, the pcie2x1 hosts, the firmware-bootargs property, and the verified official-image boot with a network endpoint on pcie2x1l0. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Model the RK3588 I2C6 controller register contract used by drivers/i2c/busses/i2c-rk3x.c: CON/MOD/START/STOP, MRXADDR/ MRXRADDR, MTXCNT/MRXCNT, the TX/RX buffers, IEN/IPD and the v5 auto-stop mode (CON1). Transfers execute synchronously against the attached I2CBus and post MBTF/MBRF/STOP/NAKRCV with a level IRQ asserted while (IPD & IEN). Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Model the haoyu,hym8563 RTC used on the ROCK 5B+ (I2C6, 0x51): BCD time registers 0x02-0x08 with VL/century bits, CTL1/CTL2, alarm, CLKOUT and timer registers. The clock is seeded from the QEMU host time and the open-drain INT output is wired to GPIO0 RK_PB0. Wire the device on the board, add FDT nodes and qtest coverage of TX/RX/NAK transfers and the register block round-trip. The guest now boots with a correct system clock instead of waiting for NTP, fixing apt's stale Release-file timestamp errors. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Add build-qemu.sh (configure and build aarch64-softmmu with slirp), fetch-radxa-image.sh (download, verify and unpack the Radxa Bookworm image) and run-rock5b-plus.sh (boot the image on the rock-5b-plus machine with the e1000e NIC), plus a README covering the full flow. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Only the firmware boot needs every PCIe link down (U-Boot skips hosts with unprogrammed iATUs). Direct -kernel boots and qtests keep the default link-up state, restoring the rk3588-evb pcie qtest expectation and the rock-5b-plus machine-creation test. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
i2c_slave_create_simple() returns I2CSlave *, which is not interchangeable with DeviceState * in C; wrap it in DEVICE() so -Werror builds (CI) compile. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Remove the leftover unused variable so -Werror test builds (CI) compile. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
The ROCK 5B+ ships with 8 GB of LPDDR5; default the machine to 8 GiB. RAM above the 4 GiB window is mapped in the high window at 4 GiB and described as a second DDR ATAG bank, which U-Boot turns into a second memory bank. Direct -kernel boots stay limited to the low window (the generic loader describes a single bank) and the EVB machine keeps its 2 GiB default. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
The default inbound window exists to pass inbound TLPs through to guest memory, but its 32-bit limit left DMA above 4 GiB untranslated: guests with high RAM stalled on TX completions and the e1000e watchdog reset the NIC every few seconds. Widen the limit field and cover the whole address space (VMState v2). Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Exercise the 16550 core (scratch, divisor latch, MCR loopback, LSR flags) and the DesignWare vendor window (USR FIFO status and scratch storage) of the UART2 console. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Model every RK3588 UART (uart0-uart9) with its 16550 core and DesignWare vendor window, wired to the GIC, and add FDT nodes for all of them. Only the ports with I/O routed out on the ROCK 5B+ (UART1, UART2, UART3, UART4, UART7) bind a serial chardev; UART2 keeps the console slot and the rest are modeled without external output. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Check every UART's 16550 core (scratch, LSR flags) and vendor USR window, and verify the machine FDT exposes all ten ports with the right interrupt numbers. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Model the real ROCK 5B+ split boot media: SPI NOR supplies the RKNS/FIT firmware while the SD card remains the U-Boot payload device. Select the SPI FIT offset and boot-source code accordingly, while retaining the complete-image SD fallback. Identify the board's XTX XT25F128 flash and cap the SFC FIFO level fields to their five-bit hardware width. Accept the lowercase U-Boot FIT OS spelling used by the Radxa image and cover the real JEDEC ID in qtest. Signed-off-by: Chao Liu <chao.liu@processmission.com>
Document the SPI NOR firmware image and SD payload layout used by the ROCK 5B+ model, including the U-Boot device numbering and QEMU command line for the split-media boot path. Signed-off-by: Chao Liu <chao.liu@processmission.com>
The XT25F128B on the ROCK 5B+ uses JEDEC ID 0x0b4018; the model dropped the 0x0b manufacturer byte and had no XTX handling, so the guest read "40 18 18", and the spi-nor quad-enable sequence collected only one WRSR byte (SR2 was never set), failing the probe with -EIO. Add the XTX manufacturer with the Winbond-like status-register and quad-enable behavior. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Check the SFDP read (0x5a), the spi-nor quad-enable sequence (WREN + 16-bit WRSR with SR2 QE bit, then RDSR/RDSR2 read-back) and the corrected XT25F128B JEDEC ID (0x0b4018). Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Clamp MTXCNT/MRXCNT to the 32-byte FIFO so a large guest count cannot overrun the internal buffers. Keep the bus transaction open across FIFO refills (the driver writes MTXCNT again after MBTF) until software STOP or hardware auto-stop, consuming the address byte only on the first chunk. Serialize the armed state and reassert the IRQ after migration. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Reject DMA read triggers before the command/address phase has allocated the RX buffer, and cap PIO write lengths so a huge SFC_LEN_EXT cannot grow the transfer buffer without bound. After migration, reassert chip select when a pending operation already sent its command/address phase and recompute the IRQ output from the restored registers. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
The destination restores ISR/IMR and the FIFO but not the GPIO output level; recompute the IRQ in a post-load hook so a pending RF_FULL or TX_EMPTY interrupt wakes the driver again. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Bulk SPI frames address sequential registers; increment frame_addr after each data byte in both the write and read states so multi-register transfers no longer repeat the first register. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Add a one-second tick that decrements the countdown register and sets TF when it reaches zero, compares the alarm fields (SEC..DAY) against the current time and raises AF on match, then re-evaluates the IRQ output so AIE/TIE wakeups actually fire. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
The AMBA probe reads PIDR/CIDR n as separate 32-bit registers at 4-byte spacing; store each byte at its register offset so the reconstructed IDs match the PL330 and the device binds. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
qemu_guest_getrandom() records and replays the generated words, so record/replay runs no longer diverge from the host entropy source. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Keep the viewport limit 32-bit so nested VMState arrays keep the v1 stream layout, reconstruct the window end's upper bits from the base for outbound windows above 4 GiB, and treat the untouched default inbound window as full-space. Migrate the dynamic link state of the Rockchip host so a firmware-booted VM keeps its links up across migration. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Only patch the bootargs property when it carries a NUL terminator and the requested text forms a complete argument, so malformed firmware DTBs cannot overrun the copy and substrings no longer silently skip the patch. Give pcie2x1l2 its own prefetch window and keep UART2's chardev slot unique in zephyr-ram mode. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Rebuild the table with the actual Winbond encoding aligned to the Linux spi-nor field map: 3-byte-only addressing (DWORD1 bits 18:17), 128 Mbit density, real read settings and erase types, sized to a power of two. Model the XT25F128B read dummy bytes (0x0b/0x3b/0x6b: one, 0xbb: one, 0xeb: three) so the flash's protocol state matches the dummy cycles the SFC controller clocks from the SFDP settings. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
Rearm the one-second timer from the tick callback so alarms and countdowns keep expiring instead of stopping after the first virtual second. Alarm registers 0x09..0x0c hold minute, hour, day and weekday, so compare each against the matching live time register rather than starting at the seconds register. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
SFC_DATA writes hand their words to the flash synchronously, so the TX FIFO occupancy must not be derived from the cumulative operation length: tx_len grows to the full transfer and made FSR report zero space (TX full) after the first 128 bytes of a PIO write. Report the FIFO as empty with all entries free again. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
1481be2 to
36a5af5
Compare
There was a problem hiding this comment.
💡 Codex Review
Here are some automated review suggestions for this pull request.
Reviewed commit: 36a5af577a
ℹ️ About Codex in GitHub
Your team has set up Codex to review pull requests in this repo. Reviews are triggered when you
- Open a pull request for review
- Mark a draft as ready
- Comment "@codex review".
If Codex has suggestions, it will comment; otherwise it will react with 👍.
Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".
| for (i = 0; i < 4; i++) { | ||
| uint8_t mask = i == 0 ? 0x7f : 0x3f; | ||
|
|
||
| if (!(alarm[i] & BIT(7)) && | ||
| (s->regs[HYM8563_SEC + 1 + i] & mask) != (alarm[i] & mask)) { |
There was a problem hiding this comment.
When an alarm is programmed for a future minute/hour/day, each tick compares it with regs[0x03..0x06], but those live-time registers are refreshed only by hym8563_capture_current_time() during I2C_START_RECV; without periodic RTC reads they remain frozen at the last read or reset time, so the alarm never matches (or repeatedly matches stale values). Fresh evidence after the earlier alarm-field fix is that the corrected field indexes still do not obtain the current time before this comparison.
Useful? React with 👍 / 👎.
qtest intercepts the GIC inputs and aborts on any raise event with an IRQ above MAX_IRQ (256); the migration tests that intercept the GIC hit this when rk3x_i2c/rockchip_spi/rockchip_sfc reassert their interrupts after load (SPI 323/328) or the hym8563 tick drives the RTC interrupt through GPIO0 (SPI 277). Skip the IRQ recomputation and leave the RTC tick disarmed under qtest, where migration tests inspect register state rather than IRQ lines. Signed-off-by: Chao Liu <zevorn@ChaodeMacBook-Pro.local>
There was a problem hiding this comment.
💡 Codex Review
Here are some automated review suggestions for this pull request.
Reviewed commit: 1d7e2cad04
ℹ️ About Codex in GitHub
Your team has set up Codex to review pull requests in this repo. Reviews are triggered when you
- Open a pull request for review
- Mark a draft as ready
- Comment "@codex review".
If Codex has suggestions, it will comment; otherwise it will react with 👍.
Codex can also answer questions or update the PR. Try commenting "@codex address that feedback".
| .name = "rockchip-pcie-host", | ||
| .version_id = 1, | ||
| .minimum_version_id = 1, |
There was a problem hiding this comment.
When migrating an RK3588 VM from a QEMU version before this change, the source registers each Rockchip host under the inherited designware-pcie-host VMState name, while this destination now expects rockchip-pcie-host; because the section identity changes and the new boolean is added while the version remains 1, the old section cannot be matched or decoded. Fresh evidence after the earlier link-state finding is that the attempted serialization replaces the inherited top-level VMState rather than extending its compatible layout; retain the old identity and version the added state (or use a compatible subsection).
Useful? React with 👍 / 👎.
| .fields = (const VMStateField[]) { | ||
| VMSTATE_UINT32_ARRAY(regs, RK3588RNGState, RK3588_RNG_MMIO_SIZE / 4), | ||
| VMSTATE_UINT32_ARRAY(rand_words, RK3588RNGState, 8), | ||
| VMSTATE_BOOL(rand_ready, RK3588RNGState), |
There was a problem hiding this comment.
If migration occurs after a guest starts generation and before it acknowledges RAND_RDY, rand_ready is restored but the destination IRQ output remains at its reset-low level because this VMState has no post-load callback. An interrupt-driven guest can therefore remain blocked despite the restored ready status; recompute the IRQ from the migrated state after loading.
Useful? React with 👍 / 👎.
| if ((s->regs[0x0e] & BIT(7)) && s->regs[0x0f] > 0) { | ||
| s->regs[0x0f]--; |
There was a problem hiding this comment.
When the guest selects any timer frequency other than 1 Hz in TMR_CTL bits 1:0, this unconditional once-per-second decrement expires the countdown at the wrong time: the 4096 Hz and 64 Hz modes run far too slowly, while the 1/60 Hz mode runs 60 times too quickly. Fresh evidence after the earlier timer-scheduling fix is that the recurring callback still ignores the frequency selector; schedule or accumulate ticks according to the selected TD value.
Useful? React with 👍 / 👎.
1 participant
Summary
Model the remaining RK3588 peripheral devices needed to boot the official
Radxa ROCK 5B+ Bookworm image headless and to exercise a PCIe network
endpoint on
pcie2x1l0:pcie2x1l0/pcie2x1l2) with FDT nodes, serial PHYsyscons, ITS0 MSI routing and the U-Boot/kernel link-up handoff
firmware-bootargsmachine property that patches/chosen/bootargsinplace when U-Boot rewrites it before entering the kernel
The unmodified official image now boots headless to
rock-5b-plus login:(
-machine rock-5b-plus,firmware-bootargs='cpuidle.off=1 systemd.unit=multi-user.target'), and a NIC onpcie2x1l0works end toend (e1000e driver shipped in the image; DHCP/ping/HTTP over
-netdev user).Commits
hw/ssi: add Rockchip SFC controller and w25q128 SFDP flashhw/ssi: add Rockchip SPI controller and RK806 PMIChw/misc: add RK3588 TSADC thermal sensor modelhw/misc: add RK3588 TRNGv1 modelhw/misc: add RK3588 PL330 DMA controller stubhw/arm/rk3588: add PCIe 2.0 x1 hosts and endpoint supporthw/arm/rk3588: patch /chosen/bootargs for firmware-bootargshw/arm/rk3588: answer vendor FIQ debugger SIP serviceshw/arm/rk3588: back the vendor ramoops window with RAMtests/qtest: add rock5b-plus SDHCI CMD1 testdocs: document RK3588 peripheral models and Rock 5B+ bootVerification
-drive if=sd,index=0),/proc/mtdshows the 16 MiB SFC flash,lspcienumerates the pcie2x1l0 root bridgepcie2x1l0(image-shipped driver): DHCP 10.0.2.15, ping andHTTP to the host work