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5 changes: 2 additions & 3 deletions drivers/tty/serial/qcom_geni_serial.c
Original file line number Diff line number Diff line change
Expand Up @@ -1295,9 +1295,8 @@ static int geni_serial_set_rate(struct uart_port *uport, unsigned int baud)
* Bump up BW vote on CPU and CORE path as driver supports FIFO mode
* only.
*/
avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
: GENI_DEFAULT_BW;
port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
avg_bw_core = (baud > 115200) ? CORE_2X_50_MHZ : CORE_2X_19_2_MHZ;
port->se.icc_paths[GENI_TO_CORE].avg_bw = Bps_to_icc(avg_bw_core);
port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
geni_icc_set_bw(&port->se);

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21 changes: 11 additions & 10 deletions include/linux/soc/qcom/geni-se.h
Original file line number Diff line number Diff line change
Expand Up @@ -349,17 +349,18 @@ struct geni_se {
#define QUP_SE_VERSION_2_5 0x20050000

/*
* Define bandwidth thresholds that cause the underlying Core 2X interconnect
* clock to run at the named frequency. These baseline values are recommended
* by the hardware team, and are not dynamically scaled with GENI bandwidth
* beyond basic on/off.
* ICC bandwidth values in Bps for the GENI_TO_CORE ("qup-core") path.
* Convert them with Bps_to_icc() before setting avg_bw. The QUP ICC provider
* maps each threshold to the Core 2X rate named by the macro suffix.
*
* These values are core clock votes, not GENI transfer bandwidths.
*/
#define CORE_2X_19_2_MHZ 960
#define CORE_2X_50_MHZ 2500
#define CORE_2X_100_MHZ 5000
#define CORE_2X_150_MHZ 7500
#define CORE_2X_200_MHZ 10000
#define CORE_2X_236_MHZ 16383
#define CORE_2X_19_2_MHZ 9600000
#define CORE_2X_50_MHZ 25000000
#define CORE_2X_100_MHZ 50000000
#define CORE_2X_150_MHZ 75000000
#define CORE_2X_200_MHZ 100000000
#define CORE_2X_236_MHZ 118000000

#define GENI_DEFAULT_BW Bps_to_icc(1000)

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