Issues

[Toolchain] On zhang-21, /usr/bin/ld 2.30 fails every Vitis HLS cosim link; cosim.py -B/usr/bin assumes binutils 2.42

sunwookim028/allo#50 · opened

on Oct 8, 2026

[TinyTPU] mutate.py aborts before testing: the vadd_holds_stale_x anchor occurs twice in accumulator.py since vaddrelu

sunwookim028/allo#49 · opened

on Oct 8, 2026

Action/compose: arithmetic does not flow from actions.py into compose.py

sunwookim028/allo#47 · opened

on Sep 25, 2026

1

Power in the CHIA objective: works on a fixture, never measured on TinyTPU

sunwookim028/allo#46 · opened

on Sep 25, 2026

GDS / place-and-route: documented, never run

sunwookim028/allo#45 · opened

on Sep 25, 2026

[limitation G] `= 0` on an array is a runtime zero-fill loop, and costs measured cycles

sunwookim028/allo#34 · opened

on Sep 22, 2026

1

[limitation F] The AIE `cpp-style` typing rules reject every bitwise op

sunwookim028/allo#33 · opened

on Sep 22, 2026

[limitation E] Same-type shadowing of a region parameter gives an MLIR region-isolation error

sunwookim028/allo#32 · opened

on Sep 22, 2026

[limitation D] Catapult `full()` always returns `false`

sunwookim028/allo#31 · opened

on Sep 22, 2026

[limitation C] `customize()` calls `sys.exit(1)` on a frontend error, which no `except Exception` can catch

sunwookim028/allo#30 · opened

on Sep 22, 2026

[limitation 23] `m_axi` port widening is not reachable from user code: `align_value` is necessary and not sufficient

sunwookim028/allo#26 · opened

on Sep 22, 2026

[limitation 22] The SystemC fork's `Wire` is semantically incomplete, and wrong in RTL rather than only in simulation

sunwookim028/allo#25 · opened

on Sep 22, 2026

1

[limitation 19] `try_get`/`try_put` on the TAPA target fail to emit, with a message that blames `wrap_io`

sunwookim028/allo#24 · opened

on Sep 22, 2026

[limitation 18] Catapult lowers `try_get`/`try_put` to blocking reads with `success` hard-coded true

sunwookim028/allo#23 · opened

on Sep 22, 2026

[limitation 17] Frontend constraints worth documenting: rejected constructs and `meta_if` scoping

sunwookim028/allo#22 · opened

on Sep 22, 2026

[limitation 16] `cosim` is not wired into `df.build`, and `m_axi` is emitted with no `depth=`

sunwookim028/allo#21 · opened

on Sep 22, 2026

1

[limitation 15] Vitis csim executes dataflow processes in declaration order, and hangs silently when they are misordered

sunwookim028/allo#20 · opened

on Sep 22, 2026

[limitation 14] `wrap_io=False` rejects multi-dimensional arguments to nested kernels, including locals

sunwookim028/allo#19 · opened

on Sep 22, 2026

[limitation 10] Frontend error messages point at lowered MLIR, not at the user's source

sunwookim028/allo#18 · opened

on Sep 22, 2026

[limitation 8] A sub-region called from two call sites is rebuilt under the same symbol names

sunwookim028/allo#17 · opened

on Sep 22, 2026

1

[limitation 5] Variable shadowing between region params and kernel-local names

sunwookim028/allo#16 · opened

on Sep 22, 2026

1

[limitation 4] `math.exp` / `math.log` are not recognized by the AST builder

sunwookim028/allo#15 · opened

on Sep 22, 2026

1

Feature map: fork vs upstream (living tracking issue)

sunwookim028/allo#13 · opened

on Jul 15, 2026

1

[Feature] IP Integration C++ - support of streams as top-level inputs to functions

sunwookim028/allo#12 · opened

on Jul 8, 2026

2

[Feature] No shared mutable memory across kernels in dataflow regions

sunwookim028/allo#11 · opened

on Jul 8, 2026

2

Navigation Menu

Repository navigation

Issues

[Toolchain] On zhang-21, /usr/bin/ld 2.30 fails every Vitis HLS cosim link; cosim.py -B/usr/bin assumes binutils 2.42

[TinyTPU] mutate.py aborts before testing: the vadd_holds_stale_x anchor occurs twice in accumulator.py since vaddrelu

Action/compose: arithmetic does not flow from actions.py into compose.py

Power in the CHIA objective: works on a fixture, never measured on TinyTPU

GDS / place-and-route: documented, never run

[limitation G] `= 0` on an array is a runtime zero-fill loop, and costs measured cycles

[limitation F] The AIE `cpp-style` typing rules reject every bitwise op

[limitation E] Same-type shadowing of a region parameter gives an MLIR region-isolation error

[limitation D] Catapult `full()` always returns `false`

[limitation C] `customize()` calls `sys.exit(1)` on a frontend error, which no `except Exception` can catch

[limitation 23] `m_axi` port widening is not reachable from user code: `align_value` is necessary and not sufficient

[limitation 22] The SystemC fork's `Wire` is semantically incomplete, and wrong in RTL rather than only in simulation

[limitation 19] `try_get`/`try_put` on the TAPA target fail to emit, with a message that blames `wrap_io`

[limitation 18] Catapult lowers `try_get`/`try_put` to blocking reads with `success` hard-coded true

[limitation 17] Frontend constraints worth documenting: rejected constructs and `meta_if` scoping

[limitation 16] `cosim` is not wired into `df.build`, and `m_axi` is emitted with no `depth=`

[limitation 15] Vitis csim executes dataflow processes in declaration order, and hangs silently when they are misordered

[limitation 14] `wrap_io=False` rejects multi-dimensional arguments to nested kernels, including locals

[limitation 10] Frontend error messages point at lowered MLIR, not at the user's source

[limitation 8] A sub-region called from two call sites is rebuilt under the same symbol names

[limitation 5] Variable shadowing between region params and kernel-local names

[limitation 4] `math.exp` / `math.log` are not recognized by the AST builder

Feature map: fork vs upstream (living tracking issue)

[Feature] IP Integration C++ - support of streams as top-level inputs to functions

[Feature] No shared mutable memory across kernels in dataflow regions