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…isters it before the system bus
3 of 11 tasks
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Part of #9.
vfio-pci now resets a device the way QEMU 11.1 does when the device has no FLR.
vfio_pci_reset()tries FLR first. Without it, it tries a bus or slot reset throughVFIO_DEVICE_PCI_HOT_RESET, and falls back to the PM reset ofVFIO_DEVICE_RESETonly when nothing else worked. On a system reset,vfio_device_reset_handler()runs before any device is reset and resets together the devices in use that share a bus.What is in it:
VFIO_DEVICE_GET_PCI_HOT_RESET_INFO, which reports how many devices a hot reset takes along even when it fails withENOSPC, andVFIO_DEVICE_PCI_HOT_RESETwith the group descriptors as proof of ownership. The group descriptor is now reachable throughAsFd.vfio_pci_pre_reset()andvfio_pci_post_reset(). The first stops interrupts and DMA, clears INTx Disable and brings the device to D0. The second turns INTx back on and clears the BARs.vfio_pci_compute_needs_reset()andvfio_legacy_pci_hot_reset(), with QEMU's errors for a device with no reset mechanism and for a dependent group that is not owned.qemu_register_reset()handlers run, since the system bus reset is registered only after every-deviceis realized. The first vfio-pci registers the vfio reset handler there.machine_done()runs once every device is plugged, resets it on both the TCG and KVM paths. ruvm has nodevice_add, so there is no hotplug path that would need its own reset after realize.Checked:
On server2, on c64ade1, the branch with main up to #343 merged in:
-D warningsand--all-targetsfor ruvm-mem, ruvm-hw-iommu, ruvm-sys, ruvm-hw-pci, ruvm-hw-vfio, ruvm-machine-x86, ruvm-machine-arm and ruvm-system.-device vfio-pci,host=0000:01:00.0,addr=2under qtest and strace, as QEMU 11.1, ruvm and QEMU 11.1 again, one at a time. qtest sets RAL0 of the e1000e, resets the system through 0xcf9, waits until BAR0 reads 0, maps BAR0 again and reads RAL0 and RAH0. The runs waited until the host load was under 16 and ran at a host load between 15 and 21.The ioctls on the device descriptor are the same in all three, at start and again after the 0xcf9 reset:
All the answers are the same in the three runs. RAL0 reads 0x12005452, reads back 0xa1b2c3d4 after the write, and reads 0x12005452 again after the reset, with RAH0 0x80005634. So the device really was reset. ruvm took two BAR0 polls to see the reset where QEMU took one.
Before this change, ruvm reset the device at realize too, which added four calls at start (ENOSPC, 0, ENOTTY, 0) before the sequence above. The compare that found it ran on 919a7c1.