AXI4-Lite: hold BVALID/RVALID until ready in bus-error mode - #88
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tgingold-cern merged 1 commit intoAug 25, 2026
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With bus-error enabled, the write and read response channels cleared axi_wdone/axi_rdone unconditionally every cycle and no longer cleared them on the BREADY/RREADY handshake. BVALID/RVALID therefore asserted for a single cycle after the internal ack instead of being held until the master accepted the response (AXI4-Lite A3.2.1). A master that was not immediately ready lost the response, and because AWREADY/WREADY (resp. ARREADY) are only re-asserted once the response is accepted, the slave then deadlocked. Drive the handshake in bus-error mode exactly as without it: hold axi_wdone/axi_rdone until the handshake, and register BRESP/RRESP (set on ack, held until accepted) so the response is stable while VALID is high. The reset-time behaviour (accept accesses and return SLVERR while in reset) is preserved by forcing BVALID/RVALID high from the reset signal, so out of reset VALID reflects only a real response. The existing bus-error testbench used an always-ready master and could not observe the deadlock; extend it to hold BREADY/RREADY low for several cycles and check VALID stays asserted with stable data/response. That check fails against the previous output and passes with this change. Fixes tgingold-cern#86
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Summary
Fixes #86.
With
bus-errorenabled, the AXI4-Lite write and read response channels madeBVALID/RVALIDa one-cycle pulse and could deadlock the slave:axi_wdone/axi_rdoneunconditionally every cycle, and the clear-on-handshake was gated behindif not opts.bus_error, so it was dropped.BVALID/RVALIDtherefore asserted for a single cycle after the internal ack, instead of being held until the master assertedBREADY/RREADY(AXI4-Lite A3.2.1).AWREADY/WREADY(resp.ARREADY) are only re-asserted once the response is accepted (axi_wdone & bready), the slave then wedged permanently.Fix
Drive the handshake in bus-error mode exactly as without it:
axi_wdone/axi_rdoneuntil the handshake (restore the clear onVALID & READY, remove the unconditional per-cycle clear).BRESP/RRESP(set on ack, held until accepted) so the response value is stable whileVALIDis high — the previous per-cycle reset ofaxi_werr/axi_rerrwould otherwise change the response whileVALIDwas held.The existing reset-time behaviour is preserved: accesses issued while in reset are still completed with
SLVERRrather than stalling.BVALID/RVALIDare forced high from the reset signal during reset, so out of resetVALIDreflects only a real, held response (no phantom response leaks past reset).Non-bus-error output is unchanged.
Testing
cd proto && python tests.py— all generation tests pass (output unchanged except the bus-error golden).testfiles/tb/buserr_axi4_tb.vhdl: the existing testbench used an always-ready master, so it could never observe the pulse/deadlock. Extended it to holdBREADY/RREADYlow for several cycles and assert thatVALIDstays high with stableDATA/RESP.RVALID dropped before RREADY), i.e. the test genuinely catches the bug.