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Merged
titzer merged 2 commits into from
Oct 21, 2026
Merged

[spc] Fix register clobbering in some SIMD instructions #730

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0459aa7
Add regression test
titzer Oct 21, 2026
0c10932
Fix register clobbering in some SIMD instructions
titzer Oct 21, 2026
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10 changes: 5 additions & 5 deletions src/engine/x86-64/X86_64Interpreter.v3
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Original file line number Diff line number Diff line change
Expand Up @@ -3273,7 +3273,7 @@ class X86_64InterpreterGen(ic: X86_64InterpreterCode, w: DataWriter) {
genSimdUnop_x_r(Opcode.I8X16_BITMASK, asm.pmovmskb_r_s);
genSimdUnop_x_r(Opcode.I32X4_BITMASK, asm.movmskps_r_s);
genSimdUnop_x_r(Opcode.I64X2_BITMASK, asm.movmskpd_r_s);
genSimdUnop_x_r(Opcode.I16X8_BITMASK, masm.emit_i16x8_bitmask);
genSimdUnop_xxtmp_r(Opcode.I16X8_BITMASK, masm.emit_i16x8_bitmask);

// V128 shifts
for (t in [
Expand Down Expand Up @@ -3318,7 +3318,7 @@ class X86_64InterpreterGen(ic: X86_64InterpreterCode, w: DataWriter) {
genSimdBinop(Opcode.I8X16_MAX_U, asm.pmaxub_s_s);
genSimdBinop(Opcode.I8X16_AVGR_U, asm.pavgb_s_s);
genSimdBinop(Opcode.I8X16_EQ, asm.pcmpeqb_s_s);
genSimdBinop(Opcode.I8X16_NE, masm.emit_i8x16_ne);
genSimdBinop(Opcode.I8X16_NE, masm.emit_i8x16_ne(_, _, r_xmm2));
genSimdBinop(Opcode.I8X16_ADD_SAT_S, asm.paddsb_s_s);
genSimdBinop(Opcode.I8X16_ADD_SAT_U, asm.paddusb_s_s);
genSimdBinop(Opcode.I8X16_SUB_SAT_S, asm.psubsb_s_s);
Expand All @@ -3342,7 +3342,7 @@ class X86_64InterpreterGen(ic: X86_64InterpreterCode, w: DataWriter) {
genSimdBinop(Opcode.I16X8_MAX_U, asm.pmaxuw_s_s);
genSimdBinop(Opcode.I16X8_AVGR_U, asm.pavgw_s_s);
genSimdBinop(Opcode.I16X8_EQ, asm.pcmpeqw_s_s);
genSimdBinop(Opcode.I16X8_NE, masm.emit_i16x8_ne);
genSimdBinop(Opcode.I16X8_NE, masm.emit_i16x8_ne(_, _, r_xmm2));
genSimdBinop(Opcode.I16X8_ADD_SAT_S, asm.paddsw_s_s);
genSimdBinop(Opcode.I16X8_ADD_SAT_U, asm.paddusw_s_s);
genSimdBinop(Opcode.I16X8_SUB_SAT_S, asm.psubsw_s_s);
Expand All @@ -3369,7 +3369,7 @@ class X86_64InterpreterGen(ic: X86_64InterpreterCode, w: DataWriter) {
genSimdBinop(Opcode.I32X4_MAX_S, asm.pmaxsd_s_s);
genSimdBinop(Opcode.I32X4_MAX_U, asm.pmaxud_s_s);
genSimdBinop(Opcode.I32X4_EQ, asm.pcmpeqd_s_s);
genSimdBinop(Opcode.I32X4_NE, masm.emit_i32x4_ne);
genSimdBinop(Opcode.I32X4_NE, masm.emit_i32x4_ne(_, _, r_xmm2));
genSimdBinop(Opcode.I32X4_EXTMUL_LOW_I16X8_S, masm.emit_i32x4_extmul(_, _, r_xmm2, true, true));
genSimdBinop(Opcode.I32X4_EXTMUL_LOW_I16X8_U, masm.emit_i32x4_extmul(_, _, r_xmm2, true, false));
genSimdBinop(Opcode.I32X4_EXTMUL_HIGH_I16X8_S, masm.emit_i32x4_extmul(_, _, r_xmm2, false, true));
Expand All @@ -3386,7 +3386,7 @@ class X86_64InterpreterGen(ic: X86_64InterpreterCode, w: DataWriter) {
genSimdBinop(Opcode.I64X2_SUB, asm.psubq_s_s);
genSimdBinop(Opcode.I64X2_MUL, masm.emit_i64x2_mul(_, _, r_xmm2, r_xmm3));
genSimdBinop(Opcode.I64X2_EQ, asm.pcmpeqq_s_s);
genSimdBinop(Opcode.I64X2_NE, masm.emit_i64x2_ne);
genSimdBinop(Opcode.I64X2_NE, masm.emit_i64x2_ne(_, _, r_xmm2));
genSimdBinop(Opcode.I64X2_EXTMUL_LOW_I32X4_S, masm.emit_i64x2_extmul(_, _, r_xmm2, true, true));
genSimdBinop(Opcode.I64X2_EXTMUL_LOW_I32X4_U, masm.emit_i64x2_extmul(_, _, r_xmm2, true, false));
genSimdBinop(Opcode.I64X2_EXTMUL_HIGH_I32X4_S, masm.emit_i64x2_extmul(_, _, r_xmm2, false, true));
Expand Down
38 changes: 20 additions & 18 deletions src/engine/x86-64/X86_64MacroAssembler.v3
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Expand Up @@ -1238,22 +1238,22 @@ class X86_64MacroAssembler extends MacroAssembler {
// 5. Add 3 and 4.
asm.paddq_s_s(lhs, tmp2);
}
def emit_v128_ne<T>(dst: X86_64Xmmr, src: X86_64Xmmr, f: (X86_64Xmmr, X86_64Xmmr) -> T) {
def emit_v128_ne<T>(dst: X86_64Xmmr, src: X86_64Xmmr, scratch: X86_64Xmmr, f: (X86_64Xmmr, X86_64Xmmr) -> T) {
f(dst, src);
f(src, src);
asm.pxor_s_s(dst, src);
f(scratch, scratch);
asm.pxor_s_s(dst, scratch);
}
def emit_i8x16_ne(dst: X86_64Xmmr, src: X86_64Xmmr) {
emit_v128_ne(dst, src, asm.pcmpeqb_s_s);
def emit_i8x16_ne(dst: X86_64Xmmr, src: X86_64Xmmr, scratch: X86_64Xmmr) {
emit_v128_ne(dst, src, scratch, asm.pcmpeqb_s_s);
}
def emit_i16x8_ne(dst: X86_64Xmmr, src: X86_64Xmmr) {
emit_v128_ne(dst, src, asm.pcmpeqw_s_s);
def emit_i16x8_ne(dst: X86_64Xmmr, src: X86_64Xmmr, scratch: X86_64Xmmr) {
emit_v128_ne(dst, src, scratch, asm.pcmpeqw_s_s);
}
def emit_i32x4_ne(dst: X86_64Xmmr, src: X86_64Xmmr) {
emit_v128_ne(dst, src, asm.pcmpeqd_s_s);
def emit_i32x4_ne(dst: X86_64Xmmr, src: X86_64Xmmr, scratch: X86_64Xmmr) {
emit_v128_ne(dst, src, scratch, asm.pcmpeqd_s_s);
}
def emit_i64x2_ne(dst: X86_64Xmmr, src: X86_64Xmmr) {
emit_v128_ne(dst, src, asm.pcmpeqq_s_s);
def emit_i64x2_ne(dst: X86_64Xmmr, src: X86_64Xmmr, scratch: X86_64Xmmr) {
emit_v128_ne(dst, src, scratch, asm.pcmpeqq_s_s);
}
def emit_v128_gt_u<T>(dst: X86_64Xmmr, src: X86_64Xmmr, scratch: X86_64Xmmr,
pmax: (X86_64Xmmr, X86_64Xmmr) -> T, pcmp: (X86_64Xmmr, X86_64Xmmr) -> T) {
Expand Down Expand Up @@ -1295,10 +1295,11 @@ class X86_64MacroAssembler extends MacroAssembler {
emit_v128_ge(dst, src, asm.pminud_s_s, asm.pcmpeqd_s_s);
}
def emit_i64x2_ge_s(dst: X86_64Xmmr, src: X86_64Xmmr, scratch: X86_64Xmmr) {
asm.pcmpgtq_s_s(src, dst);
asm.pcmpeqd_s_s(scratch, scratch);
emit_v128_xorps(src, scratch);
asm.movaps_s_s(dst, src);
// ge_s(dst, src) == !(src > dst)
asm.movaps_s_s(scratch, src);
asm.pcmpgtq_s_s(scratch, dst);
asm.pcmpeqd_s_s(dst, dst);
emit_v128_xorps(dst, scratch);
}
def emit_i8x16_shl(dst: X86_64Xmmr, shift: X86_64Gpr, tmp1: X86_64Gpr, tmp2: X86_64Xmmr, tmp3: X86_64Xmmr) {
// Take shift value modulo 8.
Expand Down Expand Up @@ -1436,9 +1437,10 @@ class X86_64MacroAssembler extends MacroAssembler {
def emit_i32x4_alltrue(dst: X86_64Gpr, src: X86_64Xmmr, tmp: X86_64Xmmr) { emit_v128_alltrue(dst, src, tmp, asm.pcmpeqd_s_s); }
def emit_i64x2_alltrue(dst: X86_64Gpr, src: X86_64Xmmr, tmp: X86_64Xmmr) { emit_v128_alltrue(dst, src, tmp, asm.pcmpeqq_s_s); }

def emit_i16x8_bitmask(dst: X86_64Gpr, src: X86_64Xmmr) {
asm.packsswb_s_s(src, src);
asm.pmovmskb_r_s(dst, src);
def emit_i16x8_bitmask(dst: X86_64Gpr, src: X86_64Xmmr, scratch: X86_64Xmmr) {
// Only the high 8 bytes (packed from src) are used; the low 8 bytes are garbage.
asm.packsswb_s_s(scratch, src);
asm.pmovmskb_r_s(dst, scratch);
asm.shr_r_i(dst, 8);
}
def emit_i8x16_popcnt(dst: X86_64Xmmr, tmp1: X86_64Gpr, xtmp1: X86_64Xmmr, xtmp2: X86_64Xmmr, mask: X86_64Xmmr) {
Expand Down
18 changes: 10 additions & 8 deletions src/engine/x86-64/X86_64SinglePassCompiler.v3
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Original file line number Diff line number Diff line change
Expand Up @@ -523,7 +523,7 @@ class X86_64SinglePassCompiler extends SinglePassCompiler {
def visit_I32X4_ALLTRUE() { do_op1_r_x(ValueKind.I32, mmasm.emit_i32x4_alltrue(_, _, X(allocTmp(ValueKind.V128)))); }
def visit_I64X2_ALLTRUE() { do_op1_r_x(ValueKind.I32, mmasm.emit_i64x2_alltrue(_, _, X(allocTmp(ValueKind.V128)))); }
def visit_I8X16_BITMASK() { do_op1_r_x(ValueKind.I32, asm.pmovmskb_r_s); }
def visit_I16X8_BITMASK() { do_op1_r_x(ValueKind.I32, mmasm.emit_i16x8_bitmask); }
def visit_I16X8_BITMASK() { do_op1_r_x(ValueKind.I32, mmasm.emit_i16x8_bitmask(_, _, X(allocTmp(ValueKind.V128)))); }
def visit_I32X4_BITMASK() { do_op1_r_x(ValueKind.I32, asm.movmskps_r_s); }
def visit_I64X2_BITMASK() { do_op1_r_x(ValueKind.I32, asm.movmskpd_r_s); }

Expand All @@ -534,7 +534,7 @@ class X86_64SinglePassCompiler extends SinglePassCompiler {
def visit_I8X16_SUB() { do_op2_x_x(ValueKind.V128, asm.psubb_s_s); }
def visit_I8X16_NEG() { do_op1_x_xtmp(ValueKind.V128, mmasm.emit_i8x16_neg); }
def visit_I8X16_EQ() { do_op2_x_x(ValueKind.V128, asm.pcmpeqb_s_s); }
def visit_I8X16_NE() { do_op2_x_x(ValueKind.V128, mmasm.emit_i8x16_ne); }
def visit_I8X16_NE() { do_op2_x_x_xtmp(ValueKind.V128, mmasm.emit_i8x16_ne); }
def visit_I8X16_GT_S() { do_op2_x_x(ValueKind.V128, asm.pcmpgtb_s_s); }
def visit_I8X16_GT_U() { do_op2_x_x_xtmp(ValueKind.V128, mmasm.emit_i8x16_gt_u); }
def visit_I8X16_LT_S() { do_c_op2_x_x(ValueKind.V128, asm.pcmpgtb_s_s); }
Expand Down Expand Up @@ -565,7 +565,7 @@ class X86_64SinglePassCompiler extends SinglePassCompiler {
def visit_I16X8_MUL() { do_op2_x_x(ValueKind.V128, asm.pmullw_s_s); }
def visit_I16X8_NEG() { do_op1_x_xtmp(ValueKind.V128, mmasm.emit_i16x8_neg); }
def visit_I16X8_EQ() { do_op2_x_x(ValueKind.V128, asm.pcmpeqw_s_s); }
def visit_I16X8_NE() { do_op2_x_x(ValueKind.V128, mmasm.emit_i16x8_ne); }
def visit_I16X8_NE() { do_op2_x_x_xtmp(ValueKind.V128, mmasm.emit_i16x8_ne); }
def visit_I16X8_GT_S() { do_op2_x_x(ValueKind.V128, asm.pcmpgtw_s_s); }
def visit_I16X8_GT_U() { do_op2_x_x_xtmp(ValueKind.V128, mmasm.emit_i16x8_gt_u); }
def visit_I16X8_LT_S() { do_c_op2_x_x(ValueKind.V128, asm.pcmpgtw_s_s); }
Expand Down Expand Up @@ -607,7 +607,7 @@ class X86_64SinglePassCompiler extends SinglePassCompiler {
def visit_I32X4_MUL() { do_op2_x_x(ValueKind.V128, asm.pmulld_s_s); }
def visit_I32X4_NEG() { do_op1_x_xtmp(ValueKind.V128, mmasm.emit_i32x4_neg); }
def visit_I32X4_EQ() { do_op2_x_x(ValueKind.V128, asm.pcmpeqd_s_s); }
def visit_I32X4_NE() { do_op2_x_x(ValueKind.V128, mmasm.emit_i32x4_ne); }
def visit_I32X4_NE() { do_op2_x_x_xtmp(ValueKind.V128, mmasm.emit_i32x4_ne); }
def visit_I32X4_GT_S() { do_op2_x_x(ValueKind.V128, asm.pcmpgtd_s_s); }
def visit_I32X4_GT_U() { do_op2_x_x_xtmp(ValueKind.V128, mmasm.emit_i32x4_gt_u); }
def visit_I32X4_LT_S() { do_c_op2_x_x(ValueKind.V128, asm.pcmpgtd_s_s); }
Expand Down Expand Up @@ -649,7 +649,7 @@ class X86_64SinglePassCompiler extends SinglePassCompiler {
def visit_I64X2_MUL() { do_op2_x_x(ValueKind.V128, mmasm.emit_i64x2_mul(_, _, X(allocTmp(ValueKind.V128)), X(allocTmp(ValueKind.V128)))); }
def visit_I64X2_NEG() { do_op1_x_xtmp(ValueKind.V128, mmasm.emit_i64x2_neg); }
def visit_I64X2_EQ() { do_op2_x_x(ValueKind.V128, asm.pcmpeqq_s_s); }
def visit_I64X2_NE() { do_op2_x_x(ValueKind.V128, mmasm.emit_i64x2_ne); }
def visit_I64X2_NE() { do_op2_x_x_xtmp(ValueKind.V128, mmasm.emit_i64x2_ne); }
def visit_I64X2_GT_S() { do_op2_x_x(ValueKind.V128, asm.pcmpgtq_s_s); }
def visit_I64X2_LT_S() { do_c_op2_x_x(ValueKind.V128, asm.pcmpgtq_s_s); }
def visit_I64X2_GE_S() { do_op2_x_x_xtmp(ValueKind.V128, mmasm.emit_i64x2_ge_s); }
Expand Down Expand Up @@ -839,6 +839,7 @@ class X86_64SinglePassCompiler extends SinglePassCompiler {
var a = popRegToOverwrite();
var gtmp = G(allocTmp(ValueKind.I64));
var xtmp_mask = X(allocTmp(ValueKind.V128));
var xtmp_b = X(allocTmp(ValueKind.V128));

def SIMD_128_SIZE: byte = 16;
var mask1: Array<u64> = [0x0, 0x0];
Expand All @@ -856,11 +857,12 @@ class X86_64SinglePassCompiler extends SinglePassCompiler {
// Extract bytes from a
mmasm.load_v128_mask(xtmp_mask, (mask1[0], mask1[1]), gtmp);
asm.pshufb_s_s(X(a.reg), xtmp_mask);
// Extract bytes from b
// Extract bytes from b (into a temp, since b's register may be shared, e.g. with a local)
mmasm.load_v128_mask(xtmp_mask, (mask2[0], mask2[1]), gtmp);
asm.pshufb_s_s(X(b.reg), xtmp_mask);
asm.movaps_s_s(xtmp_b, X(b.reg));
asm.pshufb_s_s(xtmp_b, xtmp_mask);
// Merge the two results
asm.orps_s_s(X(a.reg), X(b.reg));
asm.orps_s_s(X(a.reg), xtmp_b);
state.push(a.kindFlagsMatching(ValueKind.V128, IN_REG), a.reg, 0);
}

Expand Down
10 changes: 10 additions & 0 deletions test/regress/simd/issue_650a.bin.wast
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@@ -0,0 +1,10 @@
(module definition binary
"\00\61\73\6d\01\00\00\00\01\85\80\80\80\00\01\60"
"\00\01\7f\03\82\80\80\80\00\01\00\07\88\80\80\80"
"\00\01\04\6d\61\69\6e\00\00\0a\aa\80\80\80\00\01"
"\a4\80\80\80\00\01\01\7b\fd\0c\00\00\00\00\00\9c"
"\00\00\00\00\00\00\00\00\00\00\21\00\20\00\20\00"
"\fd\24\1a\20\00\fd\15\05\0b"
)
(module instance)
(assert_return (invoke "main") (i32.const 0xffff_ff9c))
9 changes: 9 additions & 0 deletions test/regress/simd/issue_650a.wast
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@@ -0,0 +1,9 @@
(module
(func (export "main") (result i32)
(local $v v128)
v128.const i8x16 0 0 0 0 0 0x9c 0 0 0 0 0 0 0 0 0 0 ;; lane 5 = 0x9c (-100)
local.set $v
local.get $v local.get $v i8x16.ne drop ;; result discarded
local.get $v i8x16.extract_lane_s 5)) ;; return local back

(assert_return (invoke "main") (i32.const -100))
10 changes: 10 additions & 0 deletions test/regress/simd/issue_650b.bin.wast
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Original file line number Diff line number Diff line change
@@ -0,0 +1,10 @@
(module definition binary
"\00\61\73\6d\01\00\00\00\01\85\80\80\80\00\01\60"
"\00\01\7f\03\82\80\80\80\00\01\00\07\88\80\80\80"
"\00\01\04\6d\61\69\6e\00\00\0a\aa\80\80\80\00\01"
"\a4\80\80\80\00\01\01\7b\fd\0c\00\00\00\00\00\00"
"\00\00\00\00\18\fc\00\00\00\00\21\00\20\00\20\00"
"\fd\2e\1a\20\00\fd\18\05\0b"
)
(module instance)
(assert_return (invoke "main") (i32.const 0xffff_fc18))
9 changes: 9 additions & 0 deletions test/regress/simd/issue_650b.wast
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@@ -0,0 +1,9 @@
(module
(func (export "main") (result i32)
(local $v v128)
v128.const i16x8 0 0 0 0 0 -1000 0 0 ;; lane 5 = -1000
local.set $v
local.get $v local.get $v i16x8.ne drop ;; result discarded
local.get $v i16x8.extract_lane_s 5)) ;; return local back

(assert_return (invoke "main") (i32.const -1000))
10 changes: 10 additions & 0 deletions test/regress/simd/issue_650c.bin.wast
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@@ -0,0 +1,10 @@
(module definition binary
"\00\61\73\6d\01\00\00\00\01\85\80\80\80\00\01\60"
"\00\01\7f\03\82\80\80\80\00\01\00\07\88\80\80\80"
"\00\01\04\6d\61\69\6e\00\00\0a\aa\80\80\80\00\01"
"\a4\80\80\80\00\01\01\7b\fd\0c\00\00\00\00\d1\2f"
"\01\00\00\00\00\00\00\00\00\00\21\00\20\00\20\00"
"\fd\38\1a\20\00\fd\1b\01\0b"
)
(module instance)
(assert_return (invoke "main") (i32.const 0x1_2fd1))
9 changes: 9 additions & 0 deletions test/regress/simd/issue_650c.wast
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@@ -0,0 +1,9 @@
(module
(func (export "main") (result i32)
(local $v v128)
v128.const i32x4 0 77777 0 0 ;; lane 1 = 77777
local.set $v
local.get $v local.get $v i32x4.ne drop ;; result discarded
local.get $v i32x4.extract_lane 1)) ;; return local back

(assert_return (invoke "main") (i32.const 77777))
10 changes: 10 additions & 0 deletions test/regress/simd/issue_650d.bin.wast
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@@ -0,0 +1,10 @@
(module definition binary
"\00\61\73\6d\01\00\00\00\01\85\80\80\80\00\01\60"
"\00\01\7e\03\82\80\80\80\00\01\00\07\88\80\80\80"
"\00\01\04\6d\61\69\6e\00\00\0a\ab\80\80\80\00\01"
"\a5\80\80\80\00\01\01\7b\fd\0c\00\00\00\00\00\00"
"\00\00\89\67\45\23\01\00\00\00\21\00\20\00\20\00"
"\fd\d7\01\1a\20\00\fd\1d\01\0b"
)
(module instance)
(assert_return (invoke "main") (i64.const 0x1_2345_6789))
9 changes: 9 additions & 0 deletions test/regress/simd/issue_650d.wast
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@@ -0,0 +1,9 @@
(module
(func (export "main") (result i64)
(local $v v128)
v128.const i64x2 0 0x123456789 ;; lane 1 = 0x123456789
local.set $v
local.get $v local.get $v i64x2.ne drop ;; result discarded
local.get $v i64x2.extract_lane 1)) ;; return local back

(assert_return (invoke "main") (i64.const 0x123456789))
11 changes: 11 additions & 0 deletions test/regress/simd/issue_650e.bin.wast
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@@ -0,0 +1,11 @@
(module definition binary
"\00\61\73\6d\01\00\00\00\01\85\80\80\80\00\01\60"
"\00\01\7e\03\82\80\80\80\00\01\00\07\88\80\80\80"
"\00\01\04\6d\61\69\6e\00\00\0a\bb\80\80\80\00\01"
"\b5\80\80\80\00\01\01\7b\fd\0c\05\00\00\00\00\00"
"\00\00\f9\ff\ff\ff\ff\ff\ff\ff\21\00\fd\0c\00\00"
"\00\00\00\00\00\00\00\00\00\00\00\00\00\00\20\00"
"\fd\db\01\1a\20\00\fd\1d\00\0b"
)
(module instance)
(assert_return (invoke "main") (i64.const 0x5))
9 changes: 9 additions & 0 deletions test/regress/simd/issue_650e.wast
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(module
(func (export "main") (result i64)
(local $v v128)
v128.const i64x2 5 -7 ;; lane 0 = 5
local.set $v
v128.const i64x2 0 0 local.get $v i64x2.ge_s drop ;; result discarded
local.get $v i64x2.extract_lane 0)) ;; return local back

(assert_return (invoke "main") (i64.const 5))
11 changes: 11 additions & 0 deletions test/regress/simd/issue_650f.bin.wast
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(module definition binary
"\00\61\73\6d\01\00\00\00\01\85\80\80\80\00\01\60"
"\00\01\7e\03\82\80\80\80\00\01\00\07\88\80\80\80"
"\00\01\04\6d\61\69\6e\00\00\0a\bb\80\80\80\00\01"
"\b5\80\80\80\00\01\01\7b\fd\0c\05\00\00\00\00\00"
"\00\00\f9\ff\ff\ff\ff\ff\ff\ff\21\00\20\00\fd\0c"
"\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00"
"\fd\da\01\1a\20\00\fd\1d\00\0b"
)
(module instance)
(assert_return (invoke "main") (i64.const 0x5))
9 changes: 9 additions & 0 deletions test/regress/simd/issue_650f.wast
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(module
(func (export "main") (result i64)
(local $v v128)
v128.const i64x2 5 -7 ;; lane 0 = 5
local.set $v
local.get $v v128.const i64x2 0 0 i64x2.le_s drop ;; result discarded
local.get $v i64x2.extract_lane 0)) ;; return local back

(assert_return (invoke "main") (i64.const 5))
10 changes: 10 additions & 0 deletions test/regress/simd/issue_650g.bin.wast
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(module definition binary
"\00\61\73\6d\01\00\00\00\01\85\80\80\80\00\01\60"
"\00\01\7f\03\82\80\80\80\00\01\00\07\88\80\80\80"
"\00\01\04\6d\61\69\6e\00\00\0a\a9\80\80\80\00\01"
"\a3\80\80\80\00\01\01\7b\fd\0c\e8\03\d0\07\b8\0b"
"\a0\0f\88\13\70\17\58\1b\40\1f\21\00\20\00\fd\84"
"\01\1a\20\00\fd\18\05\0b"
)
(module instance)
(assert_return (invoke "main") (i32.const 0x1770))
9 changes: 9 additions & 0 deletions test/regress/simd/issue_650g.wast
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(module
(func (export "main") (result i32)
(local $v v128)
v128.const i16x8 1000 2000 3000 4000 5000 6000 7000 8000 ;; lane 5 = 6000
local.set $v
local.get $v i16x8.bitmask drop ;; result discarded
local.get $v i16x8.extract_lane_s 5)) ;; return local back

(assert_return (invoke "main") (i32.const 6000))
12 changes: 12 additions & 0 deletions test/regress/simd/issue_650h.bin.wast
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(module definition binary
"\00\61\73\6d\01\00\00\00\01\85\80\80\80\00\01\60"
"\00\01\7f\03\82\80\80\80\00\01\00\07\88\80\80\80"
"\00\01\04\6d\61\69\6e\00\00\0a\ca\80\80\80\00\01"
"\c4\80\80\80\00\01\01\7b\fd\0c\00\00\00\00\00\9c"
"\00\00\00\00\00\00\00\00\00\00\21\00\fd\0c\01\02"
"\03\04\05\06\07\08\09\0a\0b\0c\0d\0e\0f\10\20\00"
"\fd\0d\00\01\02\03\04\05\06\07\08\09\0a\0b\0c\0d"
"\0e\0f\1a\20\00\fd\15\05\0b"
)
(module instance)
(assert_return (invoke "main") (i32.const 0xffff_ff9c))
12 changes: 12 additions & 0 deletions test/regress/simd/issue_650h.wast
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(module
(func (export "main") (result i32)
(local $v v128)
v128.const i8x16 0 0 0 0 0 0x9c 0 0 0 0 0 0 0 0 0 0 ;; lane 5 = 0x9c (-100)
local.set $v
v128.const i8x16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
local.get $v
i8x16.shuffle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ;; all lanes from first operand
drop ;; result discarded
local.get $v i8x16.extract_lane_s 5)) ;; return local back

(assert_return (invoke "main") (i32.const -100))
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