Deep Learning Accelerator (Convolution Neural Networks)
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Dec 15, 2017 - Verilog
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bit-serial
Here are 6 public repositories matching this topic...
A bit-serial CPU written in VHDL, with a simulator written in C.
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Sep 1, 2024 - VHDL
NeuralHorner: learned bit-serial modular arithmetic, with studies of exactness, length transfer, compression, structured failures, and a Lean-verified integer scaffold.
machine-learning recurrent-neural-networks gru modular-arithmetic bit-serial lean4 neural-arithmetic
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Aug 20, 2026 - Python
RTL implementation of a bit-serial Matrix-Vector Multiplication (MVM) unit, inspired by the Stripes hardware accelerator.
fsm rtl verilog datapath systemverilog computer-architecture modelsim digital-design bit-serial rtl-design hardware-accelerator hardware-architecture
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Sep 6, 2026 - Verilog
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