#
hitsz
Here are 29 public repositories matching this topic...
Verilog miniRV/RISC-V style CPU course project featuring single-cycle and five-stage pipeline designs with hazard handling.
cpu pipeline verilog computer-architecture risc-v digital-design computer-organization cpu-design hitsz
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Jun 16, 2026 - Verilog
哈尔滨工业大学（深圳）中文 LaTeX 简历模板，支持 XeLaTeX 与 Overleaf
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Jul 18, 2026 - TeX
This is my personal homepage. The purpose of this site is to catch the eye of potential Mitacs supervisors; unfortunately, I don’t currently have any computer science projects that are truly impressive—most of my work relates to physics-based simulations.
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Nov 2, 2026 - Astro
An automated line-following car project for the 2022 AUTO1001 course at HITSZ.
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Jul 23, 2025 - C++
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