#
outoforder
Here are 3 public repositories matching this topic...
2 Way Superscalar P6 Out of Order Processor
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Updated
May 3, 2022 - SystemVerilog
Repository for a project, developed in the Logisim Evolution simulator, that implements a complete MIPS processor architecture, incorporating a memory hierarchy with cache and a four-stage pipeline with support for out-of-order execution (OoO).
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Updated
Dec 8, 2025
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