Portable HyperRAM controller

A Docker image for Mentor/Siemens Questa

Formal AXI verification properties from the eXpect framework for secure SoC validation

Utilities for Avalon Memory Map

Synthesizable AXI4 crossbar with a full UVM verification environment — RTL, SVA, coverage, stress, and CI.

ieee_proposed with names changed to floatfixlib to be compatible with Quartus Prime Lite and support fixed, float, etc.

✅ Formal verification of a 16-bit SIMD processor

This repository contains the digital design and verification of the AMBA3 (Advanced Microcontroller Bus Architecture) and AMBA4 APB (Advanced Peripheral Bus) protocols.

RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.

Examples for 「Questa-Altera FPGA Starter Editionで始めるRTL検証」

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

Formal (VC Formal FPV) and UVM verification of an 8-lane mixed-precision INT8/BF16/NVFP4 dot-product core, with a shared SystemVerilog golden reference across assertions and scoreboards.

Configurable CRC-8/16 RTL with full UVM verification (SystemVerilog, QuestaSim). Serial and parallel modes.

This project implements a SPI (Serial Peripheral Interface) slave module with a single port RAM block. The SPI slave module receives data from a master device and communicates with the single port RAM to store and retrieve data.

UVM verification environment for an I2C controller (constrained-random + assertions + functional coverage) — Questa/ModelSim

SystemVerilog model of the Intel 8088 microprocessor bus interfacing to memory and I/O — Moore and Mealy FSM memory/IO modules, SystemVerilog interfaces with modports, a bus-functional model driving encrypted 8088 IP, and a self-checking testbench. Intro to SystemVerilog course project.

Design and UVM verification of a 64-entry 8-bit asynchronous FIFO for clock-domain crossing (80 MHz write / 50 MHz read) — Gray-coded pointers, two-flop synchronizers, wrap-aware full/empty flags, a reset-aware scoreboard, functional coverage, and Questa farm evidence. ECE 593 team project.

An application using Qeusta FPGA student version of Intel

Procesor ve VHDL pro jazyk Brainfuck