rsic-v

rusty_alloc is the worlds first Unified Allocator. A pure-Rust, memory safe alternative to mimalloc with unified performance across x86-64 Linux, windows, aarch64, wasm, and RSIC-V for ESP architecture.

This is my hobby project, which contain my rsic-v core and my convolutional layer with AMBA bus

星允派，一款双核单片机开发板，由嵌入式社区RYMCU倾力打造。板载STM32F103VET6(ARM-M3)和CH32V203C8(RISC-V)内核单片机。

ESP-ADF / ESP-GMF / esp_codec_dev remade in Rust: I2S/PDM capture and playback, a fixed-block audio pipeline, codec-chip drivers, Opus/FLAC/ADPCM framing via the Remade codecs. Memory safe, no_std core.

An implementation of rv32i single cycle processor on logisim

esp_video / esp_h264 / CameraWebServer remade in Rust: MJPEG and H.264 (rusty_h264 embedded) encode, RTP + MJPEG-over-HTTP packetizers, P4 hardware encoder wrap. Memory safe, no_std

MATA mID on the chip: a device DID with its key at rest in encrypted NVS/eFuse, signed assertions, capability verification, owner adoption (bind-to-this-hub as a signed grant) and a signed capability manifest. Replaces vendor provisioning and cloud claiming. Memory safe, no_std core.

The radio-application layer remade in Rust: Wi-Fi CSI radar (presence/motion), LoRa point-to-point over lora-phy, BLE provisioning and telemetry over trouble-host, Wi-Fi station/AP lifecycle and ESP-NOW framing — every frame mID-signed. Memory safe, no_std core.

ESP-DSP remade: the PIE (ESP32-S3 ee.*, ESP32-P4 esp.*) SIMD kernel home with scalar oracles. Created only once two function packages share a hot kernel; until then kernels live in the function's -core crate.

esp32-camera / esp_jpeg remade in Rust: sensor bring-up as data, DMA frame pools, pixel ops, JPEG/PNG via rusty_jpeg and rusty_png. Memory safe, no_std core.

Shared no_std types for the Janus ESP family: media frames, PCM, timestamps, capability manifest, and the three HAL seams (clock, rng, kv). No drivers, no allocator, no product types.

A comprehensive English reference guide for the Ai-WB2-32S (BL602) RISC-V development kit. Features step-by-step tutorials for setting up the RISC-V GNU Toolchain, configuring Eclipse CDT with CMake/MSYS2, and flashing firmware using BLDevCube.

Multi-Task Attention U-Net for VLSI routing congestion & dynamic IR drop co-estimation using CircuitNet 5-channel standard on RISC-V macros, built in PyTorch.

The FreeRTOS ports remade in Rust: the deterministic sim port (the oracle harness), the Posix host port, and the Cortex-M, RISC-V and Xtensa ports — the only crates in the family with a fenced unsafe block, at the context switch and the vector table.

coreJSON remade in Rust: the strict ECMA-404 validator and the query-by-path search, zero allocation, no_std, forbid(unsafe), with the no-panic gate every parser in the family carries.

The shared vocabulary of the Kairos family (FreeRTOS remade in Rust): ticks, priorities, generational handles, one Copy error, the Config trait, and the Port / Heap / Trace / Hooks seams. No pointers, no allocator, no arch. forbid(unsafe).

Shared files and issues for 2026 Controls. Forked from https://github.com/CalPolyWindPower/2026-Controls_Core .