Issues

• Translation entry eviction needs to be handled correctly

  bug
  ymarathe/TLB-Coherence-Simulator#22 · Filter by author ymarathe opened on Mar 15, 2018
  

• Cache to cache transfer needs to be modeled

  bug
  ymarathe/TLB-Coherence-Simulator#14 · Filter by author ymarathe opened on Feb 7, 2018

• Coherence logic marks L2 line as modified on a *_WRITE

  bugquestion
  ymarathe/TLB-Coherence-Simulator#13 · Filter by author ymarathe opened on Feb 7, 2018
  1

• Coherence logic broadcasts *_READ updates incorrectly

  bug
  ymarathe/TLB-Coherence-Simulator#12 · Filter by author ymarathe opened on Feb 7, 2018
  1

• Build trace consumption logic into the simulator

  bug
  ymarathe/TLB-Coherence-Simulator#11 · Filter by author ymarathe opened on Feb 7, 2018

• Decide on number of outstanding misses at each level

  enhancementquestion
  ymarathe/TLB-Coherence-Simulator#7 · Filter by author ymarathe opened on Feb 6, 2018
  

• Add instrumentation counters in each unit

  bug
  ymarathe/TLB-Coherence-Simulator#5 · Filter by author ymarathe opened on Feb 6, 2018

• RequestStatus is not propagated upstream in the cache hierarchy

  bug
  ymarathe/TLB-Coherence-Simulator#2 · Filter by author ymarathe opened on Feb 6, 2018

• Simulation progresses only if all cores->tick() is called

  bug
  ymarathe/TLB-Coherence-Simulator#1 · Filter by author ymarathe opened on Feb 6, 2018