Issues

• Failed parallel DCP write leaves temporary files and background work behind

  Xilinx/RapidWright#1471 · Filter by author eddieh-xlnx opened on Oct 16, 2026

• EDIF export collides renamed instance a-b with existing instance a_b

  Xilinx/RapidWright#1461 · Filter by author vera-rubin opened on Oct 12, 2026
  1

• EDIFNetlist.findParentNet(): faster search when only the parent net is needed

  enhancement
  Xilinx/RapidWright#1459 · Filter by author clavin-xlnx opened on Oct 9, 2026

• [NetlistBrowser] Add search and attribute viewer

  Xilinx/RapidWright#1423 · Filter by author clavin-xlnx opened on Sep 15, 2026

• Transfer dcp to bit

  Xilinx/RapidWright#1407 · Filter by author Fpga888v opened on Aug 28, 2026
  1

• Thread Safety of Parent Net Map

  Xilinx/RapidWright#1398 · Filter by author jakobwenzel opened on Jul 29, 2026
  2

• Disagreement between Vivado and RapidWright on SitePIP status

  Xilinx/RapidWright#1397 · Filter by author jakobwenzel opened on Jul 20, 2026
  1

• Routing issues

  Xilinx/RapidWright#1364 · Filter by author pech1002 opened on Apr 24, 2026
  3

• Add test for UltraScale+ PBlock movement

  Xilinx/RapidWright#1336 · Filter by author abutt-amd opened on Dec 9, 2025
  

• [RWRoute] Optimize Versal SLR crossings

  enhancement
  Xilinx/RapidWright#1329 · Filter by author eddieh-xlnx opened on Nov 25, 2025

• [Report Timing] intersite_delay_terms

  Xilinx/RapidWright#1312 · Filter by author coherent17 opened on Nov 5, 2025
  22

• Handling place and route for designs with encrypted cells

  enhancement
  Xilinx/RapidWright#1290 · Filter by author clavin-xlnx opened on Sep 24, 2025
  

• Partitioner branch does not check leafLUTCountLimit for valid value.

  Xilinx/RapidWright#1283 · Filter by author pnewlin-amd opened on Sep 12, 2025
  1

• Design.writeCheckpoint emits non-deterministic binary outputs

  Xilinx/RapidWright#1244 · Filter by author korbin opened on Jul 4, 2025
  3

• DesignTools.copyImplementation sometimes results in unplaced non-VCC/GND cells

  Xilinx/RapidWright#1239 · Filter by author korbin opened on Jun 27, 2025
  8

  

• Cell properties not propagated in macro cells to child instances

  enhancement
  Xilinx/RapidWright#1069 · Filter by author clavin-xlnx opened on Sep 24, 2024
  

• LUTTools.swapSingleLutPins() cannot swap H[1-6] when used as WA

  enhancement
  Xilinx/RapidWright#901 · Filter by author eddieh-xlnx opened on Nov 29, 2023

• GlobalSignalRouting.getLCBPinMappings() fails for some pins

  bug
  Xilinx/RapidWright#756 · Filter by author eddieh-xlnx opened on Jul 17, 2023
  

• [Interchange] EnumerateCellBelMapping Speedup Opportunity

  enhancement
  Xilinx/RapidWright#659 · Filter by author clavin-xlnx opened on Apr 28, 2023

• Speedup interchange.DeviceResourcesExample

  enhancement
  Xilinx/RapidWright#625 · Filter by author eddieh-xlnx opened on Mar 10, 2023

• Trimming PIPs of pins on net one-at-a-time may not work

  bug
  Xilinx/RapidWright#485 · Filter by author eddieh-xlnx opened on Jul 26, 2022

• ModuleInst.place() does not check for overlap

  Xilinx/RapidWright#478 · Filter by author clavin-xlnx opened on Jul 19, 2022

• " Too many words to allocate: 333129474" beyond the limit of capnp?

  Xilinx/RapidWright#410 · Filter by author the-centry opened on May 7, 2022
  1

• RapidWright should track in the netlist if macros have been expanded or collapsed

  Xilinx/RapidWright#388 · Filter by author clavin-xlnx opened on Apr 15, 2022
  2

• Provide the equivalent of write_checkpoint -cell in RapidWright

  enhancement
  Xilinx/RapidWright#386 · Filter by author clavin-xlnx opened on Apr 13, 2022