All pull requests

Pull requests

• [EDIFNetlist] Keep macros expanded in memory, collapse only when writing

  needs new release
  #1484·clavin-xlnx opened Oct 29, 2026Member·

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  5

• Logic equivalence checker

  #1483·clavin-xlnx opened Oct 27, 2026Member·

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  35

• [RWRoute] Timing-driven LUT pin swapping with LUT logic delays

  #1482·eddieh-xlnx opened Oct 26, 2026Collaborator·

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  2

• [DesignTools] populateBlackBox(): prefix routethru names once

  #1480·clavin-xlnx opened Oct 26, 2026Member·

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  4

• [ReportRouteStatus] Add Vivado-like reportVivadoRouteStatus()

  #1477·clavin-xlnx opened Oct 22, 2026Member·

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  24

• Write EDIF as parallel pieces; ParallelismTools joinOrdered()/joinUnordered() and chunking

  needs new release
  #1475·eddieh-xlnx opened Oct 20, 2026Collaborator·

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• 2026.1.2

  #1472·clavin-xlnx opened Oct 16, 2026Member·

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• Add opt_design-style netlist constant propagation and sweep

  #1468·clavin-xlnx opened Oct 15, 2026Member·

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  30

• [TestSiteInst] Add testGetSiteWireIndicesFromNetRoundTripsWithinSiteWireCount()

  bugneeds new release
  #1428·eddieh-xlnx opened Sep 18, 2026Collaborator·

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• Add SDF parser, writer, and timing graph annotator

  #1419·clavin-xlnx opened Sep 2, 2026Member·

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  8

• ModuleInst: reject placements landing on depopulated SLL UBUMP nodes

  #1401·andrewb1999 opened Aug 4, 2026Contributor·

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  3

• Add PBlockStaticNetFixer to Simplify Relocation of Vivado Routed Modules

  #1400·andrewb1999 opened Aug 4, 2026Contributor·

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  12

• [EDIFNetlist] NetlistValidator - A tool for checking output EDIF for inconsistencies before they are found on Vivado import

  #1387·clavin-xlnx opened Jun 25, 2026Member·

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• Enumerate Versal Delay Paths [No timing information]

  #1371·clavin-xlnx opened May 21, 2026Member·

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• Add backward routing for RapidWright.

  #1346·kylepham-amd opened Jan 7, 2026Contributor·

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  9

• Fix DesignTools.getConnectionPips for sinks driven by lut constant generators

  #1231·reillymck opened Jun 20, 2025Contributor·

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  5

• Example Clock Signal Tracer

  #1216·clavin-xlnx opened Jun 12, 2025Member·

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• [TestExamples] Test PipelineGenerator with Vivado

  #1193·eddieh-xlnx opened May 20, 2025Collaborator·

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• [EDIFNetlist] exportEDIF() to use getLibrariesInExportOrder()

  #1148·eddieh-xlnx opened Feb 14, 2025Collaborator·

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  1

• [DREAMPlaceFPGA] Add placeDesign() wrapper for DREAMPlaceFPGA

  #1137·eddieh-xlnx opened Jan 13, 2025Collaborator·

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  1

• [RWRoute] Adjust wire base costs + cross SLR estimates

  #1030·eddieh-xlnx opened Jul 12, 2024Collaborator·

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  1

• [Interchange] Exports DeviceResources Routing (Wires and Nodes) Info in Multiple Messages

  #1017·clavin-xlnx opened Jun 25, 2024Member·

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• Adding shape support for DREAMPlaceFPGA inputs and Interchange Netlist

  #1011·clavin-xlnx opened Jun 21, 2024Member·

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  3

• [TestDeviceResources] Test/verify xcau10p

  #1004·eddieh-xlnx opened Jun 13, 2024Collaborator·

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• Node.getAllWiresInNode() returns empty list when Vivado doesn't

  bug
  #1002·eddieh-xlnx opened Jun 12, 2024Collaborator·

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  2