feat(pwm): prove GPIO12 ALT0 pin-mux - #76
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Mux GPIO12 to PWM0 ALT0 with fail-closed GPFSEL1 readback and leftover restore, leaving UART GPIO14/15 FSEL bits untouched and making no PWM output claim. Metal: pwm3 ok=1 version=139 pin=12 alt=1 restore=1 kernel8.img sha256 8043786d8c9cfc3261db1306eae357b6b714f4e82f687f28e479e338309b7809 Co-authored-by: Cursor <cursoragent@cursor.com>
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Hi @infektyd - this PR hasn't had any activity in over 7 days. Please update it or close it if it's no longer needed. (No merge conflicts detected.) |
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Summary
1435923ef75685bdd892ab462160ac8a30596d41(feat(pwm): prove GPIO12 ALT0 pin-mux) onto PR feat(net): prove GENET EXT RGMII OOB #75 tippr/genet34-v138@b2990241a38487e27d63f50264e9ee8eba7af933.kernel8.imgsha2568043786d8c9cfc3261db1306eae357b6b714f4e82f687f28e479e338309b7809; serialpwm3 ok=1 version=139 pin=12 alt=1 restore=1(verified live on/dev/cu.usbserial-B0044J1Vthis session; live soak probe is valid proof; iterate AND-gate miss is not a kernel miss).Test plan
gh pr view 75still tipsb2990241a38487e27d63f50264e9ee8eba7af933and this PR bases onpr/genet34-v138.pwm3 ok=1 version=139 pin=12 alt=1 restore=1.tests/test_runtime_pwm3_v139_contract.pyis in the diff and Toolsets are not.Made with Cursor