[ishaansathaye]

Doke now has one hardware selector, three exploration depths, and one floating explanation panel. Select a processor, explore its documented structures, then follow real model values or packets through execution. The human brain remains available alone or alongside the chip, with sourced timing and parts comparisons.

This integrates the foundations from #4–#7 and replaces the separate chemistry, synapse and circuit experiences. The approved design stays focused; TPU and ASIC views use the same navigation instead of adding more top-level modes.

Try it

Live demo: https://doke.ishaan.sh/

Merged into main as c3df6e039d76ea419b2bec3376400b3c5d277c0b and deployed to Cloudflare Pages. Local preview remains http://127.0.0.1:4181/ on the development Mac.

1. Choose Ryzen 9 9950X, RTX 5090, H100 SXM, Google TPU v1, or Cisco Silicon One G200.
2. Explore processor → core / SM / array / packet path → execution. Click a component for its role and primary sources; sources keep the previous explanation in a tab.
3. On CPU/GPU/NPU, edit the input and run differences, weighted neighbors or identity as C = A × B. Inspect arrived operands, cache/sector requests, and the products actually accumulated. All schedules produce the same exact result.
4. On the ASIC, open Traffic, block an output and switch FIFO to virtual output queues. The queues, packet IDs, delivery counts and buffer drops follow the Rust model; changing queue discipline preserves admitted packets.
5. Compare the human atlas, open Timing & parts, and inspect documented clock periods beside human physiological measurements. Expand a row for the study conditions and original paper.

Build and hosting guide · Architecture and model scope

Screenshots

CPU core and GPU SM:

Tensor execution and packet queues:

Brain comparison and timing evidence:

Evidence and implementation

• 65 source-linked component explanations, including AMD/NVIDIA/Google/Cisco architecture references. Product counts and functional roles are distinct from original schematic positions, areas and wiring. TPU array windows are sampled; logical GPU lanes are distinct from physical arithmetic units.
• Rust snapshots drive activity, emitted transfers, waiting work and completed sums. CPU/GPU/NPU execute 512 integer multiply-adds for 64 outputs. Switch queues enforce admission, capacity and packet conservation.
• Execution is an authored teaching model, not a calibrated vendor emulator. TPU v1's documented weight-stationary organization is distinguished from the 4 × 4 output-stationary experiment. G200's three-port example does not assert Cisco's internal capacities or arbitration.
• Human timing records preserve species, tissue preparation, units, mean/range/onset distinctions, and SD/SEM context. Only documented clocks become periods; H100 bandwidth and G200 throughput stay off the duration axis. No brain-versus-chip intelligence or speed ranking is inferred.
• Overview/Fine/Native atlas tiers, Sharp/Ultra rendering, HDR/SDR glow, orbit/pan/pinch, keyboard input and mobile navigation remain. Native anatomy has 5,080,888 triangles; this adds surface detail, not cellular resolution.
• Fixed same-chip state preservation when returning from the brain, immediate evidence access while the atlas loads, stale lane-to-output inspector actions, and saturation of larger weighted-output values.

Validation

• 32 Rust tests; 336 generated-Wasm assertions; strict core and Wasm Clippy; Rust formatting.
• 101,929 architecture checks across 25 layout combinations; 189 timing/unit/source checks; hardware catalog validation.
• Real Chrome WebGPU and WebGL: all five profiles, matrix operations, exact retired provenance, queue interventions/conservation, immediate pause, source-tab restoration, slow-atlas loading, independent brain timing and responsive layouts.
• Independent interaction regressions cover changing PE/warp assignments, weighted output shading, consistent PE labels, and header bounds from 320 to 1024 px.
• Portable artifact tested at /doke/ with packaged CSP, actual Fine atlas loading, all new source assets, and legacy-route redirects. 64 files, approximately 124 MB total; largest file 7.54 MB, below Pages' per-file limit.
• Local WebGPU sample at 3024 × 1964 with execution and a live panel: 16.7 ms median / 18.4 ms p95 over 169 frames. This is a local responsiveness check; screenshots do not establish HDR luminance.
• Gitleaks and whitespace checks pass. Generated binaries, downloads, raw captures and private deployment settings remain ignored.

CI runs source/model checks and all three browser suites. Downloaded atlas assets are explicitly skipped in CI and exercised in local/portable review. Parallel source and model/UI reviews were completed; their findings were corrected before release.

Production verification passed over anonymous HTTPS: the release manifest and UI/data/Wasm hashes match the packaged build; security headers are active; all five profiles render and complete their workloads; Overview, Fine and Native anatomy load with validated hashes, including Native’s 5,080,888 triangles. No browser errors.

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